]> git.ipfire.org Git - thirdparty/gcc.git/commit
i386: Optimize pinsrq of 0 with index 1 into movq [PR94866]
authorUros Bizjak <ubizjak@gmail.com>
Thu, 24 Aug 2023 20:23:52 +0000 (22:23 +0200)
committerUros Bizjak <ubizjak@gmail.com>
Thu, 24 Aug 2023 20:24:43 +0000 (22:24 +0200)
commit6dd73f0f00f454a05552b008a1d56560bd3f1d4a
treed40280be6b81195a798b4103aaca923ac653379b
parent721f7e2c4e5eed645593258624dd91e6c39f3bd2
i386: Optimize pinsrq of 0 with index 1 into movq [PR94866]

Add new pattern involving vec_merge RTX that is produced by combine from the
combination of sse4_1_pinsrq and *movdi_internal:

    7: r86:DI=0
    8: r85:V2DI=vec_merge(vec_duplicate(r86:DI),r87:V2DI,0x2)
      REG_DEAD r87:V2DI
      REG_DEAD r86:DI
Successfully matched this instruction:
(set (reg:V2DI 85 [ a ])
    (vec_merge:V2DI (reg:V2DI 87)
        (const_vector:V2DI [
                (const_int 0 [0]) repeated x2
            ])
        (const_int 1 [0x1])))

PR target/94866

gcc/ChangeLog:

* config/i386/sse.md (*sse2_movq128_<mode>_1): New insn pattern.

gcc/testsuite/ChangeLog:

* g++.target/i386/pr94866.C: New test.
gcc/config/i386/sse.md
gcc/testsuite/g++.target/i386/pr94866.C [new file with mode: 0644]