i386: Handle multiple address register classes

i386: Handle multiple address register classes

The patch generalizes address register class handling to allow multiple
register classes.  For APX EGPR targets, some instructions do not support
GPR32 registers, so it is necessary to limit address register set to
avoid them.  The same situation happens for instructions with high registers,
where REX registers can not be used in the address, so the existing
infrastructure can be adapted to also handle this case.

The patch is mostly a mechanical rename of "gpr32" attribute to "addr" and
introduces no functional changes, although it fixes a couple of inconsistent
attribute values in passing.

A follow-up patch will use the above infrastructure to limit address register
class to legacy registers for instructions with high registers.

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_memory_address_use_extended_reg_class_p):
	Rename to ...
	(ix86_memory_address_reg_class): ... this.  Generalize address
	register class handling to allow multiple address register classes.
	Return maximal class for unrecognized instructions.  Improve comments.
	(ix86_insn_base_reg_class): Rewrite to handle
	multiple address register classes.
	(ix86_regno_ok_for_insn_base_p): Ditto.
	(ix86_insn_index_reg_class): Ditto.
	* config/i386/i386.md: Rename "gpr32" attribute to "addr"
	and substitute its values with "0" -> "gpr16", "1" -> "*".
	(addr): New attribute to limit allowed address register set.
	(gpr32): Remove.
	* config/i386/mmx.md: Rename "gpr32" attribute to "addr"
	and substitute its values with "0" -> "gpr16", "1" -> "*".
	* config/i386/sse.md: Ditto.