]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Optimize switch with sign-extended index.
authorJim Wilson <jimw@sifive.com>
Thu, 17 May 2018 22:37:38 +0000 (22:37 +0000)
committerJim Wilson <wilson@gcc.gnu.org>
Thu, 17 May 2018 22:37:38 +0000 (15:37 -0700)
commit7bbce9b50302959286381d9177818642bceaf301
tree0ce4f20f1d1ab9a42ba1843c8d03e69332f11446
parent4e0684beff1fcd8398425b1fbe237cdbcb34c359
RISC-V: Optimize switch with sign-extended index.

gcc/
* expr.c (do_tablejump): When converting index to Pmode, if we have a
sign extended promoted subreg, and the range does not have the sign bit
set, then do a sign extend.

* config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode
test, check for sign extended subreg and/or constant operands, and
do a sign extend in that case.

gcc/testsuite/
* gcc.target/riscv/switch-qi.c: New.
* gcc.target/riscv/switch-si.c: New.

From-SVN: r260340
gcc/ChangeLog
gcc/config/riscv/riscv.c
gcc/expr.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/riscv/switch-qi.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/switch-si.c [new file with mode: 0644]