RISC-V: Enable undefined support for RVV auto-vectorization[PR110751]

RISC-V: Enable undefined support for RVV auto-vectorization[PR110751]

Now GCC middle-end can support undefined value which is traslated into (scratch:mode).

This patch is to enable RISC-V backend undefine value in ELSE value of COND_LEN_xxx/COND_xxx.

Consider this following case:

  __attribute__((noipa))
  void vrem_int8_t (int8_t * __restrict dst, int8_t * __restrict a, int8_t * __restrict b, int n)
  {
    for (int i = 0; i < n; i++)
      dst[i] = a[i] % b[i];
  }

Before this patch:

vrem_int8_t:
        ble     a3,zero,.L5
        vsetvli a5,zero,e8,m1,ta,ma
        vmv.v.i v4,0                          ---> redundant.
.L3:
        vsetvli a5,a3,e8,m1,tu,ma             ---> should be TA.
        vmv1r.v v1,v4                         ---> redudant.
        vle8.v  v3,0(a1)
        vle8.v  v2,0(a2)
        sub     a3,a3,a5
        vrem.vv v1,v3,v2
        vse8.v  v1,0(a0)
        add     a1,a1,a5
        add     a2,a2,a5
        add     a0,a0,a5
        bne     a3,zero,.L3
.L5:
        ret

After this patch:

vrem_int8_t:
	ble	a3,zero,.L5
.L3:
	vsetvli	a5,a3,e8,m1,ta,ma
	vle8.v	v1,0(a1)
	vle8.v	v2,0(a2)
	sub	a3,a3,a5
	vrem.vv	v1,v1,v2
	vse8.v	v1,0(a0)
	add	a1,a1,a5
	add	a2,a2,a5
	add	a0,a0,a5
	bne	a3,zero,.L3
.L5:
	ret

	PR target/110751

gcc/ChangeLog:

	* config/riscv/autovec.md: Enable scratch rtx in ELSE operand.
	* config/riscv/predicates.md (autovec_else_operand): New predicate.
	* config/riscv/riscv-v.cc (get_else_operand): New function.
	(expand_cond_len_unop): Adapt ELSE value.
	(expand_cond_len_binop): Ditto.
	(expand_cond_len_ternop): Ditto.
	* config/riscv/riscv.cc (riscv_preferred_else_value): New function.
	(TARGET_PREFERRED_ELSE_VALUE): New targethook.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Adapt test.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/ternop/ternop_nofm-9.c: Ditto.