[arm] fix constraints on addsi3_carryin_alt2

addsi3_carryin_alt2 has a more strict constraint than the predicate
when adding a constant.  This leads to sub-optimal code in some
circumstances.

	* config/arm/arm.md (addsi3_carryin_alt2): Use arm_not_operand for
	operand 2.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277168 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index cb2abfe3dca5c2ea8baf8a69796b98531410effa..1c96b17631f1324f3846e92980aa7f20f09f3dbc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-10-18  Richard Earnshaw  <rearnsha@arm.com>
+
+       * config/arm/arm.md (addsi3_carryin_alt2): Use arm_not_operand for
+       operand 2.
+
 2019-10-18  Richard Earnshaw  <rearnsha@arm.com>
 
        * config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 9754a761fafbbf8ea1afd656375bb06401bb4b3b..fbe154a9873fb20cd60b04ffb71f861ea8e80736 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -893,7 +893,7 @@
   [(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
         (plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
                           (match_operand:SI 1 "s_register_operand" "%l,r,r"))
-                 (match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))]
+                 (match_operand:SI 2 "arm_not_operand" "l,rI,K")))]
   "TARGET_32BIT"
   "@
    adc%?\\t%0, %1, %2