[Arm] Add 16-bit thumb alternatives to iorsi3_compare0[_scratch]

The iorsi3_compare0 and iorsi3_compare0_scratch patterns can make use
of the 16-bit thumb orrs instruction if suitable registers are
allocated.  This patch adds the alternative to allow this to happen.

	* config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb
	insn.
	(iorsi3_compare0_scratch): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@274822 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 271786f27b3dd91ae843f3deaf9c41a87c23d366..93e8420ea93549588d7b6e8cb6fb090173456260 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-08-22  Richard Earnshaw  <rearnsha@arm.com>
+
+       * config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb
+       insn.
+       (iorsi3_compare0_scratch): Likewise.
+
 2019-08-22  Sylvia Taylor  <sylvia.taylor@arm.com>
 
        * config/aarch64/aarch64-simd-builtins.def:

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 50e1b908f59ccdf8b0d866d9f7b0f7f3050750ea..4ba246ceeee8ea991220c8527bceb101d0abdf42 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3339,27 +3339,33 @@
 
 (define_insn "*iorsi3_compare0"
   [(set (reg:CC_NOOV CC_REGNUM)
-       (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
-                                (match_operand:SI 2 "arm_rhs_operand" "I,r"))
-                        (const_int 0)))
-   (set (match_operand:SI 0 "s_register_operand" "=r,r")
+       (compare:CC_NOOV
+        (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
+                (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
+        (const_int 0)))
+   (set (match_operand:SI 0 "s_register_operand" "=r,l,r")
        (ior:SI (match_dup 1) (match_dup 2)))]
   "TARGET_32BIT"
   "orrs%?\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "logics_imm,logics_reg")]
+   (set_attr "arch" "*,t2,*")
+   (set_attr "length" "4,2,4")
+   (set_attr "type" "logics_imm,logics_reg,logics_reg")]
 )
 
 (define_insn "*iorsi3_compare0_scratch"
   [(set (reg:CC_NOOV CC_REGNUM)
-       (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r")
-                                (match_operand:SI 2 "arm_rhs_operand" "I,r"))
-                        (const_int 0)))
-   (clobber (match_scratch:SI 0 "=r,r"))]
+       (compare:CC_NOOV
+        (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r")
+                (match_operand:SI 2 "arm_rhs_operand" "I,l,r"))
+        (const_int 0)))
+   (clobber (match_scratch:SI 0 "=r,l,r"))]
   "TARGET_32BIT"
   "orrs%?\\t%0, %1, %2"
   [(set_attr "conds" "set")
-   (set_attr "type" "logics_imm,logics_reg")]
+   (set_attr "arch" "*,t2,*")
+   (set_attr "length" "4,2,4")
+   (set_attr "type" "logics_imm,logics_reg,logics_reg")]
 )
 
 (define_expand "xordi3"