From ad71cd89d327d5bf05d17bfa8f92cdaf71dbf751 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Thu, 13 Jul 2023 17:47:49 +0200 Subject: [PATCH] RA+sched: Change TRUE/FALSE to true/false gcc/ChangeLog: * haifa-sched.cc: Change TRUE/FALSE to true/false. * ira.cc: Ditto. * lra-assigns.cc: Ditto. * lra-constraints.cc: Ditto. * sel-sched.cc: Ditto. --- gcc/haifa-sched.cc | 4 ++-- gcc/ira.cc | 2 +- gcc/lra-assigns.cc | 2 +- gcc/lra-constraints.cc | 16 ++++++++-------- gcc/sel-sched.cc | 12 ++++++------ 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc index 01a2a80d9825..8e8add709b3a 100644 --- a/gcc/haifa-sched.cc +++ b/gcc/haifa-sched.cc @@ -6624,7 +6624,7 @@ schedule_block (basic_block *target_bb, state_t init_state) advance = 0; gcc_assert (scheduled_insns.length () == 0); - sort_p = TRUE; + sort_p = true; must_backtrack = false; modulo_insns_scheduled = 0; @@ -6844,7 +6844,7 @@ schedule_block (basic_block *target_bb, state_t init_state) break; } - sort_p = TRUE; + sort_p = true; if (current_sched_info->can_schedule_ready_p && ! (*current_sched_info->can_schedule_ready_p) (insn)) diff --git a/gcc/ira.cc b/gcc/ira.cc index a1860105c60b..4a6fb357ba03 100644 --- a/gcc/ira.cc +++ b/gcc/ira.cc @@ -5795,7 +5795,7 @@ ira (FILE *f) there is setjmp call because a variable not modified between setjmp and longjmp the compiler is required to preserve its value and sharing slots does not guarantee it. */ - flag_ira_share_spill_slots = FALSE; + flag_ira_share_spill_slots = false; ira_color (); diff --git a/gcc/lra-assigns.cc b/gcc/lra-assigns.cc index 3555926af669..b8582dcafff8 100644 --- a/gcc/lra-assigns.cc +++ b/gcc/lra-assigns.cc @@ -948,7 +948,7 @@ spill_for (int regno, bitmap spilled_pseudo_bitmap, bool first_p) } best_hard_regno = -1; best_cost = INT_MAX; - best_static_p = TRUE; + best_static_p = true; best_insn_pseudos_num = INT_MAX; smallest_bad_spills_num = INT_MAX; rclass_size = ira_class_hard_regs_num[rclass]; diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc index 0c6912d6e7db..76a155e99c24 100644 --- a/gcc/lra-constraints.cc +++ b/gcc/lra-constraints.cc @@ -1723,7 +1723,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode) = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); if (get_reload_reg (curr_static_id->operand[nop].type, innermode, reg, rclass, NULL, - TRUE, "slow/invalid mem", &new_reg)) + true, "slow/invalid mem", &new_reg)) { bool insert_before, insert_after; bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); @@ -1743,7 +1743,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode) = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, rclass, NULL, - TRUE, "slow/invalid mem", &new_reg)) + true, "slow/invalid mem", &new_reg)) { bool insert_before, insert_after; bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); @@ -1828,7 +1828,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode) if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, rclass, NULL, - TRUE, "subreg reg", &new_reg)) + true, "subreg reg", &new_reg)) { bool insert_before, insert_after; bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); @@ -1902,7 +1902,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode) if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, rclass, NULL, - TRUE, "paradoxical subreg", &new_reg)) + true, "paradoxical subreg", &new_reg)) { rtx subreg; bool insert_before, insert_after; @@ -4578,7 +4578,7 @@ curr_insn_transform (bool check_only_p) lra-lives.cc. */ match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &goal_alt_exclude_start_hard_regs[i], &before, - &after, TRUE); + &after, true); } continue; } @@ -4623,7 +4623,7 @@ curr_insn_transform (bool check_only_p) /* This value does not matter for MODIFY. */ GET_MODE_SIZE (GET_MODE (op))); else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, - NULL, FALSE, + NULL, false, "offsetable address", &new_reg)) { rtx addr = *loc; @@ -6188,7 +6188,7 @@ split_reg (bool before_p, int original_regno, rtx_insn *insn, { lra_assert (next_usage_insns == NULL); usage_insn = to; - after_p = TRUE; + after_p = true; } else { @@ -6299,7 +6299,7 @@ spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_i } if (insn != NEXT_INSN (to)) continue; - if (split_reg (TRUE, hard_regno, from, NULL, to)) + if (split_reg (true, hard_regno, from, NULL, to)) return true; } return false; diff --git a/gcc/sel-sched.cc b/gcc/sel-sched.cc index cb1cf75bfe47..1925f4a9461c 100644 --- a/gcc/sel-sched.cc +++ b/gcc/sel-sched.cc @@ -2023,7 +2023,7 @@ moving_insn_creates_bookkeeping_block_p (insn_t insn, { if (sched_verbose >= 9) sel_print ("no bookkeeping required: "); - return FALSE; + return false; } bbi = BLOCK_FOR_INSN (insn); @@ -2032,7 +2032,7 @@ moving_insn_creates_bookkeeping_block_p (insn_t insn, { if (sched_verbose >= 9) sel_print ("only one pred edge: "); - return TRUE; + return true; } bbt = BLOCK_FOR_INSN (through_insn); @@ -2041,11 +2041,11 @@ moving_insn_creates_bookkeeping_block_p (insn_t insn, { FOR_EACH_EDGE (e2, ei2, bbi->preds) { - if (find_block_for_bookkeeping (e1, e2, TRUE)) + if (find_block_for_bookkeeping (e1, e2, true)) { if (sched_verbose >= 9) sel_print ("found existing block: "); - return FALSE; + return false; } } } @@ -2053,7 +2053,7 @@ moving_insn_creates_bookkeeping_block_p (insn_t insn, if (sched_verbose >= 9) sel_print ("would create bookkeeping block: "); - return TRUE; + return true; } /* Return true when the conflict with newly created implicit clobbers @@ -4658,7 +4658,7 @@ find_place_for_bookkeeping (edge e1, edge e2, fence_t *fence_to_rewind) insn_t place_to_insert; /* Find a basic block that can hold bookkeeping. If it can be found, do not create new basic block, but insert bookkeeping there. */ - basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE); + basic_block book_block = find_block_for_bookkeeping (e1, e2, false); if (book_block) { -- 2.39.2