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dbus: Fix endianness bug in Frequency and Signal properties
authorSylvestre Gallon <ccna.syl@gmail.com>
Sat, 28 Jan 2012 15:57:48 +0000 (17:57 +0200)
committerJouni Malinen <j@w1.fi>
Sat, 28 Jan 2012 15:57:48 +0000 (17:57 +0200)
commit3d0a843823a05b159eeaa47b59f9e4ec66e74a8f
tree7cb354e6fe17016f132b7b54c82cc1d5af3c74b6tree | snapshot
parent6897ce14a41c30460c75fe06232f1bb91695c6aecommit | diff
dbus: Fix endianness bug in Frequency and Signal properties

These properties did not work on big endian PowerPC (always 100% for
Signal and 0 for Frequency) due to endianness problem (u32 to u16 data
loss).

Signed-off-by: Sylvestre Gallon <ccna.syl@gmail.com>
wpa_supplicant/dbus/dbus_new_handlers.c diff | blob | blame | history
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