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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
58d08319 JN |
2 | #ifndef __bif_core_defs_asm_h |
3 | #define __bif_core_defs_asm_h | |
4 | ||
5 | /* | |
6 | * This file is autogenerated from | |
7 | * file: ../../inst/bif/rtl/bif_core_regs.r | |
8 | * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp | |
9 | * last modfied: Mon Apr 11 16:06:33 2005 | |
10 | * | |
11 | * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r | |
12 | * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ | |
13 | * Any changes here will be lost. | |
14 | * | |
15 | * -*- buffer-read-only: t -*- | |
16 | */ | |
17 | ||
18 | #ifndef REG_FIELD | |
19 | #define REG_FIELD( scope, reg, field, value ) \ | |
20 | REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) | |
21 | #define REG_FIELD_X_( value, shift ) ((value) << shift) | |
22 | #endif | |
23 | ||
24 | #ifndef REG_STATE | |
25 | #define REG_STATE( scope, reg, field, symbolic_value ) \ | |
26 | REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) | |
27 | #define REG_STATE_X_( k, shift ) (k << shift) | |
28 | #endif | |
29 | ||
30 | #ifndef REG_MASK | |
31 | #define REG_MASK( scope, reg, field ) \ | |
32 | REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) | |
33 | #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) | |
34 | #endif | |
35 | ||
36 | #ifndef REG_LSB | |
37 | #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb | |
38 | #endif | |
39 | ||
40 | #ifndef REG_BIT | |
41 | #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit | |
42 | #endif | |
43 | ||
44 | #ifndef REG_ADDR | |
45 | #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) | |
46 | #define REG_ADDR_X_( inst, offs ) ((inst) + offs) | |
47 | #endif | |
48 | ||
49 | #ifndef REG_ADDR_VECT | |
50 | #define REG_ADDR_VECT( scope, inst, reg, index ) \ | |
51 | REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ | |
52 | STRIDE_##scope##_##reg ) | |
53 | #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ | |
54 | ((inst) + offs + (index) * stride) | |
55 | #endif | |
56 | ||
57 | /* Register rw_grp1_cfg, scope bif_core, type rw */ | |
58 | #define reg_bif_core_rw_grp1_cfg___lw___lsb 0 | |
59 | #define reg_bif_core_rw_grp1_cfg___lw___width 6 | |
60 | #define reg_bif_core_rw_grp1_cfg___ew___lsb 6 | |
61 | #define reg_bif_core_rw_grp1_cfg___ew___width 3 | |
62 | #define reg_bif_core_rw_grp1_cfg___zw___lsb 9 | |
63 | #define reg_bif_core_rw_grp1_cfg___zw___width 3 | |
64 | #define reg_bif_core_rw_grp1_cfg___aw___lsb 12 | |
65 | #define reg_bif_core_rw_grp1_cfg___aw___width 2 | |
66 | #define reg_bif_core_rw_grp1_cfg___dw___lsb 14 | |
67 | #define reg_bif_core_rw_grp1_cfg___dw___width 2 | |
68 | #define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 | |
69 | #define reg_bif_core_rw_grp1_cfg___ewb___width 2 | |
70 | #define reg_bif_core_rw_grp1_cfg___bw___lsb 18 | |
71 | #define reg_bif_core_rw_grp1_cfg___bw___width 1 | |
72 | #define reg_bif_core_rw_grp1_cfg___bw___bit 18 | |
73 | #define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 | |
74 | #define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 | |
75 | #define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 | |
76 | #define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 | |
77 | #define reg_bif_core_rw_grp1_cfg___erc_en___width 1 | |
78 | #define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 | |
79 | #define reg_bif_core_rw_grp1_cfg___mode___lsb 21 | |
80 | #define reg_bif_core_rw_grp1_cfg___mode___width 1 | |
81 | #define reg_bif_core_rw_grp1_cfg___mode___bit 21 | |
82 | #define reg_bif_core_rw_grp1_cfg_offset 0 | |
83 | ||
84 | /* Register rw_grp2_cfg, scope bif_core, type rw */ | |
85 | #define reg_bif_core_rw_grp2_cfg___lw___lsb 0 | |
86 | #define reg_bif_core_rw_grp2_cfg___lw___width 6 | |
87 | #define reg_bif_core_rw_grp2_cfg___ew___lsb 6 | |
88 | #define reg_bif_core_rw_grp2_cfg___ew___width 3 | |
89 | #define reg_bif_core_rw_grp2_cfg___zw___lsb 9 | |
90 | #define reg_bif_core_rw_grp2_cfg___zw___width 3 | |
91 | #define reg_bif_core_rw_grp2_cfg___aw___lsb 12 | |
92 | #define reg_bif_core_rw_grp2_cfg___aw___width 2 | |
93 | #define reg_bif_core_rw_grp2_cfg___dw___lsb 14 | |
94 | #define reg_bif_core_rw_grp2_cfg___dw___width 2 | |
95 | #define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 | |
96 | #define reg_bif_core_rw_grp2_cfg___ewb___width 2 | |
97 | #define reg_bif_core_rw_grp2_cfg___bw___lsb 18 | |
98 | #define reg_bif_core_rw_grp2_cfg___bw___width 1 | |
99 | #define reg_bif_core_rw_grp2_cfg___bw___bit 18 | |
100 | #define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 | |
101 | #define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 | |
102 | #define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 | |
103 | #define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 | |
104 | #define reg_bif_core_rw_grp2_cfg___erc_en___width 1 | |
105 | #define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 | |
106 | #define reg_bif_core_rw_grp2_cfg___mode___lsb 21 | |
107 | #define reg_bif_core_rw_grp2_cfg___mode___width 1 | |
108 | #define reg_bif_core_rw_grp2_cfg___mode___bit 21 | |
109 | #define reg_bif_core_rw_grp2_cfg_offset 4 | |
110 | ||
111 | /* Register rw_grp3_cfg, scope bif_core, type rw */ | |
112 | #define reg_bif_core_rw_grp3_cfg___lw___lsb 0 | |
113 | #define reg_bif_core_rw_grp3_cfg___lw___width 6 | |
114 | #define reg_bif_core_rw_grp3_cfg___ew___lsb 6 | |
115 | #define reg_bif_core_rw_grp3_cfg___ew___width 3 | |
116 | #define reg_bif_core_rw_grp3_cfg___zw___lsb 9 | |
117 | #define reg_bif_core_rw_grp3_cfg___zw___width 3 | |
118 | #define reg_bif_core_rw_grp3_cfg___aw___lsb 12 | |
119 | #define reg_bif_core_rw_grp3_cfg___aw___width 2 | |
120 | #define reg_bif_core_rw_grp3_cfg___dw___lsb 14 | |
121 | #define reg_bif_core_rw_grp3_cfg___dw___width 2 | |
122 | #define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 | |
123 | #define reg_bif_core_rw_grp3_cfg___ewb___width 2 | |
124 | #define reg_bif_core_rw_grp3_cfg___bw___lsb 18 | |
125 | #define reg_bif_core_rw_grp3_cfg___bw___width 1 | |
126 | #define reg_bif_core_rw_grp3_cfg___bw___bit 18 | |
127 | #define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 | |
128 | #define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 | |
129 | #define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 | |
130 | #define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 | |
131 | #define reg_bif_core_rw_grp3_cfg___erc_en___width 1 | |
132 | #define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 | |
133 | #define reg_bif_core_rw_grp3_cfg___mode___lsb 21 | |
134 | #define reg_bif_core_rw_grp3_cfg___mode___width 1 | |
135 | #define reg_bif_core_rw_grp3_cfg___mode___bit 21 | |
136 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 | |
137 | #define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 | |
138 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 | |
139 | #define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 | |
140 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 | |
141 | #define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 | |
142 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 | |
143 | #define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 | |
144 | #define reg_bif_core_rw_grp3_cfg_offset 8 | |
145 | ||
146 | /* Register rw_grp4_cfg, scope bif_core, type rw */ | |
147 | #define reg_bif_core_rw_grp4_cfg___lw___lsb 0 | |
148 | #define reg_bif_core_rw_grp4_cfg___lw___width 6 | |
149 | #define reg_bif_core_rw_grp4_cfg___ew___lsb 6 | |
150 | #define reg_bif_core_rw_grp4_cfg___ew___width 3 | |
151 | #define reg_bif_core_rw_grp4_cfg___zw___lsb 9 | |
152 | #define reg_bif_core_rw_grp4_cfg___zw___width 3 | |
153 | #define reg_bif_core_rw_grp4_cfg___aw___lsb 12 | |
154 | #define reg_bif_core_rw_grp4_cfg___aw___width 2 | |
155 | #define reg_bif_core_rw_grp4_cfg___dw___lsb 14 | |
156 | #define reg_bif_core_rw_grp4_cfg___dw___width 2 | |
157 | #define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 | |
158 | #define reg_bif_core_rw_grp4_cfg___ewb___width 2 | |
159 | #define reg_bif_core_rw_grp4_cfg___bw___lsb 18 | |
160 | #define reg_bif_core_rw_grp4_cfg___bw___width 1 | |
161 | #define reg_bif_core_rw_grp4_cfg___bw___bit 18 | |
162 | #define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 | |
163 | #define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 | |
164 | #define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 | |
165 | #define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 | |
166 | #define reg_bif_core_rw_grp4_cfg___erc_en___width 1 | |
167 | #define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 | |
168 | #define reg_bif_core_rw_grp4_cfg___mode___lsb 21 | |
169 | #define reg_bif_core_rw_grp4_cfg___mode___width 1 | |
170 | #define reg_bif_core_rw_grp4_cfg___mode___bit 21 | |
171 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 | |
172 | #define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 | |
173 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 | |
174 | #define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 | |
175 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 | |
176 | #define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 | |
177 | #define reg_bif_core_rw_grp4_cfg_offset 12 | |
178 | ||
179 | /* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ | |
180 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 | |
181 | #define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 | |
182 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 | |
183 | #define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 | |
184 | #define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 | |
185 | #define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 | |
186 | #define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 | |
187 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 | |
188 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 | |
189 | #define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 | |
190 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 | |
191 | #define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 | |
192 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 | |
193 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 | |
194 | #define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 | |
195 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 | |
196 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 | |
197 | #define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 | |
198 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 | |
199 | #define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 | |
200 | #define reg_bif_core_rw_sdram_cfg_grp0_offset 16 | |
201 | ||
202 | /* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ | |
203 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 | |
204 | #define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 | |
205 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 | |
206 | #define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 | |
207 | #define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 | |
208 | #define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 | |
209 | #define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 | |
210 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 | |
211 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 | |
212 | #define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 | |
213 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 | |
214 | #define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 | |
215 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 | |
216 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 | |
217 | #define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 | |
218 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 | |
219 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 | |
220 | #define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 | |
221 | #define reg_bif_core_rw_sdram_cfg_grp1_offset 20 | |
222 | ||
223 | /* Register rw_sdram_timing, scope bif_core, type rw */ | |
224 | #define reg_bif_core_rw_sdram_timing___cl___lsb 0 | |
225 | #define reg_bif_core_rw_sdram_timing___cl___width 3 | |
226 | #define reg_bif_core_rw_sdram_timing___rcd___lsb 3 | |
227 | #define reg_bif_core_rw_sdram_timing___rcd___width 3 | |
228 | #define reg_bif_core_rw_sdram_timing___rp___lsb 6 | |
229 | #define reg_bif_core_rw_sdram_timing___rp___width 3 | |
230 | #define reg_bif_core_rw_sdram_timing___rc___lsb 9 | |
231 | #define reg_bif_core_rw_sdram_timing___rc___width 2 | |
232 | #define reg_bif_core_rw_sdram_timing___dpl___lsb 11 | |
233 | #define reg_bif_core_rw_sdram_timing___dpl___width 2 | |
234 | #define reg_bif_core_rw_sdram_timing___pde___lsb 13 | |
235 | #define reg_bif_core_rw_sdram_timing___pde___width 1 | |
236 | #define reg_bif_core_rw_sdram_timing___pde___bit 13 | |
237 | #define reg_bif_core_rw_sdram_timing___ref___lsb 14 | |
238 | #define reg_bif_core_rw_sdram_timing___ref___width 2 | |
239 | #define reg_bif_core_rw_sdram_timing___cpd___lsb 16 | |
240 | #define reg_bif_core_rw_sdram_timing___cpd___width 1 | |
241 | #define reg_bif_core_rw_sdram_timing___cpd___bit 16 | |
242 | #define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 | |
243 | #define reg_bif_core_rw_sdram_timing___sdcke___width 1 | |
244 | #define reg_bif_core_rw_sdram_timing___sdcke___bit 17 | |
245 | #define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 | |
246 | #define reg_bif_core_rw_sdram_timing___sdclk___width 1 | |
247 | #define reg_bif_core_rw_sdram_timing___sdclk___bit 18 | |
248 | #define reg_bif_core_rw_sdram_timing_offset 24 | |
249 | ||
250 | /* Register rw_sdram_cmd, scope bif_core, type rw */ | |
251 | #define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 | |
252 | #define reg_bif_core_rw_sdram_cmd___cmd___width 3 | |
253 | #define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 | |
254 | #define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 | |
255 | #define reg_bif_core_rw_sdram_cmd_offset 28 | |
256 | ||
257 | /* Register rs_sdram_ref_stat, scope bif_core, type rs */ | |
258 | #define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 | |
259 | #define reg_bif_core_rs_sdram_ref_stat___ok___width 1 | |
260 | #define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 | |
261 | #define reg_bif_core_rs_sdram_ref_stat_offset 32 | |
262 | ||
263 | /* Register r_sdram_ref_stat, scope bif_core, type r */ | |
264 | #define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 | |
265 | #define reg_bif_core_r_sdram_ref_stat___ok___width 1 | |
266 | #define reg_bif_core_r_sdram_ref_stat___ok___bit 0 | |
267 | #define reg_bif_core_r_sdram_ref_stat_offset 36 | |
268 | ||
269 | ||
270 | /* Constants */ | |
271 | #define regk_bif_core_bank2 0x00000000 | |
272 | #define regk_bif_core_bank4 0x00000001 | |
273 | #define regk_bif_core_bit10 0x0000000a | |
274 | #define regk_bif_core_bit11 0x0000000b | |
275 | #define regk_bif_core_bit12 0x0000000c | |
276 | #define regk_bif_core_bit13 0x0000000d | |
277 | #define regk_bif_core_bit14 0x0000000e | |
278 | #define regk_bif_core_bit15 0x0000000f | |
279 | #define regk_bif_core_bit16 0x00000010 | |
280 | #define regk_bif_core_bit17 0x00000011 | |
281 | #define regk_bif_core_bit18 0x00000012 | |
282 | #define regk_bif_core_bit19 0x00000013 | |
283 | #define regk_bif_core_bit20 0x00000014 | |
284 | #define regk_bif_core_bit21 0x00000015 | |
285 | #define regk_bif_core_bit22 0x00000016 | |
286 | #define regk_bif_core_bit23 0x00000017 | |
287 | #define regk_bif_core_bit24 0x00000018 | |
288 | #define regk_bif_core_bit25 0x00000019 | |
289 | #define regk_bif_core_bit26 0x0000001a | |
290 | #define regk_bif_core_bit27 0x0000001b | |
291 | #define regk_bif_core_bit28 0x0000001c | |
292 | #define regk_bif_core_bit29 0x0000001d | |
293 | #define regk_bif_core_bit9 0x00000009 | |
294 | #define regk_bif_core_bw16 0x00000001 | |
295 | #define regk_bif_core_bw32 0x00000000 | |
296 | #define regk_bif_core_bwe 0x00000000 | |
297 | #define regk_bif_core_cwe 0x00000001 | |
298 | #define regk_bif_core_e15us 0x00000001 | |
299 | #define regk_bif_core_e7800ns 0x00000002 | |
300 | #define regk_bif_core_grp0 0x00000000 | |
301 | #define regk_bif_core_grp1 0x00000001 | |
302 | #define regk_bif_core_mrs 0x00000003 | |
303 | #define regk_bif_core_no 0x00000000 | |
304 | #define regk_bif_core_none 0x00000000 | |
305 | #define regk_bif_core_nop 0x00000000 | |
306 | #define regk_bif_core_off 0x00000000 | |
307 | #define regk_bif_core_pre 0x00000002 | |
308 | #define regk_bif_core_r_sdram_ref_stat_default 0x00000001 | |
309 | #define regk_bif_core_rd 0x00000002 | |
310 | #define regk_bif_core_ref 0x00000001 | |
311 | #define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 | |
312 | #define regk_bif_core_rw_grp1_cfg_default 0x000006cf | |
313 | #define regk_bif_core_rw_grp2_cfg_default 0x000006cf | |
314 | #define regk_bif_core_rw_grp3_cfg_default 0x000006cf | |
315 | #define regk_bif_core_rw_grp4_cfg_default 0x000006cf | |
316 | #define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 | |
317 | #define regk_bif_core_slf 0x00000004 | |
318 | #define regk_bif_core_wr 0x00000001 | |
319 | #define regk_bif_core_yes 0x00000001 | |
320 | #endif /* __bif_core_defs_asm_h */ |