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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1965aae3 PA |
2 | #ifndef _ASM_X86_PGTABLE_64_H |
3 | #define _ASM_X86_PGTABLE_64_H | |
1da177e4 | 4 | |
6df95fd7 | 5 | #include <linux/const.h> |
fb355149 JF |
6 | #include <asm/pgtable_64_types.h> |
7 | ||
9d291e78 VG |
8 | #ifndef __ASSEMBLY__ |
9 | ||
1da177e4 LT |
10 | /* |
11 | * This file contains the functions and defines necessary to modify and use | |
12 | * the x86-64 page table tree. | |
13 | */ | |
14 | #include <asm/processor.h> | |
1977f032 | 15 | #include <linux/bitops.h> |
1da177e4 | 16 | #include <linux/threads.h> |
1da177e4 | 17 | |
032370b9 KS |
18 | extern p4d_t level4_kernel_pgt[512]; |
19 | extern p4d_t level4_ident_pgt[512]; | |
1da177e4 | 20 | extern pud_t level3_kernel_pgt[512]; |
1da177e4 LT |
21 | extern pud_t level3_ident_pgt[512]; |
22 | extern pmd_t level2_kernel_pgt[512]; | |
084a2a4e JF |
23 | extern pmd_t level2_fixmap_pgt[512]; |
24 | extern pmd_t level2_ident_pgt[512]; | |
0b5a5063 | 25 | extern pte_t level1_fixmap_pgt[512]; |
65ade2f8 | 26 | extern pgd_t init_top_pgt[]; |
1da177e4 | 27 | |
65ade2f8 | 28 | #define swapper_pg_dir init_top_pgt |
1da177e4 | 29 | |
1da177e4 | 30 | extern void paging_init(void); |
1da177e4 | 31 | |
7f94401e | 32 | #define pte_ERROR(e) \ |
c767a54b | 33 | pr_err("%s:%d: bad pte %p(%016lx)\n", \ |
7f94401e JP |
34 | __FILE__, __LINE__, &(e), pte_val(e)) |
35 | #define pmd_ERROR(e) \ | |
c767a54b | 36 | pr_err("%s:%d: bad pmd %p(%016lx)\n", \ |
7f94401e JP |
37 | __FILE__, __LINE__, &(e), pmd_val(e)) |
38 | #define pud_ERROR(e) \ | |
c767a54b | 39 | pr_err("%s:%d: bad pud %p(%016lx)\n", \ |
7f94401e | 40 | __FILE__, __LINE__, &(e), pud_val(e)) |
b8504058 KS |
41 | |
42 | #if CONFIG_PGTABLE_LEVELS >= 5 | |
43 | #define p4d_ERROR(e) \ | |
44 | pr_err("%s:%d: bad p4d %p(%016lx)\n", \ | |
45 | __FILE__, __LINE__, &(e), p4d_val(e)) | |
46 | #endif | |
47 | ||
7f94401e | 48 | #define pgd_ERROR(e) \ |
c767a54b | 49 | pr_err("%s:%d: bad pgd %p(%016lx)\n", \ |
7f94401e | 50 | __FILE__, __LINE__, &(e), pgd_val(e)) |
1da177e4 | 51 | |
4891645e JF |
52 | struct mm_struct; |
53 | ||
f2a6a705 | 54 | void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte); |
0814e0ba EH |
55 | void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte); |
56 | ||
4891645e JF |
57 | static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, |
58 | pte_t *ptep) | |
1da177e4 | 59 | { |
4891645e JF |
60 | *ptep = native_make_pte(0); |
61 | } | |
1da177e4 | 62 | |
4891645e | 63 | static inline void native_set_pte(pte_t *ptep, pte_t pte) |
1da177e4 | 64 | { |
4891645e JF |
65 | *ptep = pte; |
66 | } | |
1da177e4 | 67 | |
b65e6390 IM |
68 | static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte) |
69 | { | |
70 | native_set_pte(ptep, pte); | |
71 | } | |
72 | ||
db3eb96f AA |
73 | static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) |
74 | { | |
75 | *pmdp = pmd; | |
76 | } | |
77 | ||
78 | static inline void native_pmd_clear(pmd_t *pmd) | |
79 | { | |
80 | native_set_pmd(pmd, native_make_pmd(0)); | |
81 | } | |
82 | ||
4891645e | 83 | static inline pte_t native_ptep_get_and_clear(pte_t *xp) |
1da177e4 | 84 | { |
4891645e JF |
85 | #ifdef CONFIG_SMP |
86 | return native_make_pte(xchg(&xp->pte, 0)); | |
87 | #else | |
7f94401e JP |
88 | /* native_local_ptep_get_and_clear, |
89 | but duplicated because of cyclic dependency */ | |
4891645e JF |
90 | pte_t ret = *xp; |
91 | native_pte_clear(NULL, 0, xp); | |
92 | return ret; | |
93 | #endif | |
1da177e4 LT |
94 | } |
95 | ||
db3eb96f | 96 | static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp) |
1da177e4 | 97 | { |
db3eb96f AA |
98 | #ifdef CONFIG_SMP |
99 | return native_make_pmd(xchg(&xp->pmd, 0)); | |
100 | #else | |
101 | /* native_local_pmdp_get_and_clear, | |
102 | but duplicated because of cyclic dependency */ | |
103 | pmd_t ret = *xp; | |
104 | native_pmd_clear(xp); | |
105 | return ret; | |
106 | #endif | |
4891645e | 107 | } |
1da177e4 | 108 | |
4891645e | 109 | static inline void native_set_pud(pud_t *pudp, pud_t pud) |
1da177e4 | 110 | { |
4891645e | 111 | *pudp = pud; |
1da177e4 LT |
112 | } |
113 | ||
4891645e JF |
114 | static inline void native_pud_clear(pud_t *pud) |
115 | { | |
116 | native_set_pud(pud, native_make_pud(0)); | |
117 | } | |
61e06037 | 118 | |
a00cc7d9 MW |
119 | static inline pud_t native_pudp_get_and_clear(pud_t *xp) |
120 | { | |
121 | #ifdef CONFIG_SMP | |
122 | return native_make_pud(xchg(&xp->pud, 0)); | |
123 | #else | |
124 | /* native_local_pudp_get_and_clear, | |
125 | * but duplicated because of cyclic dependency | |
126 | */ | |
127 | pud_t ret = *xp; | |
128 | ||
129 | native_pud_clear(xp); | |
130 | return ret; | |
131 | #endif | |
f2a6a705 KS |
132 | } |
133 | ||
134 | static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d) | |
135 | { | |
136 | *p4dp = p4d; | |
137 | } | |
138 | ||
139 | static inline void native_p4d_clear(p4d_t *p4d) | |
140 | { | |
b8504058 KS |
141 | #ifdef CONFIG_X86_5LEVEL |
142 | native_set_p4d(p4d, native_make_p4d(0)); | |
143 | #else | |
f2a6a705 | 144 | native_set_p4d(p4d, (p4d_t) { .pgd = native_make_pgd(0)}); |
b8504058 | 145 | #endif |
a00cc7d9 MW |
146 | } |
147 | ||
4891645e JF |
148 | static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd) |
149 | { | |
150 | *pgdp = pgd; | |
151 | } | |
8c65b4a6 | 152 | |
7f94401e | 153 | static inline void native_pgd_clear(pgd_t *pgd) |
61e06037 | 154 | { |
4891645e | 155 | native_set_pgd(pgd, native_make_pgd(0)); |
61e06037 ZA |
156 | } |
157 | ||
5372e155 | 158 | extern void sync_global_pgds(unsigned long start, unsigned long end); |
6afb5157 | 159 | |
1da177e4 LT |
160 | /* |
161 | * Conversion functions: convert a page and protection to a page entry, | |
162 | * and a page entry and page directory to the page they refer to. | |
163 | */ | |
164 | ||
1da177e4 LT |
165 | /* |
166 | * Level 4 access. | |
167 | */ | |
e00fc542 | 168 | static inline int pgd_large(pgd_t pgd) { return 0; } |
e7a9b0b3 | 169 | #define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE) |
1da177e4 LT |
170 | |
171 | /* PUD - Level3 access */ | |
1da177e4 | 172 | |
1da177e4 | 173 | /* PMD - Level 2 access */ |
1da177e4 LT |
174 | |
175 | /* PTE - Level 1 access. */ | |
176 | ||
1da177e4 | 177 | /* x86-64 always has all page tables mapped. */ |
7f94401e | 178 | #define pte_offset_map(dir, address) pte_offset_kernel((dir), (address)) |
4e60c86b | 179 | #define pte_unmap(pte) ((void)(pte))/* NOP */ |
1da177e4 | 180 | |
00839ee3 DH |
181 | /* |
182 | * Encode and de-code a swap entry | |
183 | * | |
eee4818b NH |
184 | * | ... | 11| 10| 9|8|7|6|5| 4| 3|2| 1|0| <- bit number |
185 | * | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U| W|P| <- bit names | |
186 | * | OFFSET (14->63) | TYPE (9-13) |0|0|X|X| X| X|X|SD|0| <- swp entry | |
00839ee3 DH |
187 | * |
188 | * G (8) is aliased and used as a PROT_NONE indicator for | |
189 | * !present ptes. We need to start storing swap entries above | |
190 | * there. We also need to avoid using A and D because of an | |
191 | * erratum where they can be incorrectly set by hardware on | |
192 | * non-present PTEs. | |
eee4818b NH |
193 | * |
194 | * SD (1) in swp entry is used to store soft dirty bit, which helps us | |
195 | * remember soft dirty over page migration | |
196 | * | |
197 | * Bit 7 in swp entry should be 0 because pmd_present checks not only P, | |
198 | * but also L and G. | |
00839ee3 DH |
199 | */ |
200 | #define SWP_TYPE_FIRST_BIT (_PAGE_BIT_PROTNONE + 1) | |
0a191362 | 201 | #define SWP_TYPE_BITS 5 |
00839ee3 | 202 | /* Place the offset above the type: */ |
ace7fab7 | 203 | #define SWP_OFFSET_FIRST_BIT (SWP_TYPE_FIRST_BIT + SWP_TYPE_BITS) |
1796316a JB |
204 | |
205 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) | |
206 | ||
00839ee3 | 207 | #define __swp_type(x) (((x).val >> (SWP_TYPE_FIRST_BIT)) \ |
1796316a | 208 | & ((1U << SWP_TYPE_BITS) - 1)) |
00839ee3 | 209 | #define __swp_offset(x) ((x).val >> SWP_OFFSET_FIRST_BIT) |
1796316a | 210 | #define __swp_entry(type, offset) ((swp_entry_t) { \ |
00839ee3 DH |
211 | ((type) << (SWP_TYPE_FIRST_BIT)) \ |
212 | | ((offset) << SWP_OFFSET_FIRST_BIT) }) | |
7f94401e | 213 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) }) |
616b8371 | 214 | #define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val((pmd)) }) |
c8e5393a | 215 | #define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val }) |
616b8371 | 216 | #define __swp_entry_to_pmd(x) ((pmd_t) { .pmd = (x).val }) |
1da177e4 | 217 | |
7f94401e | 218 | extern int kern_addr_valid(unsigned long addr); |
31eedd82 | 219 | extern void cleanup_highmap(void); |
1da177e4 | 220 | |
1da177e4 | 221 | #define HAVE_ARCH_UNMAPPED_AREA |
cc503c1b | 222 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN |
1da177e4 LT |
223 | |
224 | #define pgtable_cache_init() do { } while (0) | |
da8f153e | 225 | #define check_pgt_cache() do { } while (0) |
1da177e4 LT |
226 | |
227 | #define PAGE_AGP PAGE_KERNEL_NOCACHE | |
228 | #define HAVE_PAGE_AGP 1 | |
229 | ||
230 | /* fs/proc/kcore.c */ | |
231 | #define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK) | |
9063c61f | 232 | #define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK) |
1da177e4 | 233 | |
1da177e4 | 234 | #define __HAVE_ARCH_PTE_SAME |
5f6e8da7 | 235 | |
fb50b020 AD |
236 | #define vmemmap ((struct page *)VMEMMAP_START) |
237 | ||
238 | extern void init_extra_mapping_uc(unsigned long phys, unsigned long size); | |
239 | extern void init_extra_mapping_wb(unsigned long phys, unsigned long size); | |
240 | ||
e585513b KS |
241 | #define gup_fast_permitted gup_fast_permitted |
242 | static inline bool gup_fast_permitted(unsigned long start, int nr_pages, | |
243 | int write) | |
244 | { | |
245 | unsigned long len, end; | |
246 | ||
247 | len = (unsigned long)nr_pages << PAGE_SHIFT; | |
248 | end = start + len; | |
249 | if (end < start) | |
250 | return false; | |
251 | if (end >> __VIRTUAL_MASK_SHIFT) | |
252 | return false; | |
253 | return true; | |
254 | } | |
6dd29b3d | 255 | |
e585513b | 256 | #endif /* !__ASSEMBLY__ */ |
1965aae3 | 257 | #endif /* _ASM_X86_PGTABLE_64_H */ |