[thirdparty/kernel/linux.git] / include / linux / sh_intc.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __SH_INTC_H
#define __SH_INTC_H

#include <linux/ioport.h>

#ifdef CONFIG_SUPERH
#define INTC_NR_IRQS	512
#else
#define INTC_NR_IRQS	1024
#endif

/*
 * Convert back and forth between INTEVT and IRQ values.
 */
#ifdef CONFIG_CPU_HAS_INTEVT
#define evt2irq(evt)		(((evt) >> 5) - 16)
#define irq2evt(irq)		(((irq) + 16) << 5)
#else
#define evt2irq(evt)		(evt)
#define irq2evt(irq)		(irq)
#endif

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_group {
	intc_enum enum_id;
	intc_enum enum_ids[32];
};

#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }

struct intc_subgroup {
	unsigned long reg, reg_width;
	intc_enum parent_id;
	intc_enum enum_ids[32];
};

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
#ifdef CONFIG_INTC_BALANCING
	unsigned long dist_reg;
#endif
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_prio_reg {
	unsigned long set_reg, clr_reg, reg_width, field_width;
	intc_enum enum_ids[16];
#ifdef CONFIG_SMP
	unsigned long smp;
#endif
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

#ifdef CONFIG_INTC_BALANCING
#define INTC_SMP_BALANCING(reg)	.dist_reg = (reg)
#else
#define INTC_SMP_BALANCING(reg)
#endif

#ifdef CONFIG_SMP
#define INTC_SMP(stride, nr)	.smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif

struct intc_hw_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct intc_mask_reg *ack_regs;
	unsigned int nr_ack_regs;
	struct intc_subgroup *subgroups;
	unsigned int nr_subgroups;
};

#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)

#define INTC_HW_DESC(vectors, groups, mask_regs,	\
		     prio_regs,	sense_regs, ack_regs)	\
{							\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),	\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),	\
	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs),	\
}

struct intc_desc {
	char *name;
	struct resource *resource;
	unsigned int num_resources;
	intc_enum force_enable;
	intc_enum force_disable;
	bool skip_syscore_suspend;
	struct intc_hw_desc hw;
};

#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	mask_regs, prio_regs, sense_regs)				\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, NULL),		\
}

#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
	mask_regs, prio_regs, sense_regs, ack_regs)			\
struct intc_desc symbol __initdata = {					\
	.name = chipname,						\
	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
			   prio_regs, sense_regs, ack_regs),		\
}

int register_intc_controller(struct intc_desc *desc);
int intc_set_priority(unsigned int irq, unsigned int prio);
int intc_irq_lookup(const char *chipname, intc_enum enum_id);
void intc_finalize(void);

#ifdef CONFIG_INTC_USERIMASK
int register_intc_userimask(unsigned long addr);
#else
static inline int register_intc_userimask(unsigned long addr)
{
	return 0;
}
#endif

#endif /* __SH_INTC_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
bbfbd8b1 PM	2	#ifndef __SH_INTC_H
	3	#define __SH_INTC_H
	4
dec710b7 MD	5	#include <linux/ioport.h>
dec710b7 MD	6
0f552393 RH	7	#ifdef CONFIG_SUPERH
	8	#define INTC_NR_IRQS 512
	9	#else
	10	#define INTC_NR_IRQS 1024
	11	#endif
	12
7f1e7637 RH	13	/*
	14	* Convert back and forth between INTEVT and IRQ values.
	15	*/
	16	#ifdef CONFIG_CPU_HAS_INTEVT
	17	#define evt2irq(evt) (((evt) >> 5) - 16)
	18	#define irq2evt(irq) (((irq) + 16) << 5)
	19	#else
	20	#define evt2irq(evt) (evt)
	21	#define irq2evt(irq) (irq)
	22	#endif
	23
bbfbd8b1 PM	24	typedef unsigned char intc_enum;
	25
	26	struct intc_vect {
	27	intc_enum enum_id;
	28	unsigned short vect;
	29	};
	30
	31	#define INTC_VECT(enum_id, vect) { enum_id, vect }
	32	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
	33
	34	struct intc_group {
	35	intc_enum enum_id;
	36	intc_enum enum_ids[32];
	37	};
	38
	39	#define INTC_GROUP(enum_id, ids...) { enum_id, { ids } }
	40
c1e30ad9 PM	41	struct intc_subgroup {
	42	unsigned long reg, reg_width;
	43	intc_enum parent_id;
	44	intc_enum enum_ids[32];
	45	};
	46
bbfbd8b1 PM	47	struct intc_mask_reg {
	48	unsigned long set_reg, clr_reg, reg_width;
	49	intc_enum enum_ids[32];
dc825b17 PM	50	#ifdef CONFIG_INTC_BALANCING
	51	unsigned long dist_reg;
	52	#endif
bbfbd8b1 PM	53	#ifdef CONFIG_SMP
	54	unsigned long smp;
	55	#endif
	56	};
	57
	58	struct intc_prio_reg {
	59	unsigned long set_reg, clr_reg, reg_width, field_width;
	60	intc_enum enum_ids[16];
	61	#ifdef CONFIG_SMP
	62	unsigned long smp;
	63	#endif
	64	};
	65
	66	struct intc_sense_reg {
	67	unsigned long reg, reg_width, field_width;
	68	intc_enum enum_ids[16];
	69	};
	70
dc825b17 PM	71	#ifdef CONFIG_INTC_BALANCING
	72	#define INTC_SMP_BALANCING(reg) .dist_reg = (reg)
	73	#else
	74	#define INTC_SMP_BALANCING(reg)
	75	#endif
	76
bbfbd8b1	77	#ifdef CONFIG_SMP
dc825b17	78	#define INTC_SMP(stride, nr) .smp = (stride) \| ((nr) << 8)
bbfbd8b1 PM	79	#else
	80	#define INTC_SMP(stride, nr)
	81	#endif
	82
577cd758	83	struct intc_hw_desc {
bbfbd8b1 PM	84	struct intc_vect *vectors;
	85	unsigned int nr_vectors;
	86	struct intc_group *groups;
	87	unsigned int nr_groups;
	88	struct intc_mask_reg *mask_regs;
	89	unsigned int nr_mask_regs;
	90	struct intc_prio_reg *prio_regs;
	91	unsigned int nr_prio_regs;
	92	struct intc_sense_reg *sense_regs;
	93	unsigned int nr_sense_regs;
bbfbd8b1 PM	94	struct intc_mask_reg *ack_regs;
bbfbd8b1 PM	95	unsigned int nr_ack_regs;
c1e30ad9 PM	96	struct intc_subgroup *subgroups;
c1e30ad9 PM	97	unsigned int nr_subgroups;
bbfbd8b1 PM	98	};
bbfbd8b1 PM	99
99870bd7	100	#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a)
c1e30ad9	101
577cd758 MD	102	#define INTC_HW_DESC(vectors, groups, mask_regs, \
	103	prio_regs, sense_regs, ack_regs) \
	104	{ \
	105	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	106	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	107	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
	108	}
	109
	110	struct intc_desc {
	111	char *name;
dec710b7 MD	112	struct resource *resource;
dec710b7 MD	113	unsigned int num_resources;
d5190953	114	intc_enum force_enable;
d85429a3	115	intc_enum force_disable;
0f966d74	116	bool skip_syscore_suspend;
577cd758 MD	117	struct intc_hw_desc hw;
	118	};
	119
bbfbd8b1 PM	120	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	121	mask_regs, prio_regs, sense_regs) \
	122	struct intc_desc symbol __initdata = { \
577cd758 MD	123	.name = chipname, \
	124	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	125	prio_regs, sense_regs, NULL), \
bbfbd8b1 PM	126	}
bbfbd8b1 PM	127
bbfbd8b1 PM	128	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
	129	mask_regs, prio_regs, sense_regs, ack_regs) \
	130	struct intc_desc symbol __initdata = { \
577cd758 MD	131	.name = chipname, \
	132	.hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	133	prio_regs, sense_regs, ack_regs), \
bbfbd8b1	134	}
bbfbd8b1	135
2be6bb0c	136	int register_intc_controller(struct intc_desc *desc);
bbfbd8b1	137	int intc_set_priority(unsigned int irq, unsigned int prio);
d74310d3	138	int intc_irq_lookup(const char *chipname, intc_enum enum_id);
c1e30ad9	139	void intc_finalize(void);
bbfbd8b1	140
43b8774d PM	141	#ifdef CONFIG_INTC_USERIMASK
	142	int register_intc_userimask(unsigned long addr);
	143	#else
	144	static inline int register_intc_userimask(unsigned long addr)
	145	{
	146	return 0;
	147	}
	148	#endif
	149
bbfbd8b1	150	#endif /* __SH_INTC_H */