]>
Commit | Line | Data |
---|---|---|
2a2a4ae2 SL |
1 | From bd97afdeb176e8f5ba6d0fda4adc25819ab5120f Mon Sep 17 00:00:00 2001 |
2 | From: Tony Lindgren <tony@atomide.com> | |
3 | Date: Mon, 6 May 2019 14:08:54 -0700 | |
4 | Subject: clk: ti: clkctrl: Fix clkdm_clk handling | |
5 | ||
6 | [ Upstream commit 1cc54078d104f5b4d7e9f8d55362efa5a8daffdb ] | |
7 | ||
8 | We need to always call clkdm_clk_enable() and clkdm_clk_disable() even | |
9 | the clkctrl clock(s) enabled for the domain do not have any gate register | |
10 | bits. Otherwise clockdomains may never get enabled except when devices get | |
11 | probed with the legacy "ti,hwmods" devicetree property. | |
12 | ||
13 | Fixes: 88a172526c32 ("clk: ti: add support for clkctrl clocks") | |
14 | Signed-off-by: Tony Lindgren <tony@atomide.com> | |
15 | Signed-off-by: Stephen Boyd <sboyd@kernel.org> | |
16 | Signed-off-by: Sasha Levin <sashal@kernel.org> | |
17 | --- | |
18 | drivers/clk/ti/clkctrl.c | 8 ++++---- | |
19 | 1 file changed, 4 insertions(+), 4 deletions(-) | |
20 | ||
21 | diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c | |
22 | index 53e71d0503ec..82e4d5cccf84 100644 | |
23 | --- a/drivers/clk/ti/clkctrl.c | |
24 | +++ b/drivers/clk/ti/clkctrl.c | |
25 | @@ -124,9 +124,6 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) | |
26 | int ret; | |
27 | union omap4_timeout timeout = { 0 }; | |
28 | ||
29 | - if (!clk->enable_bit) | |
30 | - return 0; | |
31 | - | |
32 | if (clk->clkdm) { | |
33 | ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); | |
34 | if (ret) { | |
35 | @@ -138,6 +135,9 @@ static int _omap4_clkctrl_clk_enable(struct clk_hw *hw) | |
36 | } | |
37 | } | |
38 | ||
39 | + if (!clk->enable_bit) | |
40 | + return 0; | |
41 | + | |
42 | val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); | |
43 | ||
44 | val &= ~OMAP4_MODULEMODE_MASK; | |
45 | @@ -166,7 +166,7 @@ static void _omap4_clkctrl_clk_disable(struct clk_hw *hw) | |
46 | union omap4_timeout timeout = { 0 }; | |
47 | ||
48 | if (!clk->enable_bit) | |
49 | - return; | |
50 | + goto exit; | |
51 | ||
52 | val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); | |
53 | ||
54 | -- | |
55 | 2.20.1 | |
56 |