projects / thirdparty / kernel / stable-queue.git / blame
| Commit | Line | Data |
|---|---|---|
| d33cec38 GKH |
1 | From 6b2fde3dbfab6ebc45b0cd605e17ca5057ff9a3b Mon Sep 17 00:00:00 2001 |
| 2 | From: Jonas Karlman <jonas@kwiboo.se> | |
| 3 | Date: Sun, 24 Feb 2019 21:51:22 +0000 | |
| 4 | Subject: ARM: dts: rockchip: fix rk3288 cpu opp node reference | |
| 5 | ||
| 6 | From: Jonas Karlman <jonas@kwiboo.se> | |
| 7 | ||
| 8 | commit 6b2fde3dbfab6ebc45b0cd605e17ca5057ff9a3b upstream. | |
| 9 | ||
| 10 | The following error can be seen during boot: | |
| 11 | ||
| 12 | of: /cpus/cpu@501: Couldn't find opp node | |
| 13 | ||
| 14 | Change cpu nodes to use operating-points-v2 in order to fix this. | |
| 15 | ||
| 16 | Fixes: ce76de984649 ("ARM: dts: rockchip: convert rk3288 to operating-points-v2") | |
| 17 | Cc: stable@vger.kernel.org | |
| 18 | Signed-off-by: Jonas Karlman <jonas@kwiboo.se> | |
| 19 | Signed-off-by: Heiko Stuebner <heiko@sntech.de> | |
| 20 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | |
| 21 | ||
| 22 | --- | |
| 23 | arch/arm/boot/dts/rk3288.dtsi | 6 +++--- | |
| 24 | 1 file changed, 3 insertions(+), 3 deletions(-) | |
| 25 | ||
| 26 | --- a/arch/arm/boot/dts/rk3288.dtsi | |
| 27 | +++ b/arch/arm/boot/dts/rk3288.dtsi | |
| 28 | @@ -70,7 +70,7 @@ | |
| 29 | compatible = "arm,cortex-a12"; | |
| 30 | reg = <0x501>; | |
| 31 | resets = <&cru SRST_CORE1>; | |
| 32 | - operating-points = <&cpu_opp_table>; | |
| 33 | + operating-points-v2 = <&cpu_opp_table>; | |
| 34 | #cooling-cells = <2>; /* min followed by max */ | |
| 35 | clock-latency = <40000>; | |
| 36 | clocks = <&cru ARMCLK>; | |
| 37 | @@ -80,7 +80,7 @@ | |
| 38 | compatible = "arm,cortex-a12"; | |
| 39 | reg = <0x502>; | |
| 40 | resets = <&cru SRST_CORE2>; | |
| 41 | - operating-points = <&cpu_opp_table>; | |
| 42 | + operating-points-v2 = <&cpu_opp_table>; | |
| 43 | #cooling-cells = <2>; /* min followed by max */ | |
| 44 | clock-latency = <40000>; | |
| 45 | clocks = <&cru ARMCLK>; | |
| 46 | @@ -90,7 +90,7 @@ | |
| 47 | compatible = "arm,cortex-a12"; | |
| 48 | reg = <0x503>; | |
| 49 | resets = <&cru SRST_CORE3>; | |
| 50 | - operating-points = <&cpu_opp_table>; | |
| 51 | + operating-points-v2 = <&cpu_opp_table>; | |
| 52 | #cooling-cells = <2>; /* min followed by max */ | |
| 53 | clock-latency = <40000>; | |
| 54 | clocks = <&cru ARMCLK>; |