]> git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blame - releases/4.19.51/arm-dts-imx6ul-specify-imx6ul_clk_ipg-as-ipg-clock-t.patch
Linux 4.19.51
[thirdparty/kernel/stable-queue.git] / releases / 4.19.51 / arm-dts-imx6ul-specify-imx6ul_clk_ipg-as-ipg-clock-t.patch
CommitLineData
37554d48
SL
1From 8988b21df8124166a7907a234a895b3c3d610289 Mon Sep 17 00:00:00 2001
2From: Andrey Smirnov <andrew.smirnov@gmail.com>
3Date: Thu, 28 Mar 2019 23:49:19 -0700
4Subject: ARM: dts: imx6ul: Specify IMX6UL_CLK_IPG as "ipg" clock to SDMA
5
6[ Upstream commit 7b3132ecefdd1fcdf6b86e62021d0e55ea8034db ]
7
8Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb"
9clock to determine if it needs to configure the IP block as operating
10at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both
11clocks as IMX6UL_CLK_SDMA results in driver incorrectly thinking that
12ratio is 1:1 which results in broken SDMA funtionality. Fix the code
13to specify IMX6UL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting
14incorrect clock ratio.
15
16Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
17Cc: Angus Ainslie (Purism) <angus@akkea.ca>
18Cc: Chris Healy <cphealy@gmail.com>
19Cc: Lucas Stach <l.stach@pengutronix.de>
20Cc: Fabio Estevam <fabio.estevam@nxp.com>
21Cc: Shawn Guo <shawnguo@kernel.org>
22Cc: linux-arm-kernel@lists.infradead.org
23Cc: linux-kernel@vger.kernel.org
24Signed-off-by: Shawn Guo <shawnguo@kernel.org>
25Signed-off-by: Sasha Levin <sashal@kernel.org>
26---
27 arch/arm/boot/dts/imx6ul.dtsi | 2 +-
28 1 file changed, 1 insertion(+), 1 deletion(-)
29
30diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
31index 6dc0b569acdf..2366f093cc76 100644
32--- a/arch/arm/boot/dts/imx6ul.dtsi
33+++ b/arch/arm/boot/dts/imx6ul.dtsi
34@@ -707,7 +707,7 @@
35 "fsl,imx35-sdma";
36 reg = <0x020ec000 0x4000>;
37 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
38- clocks = <&clks IMX6UL_CLK_SDMA>,
39+ clocks = <&clks IMX6UL_CLK_IPG>,
40 <&clks IMX6UL_CLK_SDMA>;
41 clock-names = "ipg", "ahb";
42 #dma-cells = <3>;
43--
442.20.1
45