[thirdparty/kernel/stable.git] / arch / arm64 / include / uapi / asm / kvm.h

/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/uapi/asm/kvm.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM_KVM_H__
#define __ARM_KVM_H__

#define KVM_SPSR_EL1	0
#define KVM_SPSR_SVC	KVM_SPSR_EL1
#define KVM_SPSR_ABT	1
#define KVM_SPSR_UND	2
#define KVM_SPSR_IRQ	3
#define KVM_SPSR_FIQ	4
#define KVM_NR_SPSR	5

#ifndef __ASSEMBLY__
#include <linux/psci.h>
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/sve_context.h>

#define __KVM_HAVE_GUEST_DEBUG
#define __KVM_HAVE_IRQ_LINE
#define __KVM_HAVE_READONLY_MEM
#define __KVM_HAVE_VCPU_EVENTS

#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
#define KVM_DIRTY_LOG_PAGE_OFFSET 64

#define KVM_REG_SIZE(id)						\
	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))

struct kvm_regs {
	struct user_pt_regs regs;	/* sp = sp_el0 */

	__u64	sp_el1;
	__u64	elr_el1;

	__u64	spsr[KVM_NR_SPSR];

	struct user_fpsimd_state fp_regs;
};

/*
 * Supported CPU Targets - Adding a new target type is not recommended,
 * unless there are some special registers not supported by the
 * genericv8 syreg table.
 */
#define KVM_ARM_TARGET_AEM_V8		0
#define KVM_ARM_TARGET_FOUNDATION_V8	1
#define KVM_ARM_TARGET_CORTEX_A57	2
#define KVM_ARM_TARGET_XGENE_POTENZA	3
#define KVM_ARM_TARGET_CORTEX_A53	4
/* Generic ARM v8 target */
#define KVM_ARM_TARGET_GENERIC_V8	5

#define KVM_ARM_NUM_TARGETS		6

/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
#define KVM_ARM_DEVICE_TYPE_SHIFT	0
#define KVM_ARM_DEVICE_TYPE_MASK	__GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
						  KVM_ARM_DEVICE_TYPE_SHIFT)
#define KVM_ARM_DEVICE_ID_SHIFT		16
#define KVM_ARM_DEVICE_ID_MASK		__GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
						  KVM_ARM_DEVICE_ID_SHIFT)

/* Supported device IDs */
#define KVM_ARM_DEVICE_VGIC_V2		0

/* Supported VGIC address types  */
#define KVM_VGIC_V2_ADDR_TYPE_DIST	0
#define KVM_VGIC_V2_ADDR_TYPE_CPU	1

#define KVM_VGIC_V2_DIST_SIZE		0x1000
#define KVM_VGIC_V2_CPU_SIZE		0x2000

/* Supported VGICv3 address types  */
#define KVM_VGIC_V3_ADDR_TYPE_DIST	2
#define KVM_VGIC_V3_ADDR_TYPE_REDIST	3
#define KVM_VGIC_ITS_ADDR_TYPE		4
#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION	5

#define KVM_VGIC_V3_DIST_SIZE		SZ_64K
#define KVM_VGIC_V3_REDIST_SIZE		(2 * SZ_64K)
#define KVM_VGIC_V3_ITS_SIZE		(2 * SZ_64K)

#define KVM_ARM_VCPU_POWER_OFF		0 /* CPU is started in OFF state */
#define KVM_ARM_VCPU_EL1_32BIT		1 /* CPU running a 32bit VM */
#define KVM_ARM_VCPU_PSCI_0_2		2 /* CPU uses PSCI v0.2 */
#define KVM_ARM_VCPU_PMU_V3		3 /* Support guest PMUv3 */
#define KVM_ARM_VCPU_SVE		4 /* enable SVE for this CPU */
#define KVM_ARM_VCPU_PTRAUTH_ADDRESS	5 /* VCPU uses address authentication */
#define KVM_ARM_VCPU_PTRAUTH_GENERIC	6 /* VCPU uses generic authentication */
#define KVM_ARM_VCPU_HAS_EL2		7 /* Support nested virtualization */

struct kvm_vcpu_init {
	__u32 target;
	__u32 features[7];
};

struct kvm_sregs {
};

struct kvm_fpu {
};

/*
 * See v8 ARM ARM D7.3: Debug Registers
 *
 * The architectural limit is 16 debug registers of each type although
 * in practice there are usually less (see ID_AA64DFR0_EL1).
 *
 * Although the control registers are architecturally defined as 32
 * bits wide we use a 64 bit structure here to keep parity with
 * KVM_GET/SET_ONE_REG behaviour which treats all system registers as
 * 64 bit values. It also allows for the possibility of the
 * architecture expanding the control registers without having to
 * change the userspace ABI.
 */
#define KVM_ARM_MAX_DBG_REGS 16
struct kvm_guest_debug_arch {
	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
};

#define KVM_DEBUG_ARCH_HSR_HIGH_VALID	(1 << 0)
struct kvm_debug_exit_arch {
	__u32 hsr;
	__u32 hsr_high;	/* ESR_EL2[61:32] */
	__u64 far;	/* used for watchpoints */
};

/*
 * Architecture specific defines for kvm_guest_debug->control
 */

#define KVM_GUESTDBG_USE_SW_BP		(1 << 16)
#define KVM_GUESTDBG_USE_HW		(1 << 17)

struct kvm_sync_regs {
	/* Used with KVM_CAP_ARM_USER_IRQ */
	__u64 device_irq_level;
};

/* Bits for run->s.regs.device_irq_level */
#define KVM_ARM_DEV_EL1_VTIMER		(1 << 0)
#define KVM_ARM_DEV_EL1_PTIMER		(1 << 1)
#define KVM_ARM_DEV_PMU			(1 << 2)

/*
 * PMU filter structure. Describe a range of events with a particular
 * action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
 */
struct kvm_pmu_event_filter {
	__u16	base_event;
	__u16	nevents;

#define KVM_PMU_EVENT_ALLOW	0
#define KVM_PMU_EVENT_DENY	1

	__u8	action;
	__u8	pad[3];
};

/* for KVM_GET/SET_VCPU_EVENTS */
struct kvm_vcpu_events {
	struct {
		__u8 serror_pending;
		__u8 serror_has_esr;
		__u8 ext_dabt_pending;
		/* Align it to 8 bytes */
		__u8 pad[5];
		__u64 serror_esr;
	} exception;
	__u32 reserved[12];
};

struct kvm_arm_copy_mte_tags {
	__u64 guest_ipa;
	__u64 length;
	void __user *addr;
	__u64 flags;
	__u64 reserved[2];
};

/*
 * Counter/Timer offset structure. Describe the virtual/physical offset.
 * To be used with KVM_ARM_SET_COUNTER_OFFSET.
 */
struct kvm_arm_counter_offset {
	__u64 counter_offset;
	__u64 reserved;
};

#define KVM_ARM_TAGS_TO_GUEST		0
#define KVM_ARM_TAGS_FROM_GUEST		1

/* If you need to interpret the index values, here is the key: */
#define KVM_REG_ARM_COPROC_MASK		0x000000000FFF0000
#define KVM_REG_ARM_COPROC_SHIFT	16

/* Normal registers are mapped as coprocessor 16. */
#define KVM_REG_ARM_CORE		(0x0010 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_CORE_REG(name)	(offsetof(struct kvm_regs, name) / sizeof(__u32))

/* Some registers need more space to represent values. */
#define KVM_REG_ARM_DEMUX		(0x0011 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_DEMUX_ID_MASK	0x000000000000FF00
#define KVM_REG_ARM_DEMUX_ID_SHIFT	8
#define KVM_REG_ARM_DEMUX_ID_CCSIDR	(0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
#define KVM_REG_ARM_DEMUX_VAL_MASK	0x00000000000000FF
#define KVM_REG_ARM_DEMUX_VAL_SHIFT	0

/* AArch64 system registers */
#define KVM_REG_ARM64_SYSREG		(0x0013 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM64_SYSREG_OP0_MASK	0x000000000000c000
#define KVM_REG_ARM64_SYSREG_OP0_SHIFT	14
#define KVM_REG_ARM64_SYSREG_OP1_MASK	0x0000000000003800
#define KVM_REG_ARM64_SYSREG_OP1_SHIFT	11
#define KVM_REG_ARM64_SYSREG_CRN_MASK	0x0000000000000780
#define KVM_REG_ARM64_SYSREG_CRN_SHIFT	7
#define KVM_REG_ARM64_SYSREG_CRM_MASK	0x0000000000000078
#define KVM_REG_ARM64_SYSREG_CRM_SHIFT	3
#define KVM_REG_ARM64_SYSREG_OP2_MASK	0x0000000000000007
#define KVM_REG_ARM64_SYSREG_OP2_SHIFT	0

#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)

#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
	(KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | \
	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | \
	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | \
	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))

#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) | KVM_REG_SIZE_U64)

/* Physical Timer EL0 Registers */
#define KVM_REG_ARM_PTIMER_CTL		ARM64_SYS_REG(3, 3, 14, 2, 1)
#define KVM_REG_ARM_PTIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 2, 2)
#define KVM_REG_ARM_PTIMER_CNT		ARM64_SYS_REG(3, 3, 14, 0, 1)

/*
 * EL0 Virtual Timer Registers
 *
 * WARNING:
 *      KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
 *      with the appropriate register encodings.  Their values have been
 *      accidentally swapped.  As this is set API, the definitions here
 *      must be used, rather than ones derived from the encodings.
 */
#define KVM_REG_ARM_TIMER_CTL		ARM64_SYS_REG(3, 3, 14, 3, 1)
#define KVM_REG_ARM_TIMER_CVAL		ARM64_SYS_REG(3, 3, 14, 0, 2)
#define KVM_REG_ARM_TIMER_CNT		ARM64_SYS_REG(3, 3, 14, 3, 2)

/* KVM-as-firmware specific pseudo-registers */
#define KVM_REG_ARM_FW			(0x0014 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_FW_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
					 KVM_REG_ARM_FW | ((r) & 0xffff))
#define KVM_REG_ARM_PSCI_VERSION	KVM_REG_ARM_FW_REG(0)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1	KVM_REG_ARM_FW_REG(1)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL		0
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL		1
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED	2

/*
 * Only two states can be presented by the host kernel:
 * - NOT_REQUIRED: the guest doesn't need to do anything
 * - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
 *
 * All the other values are deprecated. The host still accepts all
 * values (they are ABI), but will narrow them to the above two.
 */
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2	KVM_REG_ARM_FW_REG(2)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL		0
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN		1
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL		2
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED	3
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED     	(1U << 4)

#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3	KVM_REG_ARM_FW_REG(3)
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL		0
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL		1
#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED	2

/* SVE registers */
#define KVM_REG_ARM64_SVE		(0x15 << KVM_REG_ARM_COPROC_SHIFT)

/* Z- and P-regs occupy blocks at the following offsets within this range: */
#define KVM_REG_ARM64_SVE_ZREG_BASE	0
#define KVM_REG_ARM64_SVE_PREG_BASE	0x400
#define KVM_REG_ARM64_SVE_FFR_BASE	0x600

#define KVM_ARM64_SVE_NUM_ZREGS		__SVE_NUM_ZREGS
#define KVM_ARM64_SVE_NUM_PREGS		__SVE_NUM_PREGS

#define KVM_ARM64_SVE_MAX_SLICES	32

#define KVM_REG_ARM64_SVE_ZREG(n, i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_ZREG_BASE | \
	 KVM_REG_SIZE_U2048 |						\
	 (((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) |			\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

#define KVM_REG_ARM64_SVE_PREG(n, i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_PREG_BASE | \
	 KVM_REG_SIZE_U256 |						\
	 (((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) |			\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

#define KVM_REG_ARM64_SVE_FFR(i)					\
	(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | KVM_REG_ARM64_SVE_FFR_BASE | \
	 KVM_REG_SIZE_U256 |						\
	 ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))

/*
 * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
 * KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
 * invariant layout which differs from the layout used for the FPSIMD
 * V-registers on big-endian systems: see sigcontext.h for more explanation.
 */

#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX

/* Vector lengths pseudo-register: */
#define KVM_REG_ARM64_SVE_VLS		(KVM_REG_ARM64 | KVM_REG_ARM64_SVE | \
					 KVM_REG_SIZE_U512 | 0xffff)
#define KVM_ARM64_SVE_VLS_WORDS	\
	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)

/* Bitmap feature firmware registers */
#define KVM_REG_ARM_FW_FEAT_BMAP		(0x0016 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r)		(KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
						KVM_REG_ARM_FW_FEAT_BMAP |	\
						((r) & 0xffff))

#define KVM_REG_ARM_STD_BMAP			KVM_REG_ARM_FW_FEAT_BMAP_REG(0)

enum {
	KVM_REG_ARM_STD_BIT_TRNG_V1_0	= 0,
#ifdef __KERNEL__
	KVM_REG_ARM_STD_BMAP_BIT_COUNT,
#endif
};

#define KVM_REG_ARM_STD_HYP_BMAP		KVM_REG_ARM_FW_FEAT_BMAP_REG(1)

enum {
	KVM_REG_ARM_STD_HYP_BIT_PV_TIME	= 0,
#ifdef __KERNEL__
	KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT,
#endif
};

#define KVM_REG_ARM_VENDOR_HYP_BMAP		KVM_REG_ARM_FW_FEAT_BMAP_REG(2)

enum {
	KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT	= 0,
	KVM_REG_ARM_VENDOR_HYP_BIT_PTP		= 1,
#ifdef __KERNEL__
	KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
#endif
};

/* Device Control API on vm fd */
#define KVM_ARM_VM_SMCCC_CTRL		0
#define   KVM_ARM_VM_SMCCC_FILTER	0

/* Device Control API: ARM VGIC */
#define KVM_DEV_ARM_VGIC_GRP_ADDR	0
#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS	1
#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS	2
#define   KVM_DEV_ARM_VGIC_CPUID_SHIFT	32
#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
#define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
#define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
			(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0
#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
#define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3
#define KVM_DEV_ARM_VGIC_GRP_CTRL	4
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7
#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT	10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
			(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK	0x3ff
#define VGIC_LEVEL_INFO_LINE_LEVEL	0

#define   KVM_DEV_ARM_VGIC_CTRL_INIT		0
#define   KVM_DEV_ARM_ITS_SAVE_TABLES           1
#define   KVM_DEV_ARM_ITS_RESTORE_TABLES        2
#define   KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES	3
#define   KVM_DEV_ARM_ITS_CTRL_RESET		4

/* Device Control API on vcpu fd */
#define KVM_ARM_VCPU_PMU_V3_CTRL	0
#define   KVM_ARM_VCPU_PMU_V3_IRQ	0
#define   KVM_ARM_VCPU_PMU_V3_INIT	1
#define   KVM_ARM_VCPU_PMU_V3_FILTER	2
#define   KVM_ARM_VCPU_PMU_V3_SET_PMU	3
#define KVM_ARM_VCPU_TIMER_CTRL		1
#define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER		0
#define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER		1
#define   KVM_ARM_VCPU_TIMER_IRQ_HVTIMER	2
#define   KVM_ARM_VCPU_TIMER_IRQ_HPTIMER	3
#define KVM_ARM_VCPU_PVTIME_CTRL	2
#define   KVM_ARM_VCPU_PVTIME_IPA	0

/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_VCPU2_SHIFT		28
#define KVM_ARM_IRQ_VCPU2_MASK		0xf
#define KVM_ARM_IRQ_TYPE_SHIFT		24
#define KVM_ARM_IRQ_TYPE_MASK		0xf
#define KVM_ARM_IRQ_VCPU_SHIFT		16
#define KVM_ARM_IRQ_VCPU_MASK		0xff
#define KVM_ARM_IRQ_NUM_SHIFT		0
#define KVM_ARM_IRQ_NUM_MASK		0xffff

/* irq_type field */
#define KVM_ARM_IRQ_TYPE_CPU		0
#define KVM_ARM_IRQ_TYPE_SPI		1
#define KVM_ARM_IRQ_TYPE_PPI		2

/* out-of-kernel GIC cpu interrupt injection irq_number field */
#define KVM_ARM_IRQ_CPU_IRQ		0
#define KVM_ARM_IRQ_CPU_FIQ		1

/*
 * This used to hold the highest supported SPI, but it is now obsolete
 * and only here to provide source code level compatibility with older
 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
 */
#ifndef __KERNEL__
#define KVM_ARM_IRQ_GIC_MAX		127
#endif

/* One single KVM irqchip, ie. the VGIC */
#define KVM_NR_IRQCHIPS          1

/* PSCI interface */
#define KVM_PSCI_FN_BASE		0x95c1ba5e
#define KVM_PSCI_FN(n)			(KVM_PSCI_FN_BASE + (n))

#define KVM_PSCI_FN_CPU_SUSPEND		KVM_PSCI_FN(0)
#define KVM_PSCI_FN_CPU_OFF		KVM_PSCI_FN(1)
#define KVM_PSCI_FN_CPU_ON		KVM_PSCI_FN(2)
#define KVM_PSCI_FN_MIGRATE		KVM_PSCI_FN(3)

#define KVM_PSCI_RET_SUCCESS		PSCI_RET_SUCCESS
#define KVM_PSCI_RET_NI			PSCI_RET_NOT_SUPPORTED
#define KVM_PSCI_RET_INVAL		PSCI_RET_INVALID_PARAMS
#define KVM_PSCI_RET_DENIED		PSCI_RET_DENIED

/* arm64-specific kvm_run::system_event flags */
/*
 * Reset caused by a PSCI v1.1 SYSTEM_RESET2 call.
 * Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET.
 */
#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2	(1ULL << 0)

/* run->fail_entry.hardware_entry_failure_reason codes. */
#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED	(1ULL << 0)

enum kvm_smccc_filter_action {
	KVM_SMCCC_FILTER_HANDLE = 0,
	KVM_SMCCC_FILTER_DENY,
	KVM_SMCCC_FILTER_FWD_TO_USER,

#ifdef __KERNEL__
	NR_SMCCC_FILTER_ACTIONS
#endif
};

struct kvm_smccc_filter {
	__u32 base;
	__u32 nr_functions;
	__u8 action;
	__u8 pad[15];
};

/* arm64-specific KVM_EXIT_HYPERCALL flags */
#define KVM_HYPERCALL_EXIT_SMC		(1U << 0)
#define KVM_HYPERCALL_EXIT_16BIT	(1U << 1)

/*
 * Get feature ID registers userspace writable mask.
 *
 * From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model
 * Feature Register 2"):
 *
 * "The Feature ID space is defined as the System register space in
 * AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7},
 * op2=={0-7}."
 *
 * This covers all currently known R/O registers that indicate
 * anything useful feature wise, including the ID registers.
 *
 * If we ever need to introduce a new range, it will be described as
 * such in the range field.
 */
#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2)		\
	({								\
		__u64 __op1 = (op1) & 3;				\
		__op1 -= (__op1 == 3);					\
		(__op1 << 6 | ((crm) & 7) << 3 | (op2));		\
	})

#define KVM_ARM_FEATURE_ID_RANGE	0
#define KVM_ARM_FEATURE_ID_RANGE_SIZE	(3 * 8 * 8)

struct reg_mask_range {
	__u64 addr;		/* Pointer to mask array */
	__u32 range;		/* Requested range */
	__u32 reserved[13];
};

#endif

#endif /* __ARM_KVM_H__ */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
54f81d0e MZ	2	/*
	3	* Copyright (C) 2012,2013 - ARM Ltd
	4	* Author: Marc Zyngier <marc.zyngier@arm.com>
	5	*
	6	* Derived from arch/arm/include/uapi/asm/kvm.h:
	7	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	8	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#ifndef __ARM_KVM_H__
	24	#define __ARM_KVM_H__
	25
	26	#define KVM_SPSR_EL1 0
40033a61 MZ	27	#define KVM_SPSR_SVC KVM_SPSR_EL1
	28	#define KVM_SPSR_ABT 1
	29	#define KVM_SPSR_UND 2
	30	#define KVM_SPSR_IRQ 3
	31	#define KVM_SPSR_FIQ 4
	32	#define KVM_NR_SPSR 5
54f81d0e MZ	33
54f81d0e MZ	34	#ifndef __ASSEMBLY__
7d0f84aa	35	#include <linux/psci.h>
d1927915	36	#include <linux/types.h>
54f81d0e	37	#include <asm/ptrace.h>
8ae6efdd	38	#include <asm/sve_context.h>
54f81d0e MZ	39
	40	#define __KVM_HAVE_GUEST_DEBUG
	41	#define __KVM_HAVE_IRQ_LINE
98047888	42	#define __KVM_HAVE_READONLY_MEM
b7b27fac	43	#define __KVM_HAVE_VCPU_EVENTS
54f81d0e	44
4b4357e0	45	#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
9cb1096f	46	#define KVM_DIRTY_LOG_PAGE_OFFSET 64
4b4357e0	47
54f81d0e MZ	48	#define KVM_REG_SIZE(id) \
	49	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
	50
	51	struct kvm_regs {
	52	struct user_pt_regs regs; /* sp = sp_el0 */
	53
	54	__u64 sp_el1;
	55	__u64 elr_el1;
	56
	57	__u64 spsr[KVM_NR_SPSR];
	58
	59	struct user_fpsimd_state fp_regs;
	60	};
	61
bca556ac SP	62	/*
	63	* Supported CPU Targets - Adding a new target type is not recommended,
	64	* unless there are some special registers not supported by the
	65	* genericv8 syreg table.
	66	*/
54f81d0e MZ	67	#define KVM_ARM_TARGET_AEM_V8 0
	68	#define KVM_ARM_TARGET_FOUNDATION_V8 1
	69	#define KVM_ARM_TARGET_CORTEX_A57 2
e28100bd	70	#define KVM_ARM_TARGET_XGENE_POTENZA 3
1252b331	71	#define KVM_ARM_TARGET_CORTEX_A53 4
bca556ac SP	72	/* Generic ARM v8 target */
bca556ac SP	73	#define KVM_ARM_TARGET_GENERIC_V8 5
54f81d0e	74
bca556ac	75	#define KVM_ARM_NUM_TARGETS 6
54f81d0e MZ	76
	77	/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
	78	#define KVM_ARM_DEVICE_TYPE_SHIFT 0
45882241 PB	79	#define KVM_ARM_DEVICE_TYPE_MASK __GENMASK(KVM_ARM_DEVICE_TYPE_SHIFT + 15, \
45882241 PB	80	KVM_ARM_DEVICE_TYPE_SHIFT)
54f81d0e	81	#define KVM_ARM_DEVICE_ID_SHIFT 16
45882241 PB	82	#define KVM_ARM_DEVICE_ID_MASK __GENMASK(KVM_ARM_DEVICE_ID_SHIFT + 15, \
45882241 PB	83	KVM_ARM_DEVICE_ID_SHIFT)
54f81d0e MZ	84
	85	/* Supported device IDs */
	86	#define KVM_ARM_DEVICE_VGIC_V2 0
	87
	88	/* Supported VGIC address types */
	89	#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
	90	#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
	91
	92	#define KVM_VGIC_V2_DIST_SIZE 0x1000
	93	#define KVM_VGIC_V2_CPU_SIZE 0x2000
	94
ac3d3735 AP	95	/* Supported VGICv3 address types */
	96	#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
	97	#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
1085fdc6	98	#define KVM_VGIC_ITS_ADDR_TYPE 4
6e407673	99	#define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
ac3d3735 AP	100
	101	#define KVM_VGIC_V3_DIST_SIZE SZ_64K
	102	#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
1085fdc6	103	#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
ac3d3735	104
dcd2e40c	105	#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
0d854a60	106	#define KVM_ARM_VCPU_EL1_32BIT 1 /* CPU running a 32bit VM */
7d0f84aa	107	#define KVM_ARM_VCPU_PSCI_0_2 2 /* CPU uses PSCI v0.2 */
808e7381	108	#define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
9033bba4	109	#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
a22fa321 ADK	110	#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
a22fa321 ADK	111	#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
89b0e7de	112	#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
dcd2e40c	113
54f81d0e MZ	114	struct kvm_vcpu_init {
	115	__u32 target;
	116	__u32 features[7];
	117	};
	118
	119	struct kvm_sregs {
	120	};
	121
	122	struct kvm_fpu {
	123	};
	124
21b6f32f AB	125	/*
	126	* See v8 ARM ARM D7.3: Debug Registers
	127	*
	128	* The architectural limit is 16 debug registers of each type although
	129	* in practice there are usually less (see ID_AA64DFR0_EL1).
	130	*
	131	* Although the control registers are architecturally defined as 32
	132	* bits wide we use a 64 bit structure here to keep parity with
	133	* KVM_GET/SET_ONE_REG behaviour which treats all system registers as
	134	* 64 bit values. It also allows for the possibility of the
	135	* architecture expanding the control registers without having to
	136	* change the userspace ABI.
	137	*/
	138	#define KVM_ARM_MAX_DBG_REGS 16
54f81d0e	139	struct kvm_guest_debug_arch {
21b6f32f AB	140	__u64 dbg_bcr[KVM_ARM_MAX_DBG_REGS];
	141	__u64 dbg_bvr[KVM_ARM_MAX_DBG_REGS];
	142	__u64 dbg_wcr[KVM_ARM_MAX_DBG_REGS];
	143	__u64 dbg_wvr[KVM_ARM_MAX_DBG_REGS];
54f81d0e MZ	144	};
54f81d0e MZ	145
18f3976f	146	#define KVM_DEBUG_ARCH_HSR_HIGH_VALID (1 << 0)
54f81d0e	147	struct kvm_debug_exit_arch {
21b6f32f	148	__u32 hsr;
18f3976f	149	__u32 hsr_high; /* ESR_EL2[61:32] */
21b6f32f	150	__u64 far; /* used for watchpoints */
54f81d0e MZ	151	};
54f81d0e MZ	152
21b6f32f AB	153	/*
	154	* Architecture specific defines for kvm_guest_debug->control
	155	*/
	156
	157	#define KVM_GUESTDBG_USE_SW_BP (1 << 16)
	158	#define KVM_GUESTDBG_USE_HW (1 << 17)
	159
54f81d0e	160	struct kvm_sync_regs {
3fe17e68 AG	161	/* Used with KVM_CAP_ARM_USER_IRQ */
3fe17e68 AG	162	__u64 device_irq_level;
54f81d0e MZ	163	};
54f81d0e MZ	164
5d9cb716 PB	165	/* Bits for run->s.regs.device_irq_level */
	166	#define KVM_ARM_DEV_EL1_VTIMER (1 << 0)
	167	#define KVM_ARM_DEV_EL1_PTIMER (1 << 1)
	168	#define KVM_ARM_DEV_PMU (1 << 2)
	169
d7eec236 MZ	170	/*
	171	* PMU filter structure. Describe a range of events with a particular
	172	* action. To be used with KVM_ARM_VCPU_PMU_V3_FILTER.
	173	*/
	174	struct kvm_pmu_event_filter {
	175	__u16 base_event;
	176	__u16 nevents;
	177
	178	#define KVM_PMU_EVENT_ALLOW 0
	179	#define KVM_PMU_EVENT_DENY 1
	180
	181	__u8 action;
	182	__u8 pad[3];
	183	};
	184
b7b27fac DG	185	/* for KVM_GET/SET_VCPU_EVENTS */
	186	struct kvm_vcpu_events {
	187	struct {
	188	__u8 serror_pending;
	189	__u8 serror_has_esr;
da345174	190	__u8 ext_dabt_pending;
b7b27fac	191	/* Align it to 8 bytes */
da345174	192	__u8 pad[5];
b7b27fac DG	193	__u64 serror_esr;
	194	} exception;
	195	__u32 reserved[12];
	196	};
	197
f0376edb SP	198	struct kvm_arm_copy_mte_tags {
	199	__u64 guest_ipa;
	200	__u64 length;
	201	void __user *addr;
	202	__u64 flags;
	203	__u64 reserved[2];
	204	};
	205
30ec7997 MZ	206	/*
	207	* Counter/Timer offset structure. Describe the virtual/physical offset.
	208	* To be used with KVM_ARM_SET_COUNTER_OFFSET.
	209	*/
	210	struct kvm_arm_counter_offset {
	211	__u64 counter_offset;
	212	__u64 reserved;
	213	};
	214
f0376edb SP	215	#define KVM_ARM_TAGS_TO_GUEST 0
	216	#define KVM_ARM_TAGS_FROM_GUEST 1
	217
7c8c5e6a MZ	218	/* If you need to interpret the index values, here is the key: */
	219	#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
	220	#define KVM_REG_ARM_COPROC_SHIFT 16
	221
	222	/* Normal registers are mapped as coprocessor 16. */
	223	#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
	224	#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / sizeof(__u32))
	225
	226	/* Some registers need more space to represent values. */
	227	#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
	228	#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
	229	#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
	230	#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
	231	#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
	232	#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
	233
	234	/* AArch64 system registers */
	235	#define KVM_REG_ARM64_SYSREG (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
	236	#define KVM_REG_ARM64_SYSREG_OP0_MASK 0x000000000000c000
	237	#define KVM_REG_ARM64_SYSREG_OP0_SHIFT 14
	238	#define KVM_REG_ARM64_SYSREG_OP1_MASK 0x0000000000003800
	239	#define KVM_REG_ARM64_SYSREG_OP1_SHIFT 11
	240	#define KVM_REG_ARM64_SYSREG_CRN_MASK 0x0000000000000780
	241	#define KVM_REG_ARM64_SYSREG_CRN_SHIFT 7
	242	#define KVM_REG_ARM64_SYSREG_CRM_MASK 0x0000000000000078
	243	#define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
	244	#define KVM_REG_ARM64_SYSREG_OP2_MASK 0x0000000000000007
	245	#define KVM_REG_ARM64_SYSREG_OP2_SHIFT 0
	246
39735a3a AP	247	#define ARM64_SYS_REG_SHIFT_MASK(x,n) \
	248	(((x) << KVM_REG_ARM64_SYSREG_ ## n ## _SHIFT) & \
	249	KVM_REG_ARM64_SYSREG_ ## n ## _MASK)
	250
	251	#define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
	252	(KVM_REG_ARM64 \| KVM_REG_ARM64_SYSREG \| \
	253	ARM64_SYS_REG_SHIFT_MASK(op0, OP0) \| \
	254	ARM64_SYS_REG_SHIFT_MASK(op1, OP1) \| \
	255	ARM64_SYS_REG_SHIFT_MASK(crn, CRN) \| \
	256	ARM64_SYS_REG_SHIFT_MASK(crm, CRM) \| \
	257	ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
	258
	259	#define ARM64_SYS_REG(...) (__ARM64_SYS_REG(__VA_ARGS__) \| KVM_REG_SIZE_U64)
	260
5c5196da CD	261	/* Physical Timer EL0 Registers */
	262	#define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
	263	#define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
	264	#define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
	265
290a6bb0 AJ	266	/*
	267	* EL0 Virtual Timer Registers
	268	*
	269	* WARNING:
	270	* KVM_REG_ARM_TIMER_CVAL and KVM_REG_ARM_TIMER_CNT are not defined
	271	* with the appropriate register encodings. Their values have been
	272	* accidentally swapped. As this is set API, the definitions here
	273	* must be used, rather than ones derived from the encodings.
	274	*/
39735a3a	275	#define KVM_REG_ARM_TIMER_CTL ARM64_SYS_REG(3, 3, 14, 3, 1)
39735a3a	276	#define KVM_REG_ARM_TIMER_CVAL ARM64_SYS_REG(3, 3, 14, 0, 2)
290a6bb0	277	#define KVM_REG_ARM_TIMER_CNT ARM64_SYS_REG(3, 3, 14, 3, 2)
39735a3a	278
85bd0ba1 MZ	279	/* KVM-as-firmware specific pseudo-registers */
	280	#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
	281	#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
	282	KVM_REG_ARM_FW \| ((r) & 0xffff))
	283	#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
99adb567 AP	284	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
	285	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL 0
	286	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL 1
	287	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED 2
29e8910a MZ	288
	289	/*
	290	* Only two states can be presented by the host kernel:
	291	* - NOT_REQUIRED: the guest doesn't need to do anything
	292	* - NOT_AVAIL: the guest isn't mitigated (it can still use SSBS if available)
	293	*
	294	* All the other values are deprecated. The host still accepts all
	295	* values (they are ABI), but will narrow them to the above two.
	296	*/
99adb567 AP	297	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
	298	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL 0
	299	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN 1
	300	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL 2
	301	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3
	302	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
85bd0ba1	303
a5905d6a JM	304	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3)
	305	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0
	306	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1
	307	#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2
	308
e1c9c983 DM	309	/* SVE registers */
	310	#define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT)
	311
	312	/* Z- and P-regs occupy blocks at the following offsets within this range: */
	313	#define KVM_REG_ARM64_SVE_ZREG_BASE 0
	314	#define KVM_REG_ARM64_SVE_PREG_BASE 0x400
8ae6efdd	315	#define KVM_REG_ARM64_SVE_FFR_BASE 0x600
e1c9c983	316
8ae6efdd DM	317	#define KVM_ARM64_SVE_NUM_ZREGS __SVE_NUM_ZREGS
	318	#define KVM_ARM64_SVE_NUM_PREGS __SVE_NUM_PREGS
	319
	320	#define KVM_ARM64_SVE_MAX_SLICES 32
	321
	322	#define KVM_REG_ARM64_SVE_ZREG(n, i) \
	323	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_ZREG_BASE \| \
	324	KVM_REG_SIZE_U2048 \| \
	325	(((n) & (KVM_ARM64_SVE_NUM_ZREGS - 1)) << 5) \| \
	326	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
	327
	328	#define KVM_REG_ARM64_SVE_PREG(n, i) \
	329	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_PREG_BASE \| \
	330	KVM_REG_SIZE_U256 \| \
	331	(((n) & (KVM_ARM64_SVE_NUM_PREGS - 1)) << 5) \| \
	332	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
	333
	334	#define KVM_REG_ARM64_SVE_FFR(i) \
	335	(KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| KVM_REG_ARM64_SVE_FFR_BASE \| \
	336	KVM_REG_SIZE_U256 \| \
	337	((i) & (KVM_ARM64_SVE_MAX_SLICES - 1)))
e1c9c983	338
41040cf7 DM	339	/*
	340	* Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and
	341	* KVM_REG_ARM64_SVE_FFR() are represented in memory in an endianness-
	342	* invariant layout which differs from the layout used for the FPSIMD
	343	* V-registers on big-endian systems: see sigcontext.h for more explanation.
	344	*/
	345
4bd774e5 DM	346	#define KVM_ARM64_SVE_VQ_MIN __SVE_VQ_MIN
	347	#define KVM_ARM64_SVE_VQ_MAX __SVE_VQ_MAX
	348
9033bba4 DM	349	/* Vector lengths pseudo-register: */
	350	#define KVM_REG_ARM64_SVE_VLS (KVM_REG_ARM64 \| KVM_REG_ARM64_SVE \| \
	351	KVM_REG_SIZE_U512 \| 0xffff)
4bd774e5 DM	352	#define KVM_ARM64_SVE_VLS_WORDS \
4bd774e5 DM	353	((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
9033bba4	354
05714cab RRA	355	/* Bitmap feature firmware registers */
	356	#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT)
	357	#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 \| KVM_REG_SIZE_U64 \| \
	358	KVM_REG_ARM_FW_FEAT_BMAP \| \
	359	((r) & 0xffff))
	360
	361	#define KVM_REG_ARM_STD_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(0)
	362
	363	enum {
	364	KVM_REG_ARM_STD_BIT_TRNG_V1_0 = 0,
2cde51f1	365	#ifdef __KERNEL__
05714cab	366	KVM_REG_ARM_STD_BMAP_BIT_COUNT,
2cde51f1	367	#endif
05714cab RRA	368	};
05714cab RRA	369
428fd678 RRA	370	#define KVM_REG_ARM_STD_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(1)
	371
	372	enum {
	373	KVM_REG_ARM_STD_HYP_BIT_PV_TIME = 0,
2cde51f1	374	#ifdef __KERNEL__
428fd678	375	KVM_REG_ARM_STD_HYP_BMAP_BIT_COUNT,
2cde51f1	376	#endif
428fd678 RRA	377	};
428fd678 RRA	378
b22216e1 RRA	379	#define KVM_REG_ARM_VENDOR_HYP_BMAP KVM_REG_ARM_FW_FEAT_BMAP_REG(2)
	380
	381	enum {
	382	KVM_REG_ARM_VENDOR_HYP_BIT_FUNC_FEAT = 0,
	383	KVM_REG_ARM_VENDOR_HYP_BIT_PTP = 1,
2cde51f1	384	#ifdef __KERNEL__
b22216e1	385	KVM_REG_ARM_VENDOR_HYP_BMAP_BIT_COUNT,
2cde51f1	386	#endif
b22216e1 RRA	387	};
b22216e1 RRA	388
821d935c OU	389	/* Device Control API on vm fd */
	390	#define KVM_ARM_VM_SMCCC_CTRL 0
	391	#define KVM_ARM_VM_SMCCC_FILTER 0
	392
2a2f3e26 CD	393	/* Device Control API: ARM VGIC */
	394	#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
	395	#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
	396	#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
	397	#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
	398	#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
94574c94 VK	399	#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
	400	#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
	401	(0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
2a2f3e26 CD	402	#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
2a2f3e26 CD	403	#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
d017d7b0	404	#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
a98f26f1	405	#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
065c0034	406	#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
94574c94	407	#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
d017d7b0	408	#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
e96a006c	409	#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
876ae234	410	#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
e96a006c VK	411	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
	412	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
	413	(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
	414	#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
	415	#define VGIC_LEVEL_INFO_LINE_LEVEL 0
d017d7b0	416
3b65808f EA	417	#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
	418	#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
	419	#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
28077125	420	#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
3eb4271b	421	#define KVM_DEV_ARM_ITS_CTRL_RESET 4
2a2f3e26	422
bb0c70bc SZ	423	/* Device Control API on vcpu fd */
	424	#define KVM_ARM_VCPU_PMU_V3_CTRL 0
	425	#define KVM_ARM_VCPU_PMU_V3_IRQ 0
	426	#define KVM_ARM_VCPU_PMU_V3_INIT 1
d7eec236	427	#define KVM_ARM_VCPU_PMU_V3_FILTER 2
6ee7fca2	428	#define KVM_ARM_VCPU_PMU_V3_SET_PMU 3
99a1db7a CD	429	#define KVM_ARM_VCPU_TIMER_CTRL 1
	430	#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
	431	#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
81dc9504 MZ	432	#define KVM_ARM_VCPU_TIMER_IRQ_HVTIMER 2
81dc9504 MZ	433	#define KVM_ARM_VCPU_TIMER_IRQ_HPTIMER 3
58772e9a SP	434	#define KVM_ARM_VCPU_PVTIME_CTRL 2
58772e9a SP	435	#define KVM_ARM_VCPU_PVTIME_IPA 0
bb0c70bc	436
54f81d0e	437	/* KVM_IRQ_LINE irq field index values */
92f35b75 MZ	438	#define KVM_ARM_IRQ_VCPU2_SHIFT 28
92f35b75 MZ	439	#define KVM_ARM_IRQ_VCPU2_MASK 0xf
54f81d0e	440	#define KVM_ARM_IRQ_TYPE_SHIFT 24
92f35b75	441	#define KVM_ARM_IRQ_TYPE_MASK 0xf
54f81d0e MZ	442	#define KVM_ARM_IRQ_VCPU_SHIFT 16
	443	#define KVM_ARM_IRQ_VCPU_MASK 0xff
	444	#define KVM_ARM_IRQ_NUM_SHIFT 0
	445	#define KVM_ARM_IRQ_NUM_MASK 0xffff
	446
	447	/* irq_type field */
	448	#define KVM_ARM_IRQ_TYPE_CPU 0
	449	#define KVM_ARM_IRQ_TYPE_SPI 1
	450	#define KVM_ARM_IRQ_TYPE_PPI 2
	451
	452	/* out-of-kernel GIC cpu interrupt injection irq_number field */
	453	#define KVM_ARM_IRQ_CPU_IRQ 0
	454	#define KVM_ARM_IRQ_CPU_FIQ 1
	455
fd1d0ddf AP	456	/*
	457	* This used to hold the highest supported SPI, but it is now obsolete
	458	* and only here to provide source code level compatibility with older
	459	* userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
	460	*/
	461	#ifndef __KERNEL__
54f81d0e	462	#define KVM_ARM_IRQ_GIC_MAX 127
fd1d0ddf	463	#endif
54f81d0e	464
174178fe EA	465	/* One single KVM irqchip, ie. the VGIC */
	466	#define KVM_NR_IRQCHIPS 1
	467
dcd2e40c MZ	468	/* PSCI interface */
	469	#define KVM_PSCI_FN_BASE 0x95c1ba5e
	470	#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
	471
	472	#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
	473	#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
	474	#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
	475	#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
	476
7d0f84aa AP	477	#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
	478	#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
	479	#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
	480	#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
dcd2e40c	481
34739fd9 WD	482	/* arm64-specific kvm_run::system_event flags */
	483	/*
	484	* Reset caused by a PSCI v1.1 SYSTEM_RESET2 call.
	485	* Valid only when the system event has a type of KVM_SYSTEM_EVENT_RESET.
	486	*/
	487	#define KVM_SYSTEM_EVENT_RESET_FLAG_PSCI_RESET2 (1ULL << 0)
	488
583cda1b AE	489	/* run->fail_entry.hardware_entry_failure_reason codes. */
	490	#define KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED (1ULL << 0)
	491
a8308b3f OU	492	enum kvm_smccc_filter_action {
	493	KVM_SMCCC_FILTER_HANDLE = 0,
	494	KVM_SMCCC_FILTER_DENY,
d824dff1	495	KVM_SMCCC_FILTER_FWD_TO_USER,
a8308b3f OU	496
	497	#ifdef __KERNEL__
	498	NR_SMCCC_FILTER_ACTIONS
	499	#endif
	500	};
	501
821d935c OU	502	struct kvm_smccc_filter {
	503	__u32 base;
	504	__u32 nr_functions;
	505	__u8 action;
	506	__u8 pad[15];
	507	};
	508
d824dff1	509	/* arm64-specific KVM_EXIT_HYPERCALL flags */
0e5c9a9d MZ	510	#define KVM_HYPERCALL_EXIT_SMC (1U << 0)
0e5c9a9d MZ	511	#define KVM_HYPERCALL_EXIT_16BIT (1U << 1)
d824dff1	512
3f9cd0ca JZ	513	/*
	514	* Get feature ID registers userspace writable mask.
	515	*
	516	* From DDI0487J.a, D19.2.66 ("ID_AA64MMFR2_EL1, AArch64 Memory Model
	517	* Feature Register 2"):
	518	*
	519	* "The Feature ID space is defined as the System register space in
	520	* AArch64 with op0==3, op1=={0, 1, 3}, CRn==0, CRm=={0-7},
	521	* op2=={0-7}."
	522	*
	523	* This covers all currently known R/O registers that indicate
	524	* anything useful feature wise, including the ID registers.
	525	*
	526	* If we ever need to introduce a new range, it will be described as
	527	* such in the range field.
	528	*/
	529	#define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \
	530	({ \
	531	__u64 __op1 = (op1) & 3; \
	532	__op1 -= (__op1 == 3); \
	533	(__op1 << 6 \| ((crm) & 7) << 3 \| (op2)); \
	534	})
	535
	536	#define KVM_ARM_FEATURE_ID_RANGE 0
	537	#define KVM_ARM_FEATURE_ID_RANGE_SIZE (3 * 8 * 8)
	538
	539	struct reg_mask_range {
	540	__u64 addr; /* Pointer to mask array */
	541	__u32 range; /* Requested range */
	542	__u32 reserved[13];
	543	};
	544
54f81d0e MZ	545	#endif
	546
	547	#endif /* __ARM_KVM_H__ */