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Commit | Line | Data |
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b3901d54 CM |
1 | /* |
2 | * Based on arch/arm/kernel/process.c | |
3 | * | |
4 | * Original Copyright (C) 1995 Linus Torvalds | |
5 | * Copyright (C) 1996-2000 Russell King - Converted to ARM. | |
6 | * Copyright (C) 2012 ARM Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #include <stdarg.h> | |
22 | ||
fd92d4a5 | 23 | #include <linux/compat.h> |
60c0d45a | 24 | #include <linux/efi.h> |
b3901d54 CM |
25 | #include <linux/export.h> |
26 | #include <linux/sched.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/stddef.h> | |
30 | #include <linux/unistd.h> | |
31 | #include <linux/user.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/reboot.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/kallsyms.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/cpu.h> | |
38 | #include <linux/elfcore.h> | |
39 | #include <linux/pm.h> | |
40 | #include <linux/tick.h> | |
41 | #include <linux/utsname.h> | |
42 | #include <linux/uaccess.h> | |
43 | #include <linux/random.h> | |
44 | #include <linux/hw_breakpoint.h> | |
45 | #include <linux/personality.h> | |
46 | #include <linux/notifier.h> | |
096b3224 | 47 | #include <trace/events/power.h> |
c02433dd | 48 | #include <linux/percpu.h> |
b3901d54 | 49 | |
57f4959b | 50 | #include <asm/alternative.h> |
b3901d54 CM |
51 | #include <asm/compat.h> |
52 | #include <asm/cacheflush.h> | |
d0854412 | 53 | #include <asm/exec.h> |
ec45d1cf WD |
54 | #include <asm/fpsimd.h> |
55 | #include <asm/mmu_context.h> | |
b3901d54 CM |
56 | #include <asm/processor.h> |
57 | #include <asm/stacktrace.h> | |
b3901d54 | 58 | |
c0c264ae LA |
59 | #ifdef CONFIG_CC_STACKPROTECTOR |
60 | #include <linux/stackprotector.h> | |
61 | unsigned long __stack_chk_guard __read_mostly; | |
62 | EXPORT_SYMBOL(__stack_chk_guard); | |
63 | #endif | |
64 | ||
b3901d54 CM |
65 | /* |
66 | * Function pointers to optional machine specific functions | |
67 | */ | |
68 | void (*pm_power_off)(void); | |
69 | EXPORT_SYMBOL_GPL(pm_power_off); | |
70 | ||
b0946fc8 | 71 | void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd); |
b3901d54 | 72 | |
b3901d54 CM |
73 | /* |
74 | * This is our default idle handler. | |
75 | */ | |
0087298f | 76 | void arch_cpu_idle(void) |
b3901d54 CM |
77 | { |
78 | /* | |
79 | * This should do all the clock switching and wait for interrupt | |
80 | * tricks | |
81 | */ | |
096b3224 | 82 | trace_cpu_idle_rcuidle(1, smp_processor_id()); |
6990566b NP |
83 | cpu_do_idle(); |
84 | local_irq_enable(); | |
096b3224 | 85 | trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); |
b3901d54 CM |
86 | } |
87 | ||
9327e2c6 MR |
88 | #ifdef CONFIG_HOTPLUG_CPU |
89 | void arch_cpu_idle_dead(void) | |
90 | { | |
91 | cpu_die(); | |
92 | } | |
93 | #endif | |
94 | ||
90f51a09 AK |
95 | /* |
96 | * Called by kexec, immediately prior to machine_kexec(). | |
97 | * | |
98 | * This must completely disable all secondary CPUs; simply causing those CPUs | |
99 | * to execute e.g. a RAM-based pin loop is not sufficient. This allows the | |
100 | * kexec'd kernel to use any and all RAM as it sees fit, without having to | |
101 | * avoid any code or data used by any SW CPU pin loop. The CPU hotplug | |
102 | * functionality embodied in disable_nonboot_cpus() to achieve this. | |
103 | */ | |
b3901d54 CM |
104 | void machine_shutdown(void) |
105 | { | |
90f51a09 | 106 | disable_nonboot_cpus(); |
b3901d54 CM |
107 | } |
108 | ||
90f51a09 AK |
109 | /* |
110 | * Halting simply requires that the secondary CPUs stop performing any | |
111 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
112 | * achieves this. | |
113 | */ | |
b3901d54 CM |
114 | void machine_halt(void) |
115 | { | |
b9acc49e | 116 | local_irq_disable(); |
90f51a09 | 117 | smp_send_stop(); |
b3901d54 CM |
118 | while (1); |
119 | } | |
120 | ||
90f51a09 AK |
121 | /* |
122 | * Power-off simply requires that the secondary CPUs stop performing any | |
123 | * activity (executing tasks, handling interrupts). smp_send_stop() | |
124 | * achieves this. When the system power is turned off, it will take all CPUs | |
125 | * with it. | |
126 | */ | |
b3901d54 CM |
127 | void machine_power_off(void) |
128 | { | |
b9acc49e | 129 | local_irq_disable(); |
90f51a09 | 130 | smp_send_stop(); |
b3901d54 CM |
131 | if (pm_power_off) |
132 | pm_power_off(); | |
133 | } | |
134 | ||
90f51a09 AK |
135 | /* |
136 | * Restart requires that the secondary CPUs stop performing any activity | |
68234df4 | 137 | * while the primary CPU resets the system. Systems with multiple CPUs must |
90f51a09 AK |
138 | * provide a HW restart implementation, to ensure that all CPUs reset at once. |
139 | * This is required so that any code running after reset on the primary CPU | |
140 | * doesn't have to co-ordinate with other CPUs to ensure they aren't still | |
141 | * executing pre-reset code, and using RAM that the primary CPU's code wishes | |
142 | * to use. Implementing such co-ordination would be essentially impossible. | |
143 | */ | |
b3901d54 CM |
144 | void machine_restart(char *cmd) |
145 | { | |
b3901d54 CM |
146 | /* Disable interrupts first */ |
147 | local_irq_disable(); | |
b9acc49e | 148 | smp_send_stop(); |
b3901d54 | 149 | |
60c0d45a AB |
150 | /* |
151 | * UpdateCapsule() depends on the system being reset via | |
152 | * ResetSystem(). | |
153 | */ | |
154 | if (efi_enabled(EFI_RUNTIME_SERVICES)) | |
155 | efi_reboot(reboot_mode, NULL); | |
156 | ||
b3901d54 | 157 | /* Now call the architecture specific reboot code. */ |
aa1e8ec1 | 158 | if (arm_pm_restart) |
ff701306 | 159 | arm_pm_restart(reboot_mode, cmd); |
1c7ffc32 GR |
160 | else |
161 | do_kernel_restart(cmd); | |
b3901d54 CM |
162 | |
163 | /* | |
164 | * Whoops - the architecture was unable to reboot. | |
165 | */ | |
166 | printk("Reboot failed -- System halted\n"); | |
167 | while (1); | |
168 | } | |
169 | ||
170 | void __show_regs(struct pt_regs *regs) | |
171 | { | |
6ca68e80 CM |
172 | int i, top_reg; |
173 | u64 lr, sp; | |
174 | ||
175 | if (compat_user_mode(regs)) { | |
176 | lr = regs->compat_lr; | |
177 | sp = regs->compat_sp; | |
178 | top_reg = 12; | |
179 | } else { | |
180 | lr = regs->regs[30]; | |
181 | sp = regs->sp; | |
182 | top_reg = 29; | |
183 | } | |
b3901d54 | 184 | |
a43cb95d | 185 | show_regs_print_info(KERN_DEFAULT); |
b3901d54 | 186 | print_symbol("PC is at %s\n", instruction_pointer(regs)); |
6ca68e80 | 187 | print_symbol("LR is at %s\n", lr); |
b3901d54 | 188 | printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", |
6ca68e80 CM |
189 | regs->pc, lr, regs->pstate); |
190 | printk("sp : %016llx\n", sp); | |
db4b0710 MR |
191 | |
192 | i = top_reg; | |
193 | ||
194 | while (i >= 0) { | |
b3901d54 | 195 | printk("x%-2d: %016llx ", i, regs->regs[i]); |
db4b0710 MR |
196 | i--; |
197 | ||
198 | if (i % 2 == 0) { | |
199 | pr_cont("x%-2d: %016llx ", i, regs->regs[i]); | |
200 | i--; | |
201 | } | |
202 | ||
203 | pr_cont("\n"); | |
b3901d54 CM |
204 | } |
205 | printk("\n"); | |
206 | } | |
207 | ||
208 | void show_regs(struct pt_regs * regs) | |
209 | { | |
210 | printk("\n"); | |
b3901d54 CM |
211 | __show_regs(regs); |
212 | } | |
213 | ||
eb35bdd7 WD |
214 | static void tls_thread_flush(void) |
215 | { | |
adf75899 | 216 | write_sysreg(0, tpidr_el0); |
eb35bdd7 WD |
217 | |
218 | if (is_compat_task()) { | |
219 | current->thread.tp_value = 0; | |
220 | ||
221 | /* | |
222 | * We need to ensure ordering between the shadow state and the | |
223 | * hardware state, so that we don't corrupt the hardware state | |
224 | * with a stale shadow state during context switch. | |
225 | */ | |
226 | barrier(); | |
adf75899 | 227 | write_sysreg(0, tpidrro_el0); |
eb35bdd7 WD |
228 | } |
229 | } | |
230 | ||
b3901d54 CM |
231 | void flush_thread(void) |
232 | { | |
233 | fpsimd_flush_thread(); | |
eb35bdd7 | 234 | tls_thread_flush(); |
b3901d54 CM |
235 | flush_ptrace_hw_breakpoint(current); |
236 | } | |
237 | ||
238 | void release_thread(struct task_struct *dead_task) | |
239 | { | |
240 | } | |
241 | ||
242 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) | |
243 | { | |
6eb6c801 JL |
244 | if (current->mm) |
245 | fpsimd_preserve_current_state(); | |
b3901d54 CM |
246 | *dst = *src; |
247 | return 0; | |
248 | } | |
249 | ||
250 | asmlinkage void ret_from_fork(void) asm("ret_from_fork"); | |
251 | ||
252 | int copy_thread(unsigned long clone_flags, unsigned long stack_start, | |
afa86fc4 | 253 | unsigned long stk_sz, struct task_struct *p) |
b3901d54 CM |
254 | { |
255 | struct pt_regs *childregs = task_pt_regs(p); | |
b3901d54 | 256 | |
c34501d2 | 257 | memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); |
b3901d54 | 258 | |
9ac08002 AV |
259 | if (likely(!(p->flags & PF_KTHREAD))) { |
260 | *childregs = *current_pt_regs(); | |
c34501d2 | 261 | childregs->regs[0] = 0; |
d00a3810 WD |
262 | |
263 | /* | |
264 | * Read the current TLS pointer from tpidr_el0 as it may be | |
265 | * out-of-sync with the saved value. | |
266 | */ | |
adf75899 | 267 | *task_user_tls(p) = read_sysreg(tpidr_el0); |
d00a3810 WD |
268 | |
269 | if (stack_start) { | |
270 | if (is_compat_thread(task_thread_info(p))) | |
e0fd18ce | 271 | childregs->compat_sp = stack_start; |
d00a3810 | 272 | else |
e0fd18ce | 273 | childregs->sp = stack_start; |
c34501d2 | 274 | } |
d00a3810 | 275 | |
b3901d54 | 276 | /* |
c34501d2 CM |
277 | * If a TLS pointer was passed to clone (4th argument), use it |
278 | * for the new thread. | |
b3901d54 | 279 | */ |
c34501d2 | 280 | if (clone_flags & CLONE_SETTLS) |
d00a3810 | 281 | p->thread.tp_value = childregs->regs[3]; |
c34501d2 CM |
282 | } else { |
283 | memset(childregs, 0, sizeof(struct pt_regs)); | |
284 | childregs->pstate = PSR_MODE_EL1h; | |
57f4959b | 285 | if (IS_ENABLED(CONFIG_ARM64_UAO) && |
a4023f68 | 286 | cpus_have_const_cap(ARM64_HAS_UAO)) |
57f4959b | 287 | childregs->pstate |= PSR_UAO_BIT; |
c34501d2 CM |
288 | p->thread.cpu_context.x19 = stack_start; |
289 | p->thread.cpu_context.x20 = stk_sz; | |
b3901d54 | 290 | } |
b3901d54 | 291 | p->thread.cpu_context.pc = (unsigned long)ret_from_fork; |
c34501d2 | 292 | p->thread.cpu_context.sp = (unsigned long)childregs; |
b3901d54 CM |
293 | |
294 | ptrace_hw_copy_thread(p); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | static void tls_thread_switch(struct task_struct *next) | |
300 | { | |
301 | unsigned long tpidr, tpidrro; | |
302 | ||
adf75899 | 303 | tpidr = read_sysreg(tpidr_el0); |
d00a3810 | 304 | *task_user_tls(current) = tpidr; |
b3901d54 | 305 | |
d00a3810 WD |
306 | tpidr = *task_user_tls(next); |
307 | tpidrro = is_compat_thread(task_thread_info(next)) ? | |
308 | next->thread.tp_value : 0; | |
b3901d54 | 309 | |
adf75899 MR |
310 | write_sysreg(tpidr, tpidr_el0); |
311 | write_sysreg(tpidrro, tpidrro_el0); | |
b3901d54 CM |
312 | } |
313 | ||
57f4959b | 314 | /* Restore the UAO state depending on next's addr_limit */ |
d0854412 | 315 | void uao_thread_switch(struct task_struct *next) |
57f4959b | 316 | { |
e950631e CM |
317 | if (IS_ENABLED(CONFIG_ARM64_UAO)) { |
318 | if (task_thread_info(next)->addr_limit == KERNEL_DS) | |
319 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); | |
320 | else | |
321 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO)); | |
322 | } | |
57f4959b JM |
323 | } |
324 | ||
c02433dd MR |
325 | /* |
326 | * We store our current task in sp_el0, which is clobbered by userspace. Keep a | |
327 | * shadow copy so that we can restore this upon entry from userspace. | |
328 | * | |
329 | * This is *only* for exception entry from EL0, and is not valid until we | |
330 | * __switch_to() a user task. | |
331 | */ | |
332 | DEFINE_PER_CPU(struct task_struct *, __entry_task); | |
333 | ||
334 | static void entry_task_switch(struct task_struct *next) | |
335 | { | |
336 | __this_cpu_write(__entry_task, next); | |
337 | } | |
338 | ||
b3901d54 CM |
339 | /* |
340 | * Thread switching. | |
341 | */ | |
8f4b326d | 342 | __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, |
b3901d54 CM |
343 | struct task_struct *next) |
344 | { | |
345 | struct task_struct *last; | |
346 | ||
347 | fpsimd_thread_switch(next); | |
348 | tls_thread_switch(next); | |
349 | hw_breakpoint_thread_switch(next); | |
3325732f | 350 | contextidr_thread_switch(next); |
c02433dd | 351 | entry_task_switch(next); |
57f4959b | 352 | uao_thread_switch(next); |
b3901d54 | 353 | |
5108c67c CM |
354 | /* |
355 | * Complete any pending TLB or cache maintenance on this CPU in case | |
356 | * the thread migrates to a different CPU. | |
357 | */ | |
98f7685e | 358 | dsb(ish); |
b3901d54 CM |
359 | |
360 | /* the actual thread switch */ | |
361 | last = cpu_switch_to(prev, next); | |
362 | ||
363 | return last; | |
364 | } | |
365 | ||
b3901d54 CM |
366 | unsigned long get_wchan(struct task_struct *p) |
367 | { | |
368 | struct stackframe frame; | |
9bbd4c56 | 369 | unsigned long stack_page, ret = 0; |
b3901d54 CM |
370 | int count = 0; |
371 | if (!p || p == current || p->state == TASK_RUNNING) | |
372 | return 0; | |
373 | ||
9bbd4c56 MR |
374 | stack_page = (unsigned long)try_get_task_stack(p); |
375 | if (!stack_page) | |
376 | return 0; | |
377 | ||
b3901d54 CM |
378 | frame.fp = thread_saved_fp(p); |
379 | frame.sp = thread_saved_sp(p); | |
380 | frame.pc = thread_saved_pc(p); | |
20380bb3 AT |
381 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
382 | frame.graph = p->curr_ret_stack; | |
383 | #endif | |
b3901d54 | 384 | do { |
408c3658 KK |
385 | if (frame.sp < stack_page || |
386 | frame.sp >= stack_page + THREAD_SIZE || | |
fe13f95b | 387 | unwind_frame(p, &frame)) |
9bbd4c56 MR |
388 | goto out; |
389 | if (!in_sched_functions(frame.pc)) { | |
390 | ret = frame.pc; | |
391 | goto out; | |
392 | } | |
b3901d54 | 393 | } while (count ++ < 16); |
9bbd4c56 MR |
394 | |
395 | out: | |
396 | put_task_stack(p); | |
397 | return ret; | |
b3901d54 CM |
398 | } |
399 | ||
400 | unsigned long arch_align_stack(unsigned long sp) | |
401 | { | |
402 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
403 | sp -= get_random_int() & ~PAGE_MASK; | |
404 | return sp & ~0xf; | |
405 | } | |
406 | ||
b3901d54 CM |
407 | unsigned long arch_randomize_brk(struct mm_struct *mm) |
408 | { | |
61462c8a | 409 | if (is_compat_task()) |
fa5114c7 | 410 | return randomize_page(mm->brk, 0x02000000); |
61462c8a | 411 | else |
fa5114c7 | 412 | return randomize_page(mm->brk, 0x40000000); |
b3901d54 | 413 | } |