[thirdparty/kernel/stable.git] / arch / powerpc / mm / ppc_mmu_32.c

/*
 * This file contains the routines for handling the MMU on those
 * PowerPC implementations where the MMU substantially follows the
 * architecture specification.  This includes the 6xx, 7xx, 7xxx,
 * and 8260 implementations but excludes the 8xx and 4xx.
 *  -- paulus
 *
 *  Derived from arch/ppc/mm/init.c:
 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
 *
 *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
 *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
 *    Copyright (C) 1996 Paul Mackerras
 *
 *  Derived from "arch/i386/mm/init.c"
 *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */

#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/highmem.h>
#include <linux/memblock.h>

#include <asm/prom.h>
#include <asm/mmu.h>
#include <asm/machdep.h>
#include <asm/code-patching.h>
#include <asm/sections.h>

#include "mmu_decl.h"

struct hash_pte *Hash, *Hash_end;
unsigned long Hash_size, Hash_mask;
unsigned long _SDR1;

struct ppc_bat BATS[8][2];	/* 8 pairs of IBAT, DBAT */

struct batrange {		/* stores address ranges mapped by BATs */
	unsigned long start;
	unsigned long limit;
	phys_addr_t phys;
} bat_addrs[8];

/*
 * Return PA for this VA if it is mapped by a BAT, or 0
 */
phys_addr_t v_block_mapped(unsigned long va)
{
	int b;
	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
		if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
			return bat_addrs[b].phys + (va - bat_addrs[b].start);
	return 0;
}

/*
 * Return VA for a given PA or 0 if not mapped
 */
unsigned long p_block_mapped(phys_addr_t pa)
{
	int b;
	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
		if (pa >= bat_addrs[b].phys
	    	    && pa < (bat_addrs[b].limit-bat_addrs[b].start)
		              +bat_addrs[b].phys)
			return bat_addrs[b].start+(pa-bat_addrs[b].phys);
	return 0;
}

static int find_free_bat(void)
{
	int b;

	if (cpu_has_feature(CPU_FTR_601)) {
		for (b = 0; b < 4; b++) {
			struct ppc_bat *bat = BATS[b];

			if (!(bat[0].batl & 0x40))
				return b;
		}
	} else {
		int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;

		for (b = 0; b < n; b++) {
			struct ppc_bat *bat = BATS[b];

			if (!(bat[1].batu & 3))
				return b;
		}
	}
	return -1;
}

static unsigned int block_size(unsigned long base, unsigned long top)
{
	unsigned int max_size = (cpu_has_feature(CPU_FTR_601) ? 8 : 256) << 20;
	unsigned int base_shift = (fls(base) - 1) & 31;
	unsigned int block_shift = (fls(top - base) - 1) & 31;

	return min3(max_size, 1U << base_shift, 1U << block_shift);
}

/*
 * Set up one of the IBAT (block address translation) register pairs.
 * The parameters are not checked; in particular size must be a power
 * of 2 between 128k and 256M.
 * Only for 603+ ...
 */
static void setibat(int index, unsigned long virt, phys_addr_t phys,
		    unsigned int size, pgprot_t prot)
{
	unsigned int bl = (size >> 17) - 1;
	int wimgxpp;
	struct ppc_bat *bat = BATS[index];
	unsigned long flags = pgprot_val(prot);

	if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
		flags &= ~_PAGE_COHERENT;

	wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX);
	bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
	bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
	if (flags & _PAGE_USER)
		bat[0].batu |= 1;	/* Vp = 1 */
}

static void clearibat(int index)
{
	struct ppc_bat *bat = BATS[index];

	bat[0].batu = 0;
	bat[0].batl = 0;
}

static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
{
	int idx;

	while ((idx = find_free_bat()) != -1 && base != top) {
		unsigned int size = block_size(base, top);

		if (size < 128 << 10)
			break;
		setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
		base += size;
	}

	return base;
}

unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
{
	int done;
	unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;

	if (__map_without_bats) {
		pr_debug("RAM mapped without BATs\n");
		return base;
	}

	if (!strict_kernel_rwx_enabled() || base >= border || top <= border)
		return __mmu_mapin_ram(base, top);

	done = __mmu_mapin_ram(base, border);
	if (done != border - base)
		return done;

	return done + __mmu_mapin_ram(border, top);
}

void mmu_mark_initmem_nx(void)
{
	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
	int i;
	unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
	unsigned long top = (unsigned long)_etext - PAGE_OFFSET;
	unsigned long size;

	if (cpu_has_feature(CPU_FTR_601))
		return;

	for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) {
		size = block_size(base, top);
		setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
		base += size;
	}
	if (base < top) {
		size = block_size(base, top);
		size = max(size, 128UL << 10);
		if ((top - base) > size) {
			if (strict_kernel_rwx_enabled())
				pr_warn("Kernel _etext not properly aligned\n");
			size <<= 1;
		}
		setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
		base += size;
	}
	for (; i < nb; i++)
		clearibat(i);

	update_bats();

	for (i = TASK_SIZE >> 28; i < 16; i++) {
		/* Do not set NX on VM space for modules */
		if (IS_ENABLED(CONFIG_MODULES) &&
		    (VMALLOC_START & 0xf0000000) == i << 28)
			break;
		mtsrin(mfsrin(i << 28) | 0x10000000, i << 28);
	}
}

void mmu_mark_rodata_ro(void)
{
	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
	int i;

	if (cpu_has_feature(CPU_FTR_601))
		return;

	for (i = 0; i < nb; i++) {
		struct ppc_bat *bat = BATS[i];

		if (bat_addrs[i].start < (unsigned long)__init_begin)
			bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX;
	}

	update_bats();
}

/*
 * Set up one of the I/D BAT (block address translation) register pairs.
 * The parameters are not checked; in particular size must be a power
 * of 2 between 128k and 256M.
 * On 603+, only set IBAT when _PAGE_EXEC is set
 */
void __init setbat(int index, unsigned long virt, phys_addr_t phys,
		   unsigned int size, pgprot_t prot)
{
	unsigned int bl;
	int wimgxpp;
	struct ppc_bat *bat = BATS[index];
	unsigned long flags = pgprot_val(prot);

	if ((flags & _PAGE_NO_CACHE) ||
	    (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
		flags &= ~_PAGE_COHERENT;

	bl = (size >> 17) - 1;
	if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
		/* 603, 604, etc. */
		/* Do DBAT first */
		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
				   | _PAGE_COHERENT | _PAGE_GUARDED);
		wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
		bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
		bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
		if (flags & _PAGE_USER)
			bat[1].batu |= 1; 	/* Vp = 1 */
		if (flags & _PAGE_GUARDED) {
			/* G bit must be zero in IBATs */
			flags &= ~_PAGE_EXEC;
		}
		if (flags & _PAGE_EXEC)
			bat[0] = bat[1];
		else
			bat[0].batu = bat[0].batl = 0;
	} else {
		/* 601 cpu */
		if (bl > BL_8M)
			bl = BL_8M;
		wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
				   | _PAGE_COHERENT);
		wimgxpp |= (flags & _PAGE_RW)?
			((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
		bat->batu = virt | wimgxpp | 4;	/* Ks=0, Ku=1 */
		bat->batl = phys | bl | 0x40;	/* V=1 */
	}

	bat_addrs[index].start = virt;
	bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
	bat_addrs[index].phys = phys;
}

/*
 * Preload a translation in the hash table
 */
void hash_preload(struct mm_struct *mm, unsigned long ea,
		  bool is_exec, unsigned long trap)
{
	pmd_t *pmd;

	if (!Hash)
		return;
	pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
	if (!pmd_none(*pmd))
		add_hash_page(mm->context.id, ea, pmd_val(*pmd));
}

/*
 * Initialize the hash table and patch the instructions in hashtable.S.
 */
void __init MMU_init_hw(void)
{
	unsigned int hmask, mb, mb2;
	unsigned int n_hpteg, lg_n_hpteg;

	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
		return;

	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);

#define LG_HPTEG_SIZE	6		/* 64 bytes per HPTEG */
#define SDR1_LOW_BITS	((n_hpteg - 1) >> 10)
#define MIN_N_HPTEG	1024		/* min 64kB hash table */

	/*
	 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
	 * This is less than the recommended amount, but then
	 * Linux ain't AIX.
	 */
	n_hpteg = total_memory / (PAGE_SIZE * 8);
	if (n_hpteg < MIN_N_HPTEG)
		n_hpteg = MIN_N_HPTEG;
	lg_n_hpteg = __ilog2(n_hpteg);
	if (n_hpteg & (n_hpteg - 1)) {
		++lg_n_hpteg;		/* round up if not power of 2 */
		n_hpteg = 1 << lg_n_hpteg;
	}
	Hash_size = n_hpteg << LG_HPTEG_SIZE;

	/*
	 * Find some memory for the hash table.
	 */
	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
	Hash = __va(memblock_phys_alloc(Hash_size, Hash_size));
	memset(Hash, 0, Hash_size);
	_SDR1 = __pa(Hash) | SDR1_LOW_BITS;

	Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);

	printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
	       (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);


	/*
	 * Patch up the instructions in hashtable.S:create_hpte
	 */
	if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
	Hash_mask = n_hpteg - 1;
	hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
	mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
	if (lg_n_hpteg > 16)
		mb2 = 16 - LG_HPTEG_SIZE;

	modify_instruction_site(&patch__hash_page_A0, 0xffff,
				((unsigned int)Hash - PAGE_OFFSET) >> 16);
	modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
	modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);

	/*
	 * Patch up the instructions in hashtable.S:flush_hash_page
	 */
	modify_instruction_site(&patch__flush_hash_A0, 0xffff,
				((unsigned int)Hash - PAGE_OFFSET) >> 16);
	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);

	if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
}

void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				phys_addr_t first_memblock_size)
{
	/* We don't currently support the first MEMBLOCK not mapping 0
	 * physical on those processors
	 */
	BUG_ON(first_memblock_base != 0);

	/* 601 can only access 16MB at the moment */
	if (PVR_VER(mfspr(SPRN_PVR)) == 1)
		memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
	else /* Anything else has 256M mapped */
		memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
}
Commit	Line	Data
14cf11af PM	1	/*
	2	* This file contains the routines for handling the MMU on those
	3	* PowerPC implementations where the MMU substantially follows the
	4	* architecture specification. This includes the 6xx, 7xx, 7xxx,
0f369103	5	* and 8260 implementations but excludes the 8xx and 4xx.
14cf11af PM	6	* -- paulus
	7	*
	8	* Derived from arch/ppc/mm/init.c:
	9	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	10	*
	11	* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
	12	* and Cort Dougan (PReP) (cort@cs.nmt.edu)
	13	* Copyright (C) 1996 Paul Mackerras
14cf11af PM	14	*
	15	* Derived from "arch/i386/mm/init.c"
	16	* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License
	20	* as published by the Free Software Foundation; either version
	21	* 2 of the License, or (at your option) any later version.
	22	*
	23	*/
	24
14cf11af PM	25	#include <linux/kernel.h>
	26	#include <linux/mm.h>
	27	#include <linux/init.h>
	28	#include <linux/highmem.h>
95f72d1e	29	#include <linux/memblock.h>
14cf11af PM	30
	31	#include <asm/prom.h>
	32	#include <asm/mmu.h>
	33	#include <asm/machdep.h>
9efc74ff	34	#include <asm/code-patching.h>
63b2bc61	35	#include <asm/sections.h>
14cf11af PM	36
14cf11af PM	37	#include "mmu_decl.h"
14cf11af	38
8e561e7e	39	struct hash_pte Hash, Hash_end;
14cf11af PM	40	unsigned long Hash_size, Hash_mask;
	41	unsigned long _SDR1;
	42
316a4058	43	struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */
14cf11af PM	44
	45	struct batrange { /* stores address ranges mapped by BATs */
	46	unsigned long start;
	47	unsigned long limit;
7c5c4325	48	phys_addr_t phys;
ee0339f2	49	} bat_addrs[8];
14cf11af PM	50
	51	/*
	52	* Return PA for this VA if it is mapped by a BAT, or 0
	53	*/
3084cdb7	54	phys_addr_t v_block_mapped(unsigned long va)
14cf11af PM	55	{
14cf11af PM	56	int b;
e93ba1b7	57	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
14cf11af PM	58	if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
	59	return bat_addrs[b].phys + (va - bat_addrs[b].start);
	60	return 0;
	61	}
	62
	63	/*
	64	* Return VA for a given PA or 0 if not mapped
	65	*/
3084cdb7	66	unsigned long p_block_mapped(phys_addr_t pa)
14cf11af PM	67	{
14cf11af PM	68	int b;
e93ba1b7	69	for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
14cf11af PM	70	if (pa >= bat_addrs[b].phys
	71	&& pa < (bat_addrs[b].limit-bat_addrs[b].start)
	72	+bat_addrs[b].phys)
	73	return bat_addrs[b].start+(pa-bat_addrs[b].phys);
	74	return 0;
	75	}
	76
e4d6654e CL	77	static int find_free_bat(void)
	78	{
	79	int b;
	80
	81	if (cpu_has_feature(CPU_FTR_601)) {
	82	for (b = 0; b < 4; b++) {
	83	struct ppc_bat *bat = BATS[b];
	84
	85	if (!(bat[0].batl & 0x40))
	86	return b;
	87	}
	88	} else {
	89	int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
	90
	91	for (b = 0; b < n; b++) {
	92	struct ppc_bat *bat = BATS[b];
	93
	94	if (!(bat[1].batu & 3))
	95	return b;
	96	}
	97	}
	98	return -1;
	99	}
	100
	101	static unsigned int block_size(unsigned long base, unsigned long top)
	102	{
	103	unsigned int max_size = (cpu_has_feature(CPU_FTR_601) ? 8 : 256) << 20;
	104	unsigned int base_shift = (fls(base) - 1) & 31;
	105	unsigned int block_shift = (fls(top - base) - 1) & 31;
	106
	107	return min3(max_size, 1U << base_shift, 1U << block_shift);
	108	}
	109
5e04ae85 CL	110	/*
	111	* Set up one of the IBAT (block address translation) register pairs.
	112	* The parameters are not checked; in particular size must be a power
	113	* of 2 between 128k and 256M.
	114	* Only for 603+ ...
	115	*/
	116	static void setibat(int index, unsigned long virt, phys_addr_t phys,
	117	unsigned int size, pgprot_t prot)
	118	{
	119	unsigned int bl = (size >> 17) - 1;
	120	int wimgxpp;
	121	struct ppc_bat *bat = BATS[index];
	122	unsigned long flags = pgprot_val(prot);
	123
	124	if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
	125	flags &= ~_PAGE_COHERENT;
	126
	127	wimgxpp = (flags & _PAGE_COHERENT) \| (_PAGE_EXEC ? BPP_RX : BPP_XX);
	128	bat[0].batu = virt \| (bl << 2) \| 2; /* Vs=1, Vp=0 */
	129	bat[0].batl = BAT_PHYS_ADDR(phys) \| wimgxpp;
	130	if (flags & _PAGE_USER)
	131	bat[0].batu \|= 1; /* Vp = 1 */
	132	}
	133
	134	static void clearibat(int index)
	135	{
	136	struct ppc_bat *bat = BATS[index];
	137
	138	bat[0].batu = 0;
	139	bat[0].batl = 0;
	140	}
	141
63b2bc61	142	static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
14cf11af	143	{
e4d6654e	144	int idx;
14cf11af	145
e4d6654e CL	146	while ((idx = find_free_bat()) != -1 && base != top) {
e4d6654e CL	147	unsigned int size = block_size(base, top);
14cf11af	148
e4d6654e	149	if (size < 128 << 10)
14cf11af	150	break;
e4d6654e CL	151	setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
e4d6654e CL	152	base += size;
14cf11af PM	153	}
14cf11af PM	154
e4d6654e	155	return base;
14cf11af PM	156	}
14cf11af PM	157
63b2bc61 CL	158	unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
	159	{
	160	int done;
	161	unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
	162
	163	if (__map_without_bats) {
	164	pr_debug("RAM mapped without BATs\n");
	165	return base;
	166	}
	167
	168	if (!strict_kernel_rwx_enabled() \|\| base >= border \|\| top <= border)
	169	return __mmu_mapin_ram(base, top);
	170
	171	done = __mmu_mapin_ram(base, border);
	172	if (done != border - base)
	173	return done;
	174
	175	return done + __mmu_mapin_ram(border, top);
	176	}
	177
	178	void mmu_mark_initmem_nx(void)
	179	{
	180	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
	181	int i;
	182	unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
	183	unsigned long top = (unsigned long)_etext - PAGE_OFFSET;
	184	unsigned long size;
	185
	186	if (cpu_has_feature(CPU_FTR_601))
	187	return;
	188
	189	for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) {
	190	size = block_size(base, top);
	191	setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
	192	base += size;
	193	}
	194	if (base < top) {
	195	size = block_size(base, top);
	196	size = max(size, 128UL << 10);
	197	if ((top - base) > size) {
	198	if (strict_kernel_rwx_enabled())
	199	pr_warn("Kernel _etext not properly aligned\n");
	200	size <<= 1;
	201	}
	202	setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
	203	base += size;
	204	}
	205	for (; i < nb; i++)
	206	clearibat(i);
	207
	208	update_bats();
	209
	210	for (i = TASK_SIZE >> 28; i < 16; i++) {
	211	/* Do not set NX on VM space for modules */
	212	if (IS_ENABLED(CONFIG_MODULES) &&
	213	(VMALLOC_START & 0xf0000000) == i << 28)
	214	break;
	215	mtsrin(mfsrin(i << 28) \| 0x10000000, i << 28);
	216	}
	217	}
	218
	219	void mmu_mark_rodata_ro(void)
	220	{
	221	int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
222	int i;
223
224	if (cpu_has_feature(CPU_FTR_601))
225	return;
226
227	for (i = 0; i < nb; i++) {
228	struct ppc_bat *bat = BATS[i];
229
230	if (bat_addrs[i].start < (unsigned long)__init_begin)
231	bat[1].batl = (bat[1].batl & ~BPP_RW) \| BPP_RX;
232	}
233
234	update_bats();
235	}
236
14cf11af PM	237	/*
	238	* Set up one of the I/D BAT (block address translation) register pairs.
	239	* The parameters are not checked; in particular size must be a power
	240	* of 2 between 128k and 256M.
df25f863	241	* On 603+, only set IBAT when _PAGE_EXEC is set
14cf11af	242	*/
7c5c4325	243	void __init setbat(int index, unsigned long virt, phys_addr_t phys,
5dd4e4f6	244	unsigned int size, pgprot_t prot)
14cf11af PM	245	{
	246	unsigned int bl;
	247	int wimgxpp;
316a4058	248	struct ppc_bat *bat = BATS[index];
5dd4e4f6	249	unsigned long flags = pgprot_val(prot);
14cf11af	250
4c456a67 GP	251	if ((flags & _PAGE_NO_CACHE) \|\|
	252	(cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
	253	flags &= ~_PAGE_COHERENT;
14cf11af PM	254
	255	bl = (size >> 17) - 1;
	256	if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
	257	/* 603, 604, etc. */
	258	/* Do DBAT first */
	259	wimgxpp = flags & (_PAGE_WRITETHRU \| _PAGE_NO_CACHE
	260	\| _PAGE_COHERENT \| _PAGE_GUARDED);
	261	wimgxpp \|= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
316a4058 BB	262	bat[1].batu = virt \| (bl << 2) \| 2; /* Vs=1, Vp=0 */
316a4058 BB	263	bat[1].batl = BAT_PHYS_ADDR(phys) \| wimgxpp;
14cf11af	264	if (flags & _PAGE_USER)
316a4058	265	bat[1].batu \|= 1; /* Vp = 1 */
14cf11af PM	266	if (flags & _PAGE_GUARDED) {
14cf11af PM	267	/* G bit must be zero in IBATs */
df25f863	268	flags &= ~_PAGE_EXEC;
14cf11af	269	}
df25f863 CL	270	if (flags & _PAGE_EXEC)
	271	bat[0] = bat[1];
	272	else
	273	bat[0].batu = bat[0].batl = 0;
14cf11af PM	274	} else {
	275	/* 601 cpu */
	276	if (bl > BL_8M)
	277	bl = BL_8M;
	278	wimgxpp = flags & (_PAGE_WRITETHRU \| _PAGE_NO_CACHE
	279	\| _PAGE_COHERENT);
	280	wimgxpp \|= (flags & _PAGE_RW)?
	281	((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
316a4058 BB	282	bat->batu = virt \| wimgxpp \| 4; /* Ks=0, Ku=1 */
316a4058 BB	283	bat->batl = phys \| bl \| 0x40; /* V=1 */
14cf11af PM	284	}
	285
	286	bat_addrs[index].start = virt;
	287	bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
	288	bat_addrs[index].phys = phys;
	289	}
	290
3c726f8d BH	291	/*
	292	* Preload a translation in the hash table
	293	*/
	294	void hash_preload(struct mm_struct *mm, unsigned long ea,
34eb138e	295	bool is_exec, unsigned long trap)
3c726f8d BH	296	{
	297	pmd_t *pmd;
	298
d8731527	299	if (!Hash)
3c726f8d	300	return;
f1a1eb29	301	pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
3c726f8d	302	if (!pmd_none(*pmd))
6218a761	303	add_hash_page(mm->context.id, ea, pmd_val(*pmd));
3c726f8d BH	304	}
3c726f8d BH	305
14cf11af PM	306	/*
	307	* Initialize the hash table and patch the instructions in hashtable.S.
	308	*/
	309	void __init MMU_init_hw(void)
	310	{
	311	unsigned int hmask, mb, mb2;
	312	unsigned int n_hpteg, lg_n_hpteg;
	313
4a3a224c	314	if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
14cf11af	315	return;
14cf11af PM	316
	317	if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
	318
14cf11af PM	319	#define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
	320	#define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
	321	#define MIN_N_HPTEG 1024 /* min 64kB hash table */
14cf11af	322
14cf11af PM	323	/*
	324	* Allow 1 HPTE (1/8 HPTEG) for each page of memory.
	325	* This is less than the recommended amount, but then
	326	* Linux ain't AIX.
	327	*/
	328	n_hpteg = total_memory / (PAGE_SIZE * 8);
	329	if (n_hpteg < MIN_N_HPTEG)
	330	n_hpteg = MIN_N_HPTEG;
	331	lg_n_hpteg = __ilog2(n_hpteg);
	332	if (n_hpteg & (n_hpteg - 1)) {
	333	++lg_n_hpteg; /* round up if not power of 2 */
	334	n_hpteg = 1 << lg_n_hpteg;
	335	}
	336	Hash_size = n_hpteg << LG_HPTEG_SIZE;
	337
	338	/*
	339	* Find some memory for the hash table.
	340	*/
	341	if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
9a8dd708	342	Hash = __va(memblock_phys_alloc(Hash_size, Hash_size));
b05ae4ee	343	memset(Hash, 0, Hash_size);
14cf11af	344	_SDR1 = __pa(Hash) \| SDR1_LOW_BITS;
14cf11af	345
8e561e7e	346	Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
14cf11af	347
c7c8eede TB	348	printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
c7c8eede TB	349	(unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
14cf11af PM	350
	351
	352	/*
	353	* Patch up the instructions in hashtable.S:create_hpte
	354	*/
	355	if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
	356	Hash_mask = n_hpteg - 1;
	357	hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
	358	mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
	359	if (lg_n_hpteg > 16)
	360	mb2 = 16 - LG_HPTEG_SIZE;
	361
6790dae8 CL	362	modify_instruction_site(&patch__hash_page_A0, 0xffff,
6790dae8 CL	363	((unsigned int)Hash - PAGE_OFFSET) >> 16);
9efc74ff CL	364	modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
	365	modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
	366	modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
	367	modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
14cf11af PM	368
	369	/*
	370	* Patch up the instructions in hashtable.S:flush_hash_page
	371	*/
6790dae8 CL	372	modify_instruction_site(&patch__flush_hash_A0, 0xffff,
6790dae8 CL	373	((unsigned int)Hash - PAGE_OFFSET) >> 16);
9efc74ff CL	374	modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
	375	modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
	376	modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
14cf11af PM	377
	378	if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
	379	}
cd3db0c4 BH	380
	381	void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	382	phys_addr_t first_memblock_size)
	383	{
	384	/* We don't currently support the first MEMBLOCK not mapping 0
	385	* physical on those processors
	386	*/
	387	BUG_ON(first_memblock_base != 0);
	388
	389	/* 601 can only access 16MB at the moment */
	390	if (PVR_VER(mfspr(SPRN_PVR)) == 1)
	391	memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
	392	else /* Anything else has 256M mapped */
	393	memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
	394	}