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Commit | Line | Data |
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3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
cea58224 | 4 | * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> |
6b44e72a | 5 | * 2006 Shaohua Li <shaohua.li@intel.com> |
14cfbe55 | 6 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
a5321aec | 25 | #include <linux/stop_machine.h> |
fe055896 | 26 | #include <linux/syscore_ops.h> |
4bae1967 | 27 | #include <linux/miscdevice.h> |
871b72dd | 28 | #include <linux/capability.h> |
fe055896 | 29 | #include <linux/firmware.h> |
4bae1967 | 30 | #include <linux/kernel.h> |
a5321aec | 31 | #include <linux/delay.h> |
3e135d88 PO |
32 | #include <linux/mutex.h> |
33 | #include <linux/cpu.h> | |
a5321aec | 34 | #include <linux/nmi.h> |
4bae1967 IM |
35 | #include <linux/fs.h> |
36 | #include <linux/mm.h> | |
3e135d88 | 37 | |
fe055896 | 38 | #include <asm/microcode_intel.h> |
78ff123b | 39 | #include <asm/cpu_device_id.h> |
fe055896 | 40 | #include <asm/microcode_amd.h> |
c93dc84c | 41 | #include <asm/perf_event.h> |
fe055896 BP |
42 | #include <asm/microcode.h> |
43 | #include <asm/processor.h> | |
44 | #include <asm/cmdline.h> | |
06b8534c | 45 | #include <asm/setup.h> |
3e135d88 | 46 | |
14cfbe55 | 47 | #define DRIVER_VERSION "2.2" |
3e135d88 | 48 | |
4bae1967 | 49 | static struct microcode_ops *microcode_ops; |
a15a7535 | 50 | static bool dis_ucode_ldr = true; |
6b26e1bf | 51 | |
24c25032 BP |
52 | bool initrd_gone; |
53 | ||
058dc498 BP |
54 | LIST_HEAD(microcode_cache); |
55 | ||
871b72dd DA |
56 | /* |
57 | * Synchronization. | |
58 | * | |
59 | * All non cpu-hotplug-callback call sites use: | |
60 | * | |
61 | * - microcode_mutex to synchronize with each other; | |
62 | * - get/put_online_cpus() to synchronize with | |
63 | * the cpu-hotplug-callback call sites. | |
64 | * | |
65 | * We guarantee that only a single cpu is being | |
66 | * updated at any particular moment of time. | |
67 | */ | |
d45de409 | 68 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 69 | |
a5321aec AR |
70 | /* |
71 | * Serialize late loading so that CPUs get updated one-by-one. | |
72 | */ | |
ff987fcf | 73 | static DEFINE_RAW_SPINLOCK(update_lock); |
a5321aec | 74 | |
4bae1967 | 75 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 76 | |
871b72dd DA |
77 | struct cpu_info_ctx { |
78 | struct cpu_signature *cpu_sig; | |
79 | int err; | |
80 | }; | |
81 | ||
f3ad136d BP |
82 | /* |
83 | * Those patch levels cannot be updated to newer ones and thus should be final. | |
84 | */ | |
85 | static u32 final_levels[] = { | |
86 | 0x01000098, | |
87 | 0x0100009f, | |
88 | 0x010000af, | |
89 | 0, /* T-101 terminator */ | |
90 | }; | |
91 | ||
92 | /* | |
93 | * Check the current patch level on this CPU. | |
94 | * | |
95 | * Returns: | |
96 | * - true: if update should stop | |
97 | * - false: otherwise | |
98 | */ | |
99 | static bool amd_check_current_patch_level(void) | |
100 | { | |
101 | u32 lvl, dummy, i; | |
102 | u32 *levels; | |
103 | ||
104 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); | |
105 | ||
106 | if (IS_ENABLED(CONFIG_X86_32)) | |
107 | levels = (u32 *)__pa_nodebug(&final_levels); | |
108 | else | |
109 | levels = final_levels; | |
110 | ||
111 | for (i = 0; levels[i]; i++) { | |
112 | if (lvl == levels[i]) | |
113 | return true; | |
114 | } | |
115 | return false; | |
116 | } | |
117 | ||
fe055896 BP |
118 | static bool __init check_loader_disabled_bsp(void) |
119 | { | |
e8c8165e BP |
120 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
121 | ||
fe055896 BP |
122 | #ifdef CONFIG_X86_32 |
123 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 124 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
125 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
126 | ||
127 | #else /* CONFIG_X86_64 */ | |
128 | const char *cmdline = boot_command_line; | |
e8c8165e | 129 | const char *option = __dis_opt_str; |
fe055896 BP |
130 | bool *res = &dis_ucode_ldr; |
131 | #endif | |
132 | ||
a15a7535 BP |
133 | /* |
134 | * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not | |
135 | * completely accurate as xen pv guests don't see that CPUID bit set but | |
136 | * that's good enough as they don't land on the BSP path anyway. | |
137 | */ | |
309aac77 | 138 | if (native_cpuid_ecx(1) & BIT(31)) |
a15a7535 BP |
139 | return *res; |
140 | ||
f3ad136d BP |
141 | if (x86_cpuid_vendor() == X86_VENDOR_AMD) { |
142 | if (amd_check_current_patch_level()) | |
143 | return *res; | |
144 | } | |
145 | ||
a15a7535 BP |
146 | if (cmdline_find_option_bool(cmdline, option) <= 0) |
147 | *res = false; | |
fe055896 BP |
148 | |
149 | return *res; | |
150 | } | |
151 | ||
152 | extern struct builtin_fw __start_builtin_fw[]; | |
153 | extern struct builtin_fw __end_builtin_fw[]; | |
154 | ||
155 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
156 | { | |
157 | #ifdef CONFIG_FW_LOADER | |
158 | struct builtin_fw *b_fw; | |
159 | ||
160 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
161 | if (!strcmp(name, b_fw->name)) { | |
162 | cd->size = b_fw->size; | |
163 | cd->data = b_fw->data; | |
164 | return true; | |
165 | } | |
166 | } | |
167 | #endif | |
168 | return false; | |
169 | } | |
170 | ||
171 | void __init load_ucode_bsp(void) | |
172 | { | |
7a93a40b | 173 | unsigned int cpuid_1_eax; |
1f161f67 | 174 | bool intel = true; |
fe055896 | 175 | |
1f161f67 | 176 | if (!have_cpuid_p()) |
fe055896 BP |
177 | return; |
178 | ||
309aac77 | 179 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 180 | |
7a93a40b | 181 | switch (x86_cpuid_vendor()) { |
fe055896 | 182 | case X86_VENDOR_INTEL: |
1f161f67 BP |
183 | if (x86_family(cpuid_1_eax) < 6) |
184 | return; | |
fe055896 | 185 | break; |
1f161f67 | 186 | |
fe055896 | 187 | case X86_VENDOR_AMD: |
1f161f67 BP |
188 | if (x86_family(cpuid_1_eax) < 0x10) |
189 | return; | |
190 | intel = false; | |
fe055896 | 191 | break; |
1f161f67 | 192 | |
fe055896 | 193 | default: |
1f161f67 | 194 | return; |
fe055896 | 195 | } |
1f161f67 BP |
196 | |
197 | if (check_loader_disabled_bsp()) | |
198 | return; | |
199 | ||
200 | if (intel) | |
201 | load_ucode_intel_bsp(); | |
202 | else | |
203 | load_ucode_amd_bsp(cpuid_1_eax); | |
fe055896 BP |
204 | } |
205 | ||
206 | static bool check_loader_disabled_ap(void) | |
207 | { | |
208 | #ifdef CONFIG_X86_32 | |
209 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
210 | #else | |
211 | return dis_ucode_ldr; | |
212 | #endif | |
213 | } | |
214 | ||
215 | void load_ucode_ap(void) | |
216 | { | |
7a93a40b | 217 | unsigned int cpuid_1_eax; |
fe055896 BP |
218 | |
219 | if (check_loader_disabled_ap()) | |
220 | return; | |
221 | ||
309aac77 | 222 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 223 | |
7a93a40b | 224 | switch (x86_cpuid_vendor()) { |
fe055896 | 225 | case X86_VENDOR_INTEL: |
309aac77 | 226 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
227 | load_ucode_intel_ap(); |
228 | break; | |
229 | case X86_VENDOR_AMD: | |
309aac77 BP |
230 | if (x86_family(cpuid_1_eax) >= 0x10) |
231 | load_ucode_amd_ap(cpuid_1_eax); | |
fe055896 BP |
232 | break; |
233 | default: | |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
4b703305 | 238 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
239 | { |
240 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
24c25032 | 241 | int ret = -EINVAL; |
fe055896 BP |
242 | |
243 | switch (c->x86_vendor) { | |
244 | case X86_VENDOR_INTEL: | |
245 | if (c->x86 >= 6) | |
24c25032 | 246 | ret = save_microcode_in_initrd_intel(); |
fe055896 BP |
247 | break; |
248 | case X86_VENDOR_AMD: | |
249 | if (c->x86 >= 0x10) | |
1d080f09 | 250 | ret = save_microcode_in_initrd_amd(cpuid_eax(1)); |
fe055896 BP |
251 | break; |
252 | default: | |
253 | break; | |
254 | } | |
255 | ||
24c25032 BP |
256 | initrd_gone = true; |
257 | ||
258 | return ret; | |
fe055896 BP |
259 | } |
260 | ||
06b8534c BP |
261 | struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) |
262 | { | |
263 | #ifdef CONFIG_BLK_DEV_INITRD | |
264 | unsigned long start = 0; | |
265 | size_t size; | |
266 | ||
267 | #ifdef CONFIG_X86_32 | |
268 | struct boot_params *params; | |
269 | ||
270 | if (use_pa) | |
271 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
272 | else | |
273 | params = &boot_params; | |
274 | ||
275 | size = params->hdr.ramdisk_size; | |
276 | ||
277 | /* | |
278 | * Set start only if we have an initrd image. We cannot use initrd_start | |
279 | * because it is not set that early yet. | |
280 | */ | |
281 | if (size) | |
282 | start = params->hdr.ramdisk_image; | |
283 | ||
284 | # else /* CONFIG_X86_64 */ | |
285 | size = (unsigned long)boot_params.ext_ramdisk_size << 32; | |
286 | size |= boot_params.hdr.ramdisk_size; | |
287 | ||
288 | if (size) { | |
289 | start = (unsigned long)boot_params.ext_ramdisk_image << 32; | |
290 | start |= boot_params.hdr.ramdisk_image; | |
291 | ||
292 | start += PAGE_OFFSET; | |
293 | } | |
294 | # endif | |
295 | ||
296 | /* | |
8877ebdd BP |
297 | * Fixup the start address: after reserve_initrd() runs, initrd_start |
298 | * has the virtual address of the beginning of the initrd. It also | |
299 | * possibly relocates the ramdisk. In either case, initrd_start contains | |
300 | * the updated address so use that instead. | |
24c25032 BP |
301 | * |
302 | * initrd_gone is for the hotplug case where we've thrown out initrd | |
303 | * already. | |
06b8534c | 304 | */ |
24c25032 BP |
305 | if (!use_pa) { |
306 | if (initrd_gone) | |
307 | return (struct cpio_data){ NULL, 0, "" }; | |
308 | if (initrd_start) | |
309 | start = initrd_start; | |
a3d98c93 BP |
310 | } else { |
311 | /* | |
312 | * The picture with physical addresses is a bit different: we | |
313 | * need to get the *physical* address to which the ramdisk was | |
314 | * relocated, i.e., relocated_ramdisk (not initrd_start) and | |
315 | * since we're running from physical addresses, we need to access | |
316 | * relocated_ramdisk through its *physical* address too. | |
317 | */ | |
318 | u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk); | |
319 | if (*rr) | |
320 | start = *rr; | |
24c25032 | 321 | } |
06b8534c BP |
322 | |
323 | return find_cpio_data(path, (void *)start, size, NULL); | |
324 | #else /* !CONFIG_BLK_DEV_INITRD */ | |
325 | return (struct cpio_data){ NULL, 0, "" }; | |
326 | #endif | |
327 | } | |
328 | ||
fe055896 BP |
329 | void reload_early_microcode(void) |
330 | { | |
331 | int vendor, family; | |
332 | ||
99f925ce BP |
333 | vendor = x86_cpuid_vendor(); |
334 | family = x86_cpuid_family(); | |
fe055896 BP |
335 | |
336 | switch (vendor) { | |
337 | case X86_VENDOR_INTEL: | |
338 | if (family >= 6) | |
339 | reload_ucode_intel(); | |
340 | break; | |
341 | case X86_VENDOR_AMD: | |
342 | if (family >= 0x10) | |
343 | reload_ucode_amd(); | |
344 | break; | |
345 | default: | |
346 | break; | |
347 | } | |
348 | } | |
349 | ||
871b72dd DA |
350 | static void collect_cpu_info_local(void *arg) |
351 | { | |
352 | struct cpu_info_ctx *ctx = arg; | |
353 | ||
354 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
355 | ctx->cpu_sig); | |
356 | } | |
357 | ||
358 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
359 | { | |
360 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
361 | int ret; | |
362 | ||
363 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
364 | if (!ret) | |
365 | ret = ctx.err; | |
366 | ||
367 | return ret; | |
368 | } | |
369 | ||
370 | static int collect_cpu_info(int cpu) | |
371 | { | |
372 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
373 | int ret; | |
374 | ||
375 | memset(uci, 0, sizeof(*uci)); | |
376 | ||
377 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
378 | if (!ret) | |
379 | uci->valid = 1; | |
380 | ||
381 | return ret; | |
382 | } | |
383 | ||
871b72dd DA |
384 | static void apply_microcode_local(void *arg) |
385 | { | |
854857f5 | 386 | enum ucode_state *err = arg; |
871b72dd | 387 | |
854857f5 | 388 | *err = microcode_ops->apply_microcode(smp_processor_id()); |
871b72dd DA |
389 | } |
390 | ||
391 | static int apply_microcode_on_target(int cpu) | |
392 | { | |
854857f5 | 393 | enum ucode_state err; |
871b72dd DA |
394 | int ret; |
395 | ||
854857f5 BP |
396 | ret = smp_call_function_single(cpu, apply_microcode_local, &err, 1); |
397 | if (!ret) { | |
398 | if (err == UCODE_ERROR) | |
399 | ret = 1; | |
400 | } | |
871b72dd DA |
401 | return ret; |
402 | } | |
403 | ||
3e135d88 | 404 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 405 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 406 | { |
3e135d88 | 407 | int error = 0; |
3e135d88 | 408 | int cpu; |
6f66cbc6 | 409 | |
a0a29b62 DA |
410 | for_each_online_cpu(cpu) { |
411 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 412 | enum ucode_state ustate; |
a0a29b62 DA |
413 | |
414 | if (!uci->valid) | |
415 | continue; | |
6f66cbc6 | 416 | |
871b72dd DA |
417 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
418 | if (ustate == UCODE_ERROR) { | |
419 | error = -1; | |
420 | break; | |
a07de9b9 | 421 | } else if (ustate == UCODE_NEW) { |
871b72dd | 422 | apply_microcode_on_target(cpu); |
a07de9b9 | 423 | } |
3e135d88 | 424 | } |
871b72dd | 425 | |
3e135d88 PO |
426 | return error; |
427 | } | |
428 | ||
3f10940e | 429 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 430 | { |
3f10940e | 431 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
432 | } |
433 | ||
d33dcb9e PO |
434 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
435 | size_t len, loff_t *ppos) | |
3e135d88 | 436 | { |
871b72dd | 437 | ssize_t ret = -EINVAL; |
3e135d88 | 438 | |
4481374c | 439 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 440 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 441 | return ret; |
3e135d88 PO |
442 | } |
443 | ||
444 | get_online_cpus(); | |
445 | mutex_lock(µcode_mutex); | |
446 | ||
871b72dd | 447 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
448 | ret = (ssize_t)len; |
449 | ||
e3e45c01 SE |
450 | if (ret > 0) |
451 | perf_check_microcode(); | |
452 | ||
3e135d88 PO |
453 | mutex_unlock(µcode_mutex); |
454 | put_online_cpus(); | |
455 | ||
456 | return ret; | |
457 | } | |
458 | ||
459 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
460 | .owner = THIS_MODULE, |
461 | .write = microcode_write, | |
462 | .open = microcode_open, | |
6038f373 | 463 | .llseek = no_llseek, |
3e135d88 PO |
464 | }; |
465 | ||
466 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
467 | .minor = MICROCODE_MINOR, |
468 | .name = "microcode", | |
e454cea2 | 469 | .nodename = "cpu/microcode", |
871b72dd | 470 | .fops = µcode_fops, |
3e135d88 PO |
471 | }; |
472 | ||
d33dcb9e | 473 | static int __init microcode_dev_init(void) |
3e135d88 PO |
474 | { |
475 | int error; | |
476 | ||
477 | error = misc_register(µcode_dev); | |
478 | if (error) { | |
f58e1f53 | 479 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
480 | return error; |
481 | } | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
bd399063 | 486 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
487 | { |
488 | misc_deregister(µcode_dev); | |
489 | } | |
3e135d88 | 490 | #else |
4bae1967 IM |
491 | #define microcode_dev_init() 0 |
492 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
493 | #endif |
494 | ||
495 | /* fake device for request_firmware */ | |
4bae1967 | 496 | static struct platform_device *microcode_pdev; |
3e135d88 | 497 | |
a5321aec AR |
498 | /* |
499 | * Late loading dance. Why the heavy-handed stomp_machine effort? | |
500 | * | |
501 | * - HT siblings must be idle and not execute other code while the other sibling | |
502 | * is loading microcode in order to avoid any negative interactions caused by | |
503 | * the loading. | |
504 | * | |
505 | * - In addition, microcode update on the cores must be serialized until this | |
506 | * requirement can be relaxed in the future. Right now, this is conservative | |
507 | * and good. | |
508 | */ | |
509 | #define SPINUNIT 100 /* 100 nsec */ | |
510 | ||
30ec26da AR |
511 | static int check_online_cpus(void) |
512 | { | |
07d981ad | 513 | unsigned int cpu; |
30ec26da | 514 | |
07d981ad JP |
515 | /* |
516 | * Make sure all CPUs are online. It's fine for SMT to be disabled if | |
517 | * all the primary threads are still online. | |
518 | */ | |
519 | for_each_present_cpu(cpu) { | |
520 | if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { | |
521 | pr_err("Not all CPUs online, aborting microcode update.\n"); | |
522 | return -EINVAL; | |
523 | } | |
524 | } | |
30ec26da | 525 | |
07d981ad | 526 | return 0; |
30ec26da AR |
527 | } |
528 | ||
bb8c13d6 BP |
529 | static atomic_t late_cpus_in; |
530 | static atomic_t late_cpus_out; | |
531 | ||
532 | static int __wait_for_cpus(atomic_t *t, long long timeout) | |
533 | { | |
534 | int all_cpus = num_online_cpus(); | |
535 | ||
536 | atomic_inc(t); | |
537 | ||
538 | while (atomic_read(t) < all_cpus) { | |
539 | if (timeout < SPINUNIT) { | |
540 | pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", | |
541 | all_cpus - atomic_read(t)); | |
542 | return 1; | |
543 | } | |
544 | ||
545 | ndelay(SPINUNIT); | |
546 | timeout -= SPINUNIT; | |
547 | ||
548 | touch_nmi_watchdog(); | |
549 | } | |
550 | return 0; | |
551 | } | |
a5321aec AR |
552 | |
553 | /* | |
554 | * Returns: | |
555 | * < 0 - on error | |
556 | * 0 - no update done | |
557 | * 1 - microcode was updated | |
558 | */ | |
559 | static int __reload_late(void *info) | |
af5c820a | 560 | { |
a5321aec AR |
561 | int cpu = smp_processor_id(); |
562 | enum ucode_state err; | |
563 | int ret = 0; | |
564 | ||
a5321aec AR |
565 | /* |
566 | * Wait for all CPUs to arrive. A load will not be attempted unless all | |
567 | * CPUs show up. | |
568 | * */ | |
bb8c13d6 BP |
569 | if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) |
570 | return -1; | |
a5321aec | 571 | |
ff987fcf | 572 | raw_spin_lock(&update_lock); |
a5321aec | 573 | apply_microcode_local(&err); |
ff987fcf | 574 | raw_spin_unlock(&update_lock); |
a5321aec | 575 | |
09e182d1 | 576 | /* siblings return UCODE_OK because their engine got updated already */ |
a5321aec AR |
577 | if (err > UCODE_NFOUND) { |
578 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
09e182d1 | 579 | ret = -1; |
bb8c13d6 | 580 | } else if (err == UCODE_UPDATED || err == UCODE_OK) { |
a5321aec AR |
581 | ret = 1; |
582 | } | |
af5c820a | 583 | |
bb8c13d6 BP |
584 | /* |
585 | * Increase the wait timeout to a safe value here since we're | |
586 | * serializing the microcode update and that could take a while on a | |
587 | * large number of CPUs. And that is fine as the *actual* timeout will | |
588 | * be determined by the last CPU finished updating and thus cut short. | |
589 | */ | |
590 | if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC * num_online_cpus())) | |
591 | panic("Timeout during microcode update!\n"); | |
a5321aec AR |
592 | |
593 | return ret; | |
594 | } | |
595 | ||
596 | /* | |
597 | * Reload microcode late on all CPUs. Wait for a sec until they | |
598 | * all gather together. | |
599 | */ | |
600 | static int microcode_reload_late(void) | |
601 | { | |
602 | int ret; | |
603 | ||
bb8c13d6 BP |
604 | atomic_set(&late_cpus_in, 0); |
605 | atomic_set(&late_cpus_out, 0); | |
a5321aec AR |
606 | |
607 | ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); | |
bb8c13d6 | 608 | if (ret > 0) |
a5321aec AR |
609 | microcode_check(); |
610 | ||
611 | return ret; | |
af5c820a RR |
612 | } |
613 | ||
8a25a2fd KS |
614 | static ssize_t reload_store(struct device *dev, |
615 | struct device_attribute *attr, | |
871b72dd | 616 | const char *buf, size_t size) |
3e135d88 | 617 | { |
3f1f576a | 618 | enum ucode_state tmp_ret = UCODE_OK; |
a5321aec | 619 | int bsp = boot_cpu_data.cpu_index; |
871b72dd | 620 | unsigned long val; |
3f1f576a | 621 | ssize_t ret = 0; |
c9fc3f77 | 622 | |
e826abd5 SK |
623 | ret = kstrtoul(buf, 0, &val); |
624 | if (ret) | |
625 | return ret; | |
871b72dd | 626 | |
c9fc3f77 BP |
627 | if (val != 1) |
628 | return size; | |
629 | ||
cfb52a5a | 630 | tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true); |
2613f36e | 631 | if (tmp_ret != UCODE_NEW) |
cfb52a5a BP |
632 | return size; |
633 | ||
c9fc3f77 | 634 | get_online_cpus(); |
30ec26da AR |
635 | |
636 | ret = check_online_cpus(); | |
637 | if (ret) | |
638 | goto put; | |
639 | ||
c93dc84c | 640 | mutex_lock(µcode_mutex); |
a5321aec | 641 | ret = microcode_reload_late(); |
c93dc84c | 642 | mutex_unlock(µcode_mutex); |
30ec26da AR |
643 | |
644 | put: | |
c9fc3f77 | 645 | put_online_cpus(); |
871b72dd | 646 | |
a5321aec | 647 | if (ret >= 0) |
871b72dd DA |
648 | ret = size; |
649 | ||
650 | return ret; | |
3e135d88 PO |
651 | } |
652 | ||
8a25a2fd KS |
653 | static ssize_t version_show(struct device *dev, |
654 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
655 | { |
656 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
657 | ||
d45de409 | 658 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
659 | } |
660 | ||
8a25a2fd KS |
661 | static ssize_t pf_show(struct device *dev, |
662 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
663 | { |
664 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
665 | ||
d45de409 | 666 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
667 | } |
668 | ||
6cbaefb4 | 669 | static DEVICE_ATTR_WO(reload); |
8a25a2fd KS |
670 | static DEVICE_ATTR(version, 0400, version_show, NULL); |
671 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
672 | |
673 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
674 | &dev_attr_version.attr, |
675 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
676 | NULL |
677 | }; | |
678 | ||
45bd07ad | 679 | static const struct attribute_group mc_attr_group = { |
871b72dd DA |
680 | .attrs = mc_default_attrs, |
681 | .name = "microcode", | |
3e135d88 PO |
682 | }; |
683 | ||
871b72dd | 684 | static void microcode_fini_cpu(int cpu) |
d45de409 | 685 | { |
06b8534c BP |
686 | if (microcode_ops->microcode_fini_cpu) |
687 | microcode_ops->microcode_fini_cpu(cpu); | |
280a9ca5 DA |
688 | } |
689 | ||
871b72dd | 690 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 691 | { |
bb9d3e47 BP |
692 | if (apply_microcode_on_target(cpu)) |
693 | return UCODE_ERROR; | |
871b72dd | 694 | |
6b14b818 BP |
695 | pr_debug("CPU%d updated upon resume\n", cpu); |
696 | ||
871b72dd | 697 | return UCODE_OK; |
d45de409 DA |
698 | } |
699 | ||
48e30685 | 700 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 701 | { |
871b72dd | 702 | enum ucode_state ustate; |
9cd4d78e FY |
703 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
704 | ||
43858f57 | 705 | if (uci->valid) |
9cd4d78e | 706 | return UCODE_OK; |
d45de409 | 707 | |
871b72dd DA |
708 | if (collect_cpu_info(cpu)) |
709 | return UCODE_ERROR; | |
d45de409 | 710 | |
871b72dd DA |
711 | /* --dimm. Trigger a delayed update? */ |
712 | if (system_state != SYSTEM_RUNNING) | |
713 | return UCODE_NFOUND; | |
d45de409 | 714 | |
2613f36e BP |
715 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, refresh_fw); |
716 | if (ustate == UCODE_NEW) { | |
f58e1f53 | 717 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 718 | apply_microcode_on_target(cpu); |
d45de409 DA |
719 | } |
720 | ||
871b72dd | 721 | return ustate; |
d45de409 DA |
722 | } |
723 | ||
871b72dd | 724 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 725 | { |
871b72dd | 726 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 727 | |
7f709d0c BP |
728 | /* Refresh CPU microcode revision after resume. */ |
729 | collect_cpu_info(cpu); | |
730 | ||
2f99f5c8 | 731 | if (uci->valid) |
bb9d3e47 | 732 | return microcode_resume_cpu(cpu); |
d45de409 | 733 | |
48e30685 | 734 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
735 | } |
736 | ||
8a25a2fd | 737 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 738 | { |
8a25a2fd | 739 | int err, cpu = dev->id; |
3e135d88 PO |
740 | |
741 | if (!cpu_online(cpu)) | |
742 | return 0; | |
743 | ||
f58e1f53 | 744 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 745 | |
8a25a2fd | 746 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
747 | if (err) |
748 | return err; | |
749 | ||
48e30685 | 750 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 751 | return -EINVAL; |
af5c820a RR |
752 | |
753 | return err; | |
3e135d88 PO |
754 | } |
755 | ||
71db87ba | 756 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 757 | { |
8a25a2fd | 758 | int cpu = dev->id; |
3e135d88 PO |
759 | |
760 | if (!cpu_online(cpu)) | |
71db87ba | 761 | return; |
3e135d88 | 762 | |
f58e1f53 | 763 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 764 | microcode_fini_cpu(cpu); |
8a25a2fd | 765 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
766 | } |
767 | ||
8a25a2fd KS |
768 | static struct subsys_interface mc_cpu_interface = { |
769 | .name = "microcode", | |
770 | .subsys = &cpu_subsys, | |
771 | .add_dev = mc_device_add, | |
772 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
773 | }; |
774 | ||
775 | /** | |
776 | * mc_bp_resume - Update boot CPU microcode during resume. | |
777 | */ | |
778 | static void mc_bp_resume(void) | |
3e135d88 | 779 | { |
f3c6ea1b | 780 | int cpu = smp_processor_id(); |
871b72dd | 781 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 782 | |
871b72dd DA |
783 | if (uci->valid && uci->mc) |
784 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 785 | else if (!uci->mc) |
fbae4ba8 | 786 | reload_early_microcode(); |
3e135d88 PO |
787 | } |
788 | ||
f3c6ea1b RW |
789 | static struct syscore_ops mc_syscore_ops = { |
790 | .resume = mc_bp_resume, | |
3e135d88 PO |
791 | }; |
792 | ||
29bd7fbc | 793 | static int mc_cpu_online(unsigned int cpu) |
3e135d88 | 794 | { |
8a25a2fd | 795 | struct device *dev; |
3e135d88 | 796 | |
8a25a2fd | 797 | dev = get_cpu_device(cpu); |
29bd7fbc SAS |
798 | microcode_update_cpu(cpu); |
799 | pr_debug("CPU%d added\n", cpu); | |
09c3f0d8 | 800 | |
29bd7fbc SAS |
801 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
802 | pr_err("Failed to create group for CPU%d\n", cpu); | |
803 | return 0; | |
804 | } | |
09c3f0d8 | 805 | |
29bd7fbc SAS |
806 | static int mc_cpu_down_prep(unsigned int cpu) |
807 | { | |
808 | struct device *dev; | |
70989449 | 809 | |
29bd7fbc SAS |
810 | dev = get_cpu_device(cpu); |
811 | /* Suspend is in progress, only remove the interface */ | |
812 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | |
813 | pr_debug("CPU%d removed\n", cpu); | |
06b8534c | 814 | |
29bd7fbc | 815 | return 0; |
3e135d88 PO |
816 | } |
817 | ||
3d8986bc BP |
818 | static struct attribute *cpu_root_microcode_attrs[] = { |
819 | &dev_attr_reload.attr, | |
820 | NULL | |
821 | }; | |
822 | ||
45bd07ad | 823 | static const struct attribute_group cpu_root_microcode_group = { |
3d8986bc BP |
824 | .name = "microcode", |
825 | .attrs = cpu_root_microcode_attrs, | |
826 | }; | |
827 | ||
9a2bc335 | 828 | int __init microcode_init(void) |
3e135d88 | 829 | { |
9a2bc335 | 830 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
831 | int error; |
832 | ||
84aba677 | 833 | if (dis_ucode_ldr) |
da63865a | 834 | return -EINVAL; |
65cef131 | 835 | |
18dbc916 DA |
836 | if (c->x86_vendor == X86_VENDOR_INTEL) |
837 | microcode_ops = init_intel_microcode(); | |
82b07865 | 838 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 839 | microcode_ops = init_amd_microcode(); |
283c1f25 | 840 | else |
f58e1f53 | 841 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
842 | |
843 | if (!microcode_ops) | |
18dbc916 | 844 | return -ENODEV; |
3e135d88 | 845 | |
3e135d88 PO |
846 | microcode_pdev = platform_device_register_simple("microcode", -1, |
847 | NULL, 0); | |
bd399063 | 848 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 849 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
850 | |
851 | get_online_cpus(); | |
871b72dd DA |
852 | mutex_lock(µcode_mutex); |
853 | ||
8a25a2fd | 854 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
855 | if (!error) |
856 | perf_check_microcode(); | |
871b72dd | 857 | mutex_unlock(µcode_mutex); |
3e135d88 | 858 | put_online_cpus(); |
871b72dd | 859 | |
bd399063 SB |
860 | if (error) |
861 | goto out_pdev; | |
3e135d88 | 862 | |
3d8986bc BP |
863 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
864 | &cpu_root_microcode_group); | |
865 | ||
866 | if (error) { | |
867 | pr_err("Error creating microcode group!\n"); | |
868 | goto out_driver; | |
869 | } | |
870 | ||
871b72dd DA |
871 | error = microcode_dev_init(); |
872 | if (error) | |
3d8986bc | 873 | goto out_ucode_group; |
871b72dd | 874 | |
f3c6ea1b | 875 | register_syscore_ops(&mc_syscore_ops); |
ecec31ce | 876 | cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:online", |
29bd7fbc | 877 | mc_cpu_online, mc_cpu_down_prep); |
8d86f390 | 878 | |
14cfbe55 | 879 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); |
8d86f390 | 880 | |
3e135d88 | 881 | return 0; |
bd399063 | 882 | |
3d8986bc BP |
883 | out_ucode_group: |
884 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
885 | &cpu_root_microcode_group); | |
886 | ||
887 | out_driver: | |
bd399063 SB |
888 | get_online_cpus(); |
889 | mutex_lock(µcode_mutex); | |
890 | ||
ff4b8a57 | 891 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
892 | |
893 | mutex_unlock(µcode_mutex); | |
894 | put_online_cpus(); | |
895 | ||
3d8986bc | 896 | out_pdev: |
bd399063 SB |
897 | platform_device_unregister(microcode_pdev); |
898 | return error; | |
899 | ||
3e135d88 | 900 | } |
4b703305 | 901 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 902 | late_initcall(microcode_init); |