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KVM: SVM: Don't allow nested guest to VMMCALL into host
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4 44#include <trace/events/kvm.h>
2ed152af 45
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
6866b83e
CO		 227u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
228{
229 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 230 return vcpu->arch.apic_base;
6866b83e 231 else
ad312c7c 232 return vcpu->arch.apic_base;
6866b83e
CO		 233}
234EXPORT_SYMBOL_GPL(kvm_get_apic_base);
235
236void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
237{
238 /* TODO: reserve bits check */
239 if (irqchip_in_kernel(vcpu->kvm))
240 kvm_lapic_set_base(vcpu, data);
241 else
ad312c7c 242 vcpu->arch.apic_base = data;
6866b83e
CO		 243}
244EXPORT_SYMBOL_GPL(kvm_set_apic_base);
245
3fd28fce
ED		 246#define EXCPT_BENIGN 0
247#define EXCPT_CONTRIBUTORY 1
248#define EXCPT_PF 2
249
250static int exception_class(int vector)
251{
252 switch (vector) {
253 case PF_VECTOR:
254 return EXCPT_PF;
255 case DE_VECTOR:
256 case TS_VECTOR:
257 case NP_VECTOR:
258 case SS_VECTOR:
259 case GP_VECTOR:
260 return EXCPT_CONTRIBUTORY;
261 default:
262 break;
263 }
264 return EXCPT_BENIGN;
265}
266
267static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 268 unsigned nr, bool has_error, u32 error_code,
269 bool reinject)
3fd28fce
ED		 270{
271 u32 prev_nr;
272 int class1, class2;
273
274 if (!vcpu->arch.exception.pending) {
275 queue:
276 vcpu->arch.exception.pending = true;
277 vcpu->arch.exception.has_error_code = has_error;
278 vcpu->arch.exception.nr = nr;
279 vcpu->arch.exception.error_code = error_code;
3f0fd292 280 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 281 return;
282 }
283
284 /* to check exception */
285 prev_nr = vcpu->arch.exception.nr;
286 if (prev_nr == DF_VECTOR) {
287 /* triple fault -> shutdown */
288 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
289 return;
290 }
291 class1 = exception_class(prev_nr);
292 class2 = exception_class(nr);
293 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
294 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
295 /* generate double fault per SDM Table 5-5 */
296 vcpu->arch.exception.pending = true;
297 vcpu->arch.exception.has_error_code = true;
298 vcpu->arch.exception.nr = DF_VECTOR;
299 vcpu->arch.exception.error_code = 0;
300 } else
301 /* replace previous exception with a new one in a hope
302 that instruction re-execution will regenerate lost
303 exception */
304 goto queue;
305}
306
298101da
AK		 307void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
308{
ce7ddec4 309 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 310}
311EXPORT_SYMBOL_GPL(kvm_queue_exception);
312
ce7ddec4
JR		 313void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
315 kvm_multiple_exception(vcpu, nr, false, 0, true);
316}
317EXPORT_SYMBOL_GPL(kvm_requeue_exception);
318
c3c91fee
AK		 319void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
320 u32 error_code)
321{
322 ++vcpu->stat.pf_guest;
ad312c7c 323 vcpu->arch.cr2 = addr;
c3c91fee
AK		 324 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
325}
326
3419ffc8
SY		 327void kvm_inject_nmi(struct kvm_vcpu *vcpu)
328{
329 vcpu->arch.nmi_pending = 1;
330}
331EXPORT_SYMBOL_GPL(kvm_inject_nmi);
332
298101da
AK		 333void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
334{
ce7ddec4 335 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
338
ce7ddec4
JR		 339void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
340{
341 kvm_multiple_exception(vcpu, nr, true, error_code, true);
342}
343EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
344
0a79b009
AK		 345/*
346 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
347 * a #GP and return false.
348 */
349bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 350{
0a79b009
AK		 351 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
352 return true;
353 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
354 return false;
298101da 355}
0a79b009 356EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 357
a03490ed
CO		 358/*
359 * Load the pae pdptrs. Return true is they are all valid.
360 */
361int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
362{
363 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
364 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
365 int i;
366 int ret;
ad312c7c 367 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 368
a03490ed
CO		 369 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
370 offset * sizeof(u64), sizeof(pdpte));
371 if (ret < 0) {
372 ret = 0;
373 goto out;
374 }
375 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 376 if (is_present_gpte(pdpte[i]) &&
20c466b5 377 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 378 ret = 0;
379 goto out;
380 }
381 }
382 ret = 1;
383
ad312c7c 384 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 385 __set_bit(VCPU_EXREG_PDPTR,
386 (unsigned long *)&vcpu->arch.regs_avail);
387 __set_bit(VCPU_EXREG_PDPTR,
388 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 389out:
a03490ed
CO		 390
391 return ret;
392}
cc4b6871 393EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 394
d835dfec
AK		 395static bool pdptrs_changed(struct kvm_vcpu *vcpu)
396{
ad312c7c 397 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 398 bool changed = true;
399 int r;
400
401 if (is_long_mode(vcpu) || !is_pae(vcpu))
402 return false;
403
6de4f3ad
AK		 404 if (!test_bit(VCPU_EXREG_PDPTR,
405 (unsigned long *)&vcpu->arch.regs_avail))
406 return true;
407
ad312c7c 408 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 409 if (r < 0)
410 goto out;
ad312c7c 411 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 412out:
d835dfec
AK		 413
414 return changed;
415}
416
2d3ad1f4 417void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 418{
f9a48e6a
AK		 419 cr0 |= X86_CR0_ET;
420
ab344828
GN		 421#ifdef CONFIG_X86_64
422 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 424 return;
425 }
ab344828
GN		 426#endif
427
428 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 429
430 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 431 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 432 return;
433 }
434
435 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
439
440 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
441#ifdef CONFIG_X86_64
f6801dff 442 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 443 int cs_db, cs_l;
444
445 if (!is_pae(vcpu)) {
c1a5d4f9 446 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 447 return;
448 }
449 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
450 if (cs_l) {
c1a5d4f9 451 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 452 return;
453
454 }
455 } else
456#endif
ad312c7c 457 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 458 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 459 return;
460 }
461
462 }
463
464 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 465
a03490ed 466 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 467 return;
468}
2d3ad1f4 469EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 470
2d3ad1f4 471void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 472{
4d4ec087 473 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 474}
2d3ad1f4 475EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 476
2d3ad1f4 477void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 478{
fc78f519 479 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 480 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
481
a03490ed 482 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 483 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 484 return;
485 }
486
487 if (is_long_mode(vcpu)) {
488 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 490 return;
491 }
a2edf57f
AK		 492 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
493 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 494 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 495 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 496 return;
497 }
498
499 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 500 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 501 return;
502 }
503 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 504 vcpu->arch.cr4 = cr4;
a03490ed 505 kvm_mmu_reset_context(vcpu);
a03490ed 506}
2d3ad1f4 507EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 508
2d3ad1f4 509void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 510{
ad312c7c 511 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 512 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 513 kvm_mmu_flush_tlb(vcpu);
514 return;
515 }
516
a03490ed
CO		 517 if (is_long_mode(vcpu)) {
518 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 519 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 520 return;
521 }
522 } else {
523 if (is_pae(vcpu)) {
524 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 529 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 530 return;
531 }
532 }
533 /*
534 * We don't check reserved bits in nonpae mode, because
535 * this isn't enforced, and VMware depends on this.
536 */
537 }
538
a03490ed
CO		 539 /*
540 * Does the new cr3 value map to physical memory? (Note, we
541 * catch an invalid cr3 even in real-mode, because it would
542 * cause trouble later on when we turn on paging anyway.)
543 *
544 * A real CPU would silently accept an invalid cr3 and would
545 * attempt to use it - with largely undefined (and often hard
546 * to debug) behavior on the guest side.
547 */
548 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 549 kvm_inject_gp(vcpu, 0);
a03490ed 550 else {
ad312c7c
ZX		 551 vcpu->arch.cr3 = cr3;
552 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 553 }
a03490ed 554}
2d3ad1f4 555EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 556
2d3ad1f4 557void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 558{
559 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 if (irqchip_in_kernel(vcpu->kvm))
564 kvm_lapic_set_tpr(vcpu, cr8);
565 else
ad312c7c 566 vcpu->arch.cr8 = cr8;
a03490ed 567}
2d3ad1f4 568EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 569
2d3ad1f4 570unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 571{
572 if (irqchip_in_kernel(vcpu->kvm))
573 return kvm_lapic_get_cr8(vcpu);
574 else
ad312c7c 575 return vcpu->arch.cr8;
a03490ed 576}
2d3ad1f4 577EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 578
020df079
GN		 579int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
580{
581 switch (dr) {
582 case 0 ... 3:
583 vcpu->arch.db[dr] = val;
584 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
585 vcpu->arch.eff_db[dr] = val;
586 break;
587 case 4:
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
589 kvm_queue_exception(vcpu, UD_VECTOR);
590 return 1;
591 }
592 /* fall through */
593 case 6:
594 if (val & 0xffffffff00000000ULL) {
595 kvm_inject_gp(vcpu, 0);
596 return 1;
597 }
598 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
599 break;
600 case 5:
601 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
602 kvm_queue_exception(vcpu, UD_VECTOR);
603 return 1;
604 }
605 /* fall through */
606 default: /* 7 */
607 if (val & 0xffffffff00000000ULL) {
608 kvm_inject_gp(vcpu, 0);
609 return 1;
610 }
611 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
612 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
613 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
614 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
615 }
616 break;
617 }
618
619 return 0;
620}
621EXPORT_SYMBOL_GPL(kvm_set_dr);
622
623int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
624{
625 switch (dr) {
626 case 0 ... 3:
627 *val = vcpu->arch.db[dr];
628 break;
629 case 4:
630 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
631 kvm_queue_exception(vcpu, UD_VECTOR);
632 return 1;
633 }
634 /* fall through */
635 case 6:
636 *val = vcpu->arch.dr6;
637 break;
638 case 5:
639 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
640 kvm_queue_exception(vcpu, UD_VECTOR);
641 return 1;
642 }
643 /* fall through */
644 default: /* 7 */
645 *val = vcpu->arch.dr7;
646 break;
647 }
648
649 return 0;
650}
651EXPORT_SYMBOL_GPL(kvm_get_dr);
652
d8017474
AG		 653static inline u32 bit(int bitno)
654{
655 return 1 << (bitno & 31);
656}
657
043405e1
CO		 658/*
659 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
660 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
661 *
662 * This list is modified at module load time to reflect the
e3267cbb
GC		 663 * capabilities of the host cpu. This capabilities test skips MSRs that are
664 * kvm-specific. Those are put in the beginning of the list.
043405e1 665 */
e3267cbb 666
10388a07 667#define KVM_SAVE_MSRS_BEGIN 5
043405e1 668static u32 msrs_to_save[] = {
e3267cbb 669 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 670 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 671 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 672 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
673 MSR_K6_STAR,
674#ifdef CONFIG_X86_64
675 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
676#endif
e3267cbb 677 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 678};
679
680static unsigned num_msrs_to_save;
681
682static u32 emulated_msrs[] = {
683 MSR_IA32_MISC_ENABLE,
684};
685
15c4a640
CO		 686static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
687{
f2b4b7dd 688 if (efer & efer_reserved_bits) {
c1a5d4f9 689 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 690 return;
691 }
692
693 if (is_paging(vcpu)
f6801dff 694 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 695 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 696 return;
697 }
698
1b2fd70c
AG		 699 if (efer & EFER_FFXSR) {
700 struct kvm_cpuid_entry2 *feat;
701
702 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
703 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 704 kvm_inject_gp(vcpu, 0);
705 return;
706 }
707 }
708
d8017474
AG		 709 if (efer & EFER_SVME) {
710 struct kvm_cpuid_entry2 *feat;
711
712 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
713 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 714 kvm_inject_gp(vcpu, 0);
715 return;
716 }
717 }
718
15c4a640
CO		 719 kvm_x86_ops->set_efer(vcpu, efer);
720
721 efer &= ~EFER_LMA;
f6801dff 722 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 723
f6801dff 724 vcpu->arch.efer = efer;
9645bb56
AK		 725
726 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
727 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 728}
729
f2b4b7dd
JR		 730void kvm_enable_efer_bits(u64 mask)
731{
732 efer_reserved_bits &= ~mask;
733}
734EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
735
736
15c4a640
CO		 737/*
738 * Writes msr value into into the appropriate "register".
739 * Returns 0 on success, non-0 otherwise.
740 * Assumes vcpu_load() was already called.
741 */
742int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
743{
744 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
745}
746
313a3dc7
CO		 747/*
748 * Adapt set_msr() to msr_io()'s calling convention
749 */
750static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
751{
752 return kvm_set_msr(vcpu, index, *data);
753}
754
18068523
GOC		 755static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
756{
9ed3c444
AK		 757 int version;
758 int r;
50d0a0f9 759 struct pvclock_wall_clock wc;
923de3cf 760 struct timespec boot;
18068523
GOC		 761
762 if (!wall_clock)
763 return;
764
9ed3c444
AK		 765 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
766 if (r)
767 return;
768
769 if (version & 1)
770 ++version; /* first time write, random junk */
771
772 ++version;
18068523 773
18068523
GOC		 774 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
775
50d0a0f9
GH		 776 /*
777 * The guest calculates current wall clock time by adding
778 * system time (updated by kvm_write_guest_time below) to the
779 * wall clock specified here. guest system time equals host
780 * system time for us, thus we must fill in host boot time here.
781 */
923de3cf 782 getboottime(&boot);
50d0a0f9
GH		 783
784 wc.sec = boot.tv_sec;
785 wc.nsec = boot.tv_nsec;
786 wc.version = version;
18068523
GOC		 787
788 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
789
790 version++;
791 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 792}
793
50d0a0f9
GH		 794static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
795{
796 uint32_t quotient, remainder;
797
798 /* Don't try to replace with do_div(), this one calculates
799 * "(dividend << 32) / divisor" */
800 __asm__ ( "divl %4"
801 : "=a" (quotient), "=d" (remainder)
802 : "0" (0), "1" (dividend), "r" (divisor) );
803 return quotient;
804}
805
806static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
807{
808 uint64_t nsecs = 1000000000LL;
809 int32_t shift = 0;
810 uint64_t tps64;
811 uint32_t tps32;
812
813 tps64 = tsc_khz * 1000LL;
814 while (tps64 > nsecs*2) {
815 tps64 >>= 1;
816 shift--;
817 }
818
819 tps32 = (uint32_t)tps64;
820 while (tps32 <= (uint32_t)nsecs) {
821 tps32 <<= 1;
822 shift++;
823 }
824
825 hv_clock->tsc_shift = shift;
826 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
827
828 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 829 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 830 hv_clock->tsc_to_system_mul);
831}
832
c8076604
GH		 833static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
834
18068523
GOC		 835static void kvm_write_guest_time(struct kvm_vcpu *v)
836{
837 struct timespec ts;
838 unsigned long flags;
839 struct kvm_vcpu_arch *vcpu = &v->arch;
840 void *shared_kaddr;
463656c0 841 unsigned long this_tsc_khz;
18068523
GOC		 842
843 if ((!vcpu->time_page))
844 return;
845
463656c0
AK		 846 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
847 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
848 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
849 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 850 }
463656c0 851 put_cpu_var(cpu_tsc_khz);
50d0a0f9 852
18068523
GOC		 853 /* Keep irq disabled to prevent changes to the clock */
854 local_irq_save(flags);
af24a4e4 855 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 856 ktime_get_ts(&ts);
923de3cf 857 monotonic_to_bootbased(&ts);
18068523
GOC		 858 local_irq_restore(flags);
859
860 /* With all the info we got, fill in the values */
861
862 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 863 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
864
18068523
GOC		 865 /*
866 * The interface expects us to write an even number signaling that the
867 * update is finished. Since the guest won't see the intermediate
50d0a0f9 868 * state, we just increase by 2 at the end.
18068523 869 */
50d0a0f9 870 vcpu->hv_clock.version += 2;
18068523
GOC		 871
872 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
873
874 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 875 sizeof(vcpu->hv_clock));
18068523
GOC		 876
877 kunmap_atomic(shared_kaddr, KM_USER0);
878
879 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
880}
881
c8076604
GH		 882static int kvm_request_guest_time_update(struct kvm_vcpu *v)
883{
884 struct kvm_vcpu_arch *vcpu = &v->arch;
885
886 if (!vcpu->time_page)
887 return 0;
888 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
889 return 1;
890}
891
9ba075a6
AK		 892static bool msr_mtrr_valid(unsigned msr)
893{
894 switch (msr) {
895 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
896 case MSR_MTRRfix64K_00000:
897 case MSR_MTRRfix16K_80000:
898 case MSR_MTRRfix16K_A0000:
899 case MSR_MTRRfix4K_C0000:
900 case MSR_MTRRfix4K_C8000:
901 case MSR_MTRRfix4K_D0000:
902 case MSR_MTRRfix4K_D8000:
903 case MSR_MTRRfix4K_E0000:
904 case MSR_MTRRfix4K_E8000:
905 case MSR_MTRRfix4K_F0000:
906 case MSR_MTRRfix4K_F8000:
907 case MSR_MTRRdefType:
908 case MSR_IA32_CR_PAT:
909 return true;
910 case 0x2f8:
911 return true;
912 }
913 return false;
914}
915
d6289b93
MT		 916static bool valid_pat_type(unsigned t)
917{
918 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
919}
920
921static bool valid_mtrr_type(unsigned t)
922{
923 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
924}
925
926static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
927{
928 int i;
929
930 if (!msr_mtrr_valid(msr))
931 return false;
932
933 if (msr == MSR_IA32_CR_PAT) {
934 for (i = 0; i < 8; i++)
935 if (!valid_pat_type((data >> (i * 8)) & 0xff))
936 return false;
937 return true;
938 } else if (msr == MSR_MTRRdefType) {
939 if (data & ~0xcff)
940 return false;
941 return valid_mtrr_type(data & 0xff);
942 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
943 for (i = 0; i < 8 ; i++)
944 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
945 return false;
946 return true;
947 }
948
949 /* variable MTRRs */
950 return valid_mtrr_type(data & 0xff);
951}
952
9ba075a6
AK		 953static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
954{
0bed3b56
SY		 955 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
956
d6289b93 957 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 958 return 1;
959
0bed3b56
SY		 960 if (msr == MSR_MTRRdefType) {
961 vcpu->arch.mtrr_state.def_type = data;
962 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
963 } else if (msr == MSR_MTRRfix64K_00000)
964 p[0] = data;
965 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
966 p[1 + msr - MSR_MTRRfix16K_80000] = data;
967 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
968 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
969 else if (msr == MSR_IA32_CR_PAT)
970 vcpu->arch.pat = data;
971 else { /* Variable MTRRs */
972 int idx, is_mtrr_mask;
973 u64 *pt;
974
975 idx = (msr - 0x200) / 2;
976 is_mtrr_mask = msr - 0x200 - 2 * idx;
977 if (!is_mtrr_mask)
978 pt =
979 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
980 else
981 pt =
982 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
983 *pt = data;
984 }
985
986 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 987 return 0;
988}
15c4a640 989
890ca9ae 990static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 991{
890ca9ae
HY		 992 u64 mcg_cap = vcpu->arch.mcg_cap;
993 unsigned bank_num = mcg_cap & 0xff;
994
15c4a640 995 switch (msr) {
15c4a640 996 case MSR_IA32_MCG_STATUS:
890ca9ae 997 vcpu->arch.mcg_status = data;
15c4a640 998 break;
c7ac679c 999 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1000 if (!(mcg_cap & MCG_CTL_P))
1001 return 1;
1002 if (data != 0 && data != ~(u64)0)
1003 return -1;
1004 vcpu->arch.mcg_ctl = data;
1005 break;
1006 default:
1007 if (msr >= MSR_IA32_MC0_CTL &&
1008 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1009 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1010 /* only 0 or all 1s can be written to IA32_MCi_CTL
1011 * some Linux kernels though clear bit 10 in bank 4 to
1012 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1013 * this to avoid an uncatched #GP in the guest
1014 */
890ca9ae 1015 if ((offset & 0x3) == 0 &&
114be429 1016 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1017 return -1;
1018 vcpu->arch.mce_banks[offset] = data;
1019 break;
1020 }
1021 return 1;
1022 }
1023 return 0;
1024}
1025
ffde22ac
ES		 1026static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1027{
1028 struct kvm *kvm = vcpu->kvm;
1029 int lm = is_long_mode(vcpu);
1030 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1031 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1032 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1033 : kvm->arch.xen_hvm_config.blob_size_32;
1034 u32 page_num = data & ~PAGE_MASK;
1035 u64 page_addr = data & PAGE_MASK;
1036 u8 *page;
1037 int r;
1038
1039 r = -E2BIG;
1040 if (page_num >= blob_size)
1041 goto out;
1042 r = -ENOMEM;
1043 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1044 if (!page)
1045 goto out;
1046 r = -EFAULT;
1047 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1048 goto out_free;
1049 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1050 goto out_free;
1051 r = 0;
1052out_free:
1053 kfree(page);
1054out:
1055 return r;
1056}
1057
55cd8e5a
GN		 1058static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1059{
1060 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1061}
1062
1063static bool kvm_hv_msr_partition_wide(u32 msr)
1064{
1065 bool r = false;
1066 switch (msr) {
1067 case HV_X64_MSR_GUEST_OS_ID:
1068 case HV_X64_MSR_HYPERCALL:
1069 r = true;
1070 break;
1071 }
1072
1073 return r;
1074}
1075
1076static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1077{
1078 struct kvm *kvm = vcpu->kvm;
1079
1080 switch (msr) {
1081 case HV_X64_MSR_GUEST_OS_ID:
1082 kvm->arch.hv_guest_os_id = data;
1083 /* setting guest os id to zero disables hypercall page */
1084 if (!kvm->arch.hv_guest_os_id)
1085 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1086 break;
1087 case HV_X64_MSR_HYPERCALL: {
1088 u64 gfn;
1089 unsigned long addr;
1090 u8 instructions[4];
1091
1092 /* if guest os id is not set hypercall should remain disabled */
1093 if (!kvm->arch.hv_guest_os_id)
1094 break;
1095 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1096 kvm->arch.hv_hypercall = data;
1097 break;
1098 }
1099 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1100 addr = gfn_to_hva(kvm, gfn);
1101 if (kvm_is_error_hva(addr))
1102 return 1;
1103 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1104 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1105 if (copy_to_user((void __user *)addr, instructions, 4))
1106 return 1;
1107 kvm->arch.hv_hypercall = data;
1108 break;
1109 }
1110 default:
1111 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1112 "data 0x%llx\n", msr, data);
1113 return 1;
1114 }
1115 return 0;
1116}
1117
1118static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1119{
10388a07
GN		 1120 switch (msr) {
1121 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1122 unsigned long addr;
55cd8e5a 1123
10388a07
GN		 1124 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1125 vcpu->arch.hv_vapic = data;
1126 break;
1127 }
1128 addr = gfn_to_hva(vcpu->kvm, data >>
1129 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1130 if (kvm_is_error_hva(addr))
1131 return 1;
1132 if (clear_user((void __user *)addr, PAGE_SIZE))
1133 return 1;
1134 vcpu->arch.hv_vapic = data;
1135 break;
1136 }
1137 case HV_X64_MSR_EOI:
1138 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1139 case HV_X64_MSR_ICR:
1140 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1141 case HV_X64_MSR_TPR:
1142 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1143 default:
1144 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1145 "data 0x%llx\n", msr, data);
1146 return 1;
1147 }
1148
1149 return 0;
55cd8e5a
GN		 1150}
1151
15c4a640
CO		 1152int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1153{
1154 switch (msr) {
15c4a640
CO		 1155 case MSR_EFER:
1156 set_efer(vcpu, data);
1157 break;
8f1589d9
AP		 1158 case MSR_K7_HWCR:
1159 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1160 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1161 if (data != 0) {
1162 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1163 data);
1164 return 1;
1165 }
15c4a640 1166 break;
f7c6d140
AP		 1167 case MSR_FAM10H_MMIO_CONF_BASE:
1168 if (data != 0) {
1169 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1170 "0x%llx\n", data);
1171 return 1;
1172 }
15c4a640 1173 break;
c323c0e5 1174 case MSR_AMD64_NB_CFG:
c7ac679c 1175 break;
b5e2fec0
AG		 1176 case MSR_IA32_DEBUGCTLMSR:
1177 if (!data) {
1178 /* We support the non-activated case already */
1179 break;
1180 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1181 /* Values other than LBR and BTF are vendor-specific,
1182 thus reserved and should throw a #GP */
1183 return 1;
1184 }
1185 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1186 __func__, data);
1187 break;
15c4a640
CO		 1188 case MSR_IA32_UCODE_REV:
1189 case MSR_IA32_UCODE_WRITE:
61a6bd67 1190 case MSR_VM_HSAVE_PA:
6098ca93 1191 case MSR_AMD64_PATCH_LOADER:
15c4a640 1192 break;
9ba075a6
AK		 1193 case 0x200 ... 0x2ff:
1194 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1195 case MSR_IA32_APICBASE:
1196 kvm_set_apic_base(vcpu, data);
1197 break;
0105d1a5
GN		 1198 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1199 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1200 case MSR_IA32_MISC_ENABLE:
ad312c7c 1201 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1202 break;
18068523
GOC		 1203 case MSR_KVM_WALL_CLOCK:
1204 vcpu->kvm->arch.wall_clock = data;
1205 kvm_write_wall_clock(vcpu->kvm, data);
1206 break;
1207 case MSR_KVM_SYSTEM_TIME: {
1208 if (vcpu->arch.time_page) {
1209 kvm_release_page_dirty(vcpu->arch.time_page);
1210 vcpu->arch.time_page = NULL;
1211 }
1212
1213 vcpu->arch.time = data;
1214
1215 /* we verify if the enable bit is set... */
1216 if (!(data & 1))
1217 break;
1218
1219 /* ...but clean it before doing the actual write */
1220 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1221
18068523
GOC		 1222 vcpu->arch.time_page =
1223 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1224
1225 if (is_error_page(vcpu->arch.time_page)) {
1226 kvm_release_page_clean(vcpu->arch.time_page);
1227 vcpu->arch.time_page = NULL;
1228 }
1229
c8076604 1230 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1231 break;
1232 }
890ca9ae
HY		 1233 case MSR_IA32_MCG_CTL:
1234 case MSR_IA32_MCG_STATUS:
1235 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1236 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1237
1238 /* Performance counters are not protected by a CPUID bit,
1239 * so we should check all of them in the generic path for the sake of
1240 * cross vendor migration.
1241 * Writing a zero into the event select MSRs disables them,
1242 * which we perfectly emulate ;-). Any other value should be at least
1243 * reported, some guests depend on them.
1244 */
1245 case MSR_P6_EVNTSEL0:
1246 case MSR_P6_EVNTSEL1:
1247 case MSR_K7_EVNTSEL0:
1248 case MSR_K7_EVNTSEL1:
1249 case MSR_K7_EVNTSEL2:
1250 case MSR_K7_EVNTSEL3:
1251 if (data != 0)
1252 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1253 "0x%x data 0x%llx\n", msr, data);
1254 break;
1255 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1256 * so we ignore writes to make it happy.
1257 */
1258 case MSR_P6_PERFCTR0:
1259 case MSR_P6_PERFCTR1:
1260 case MSR_K7_PERFCTR0:
1261 case MSR_K7_PERFCTR1:
1262 case MSR_K7_PERFCTR2:
1263 case MSR_K7_PERFCTR3:
1264 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1265 "0x%x data 0x%llx\n", msr, data);
1266 break;
55cd8e5a
GN		 1267 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1268 if (kvm_hv_msr_partition_wide(msr)) {
1269 int r;
1270 mutex_lock(&vcpu->kvm->lock);
1271 r = set_msr_hyperv_pw(vcpu, msr, data);
1272 mutex_unlock(&vcpu->kvm->lock);
1273 return r;
1274 } else
1275 return set_msr_hyperv(vcpu, msr, data);
1276 break;
15c4a640 1277 default:
ffde22ac
ES		 1278 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1279 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1280 if (!ignore_msrs) {
1281 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1282 msr, data);
1283 return 1;
1284 } else {
1285 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1286 msr, data);
1287 break;
1288 }
15c4a640
CO		 1289 }
1290 return 0;
1291}
1292EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1293
1294
1295/*
1296 * Reads an msr value (of 'msr_index') into 'pdata'.
1297 * Returns 0 on success, non-0 otherwise.
1298 * Assumes vcpu_load() was already called.
1299 */
1300int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1301{
1302 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1303}
1304
9ba075a6
AK		 1305static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1306{
0bed3b56
SY		 1307 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1308
9ba075a6
AK		 1309 if (!msr_mtrr_valid(msr))
1310 return 1;
1311
0bed3b56
SY		 1312 if (msr == MSR_MTRRdefType)
1313 *pdata = vcpu->arch.mtrr_state.def_type +
1314 (vcpu->arch.mtrr_state.enabled << 10);
1315 else if (msr == MSR_MTRRfix64K_00000)
1316 *pdata = p[0];
1317 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1318 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1319 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1320 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1321 else if (msr == MSR_IA32_CR_PAT)
1322 *pdata = vcpu->arch.pat;
1323 else { /* Variable MTRRs */
1324 int idx, is_mtrr_mask;
1325 u64 *pt;
1326
1327 idx = (msr - 0x200) / 2;
1328 is_mtrr_mask = msr - 0x200 - 2 * idx;
1329 if (!is_mtrr_mask)
1330 pt =
1331 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1332 else
1333 pt =
1334 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1335 *pdata = *pt;
1336 }
1337
9ba075a6
AK		 1338 return 0;
1339}
1340
890ca9ae 1341static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1342{
1343 u64 data;
890ca9ae
HY		 1344 u64 mcg_cap = vcpu->arch.mcg_cap;
1345 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1346
1347 switch (msr) {
15c4a640
CO		 1348 case MSR_IA32_P5_MC_ADDR:
1349 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1350 data = 0;
1351 break;
15c4a640 1352 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1353 data = vcpu->arch.mcg_cap;
1354 break;
c7ac679c 1355 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1356 if (!(mcg_cap & MCG_CTL_P))
1357 return 1;
1358 data = vcpu->arch.mcg_ctl;
1359 break;
1360 case MSR_IA32_MCG_STATUS:
1361 data = vcpu->arch.mcg_status;
1362 break;
1363 default:
1364 if (msr >= MSR_IA32_MC0_CTL &&
1365 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1366 u32 offset = msr - MSR_IA32_MC0_CTL;
1367 data = vcpu->arch.mce_banks[offset];
1368 break;
1369 }
1370 return 1;
1371 }
1372 *pdata = data;
1373 return 0;
1374}
1375
55cd8e5a
GN		 1376static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1377{
1378 u64 data = 0;
1379 struct kvm *kvm = vcpu->kvm;
1380
1381 switch (msr) {
1382 case HV_X64_MSR_GUEST_OS_ID:
1383 data = kvm->arch.hv_guest_os_id;
1384 break;
1385 case HV_X64_MSR_HYPERCALL:
1386 data = kvm->arch.hv_hypercall;
1387 break;
1388 default:
1389 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1390 return 1;
1391 }
1392
1393 *pdata = data;
1394 return 0;
1395}
1396
1397static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1398{
1399 u64 data = 0;
1400
1401 switch (msr) {
1402 case HV_X64_MSR_VP_INDEX: {
1403 int r;
1404 struct kvm_vcpu *v;
1405 kvm_for_each_vcpu(r, v, vcpu->kvm)
1406 if (v == vcpu)
1407 data = r;
1408 break;
1409 }
10388a07
GN		 1410 case HV_X64_MSR_EOI:
1411 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1412 case HV_X64_MSR_ICR:
1413 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1414 case HV_X64_MSR_TPR:
1415 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1416 default:
1417 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1418 return 1;
1419 }
1420 *pdata = data;
1421 return 0;
1422}
1423
890ca9ae
HY		 1424int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1425{
1426 u64 data;
1427
1428 switch (msr) {
890ca9ae 1429 case MSR_IA32_PLATFORM_ID:
15c4a640 1430 case MSR_IA32_UCODE_REV:
15c4a640 1431 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1432 case MSR_IA32_DEBUGCTLMSR:
1433 case MSR_IA32_LASTBRANCHFROMIP:
1434 case MSR_IA32_LASTBRANCHTOIP:
1435 case MSR_IA32_LASTINTFROMIP:
1436 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1437 case MSR_K8_SYSCFG:
1438 case MSR_K7_HWCR:
61a6bd67 1439 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1440 case MSR_P6_PERFCTR0:
1441 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1442 case MSR_P6_EVNTSEL0:
1443 case MSR_P6_EVNTSEL1:
9e699624 1444 case MSR_K7_EVNTSEL0:
1f3ee616 1445 case MSR_K7_PERFCTR0:
1fdbd48c 1446 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1447 case MSR_AMD64_NB_CFG:
f7c6d140 1448 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1449 data = 0;
1450 break;
9ba075a6
AK		 1451 case MSR_MTRRcap:
1452 data = 0x500 | KVM_NR_VAR_MTRR;
1453 break;
1454 case 0x200 ... 0x2ff:
1455 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1456 case 0xcd: /* fsb frequency */
1457 data = 3;
1458 break;
1459 case MSR_IA32_APICBASE:
1460 data = kvm_get_apic_base(vcpu);
1461 break;
0105d1a5
GN		 1462 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1463 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1464 break;
15c4a640 1465 case MSR_IA32_MISC_ENABLE:
ad312c7c 1466 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1467 break;
847f0ad8
AG		 1468 case MSR_IA32_PERF_STATUS:
1469 /* TSC increment by tick */
1470 data = 1000ULL;
1471 /* CPU multiplier */
1472 data |= (((uint64_t)4ULL) << 40);
1473 break;
15c4a640 1474 case MSR_EFER:
f6801dff 1475 data = vcpu->arch.efer;
15c4a640 1476 break;
18068523
GOC		 1477 case MSR_KVM_WALL_CLOCK:
1478 data = vcpu->kvm->arch.wall_clock;
1479 break;
1480 case MSR_KVM_SYSTEM_TIME:
1481 data = vcpu->arch.time;
1482 break;
890ca9ae
HY		 1483 case MSR_IA32_P5_MC_ADDR:
1484 case MSR_IA32_P5_MC_TYPE:
1485 case MSR_IA32_MCG_CAP:
1486 case MSR_IA32_MCG_CTL:
1487 case MSR_IA32_MCG_STATUS:
1488 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1489 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1490 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1491 if (kvm_hv_msr_partition_wide(msr)) {
1492 int r;
1493 mutex_lock(&vcpu->kvm->lock);
1494 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1495 mutex_unlock(&vcpu->kvm->lock);
1496 return r;
1497 } else
1498 return get_msr_hyperv(vcpu, msr, pdata);
1499 break;
15c4a640 1500 default:
ed85c068
AP		 1501 if (!ignore_msrs) {
1502 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1503 return 1;
1504 } else {
1505 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1506 data = 0;
1507 }
1508 break;
15c4a640
CO		 1509 }
1510 *pdata = data;
1511 return 0;
1512}
1513EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1514
313a3dc7
CO		 1515/*
1516 * Read or write a bunch of msrs. All parameters are kernel addresses.
1517 *
1518 * @return number of msrs set successfully.
1519 */
1520static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1521 struct kvm_msr_entry *entries,
1522 int (*do_msr)(struct kvm_vcpu *vcpu,
1523 unsigned index, u64 *data))
1524{
f656ce01 1525 int i, idx;
313a3dc7
CO		 1526
1527 vcpu_load(vcpu);
1528
f656ce01 1529 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1530 for (i = 0; i < msrs->nmsrs; ++i)
1531 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1532 break;
f656ce01 1533 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1534
1535 vcpu_put(vcpu);
1536
1537 return i;
1538}
1539
1540/*
1541 * Read or write a bunch of msrs. Parameters are user addresses.
1542 *
1543 * @return number of msrs set successfully.
1544 */
1545static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1546 int (*do_msr)(struct kvm_vcpu *vcpu,
1547 unsigned index, u64 *data),
1548 int writeback)
1549{
1550 struct kvm_msrs msrs;
1551 struct kvm_msr_entry *entries;
1552 int r, n;
1553 unsigned size;
1554
1555 r = -EFAULT;
1556 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1557 goto out;
1558
1559 r = -E2BIG;
1560 if (msrs.nmsrs >= MAX_IO_MSRS)
1561 goto out;
1562
1563 r = -ENOMEM;
1564 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1565 entries = vmalloc(size);
1566 if (!entries)
1567 goto out;
1568
1569 r = -EFAULT;
1570 if (copy_from_user(entries, user_msrs->entries, size))
1571 goto out_free;
1572
1573 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1574 if (r < 0)
1575 goto out_free;
1576
1577 r = -EFAULT;
1578 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1579 goto out_free;
1580
1581 r = n;
1582
1583out_free:
1584 vfree(entries);
1585out:
1586 return r;
1587}
1588
018d00d2
ZX		 1589int kvm_dev_ioctl_check_extension(long ext)
1590{
1591 int r;
1592
1593 switch (ext) {
1594 case KVM_CAP_IRQCHIP:
1595 case KVM_CAP_HLT:
1596 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1597 case KVM_CAP_SET_TSS_ADDR:
07716717 1598 case KVM_CAP_EXT_CPUID:
c8076604 1599 case KVM_CAP_CLOCKSOURCE:
7837699f 1600 case KVM_CAP_PIT:
a28e4f5a 1601 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1602 case KVM_CAP_MP_STATE:
ed848624 1603 case KVM_CAP_SYNC_MMU:
52d939a0 1604 case KVM_CAP_REINJECT_CONTROL:
4925663a 1605 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1606 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1607 case KVM_CAP_IRQFD:
d34e6b17 1608 case KVM_CAP_IOEVENTFD:
c5ff41ce 1609 case KVM_CAP_PIT2:
e9f42757 1610 case KVM_CAP_PIT_STATE2:
b927a3ce 1611 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1612 case KVM_CAP_XEN_HVM:
afbcf7ab 1613 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1614 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1615 case KVM_CAP_HYPERV:
10388a07 1616 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1617 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1618 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1619 case KVM_CAP_DEBUGREGS:
d2be1651 1620 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1621 r = 1;
1622 break;
542472b5
LV		 1623 case KVM_CAP_COALESCED_MMIO:
1624 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1625 break;
774ead3a
AK		 1626 case KVM_CAP_VAPIC:
1627 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1628 break;
f725230a
AK		 1629 case KVM_CAP_NR_VCPUS:
1630 r = KVM_MAX_VCPUS;
1631 break;
a988b910
AK		 1632 case KVM_CAP_NR_MEMSLOTS:
1633 r = KVM_MEMORY_SLOTS;
1634 break;
a68a6a72
MT		 1635 case KVM_CAP_PV_MMU: /* obsolete */
1636 r = 0;
2f333bcb 1637 break;
62c476c7 1638 case KVM_CAP_IOMMU:
19de40a8 1639 r = iommu_found();
62c476c7 1640 break;
890ca9ae
HY		 1641 case KVM_CAP_MCE:
1642 r = KVM_MAX_MCE_BANKS;
1643 break;
018d00d2
ZX		 1644 default:
1645 r = 0;
1646 break;
1647 }
1648 return r;
1649
1650}
1651
043405e1
CO		 1652long kvm_arch_dev_ioctl(struct file *filp,
1653 unsigned int ioctl, unsigned long arg)
1654{
1655 void __user *argp = (void __user *)arg;
1656 long r;
1657
1658 switch (ioctl) {
1659 case KVM_GET_MSR_INDEX_LIST: {
1660 struct kvm_msr_list __user *user_msr_list = argp;
1661 struct kvm_msr_list msr_list;
1662 unsigned n;
1663
1664 r = -EFAULT;
1665 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1666 goto out;
1667 n = msr_list.nmsrs;
1668 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1669 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1670 goto out;
1671 r = -E2BIG;
e125e7b6 1672 if (n < msr_list.nmsrs)
043405e1
CO		 1673 goto out;
1674 r = -EFAULT;
1675 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1676 num_msrs_to_save * sizeof(u32)))
1677 goto out;
e125e7b6 1678 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1679 &emulated_msrs,
1680 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1681 goto out;
1682 r = 0;
1683 break;
1684 }
674eea0f
AK		 1685 case KVM_GET_SUPPORTED_CPUID: {
1686 struct kvm_cpuid2 __user *cpuid_arg = argp;
1687 struct kvm_cpuid2 cpuid;
1688
1689 r = -EFAULT;
1690 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1691 goto out;
1692 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1693 cpuid_arg->entries);
674eea0f
AK		 1694 if (r)
1695 goto out;
1696
1697 r = -EFAULT;
1698 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1699 goto out;
1700 r = 0;
1701 break;
1702 }
890ca9ae
HY		 1703 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1704 u64 mce_cap;
1705
1706 mce_cap = KVM_MCE_CAP_SUPPORTED;
1707 r = -EFAULT;
1708 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1709 goto out;
1710 r = 0;
1711 break;
1712 }
043405e1
CO		 1713 default:
1714 r = -EINVAL;
1715 }
1716out:
1717 return r;
1718}
1719
313a3dc7
CO		 1720void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1721{
1722 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1723 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1724 unsigned long khz = cpufreq_quick_get(cpu);
1725 if (!khz)
1726 khz = tsc_khz;
1727 per_cpu(cpu_tsc_khz, cpu) = khz;
1728 }
c8076604 1729 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1730}
1731
1732void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1733{
9327fd11 1734 kvm_put_guest_fpu(vcpu);
02daab21 1735 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1736}
1737
07716717 1738static int is_efer_nx(void)
313a3dc7 1739{
e286e86e 1740 unsigned long long efer = 0;
313a3dc7 1741
e286e86e 1742 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1743 return efer & EFER_NX;
1744}
1745
1746static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1747{
1748 int i;
1749 struct kvm_cpuid_entry2 *e, *entry;
1750
313a3dc7 1751 entry = NULL;
ad312c7c
ZX		 1752 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1753 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1754 if (e->function == 0x80000001) {
1755 entry = e;
1756 break;
1757 }
1758 }
07716717 1759 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1760 entry->edx &= ~(1 << 20);
1761 printk(KERN_INFO "kvm: guest NX capability removed\n");
1762 }
1763}
1764
07716717 1765/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1766static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1767 struct kvm_cpuid *cpuid,
1768 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1769{
1770 int r, i;
1771 struct kvm_cpuid_entry *cpuid_entries;
1772
1773 r = -E2BIG;
1774 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1775 goto out;
1776 r = -ENOMEM;
1777 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1778 if (!cpuid_entries)
1779 goto out;
1780 r = -EFAULT;
1781 if (copy_from_user(cpuid_entries, entries,
1782 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1783 goto out_free;
1784 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1785 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1786 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1787 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1788 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1789 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1790 vcpu->arch.cpuid_entries[i].index = 0;
1791 vcpu->arch.cpuid_entries[i].flags = 0;
1792 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1793 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1794 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1795 }
1796 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1797 cpuid_fix_nx_cap(vcpu);
1798 r = 0;
fc61b800 1799 kvm_apic_set_version(vcpu);
0e851880 1800 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1801
1802out_free:
1803 vfree(cpuid_entries);
1804out:
1805 return r;
1806}
1807
1808static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1809 struct kvm_cpuid2 *cpuid,
1810 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1811{
1812 int r;
1813
1814 r = -E2BIG;
1815 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1816 goto out;
1817 r = -EFAULT;
ad312c7c 1818 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1819 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1820 goto out;
ad312c7c 1821 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1822 kvm_apic_set_version(vcpu);
0e851880 1823 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1824 return 0;
1825
1826out:
1827 return r;
1828}
1829
07716717 1830static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1831 struct kvm_cpuid2 *cpuid,
1832 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1833{
1834 int r;
1835
1836 r = -E2BIG;
ad312c7c 1837 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1838 goto out;
1839 r = -EFAULT;
ad312c7c 1840 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1841 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1842 goto out;
1843 return 0;
1844
1845out:
ad312c7c 1846 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1847 return r;
1848}
1849
07716717 1850static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1851 u32 index)
07716717
DK		 1852{
1853 entry->function = function;
1854 entry->index = index;
1855 cpuid_count(entry->function, entry->index,
19355475 1856 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1857 entry->flags = 0;
1858}
1859
7faa4ee1
AK		 1860#define F(x) bit(X86_FEATURE_##x)
1861
07716717
DK		 1862static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1863 u32 index, int *nent, int maxnent)
1864{
7faa4ee1 1865 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1866#ifdef CONFIG_X86_64
17cc3935
SY		 1867 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1868 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1869 unsigned f_lm = F(LM);
1870#else
17cc3935 1871 unsigned f_gbpages = 0;
7faa4ee1 1872 unsigned f_lm = 0;
07716717 1873#endif
4e47c7a6 1874 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1875
1876 /* cpuid 1.edx */
1877 const u32 kvm_supported_word0_x86_features =
1878 F(FPU) | F(VME) | F(DE) | F(PSE) |
1879 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1880 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1881 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1882 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1883 0 /* Reserved, DS, ACPI */ | F(MMX) |
1884 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1885 0 /* HTT, TM, Reserved, PBE */;
1886 /* cpuid 0x80000001.edx */
1887 const u32 kvm_supported_word1_x86_features =
1888 F(FPU) | F(VME) | F(DE) | F(PSE) |
1889 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1890 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1891 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1892 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1893 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1894 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1895 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1896 /* cpuid 1.ecx */
1897 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1898 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1899 0 /* DS-CPL, VMX, SMX, EST */ |
1900 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1901 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1902 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1903 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1904 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1905 /* cpuid 0x80000001.ecx */
07716717 1906 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1907 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1908 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1909 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1910 0 /* SKINIT */ | 0 /* WDT */;
07716717 1911
19355475 1912 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1913 get_cpu();
1914 do_cpuid_1_ent(entry, function, index);
1915 ++*nent;
1916
1917 switch (function) {
1918 case 0:
1919 entry->eax = min(entry->eax, (u32)0xb);
1920 break;
1921 case 1:
1922 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1923 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1924 /* we support x2apic emulation even if host does not support
1925 * it since we emulate x2apic in software */
1926 entry->ecx |= F(X2APIC);
07716717
DK		 1927 break;
1928 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1929 * may return different values. This forces us to get_cpu() before
1930 * issuing the first command, and also to emulate this annoying behavior
1931 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1932 case 2: {
1933 int t, times = entry->eax & 0xff;
1934
1935 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1936 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1937 for (t = 1; t < times && *nent < maxnent; ++t) {
1938 do_cpuid_1_ent(&entry[t], function, 0);
1939 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1940 ++*nent;
1941 }
1942 break;
1943 }
1944 /* function 4 and 0xb have additional index. */
1945 case 4: {
14af3f3c 1946 int i, cache_type;
07716717
DK		 1947
1948 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1949 /* read more entries until cache_type is zero */
14af3f3c
HH		 1950 for (i = 1; *nent < maxnent; ++i) {
1951 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1952 if (!cache_type)
1953 break;
14af3f3c
HH		 1954 do_cpuid_1_ent(&entry[i], function, i);
1955 entry[i].flags |=
07716717
DK		 1956 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1957 ++*nent;
1958 }
1959 break;
1960 }
1961 case 0xb: {
14af3f3c 1962 int i, level_type;
07716717
DK		 1963
1964 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1965 /* read more entries until level_type is zero */
14af3f3c 1966 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1967 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1968 if (!level_type)
1969 break;
14af3f3c
HH		 1970 do_cpuid_1_ent(&entry[i], function, i);
1971 entry[i].flags |=
07716717
DK		 1972 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1973 ++*nent;
1974 }
1975 break;
1976 }
1977 case 0x80000000:
1978 entry->eax = min(entry->eax, 0x8000001a);
1979 break;
1980 case 0x80000001:
1981 entry->edx &= kvm_supported_word1_x86_features;
1982 entry->ecx &= kvm_supported_word6_x86_features;
1983 break;
1984 }
d4330ef2
JR		 1985
1986 kvm_x86_ops->set_supported_cpuid(function, entry);
1987
07716717
DK		 1988 put_cpu();
1989}
1990
7faa4ee1
AK		 1991#undef F
1992
674eea0f 1993static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1994 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1995{
1996 struct kvm_cpuid_entry2 *cpuid_entries;
1997 int limit, nent = 0, r = -E2BIG;
1998 u32 func;
1999
2000 if (cpuid->nent < 1)
2001 goto out;
6a544355
AK		 2002 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2003 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2004 r = -ENOMEM;
2005 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2006 if (!cpuid_entries)
2007 goto out;
2008
2009 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2010 limit = cpuid_entries[0].eax;
2011 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2012 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2013 &nent, cpuid->nent);
07716717
DK		 2014 r = -E2BIG;
2015 if (nent >= cpuid->nent)
2016 goto out_free;
2017
2018 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2019 limit = cpuid_entries[nent - 1].eax;
2020 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2021 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2022 &nent, cpuid->nent);
cb007648
MM		 2023 r = -E2BIG;
2024 if (nent >= cpuid->nent)
2025 goto out_free;
2026
07716717
DK		 2027 r = -EFAULT;
2028 if (copy_to_user(entries, cpuid_entries,
19355475 2029 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2030 goto out_free;
2031 cpuid->nent = nent;
2032 r = 0;
2033
2034out_free:
2035 vfree(cpuid_entries);
2036out:
2037 return r;
2038}
2039
313a3dc7
CO		 2040static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2041 struct kvm_lapic_state *s)
2042{
2043 vcpu_load(vcpu);
ad312c7c 2044 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2045 vcpu_put(vcpu);
2046
2047 return 0;
2048}
2049
2050static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2051 struct kvm_lapic_state *s)
2052{
2053 vcpu_load(vcpu);
ad312c7c 2054 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2055 kvm_apic_post_state_restore(vcpu);
cb142eb7 2056 update_cr8_intercept(vcpu);
313a3dc7
CO		 2057 vcpu_put(vcpu);
2058
2059 return 0;
2060}
2061
f77bc6a4
ZX		 2062static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2063 struct kvm_interrupt *irq)
2064{
2065 if (irq->irq < 0 || irq->irq >= 256)
2066 return -EINVAL;
2067 if (irqchip_in_kernel(vcpu->kvm))
2068 return -ENXIO;
2069 vcpu_load(vcpu);
2070
66fd3f7f 2071 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2072
2073 vcpu_put(vcpu);
2074
2075 return 0;
2076}
2077
c4abb7c9
JK		 2078static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2079{
2080 vcpu_load(vcpu);
2081 kvm_inject_nmi(vcpu);
2082 vcpu_put(vcpu);
2083
2084 return 0;
2085}
2086
b209749f
AK		 2087static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2088 struct kvm_tpr_access_ctl *tac)
2089{
2090 if (tac->flags)
2091 return -EINVAL;
2092 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2093 return 0;
2094}
2095
890ca9ae
HY		 2096static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2097 u64 mcg_cap)
2098{
2099 int r;
2100 unsigned bank_num = mcg_cap & 0xff, bank;
2101
2102 r = -EINVAL;
a9e38c3e 2103 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2104 goto out;
2105 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2106 goto out;
2107 r = 0;
2108 vcpu->arch.mcg_cap = mcg_cap;
2109 /* Init IA32_MCG_CTL to all 1s */
2110 if (mcg_cap & MCG_CTL_P)
2111 vcpu->arch.mcg_ctl = ~(u64)0;
2112 /* Init IA32_MCi_CTL to all 1s */
2113 for (bank = 0; bank < bank_num; bank++)
2114 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2115out:
2116 return r;
2117}
2118
2119static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2120 struct kvm_x86_mce *mce)
2121{
2122 u64 mcg_cap = vcpu->arch.mcg_cap;
2123 unsigned bank_num = mcg_cap & 0xff;
2124 u64 *banks = vcpu->arch.mce_banks;
2125
2126 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2127 return -EINVAL;
2128 /*
2129 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2130 * reporting is disabled
2131 */
2132 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2133 vcpu->arch.mcg_ctl != ~(u64)0)
2134 return 0;
2135 banks += 4 * mce->bank;
2136 /*
2137 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2138 * reporting is disabled for the bank
2139 */
2140 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2141 return 0;
2142 if (mce->status & MCI_STATUS_UC) {
2143 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2144 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2145 printk(KERN_DEBUG "kvm: set_mce: "
2146 "injects mce exception while "
2147 "previous one is in progress!\n");
2148 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2149 return 0;
2150 }
2151 if (banks[1] & MCI_STATUS_VAL)
2152 mce->status |= MCI_STATUS_OVER;
2153 banks[2] = mce->addr;
2154 banks[3] = mce->misc;
2155 vcpu->arch.mcg_status = mce->mcg_status;
2156 banks[1] = mce->status;
2157 kvm_queue_exception(vcpu, MC_VECTOR);
2158 } else if (!(banks[1] & MCI_STATUS_VAL)
2159 || !(banks[1] & MCI_STATUS_UC)) {
2160 if (banks[1] & MCI_STATUS_VAL)
2161 mce->status |= MCI_STATUS_OVER;
2162 banks[2] = mce->addr;
2163 banks[3] = mce->misc;
2164 banks[1] = mce->status;
2165 } else
2166 banks[1] |= MCI_STATUS_OVER;
2167 return 0;
2168}
2169
3cfc3092
JK		 2170static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2171 struct kvm_vcpu_events *events)
2172{
2173 vcpu_load(vcpu);
2174
03b82a30
JK		 2175 events->exception.injected =
2176 vcpu->arch.exception.pending &&
2177 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2178 events->exception.nr = vcpu->arch.exception.nr;
2179 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2180 events->exception.error_code = vcpu->arch.exception.error_code;
2181
03b82a30
JK		 2182 events->interrupt.injected =
2183 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2184 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2185 events->interrupt.soft = 0;
48005f64
JK		 2186 events->interrupt.shadow =
2187 kvm_x86_ops->get_interrupt_shadow(vcpu,
2188 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2189
2190 events->nmi.injected = vcpu->arch.nmi_injected;
2191 events->nmi.pending = vcpu->arch.nmi_pending;
2192 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2193
2194 events->sipi_vector = vcpu->arch.sipi_vector;
2195
dab4b911 2196 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2197 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2198 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2199
2200 vcpu_put(vcpu);
2201}
2202
2203static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2204 struct kvm_vcpu_events *events)
2205{
dab4b911 2206 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2207 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2208 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2209 return -EINVAL;
2210
2211 vcpu_load(vcpu);
2212
2213 vcpu->arch.exception.pending = events->exception.injected;
2214 vcpu->arch.exception.nr = events->exception.nr;
2215 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2216 vcpu->arch.exception.error_code = events->exception.error_code;
2217
2218 vcpu->arch.interrupt.pending = events->interrupt.injected;
2219 vcpu->arch.interrupt.nr = events->interrupt.nr;
2220 vcpu->arch.interrupt.soft = events->interrupt.soft;
2221 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2222 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2223 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2224 kvm_x86_ops->set_interrupt_shadow(vcpu,
2225 events->interrupt.shadow);
3cfc3092
JK		 2226
2227 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2228 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2229 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2230 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2231
dab4b911
JK		 2232 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2233 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2234
2235 vcpu_put(vcpu);
2236
2237 return 0;
2238}
2239
a1efbe77
JK		 2240static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2241 struct kvm_debugregs *dbgregs)
2242{
2243 vcpu_load(vcpu);
2244
2245 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2246 dbgregs->dr6 = vcpu->arch.dr6;
2247 dbgregs->dr7 = vcpu->arch.dr7;
2248 dbgregs->flags = 0;
2249
2250 vcpu_put(vcpu);
2251}
2252
2253static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2254 struct kvm_debugregs *dbgregs)
2255{
2256 if (dbgregs->flags)
2257 return -EINVAL;
2258
2259 vcpu_load(vcpu);
2260
2261 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2262 vcpu->arch.dr6 = dbgregs->dr6;
2263 vcpu->arch.dr7 = dbgregs->dr7;
2264
2265 vcpu_put(vcpu);
2266
2267 return 0;
2268}
2269
313a3dc7
CO		 2270long kvm_arch_vcpu_ioctl(struct file *filp,
2271 unsigned int ioctl, unsigned long arg)
2272{
2273 struct kvm_vcpu *vcpu = filp->private_data;
2274 void __user *argp = (void __user *)arg;
2275 int r;
b772ff36 2276 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2277
2278 switch (ioctl) {
2279 case KVM_GET_LAPIC: {
2204ae3c
MT		 2280 r = -EINVAL;
2281 if (!vcpu->arch.apic)
2282 goto out;
b772ff36 2283 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2284
b772ff36
DH		 2285 r = -ENOMEM;
2286 if (!lapic)
2287 goto out;
2288 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2289 if (r)
2290 goto out;
2291 r = -EFAULT;
b772ff36 2292 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2293 goto out;
2294 r = 0;
2295 break;
2296 }
2297 case KVM_SET_LAPIC: {
2204ae3c
MT		 2298 r = -EINVAL;
2299 if (!vcpu->arch.apic)
2300 goto out;
b772ff36
DH		 2301 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2302 r = -ENOMEM;
2303 if (!lapic)
2304 goto out;
313a3dc7 2305 r = -EFAULT;
b772ff36 2306 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2307 goto out;
b772ff36 2308 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2309 if (r)
2310 goto out;
2311 r = 0;
2312 break;
2313 }
f77bc6a4
ZX		 2314 case KVM_INTERRUPT: {
2315 struct kvm_interrupt irq;
2316
2317 r = -EFAULT;
2318 if (copy_from_user(&irq, argp, sizeof irq))
2319 goto out;
2320 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2321 if (r)
2322 goto out;
2323 r = 0;
2324 break;
2325 }
c4abb7c9
JK		 2326 case KVM_NMI: {
2327 r = kvm_vcpu_ioctl_nmi(vcpu);
2328 if (r)
2329 goto out;
2330 r = 0;
2331 break;
2332 }
313a3dc7
CO		 2333 case KVM_SET_CPUID: {
2334 struct kvm_cpuid __user *cpuid_arg = argp;
2335 struct kvm_cpuid cpuid;
2336
2337 r = -EFAULT;
2338 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2339 goto out;
2340 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2341 if (r)
2342 goto out;
2343 break;
2344 }
07716717
DK		 2345 case KVM_SET_CPUID2: {
2346 struct kvm_cpuid2 __user *cpuid_arg = argp;
2347 struct kvm_cpuid2 cpuid;
2348
2349 r = -EFAULT;
2350 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2351 goto out;
2352 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2353 cpuid_arg->entries);
07716717
DK		 2354 if (r)
2355 goto out;
2356 break;
2357 }
2358 case KVM_GET_CPUID2: {
2359 struct kvm_cpuid2 __user *cpuid_arg = argp;
2360 struct kvm_cpuid2 cpuid;
2361
2362 r = -EFAULT;
2363 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2364 goto out;
2365 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2366 cpuid_arg->entries);
07716717
DK		 2367 if (r)
2368 goto out;
2369 r = -EFAULT;
2370 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2371 goto out;
2372 r = 0;
2373 break;
2374 }
313a3dc7
CO		 2375 case KVM_GET_MSRS:
2376 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2377 break;
2378 case KVM_SET_MSRS:
2379 r = msr_io(vcpu, argp, do_set_msr, 0);
2380 break;
b209749f
AK		 2381 case KVM_TPR_ACCESS_REPORTING: {
2382 struct kvm_tpr_access_ctl tac;
2383
2384 r = -EFAULT;
2385 if (copy_from_user(&tac, argp, sizeof tac))
2386 goto out;
2387 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2388 if (r)
2389 goto out;
2390 r = -EFAULT;
2391 if (copy_to_user(argp, &tac, sizeof tac))
2392 goto out;
2393 r = 0;
2394 break;
2395 };
b93463aa
AK		 2396 case KVM_SET_VAPIC_ADDR: {
2397 struct kvm_vapic_addr va;
2398
2399 r = -EINVAL;
2400 if (!irqchip_in_kernel(vcpu->kvm))
2401 goto out;
2402 r = -EFAULT;
2403 if (copy_from_user(&va, argp, sizeof va))
2404 goto out;
2405 r = 0;
2406 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2407 break;
2408 }
890ca9ae
HY		 2409 case KVM_X86_SETUP_MCE: {
2410 u64 mcg_cap;
2411
2412 r = -EFAULT;
2413 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2414 goto out;
2415 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2416 break;
2417 }
2418 case KVM_X86_SET_MCE: {
2419 struct kvm_x86_mce mce;
2420
2421 r = -EFAULT;
2422 if (copy_from_user(&mce, argp, sizeof mce))
2423 goto out;
2424 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2425 break;
2426 }
3cfc3092
JK		 2427 case KVM_GET_VCPU_EVENTS: {
2428 struct kvm_vcpu_events events;
2429
2430 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2431
2432 r = -EFAULT;
2433 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2434 break;
2435 r = 0;
2436 break;
2437 }
2438 case KVM_SET_VCPU_EVENTS: {
2439 struct kvm_vcpu_events events;
2440
2441 r = -EFAULT;
2442 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2443 break;
2444
2445 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2446 break;
2447 }
a1efbe77
JK		 2448 case KVM_GET_DEBUGREGS: {
2449 struct kvm_debugregs dbgregs;
2450
2451 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2452
2453 r = -EFAULT;
2454 if (copy_to_user(argp, &dbgregs,
2455 sizeof(struct kvm_debugregs)))
2456 break;
2457 r = 0;
2458 break;
2459 }
2460 case KVM_SET_DEBUGREGS: {
2461 struct kvm_debugregs dbgregs;
2462
2463 r = -EFAULT;
2464 if (copy_from_user(&dbgregs, argp,
2465 sizeof(struct kvm_debugregs)))
2466 break;
2467
2468 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2469 break;
2470 }
313a3dc7
CO		 2471 default:
2472 r = -EINVAL;
2473 }
2474out:
7a6ce84c 2475 kfree(lapic);
313a3dc7
CO		 2476 return r;
2477}
2478
1fe779f8
CO		 2479static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2480{
2481 int ret;
2482
2483 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2484 return -1;
2485 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2486 return ret;
2487}
2488
b927a3ce
SY		 2489static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2490 u64 ident_addr)
2491{
2492 kvm->arch.ept_identity_map_addr = ident_addr;
2493 return 0;
2494}
2495
1fe779f8
CO		 2496static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2497 u32 kvm_nr_mmu_pages)
2498{
2499 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2500 return -EINVAL;
2501
79fac95e 2502 mutex_lock(&kvm->slots_lock);
7c8a83b7 2503 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2504
2505 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2506 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2507
7c8a83b7 2508 spin_unlock(&kvm->mmu_lock);
79fac95e 2509 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2510 return 0;
2511}
2512
2513static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2514{
f05e70ac 2515 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2516}
2517
a983fb23
MT		 2518gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2519{
2520 int i;
2521 struct kvm_mem_alias *alias;
2522 struct kvm_mem_aliases *aliases;
2523
90d83dc3 2524 aliases = kvm_aliases(kvm);
a983fb23
MT		 2525
2526 for (i = 0; i < aliases->naliases; ++i) {
2527 alias = &aliases->aliases[i];
2528 if (alias->flags & KVM_ALIAS_INVALID)
2529 continue;
2530 if (gfn >= alias->base_gfn
2531 && gfn < alias->base_gfn + alias->npages)
2532 return alias->target_gfn + gfn - alias->base_gfn;
2533 }
2534 return gfn;
2535}
2536
e9f85cde
ZX		 2537gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2538{
2539 int i;
2540 struct kvm_mem_alias *alias;
a983fb23
MT		 2541 struct kvm_mem_aliases *aliases;
2542
90d83dc3 2543 aliases = kvm_aliases(kvm);
e9f85cde 2544
fef9cce0
MT		 2545 for (i = 0; i < aliases->naliases; ++i) {
2546 alias = &aliases->aliases[i];
e9f85cde
ZX		 2547 if (gfn >= alias->base_gfn
2548 && gfn < alias->base_gfn + alias->npages)
2549 return alias->target_gfn + gfn - alias->base_gfn;
2550 }
2551 return gfn;
2552}
2553
1fe779f8
CO		 2554/*
2555 * Set a new alias region. Aliases map a portion of physical memory into
2556 * another portion. This is useful for memory windows, for example the PC
2557 * VGA region.
2558 */
2559static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2560 struct kvm_memory_alias *alias)
2561{
2562 int r, n;
2563 struct kvm_mem_alias *p;
a983fb23 2564 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2565
2566 r = -EINVAL;
2567 /* General sanity checks */
2568 if (alias->memory_size & (PAGE_SIZE - 1))
2569 goto out;
2570 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2571 goto out;
2572 if (alias->slot >= KVM_ALIAS_SLOTS)
2573 goto out;
2574 if (alias->guest_phys_addr + alias->memory_size
2575 < alias->guest_phys_addr)
2576 goto out;
2577 if (alias->target_phys_addr + alias->memory_size
2578 < alias->target_phys_addr)
2579 goto out;
2580
a983fb23
MT		 2581 r = -ENOMEM;
2582 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2583 if (!aliases)
2584 goto out;
2585
79fac95e 2586 mutex_lock(&kvm->slots_lock);
1fe779f8 2587
a983fb23
MT		 2588 /* invalidate any gfn reference in case of deletion/shrinking */
2589 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2590 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2591 old_aliases = kvm->arch.aliases;
2592 rcu_assign_pointer(kvm->arch.aliases, aliases);
2593 synchronize_srcu_expedited(&kvm->srcu);
2594 kvm_mmu_zap_all(kvm);
2595 kfree(old_aliases);
2596
2597 r = -ENOMEM;
2598 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2599 if (!aliases)
2600 goto out_unlock;
2601
2602 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2603
2604 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2605 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2606 p->npages = alias->memory_size >> PAGE_SHIFT;
2607 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2608 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2609
2610 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2611 if (aliases->aliases[n - 1].npages)
1fe779f8 2612 break;
fef9cce0 2613 aliases->naliases = n;
1fe779f8 2614
a983fb23
MT		 2615 old_aliases = kvm->arch.aliases;
2616 rcu_assign_pointer(kvm->arch.aliases, aliases);
2617 synchronize_srcu_expedited(&kvm->srcu);
2618 kfree(old_aliases);
2619 r = 0;
1fe779f8 2620
a983fb23 2621out_unlock:
79fac95e 2622 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2623out:
2624 return r;
2625}
2626
2627static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2628{
2629 int r;
2630
2631 r = 0;
2632 switch (chip->chip_id) {
2633 case KVM_IRQCHIP_PIC_MASTER:
2634 memcpy(&chip->chip.pic,
2635 &pic_irqchip(kvm)->pics[0],
2636 sizeof(struct kvm_pic_state));
2637 break;
2638 case KVM_IRQCHIP_PIC_SLAVE:
2639 memcpy(&chip->chip.pic,
2640 &pic_irqchip(kvm)->pics[1],
2641 sizeof(struct kvm_pic_state));
2642 break;
2643 case KVM_IRQCHIP_IOAPIC:
eba0226b 2644 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2645 break;
2646 default:
2647 r = -EINVAL;
2648 break;
2649 }
2650 return r;
2651}
2652
2653static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2654{
2655 int r;
2656
2657 r = 0;
2658 switch (chip->chip_id) {
2659 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2660 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2661 memcpy(&pic_irqchip(kvm)->pics[0],
2662 &chip->chip.pic,
2663 sizeof(struct kvm_pic_state));
fa8273e9 2664 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2665 break;
2666 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2667 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2668 memcpy(&pic_irqchip(kvm)->pics[1],
2669 &chip->chip.pic,
2670 sizeof(struct kvm_pic_state));
fa8273e9 2671 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2672 break;
2673 case KVM_IRQCHIP_IOAPIC:
eba0226b 2674 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2675 break;
2676 default:
2677 r = -EINVAL;
2678 break;
2679 }
2680 kvm_pic_update_irq(pic_irqchip(kvm));
2681 return r;
2682}
2683
e0f63cb9
SY		 2684static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2685{
2686 int r = 0;
2687
894a9c55 2688 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2689 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2690 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2691 return r;
2692}
2693
2694static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2695{
2696 int r = 0;
2697
894a9c55 2698 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2699 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2700 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2701 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2702 return r;
2703}
2704
2705static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2706{
2707 int r = 0;
2708
2709 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2710 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2711 sizeof(ps->channels));
2712 ps->flags = kvm->arch.vpit->pit_state.flags;
2713 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2714 return r;
2715}
2716
2717static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2718{
2719 int r = 0, start = 0;
2720 u32 prev_legacy, cur_legacy;
2721 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2722 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2723 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2724 if (!prev_legacy && cur_legacy)
2725 start = 1;
2726 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2727 sizeof(kvm->arch.vpit->pit_state.channels));
2728 kvm->arch.vpit->pit_state.flags = ps->flags;
2729 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2730 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2731 return r;
2732}
2733
52d939a0
MT		 2734static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2735 struct kvm_reinject_control *control)
2736{
2737 if (!kvm->arch.vpit)
2738 return -ENXIO;
894a9c55 2739 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2740 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2741 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2742 return 0;
2743}
2744
5bb064dc
ZX		 2745/*
2746 * Get (and clear) the dirty memory log for a memory slot.
2747 */
2748int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2749 struct kvm_dirty_log *log)
2750{
87bf6e7d 2751 int r, i;
5bb064dc 2752 struct kvm_memory_slot *memslot;
87bf6e7d 2753 unsigned long n;
b050b015
MT		 2754 unsigned long is_dirty = 0;
2755 unsigned long *dirty_bitmap = NULL;
5bb064dc 2756
79fac95e 2757 mutex_lock(&kvm->slots_lock);
5bb064dc 2758
b050b015
MT		 2759 r = -EINVAL;
2760 if (log->slot >= KVM_MEMORY_SLOTS)
2761 goto out;
2762
2763 memslot = &kvm->memslots->memslots[log->slot];
2764 r = -ENOENT;
2765 if (!memslot->dirty_bitmap)
2766 goto out;
2767
87bf6e7d 2768 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2769
2770 r = -ENOMEM;
2771 dirty_bitmap = vmalloc(n);
2772 if (!dirty_bitmap)
5bb064dc 2773 goto out;
b050b015
MT		 2774 memset(dirty_bitmap, 0, n);
2775
2776 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2777 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2778
2779 /* If nothing is dirty, don't bother messing with page tables. */
2780 if (is_dirty) {
b050b015
MT		 2781 struct kvm_memslots *slots, *old_slots;
2782
7c8a83b7 2783 spin_lock(&kvm->mmu_lock);
5bb064dc 2784 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2785 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2786
2787 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2788 if (!slots)
2789 goto out_free;
2790
2791 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2792 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2793
2794 old_slots = kvm->memslots;
2795 rcu_assign_pointer(kvm->memslots, slots);
2796 synchronize_srcu_expedited(&kvm->srcu);
2797 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2798 kfree(old_slots);
5bb064dc 2799 }
b050b015 2800
5bb064dc 2801 r = 0;
b050b015
MT		 2802 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2803 r = -EFAULT;
2804out_free:
2805 vfree(dirty_bitmap);
5bb064dc 2806out:
79fac95e 2807 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2808 return r;
2809}
2810
1fe779f8
CO		 2811long kvm_arch_vm_ioctl(struct file *filp,
2812 unsigned int ioctl, unsigned long arg)
2813{
2814 struct kvm *kvm = filp->private_data;
2815 void __user *argp = (void __user *)arg;
367e1319 2816 int r = -ENOTTY;
f0d66275
DH		 2817 /*
2818 * This union makes it completely explicit to gcc-3.x
2819 * that these two variables' stack usage should be
2820 * combined, not added together.
2821 */
2822 union {
2823 struct kvm_pit_state ps;
e9f42757 2824 struct kvm_pit_state2 ps2;
f0d66275 2825 struct kvm_memory_alias alias;
c5ff41ce 2826 struct kvm_pit_config pit_config;
f0d66275 2827 } u;
1fe779f8
CO		 2828
2829 switch (ioctl) {
2830 case KVM_SET_TSS_ADDR:
2831 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2832 if (r < 0)
2833 goto out;
2834 break;
b927a3ce
SY		 2835 case KVM_SET_IDENTITY_MAP_ADDR: {
2836 u64 ident_addr;
2837
2838 r = -EFAULT;
2839 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2840 goto out;
2841 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2842 if (r < 0)
2843 goto out;
2844 break;
2845 }
1fe779f8
CO		 2846 case KVM_SET_MEMORY_REGION: {
2847 struct kvm_memory_region kvm_mem;
2848 struct kvm_userspace_memory_region kvm_userspace_mem;
2849
2850 r = -EFAULT;
2851 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2852 goto out;
2853 kvm_userspace_mem.slot = kvm_mem.slot;
2854 kvm_userspace_mem.flags = kvm_mem.flags;
2855 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2856 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2857 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2858 if (r)
2859 goto out;
2860 break;
2861 }
2862 case KVM_SET_NR_MMU_PAGES:
2863 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2864 if (r)
2865 goto out;
2866 break;
2867 case KVM_GET_NR_MMU_PAGES:
2868 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2869 break;
f0d66275 2870 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2871 r = -EFAULT;
f0d66275 2872 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2873 goto out;
f0d66275 2874 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2875 if (r)
2876 goto out;
2877 break;
3ddea128
MT		 2878 case KVM_CREATE_IRQCHIP: {
2879 struct kvm_pic *vpic;
2880
2881 mutex_lock(&kvm->lock);
2882 r = -EEXIST;
2883 if (kvm->arch.vpic)
2884 goto create_irqchip_unlock;
1fe779f8 2885 r = -ENOMEM;
3ddea128
MT		 2886 vpic = kvm_create_pic(kvm);
2887 if (vpic) {
1fe779f8
CO		 2888 r = kvm_ioapic_init(kvm);
2889 if (r) {
72bb2fcd
WY		 2890 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2891 &vpic->dev);
3ddea128
MT		 2892 kfree(vpic);
2893 goto create_irqchip_unlock;
1fe779f8
CO		 2894 }
2895 } else
3ddea128
MT		 2896 goto create_irqchip_unlock;
2897 smp_wmb();
2898 kvm->arch.vpic = vpic;
2899 smp_wmb();
399ec807
AK		 2900 r = kvm_setup_default_irq_routing(kvm);
2901 if (r) {
3ddea128 2902 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2903 kvm_ioapic_destroy(kvm);
2904 kvm_destroy_pic(kvm);
3ddea128 2905 mutex_unlock(&kvm->irq_lock);
399ec807 2906 }
3ddea128
MT		 2907 create_irqchip_unlock:
2908 mutex_unlock(&kvm->lock);
1fe779f8 2909 break;
3ddea128 2910 }
7837699f 2911 case KVM_CREATE_PIT:
c5ff41ce
JK		 2912 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2913 goto create_pit;
2914 case KVM_CREATE_PIT2:
2915 r = -EFAULT;
2916 if (copy_from_user(&u.pit_config, argp,
2917 sizeof(struct kvm_pit_config)))
2918 goto out;
2919 create_pit:
79fac95e 2920 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2921 r = -EEXIST;
2922 if (kvm->arch.vpit)
2923 goto create_pit_unlock;
7837699f 2924 r = -ENOMEM;
c5ff41ce 2925 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2926 if (kvm->arch.vpit)
2927 r = 0;
269e05e4 2928 create_pit_unlock:
79fac95e 2929 mutex_unlock(&kvm->slots_lock);
7837699f 2930 break;
4925663a 2931 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2932 case KVM_IRQ_LINE: {
2933 struct kvm_irq_level irq_event;
2934
2935 r = -EFAULT;
2936 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2937 goto out;
160d2f6c 2938 r = -ENXIO;
1fe779f8 2939 if (irqchip_in_kernel(kvm)) {
4925663a 2940 __s32 status;
4925663a
GN		 2941 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2942 irq_event.irq, irq_event.level);
4925663a 2943 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 2944 r = -EFAULT;
4925663a
GN		 2945 irq_event.status = status;
2946 if (copy_to_user(argp, &irq_event,
2947 sizeof irq_event))
2948 goto out;
2949 }
1fe779f8
CO		 2950 r = 0;
2951 }
2952 break;
2953 }
2954 case KVM_GET_IRQCHIP: {
2955 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2956 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2957
f0d66275
DH		 2958 r = -ENOMEM;
2959 if (!chip)
1fe779f8 2960 goto out;
f0d66275
DH		 2961 r = -EFAULT;
2962 if (copy_from_user(chip, argp, sizeof *chip))
2963 goto get_irqchip_out;
1fe779f8
CO		 2964 r = -ENXIO;
2965 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2966 goto get_irqchip_out;
2967 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2968 if (r)
f0d66275 2969 goto get_irqchip_out;
1fe779f8 2970 r = -EFAULT;
f0d66275
DH		 2971 if (copy_to_user(argp, chip, sizeof *chip))
2972 goto get_irqchip_out;
1fe779f8 2973 r = 0;
f0d66275
DH		 2974 get_irqchip_out:
2975 kfree(chip);
2976 if (r)
2977 goto out;
1fe779f8
CO		 2978 break;
2979 }
2980 case KVM_SET_IRQCHIP: {
2981 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2982 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2983
f0d66275
DH		 2984 r = -ENOMEM;
2985 if (!chip)
1fe779f8 2986 goto out;
f0d66275
DH		 2987 r = -EFAULT;
2988 if (copy_from_user(chip, argp, sizeof *chip))
2989 goto set_irqchip_out;
1fe779f8
CO		 2990 r = -ENXIO;
2991 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2992 goto set_irqchip_out;
2993 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2994 if (r)
f0d66275 2995 goto set_irqchip_out;
1fe779f8 2996 r = 0;
f0d66275
DH		 2997 set_irqchip_out:
2998 kfree(chip);
2999 if (r)
3000 goto out;
1fe779f8
CO		 3001 break;
3002 }
e0f63cb9 3003 case KVM_GET_PIT: {
e0f63cb9 3004 r = -EFAULT;
f0d66275 3005 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3006 goto out;
3007 r = -ENXIO;
3008 if (!kvm->arch.vpit)
3009 goto out;
f0d66275 3010 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3011 if (r)
3012 goto out;
3013 r = -EFAULT;
f0d66275 3014 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3015 goto out;
3016 r = 0;
3017 break;
3018 }
3019 case KVM_SET_PIT: {
e0f63cb9 3020 r = -EFAULT;
f0d66275 3021 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3022 goto out;
3023 r = -ENXIO;
3024 if (!kvm->arch.vpit)
3025 goto out;
f0d66275 3026 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3027 if (r)
3028 goto out;
3029 r = 0;
3030 break;
3031 }
e9f42757
BK		 3032 case KVM_GET_PIT2: {
3033 r = -ENXIO;
3034 if (!kvm->arch.vpit)
3035 goto out;
3036 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3037 if (r)
3038 goto out;
3039 r = -EFAULT;
3040 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3041 goto out;
3042 r = 0;
3043 break;
3044 }
3045 case KVM_SET_PIT2: {
3046 r = -EFAULT;
3047 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3048 goto out;
3049 r = -ENXIO;
3050 if (!kvm->arch.vpit)
3051 goto out;
3052 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3053 if (r)
3054 goto out;
3055 r = 0;
3056 break;
3057 }
52d939a0
MT		 3058 case KVM_REINJECT_CONTROL: {
3059 struct kvm_reinject_control control;
3060 r = -EFAULT;
3061 if (copy_from_user(&control, argp, sizeof(control)))
3062 goto out;
3063 r = kvm_vm_ioctl_reinject(kvm, &control);
3064 if (r)
3065 goto out;
3066 r = 0;
3067 break;
3068 }
ffde22ac
ES		 3069 case KVM_XEN_HVM_CONFIG: {
3070 r = -EFAULT;
3071 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3072 sizeof(struct kvm_xen_hvm_config)))
3073 goto out;
3074 r = -EINVAL;
3075 if (kvm->arch.xen_hvm_config.flags)
3076 goto out;
3077 r = 0;
3078 break;
3079 }
afbcf7ab
GC		 3080 case KVM_SET_CLOCK: {
3081 struct timespec now;
3082 struct kvm_clock_data user_ns;
3083 u64 now_ns;
3084 s64 delta;
3085
3086 r = -EFAULT;
3087 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3088 goto out;
3089
3090 r = -EINVAL;
3091 if (user_ns.flags)
3092 goto out;
3093
3094 r = 0;
3095 ktime_get_ts(&now);
3096 now_ns = timespec_to_ns(&now);
3097 delta = user_ns.clock - now_ns;
3098 kvm->arch.kvmclock_offset = delta;
3099 break;
3100 }
3101 case KVM_GET_CLOCK: {
3102 struct timespec now;
3103 struct kvm_clock_data user_ns;
3104 u64 now_ns;
3105
3106 ktime_get_ts(&now);
3107 now_ns = timespec_to_ns(&now);
3108 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3109 user_ns.flags = 0;
3110
3111 r = -EFAULT;
3112 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3113 goto out;
3114 r = 0;
3115 break;
3116 }
3117
1fe779f8
CO		 3118 default:
3119 ;
3120 }
3121out:
3122 return r;
3123}
3124
a16b043c 3125static void kvm_init_msr_list(void)
043405e1
CO		 3126{
3127 u32 dummy[2];
3128 unsigned i, j;
3129
e3267cbb
GC		 3130 /* skip the first msrs in the list. KVM-specific */
3131 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3132 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3133 continue;
3134 if (j < i)
3135 msrs_to_save[j] = msrs_to_save[i];
3136 j++;
3137 }
3138 num_msrs_to_save = j;
3139}
3140
bda9020e
MT		 3141static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3142 const void *v)
bbd9b64e 3143{
bda9020e
MT		 3144 if (vcpu->arch.apic &&
3145 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3146 return 0;
bbd9b64e 3147
e93f8a0f 3148 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3149}
3150
bda9020e 3151static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3152{
bda9020e
MT		 3153 if (vcpu->arch.apic &&
3154 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3155 return 0;
bbd9b64e 3156
e93f8a0f 3157 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3158}
3159
2dafc6c2
GN		 3160static void kvm_set_segment(struct kvm_vcpu *vcpu,
3161 struct kvm_segment *var, int seg)
3162{
3163 kvm_x86_ops->set_segment(vcpu, var, seg);
3164}
3165
3166void kvm_get_segment(struct kvm_vcpu *vcpu,
3167 struct kvm_segment *var, int seg)
3168{
3169 kvm_x86_ops->get_segment(vcpu, var, seg);
3170}
3171
1871c602
GN		 3172gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3173{
3174 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3175 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3176}
3177
3178 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3179{
3180 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3181 access |= PFERR_FETCH_MASK;
3182 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3183}
3184
3185gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3186{
3187 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3188 access |= PFERR_WRITE_MASK;
3189 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3190}
3191
3192/* uses this to access any guest's mapped memory without checking CPL */
3193gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3194{
3195 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3196}
3197
3198static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3199 struct kvm_vcpu *vcpu, u32 access,
3200 u32 *error)
bbd9b64e
CO		 3201{
3202 void *data = val;
10589a46 3203 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3204
3205 while (bytes) {
1871c602 3206 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3207 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3208 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3209 int ret;
3210
10589a46
MT		 3211 if (gpa == UNMAPPED_GVA) {
3212 r = X86EMUL_PROPAGATE_FAULT;
3213 goto out;
3214 }
77c2002e 3215 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3216 if (ret < 0) {
3217 r = X86EMUL_UNHANDLEABLE;
3218 goto out;
3219 }
bbd9b64e 3220
77c2002e
IE		 3221 bytes -= toread;
3222 data += toread;
3223 addr += toread;
bbd9b64e 3224 }
10589a46 3225out:
10589a46 3226 return r;
bbd9b64e 3227}
77c2002e 3228
1871c602
GN		 3229/* used for instruction fetching */
3230static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3231 struct kvm_vcpu *vcpu, u32 *error)
3232{
3233 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3234 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3235 access | PFERR_FETCH_MASK, error);
3236}
3237
3238static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3239 struct kvm_vcpu *vcpu, u32 *error)
3240{
3241 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3242 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3243 error);
3244}
3245
3246static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3247 struct kvm_vcpu *vcpu, u32 *error)
3248{
3249 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3250}
3251
7972995b 3252static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3253 unsigned int bytes,
7972995b 3254 struct kvm_vcpu *vcpu,
2dafc6c2 3255 u32 *error)
77c2002e
IE		 3256{
3257 void *data = val;
3258 int r = X86EMUL_CONTINUE;
3259
3260 while (bytes) {
7972995b
GN		 3261 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr,
3262 PFERR_WRITE_MASK, error);
77c2002e
IE		 3263 unsigned offset = addr & (PAGE_SIZE-1);
3264 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3265 int ret;
3266
3267 if (gpa == UNMAPPED_GVA) {
3268 r = X86EMUL_PROPAGATE_FAULT;
3269 goto out;
3270 }
3271 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3272 if (ret < 0) {
3273 r = X86EMUL_UNHANDLEABLE;
3274 goto out;
3275 }
3276
3277 bytes -= towrite;
3278 data += towrite;
3279 addr += towrite;
3280 }
3281out:
3282 return r;
3283}
3284
bbd9b64e
CO		 3285static int emulator_read_emulated(unsigned long addr,
3286 void *val,
3287 unsigned int bytes,
3288 struct kvm_vcpu *vcpu)
3289{
bbd9b64e 3290 gpa_t gpa;
1871c602 3291 u32 error_code;
bbd9b64e
CO		 3292
3293 if (vcpu->mmio_read_completed) {
3294 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3295 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3296 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3297 vcpu->mmio_read_completed = 0;
3298 return X86EMUL_CONTINUE;
3299 }
3300
1871c602
GN		 3301 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3302
3303 if (gpa == UNMAPPED_GVA) {
3304 kvm_inject_page_fault(vcpu, addr, error_code);
3305 return X86EMUL_PROPAGATE_FAULT;
3306 }
bbd9b64e
CO		 3307
3308 /* For APIC access vmexit */
3309 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3310 goto mmio;
3311
1871c602 3312 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3313 == X86EMUL_CONTINUE)
bbd9b64e 3314 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3315
3316mmio:
3317 /*
3318 * Is this MMIO handled locally?
3319 */
aec51dc4
AK		 3320 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3321 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3322 return X86EMUL_CONTINUE;
3323 }
aec51dc4
AK		 3324
3325 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3326
3327 vcpu->mmio_needed = 1;
3328 vcpu->mmio_phys_addr = gpa;
3329 vcpu->mmio_size = bytes;
3330 vcpu->mmio_is_write = 0;
3331
3332 return X86EMUL_UNHANDLEABLE;
3333}
3334
3200f405 3335int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3336 const void *val, int bytes)
bbd9b64e
CO		 3337{
3338 int ret;
3339
3340 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3341 if (ret < 0)
bbd9b64e 3342 return 0;
ad218f85 3343 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3344 return 1;
3345}
3346
3347static int emulator_write_emulated_onepage(unsigned long addr,
3348 const void *val,
3349 unsigned int bytes,
8f6abd06 3350 struct kvm_vcpu *vcpu)
bbd9b64e 3351{
10589a46 3352 gpa_t gpa;
1871c602 3353 u32 error_code;
10589a46 3354
1871c602 3355 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3356
3357 if (gpa == UNMAPPED_GVA) {
1871c602 3358 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3359 return X86EMUL_PROPAGATE_FAULT;
3360 }
3361
3362 /* For APIC access vmexit */
3363 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3364 goto mmio;
3365
3366 if (emulator_write_phys(vcpu, gpa, val, bytes))
3367 return X86EMUL_CONTINUE;
3368
3369mmio:
aec51dc4 3370 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3371 /*
3372 * Is this MMIO handled locally?
3373 */
bda9020e 3374 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3375 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3376
3377 vcpu->mmio_needed = 1;
3378 vcpu->mmio_phys_addr = gpa;
3379 vcpu->mmio_size = bytes;
3380 vcpu->mmio_is_write = 1;
3381 memcpy(vcpu->mmio_data, val, bytes);
3382
3383 return X86EMUL_CONTINUE;
3384}
3385
8f6abd06
GN		 3386int emulator_write_emulated(unsigned long addr,
3387 const void *val,
3388 unsigned int bytes,
3389 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3390{
3391 /* Crossing a page boundary? */
3392 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3393 int rc, now;
3394
3395 now = -addr & ~PAGE_MASK;
8f6abd06 3396 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
bbd9b64e
CO		 3397 if (rc != X86EMUL_CONTINUE)
3398 return rc;
3399 addr += now;
3400 val += now;
3401 bytes -= now;
3402 }
8f6abd06 3403 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
bbd9b64e
CO		 3404}
3405EXPORT_SYMBOL_GPL(emulator_write_emulated);
3406
daea3e73
AK		 3407#define CMPXCHG_TYPE(t, ptr, old, new) \
3408 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3409
3410#ifdef CONFIG_X86_64
3411# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3412#else
3413# define CMPXCHG64(ptr, old, new) \
9749a6c0 3414 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3415#endif
3416
bbd9b64e
CO		 3417static int emulator_cmpxchg_emulated(unsigned long addr,
3418 const void *old,
3419 const void *new,
3420 unsigned int bytes,
3421 struct kvm_vcpu *vcpu)
3422{
daea3e73
AK		 3423 gpa_t gpa;
3424 struct page *page;
3425 char *kaddr;
3426 bool exchanged;
2bacc55c 3427
daea3e73
AK		 3428 /* guests cmpxchg8b have to be emulated atomically */
3429 if (bytes > 8 || (bytes & (bytes - 1)))
3430 goto emul_write;
10589a46 3431
daea3e73 3432 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3433
daea3e73
AK		 3434 if (gpa == UNMAPPED_GVA ||
3435 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3436 goto emul_write;
2bacc55c 3437
daea3e73
AK		 3438 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3439 goto emul_write;
72dc67a6 3440
daea3e73 3441 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3442
daea3e73
AK		 3443 kaddr = kmap_atomic(page, KM_USER0);
3444 kaddr += offset_in_page(gpa);
3445 switch (bytes) {
3446 case 1:
3447 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3448 break;
3449 case 2:
3450 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3451 break;
3452 case 4:
3453 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3454 break;
3455 case 8:
3456 exchanged = CMPXCHG64(kaddr, old, new);
3457 break;
3458 default:
3459 BUG();
2bacc55c 3460 }
daea3e73
AK		 3461 kunmap_atomic(kaddr, KM_USER0);
3462 kvm_release_page_dirty(page);
3463
3464 if (!exchanged)
3465 return X86EMUL_CMPXCHG_FAILED;
3466
8f6abd06
GN		 3467 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3468
3469 return X86EMUL_CONTINUE;
4a5f48f6 3470
3200f405 3471emul_write:
daea3e73 3472 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3473
bbd9b64e
CO		 3474 return emulator_write_emulated(addr, new, bytes, vcpu);
3475}
3476
cf8f70bf
GN		 3477static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3478{
3479 /* TODO: String I/O for in kernel device */
3480 int r;
3481
3482 if (vcpu->arch.pio.in)
3483 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3484 vcpu->arch.pio.size, pd);
3485 else
3486 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3487 vcpu->arch.pio.port, vcpu->arch.pio.size,
3488 pd);
3489 return r;
3490}
3491
3492
3493static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3494 unsigned int count, struct kvm_vcpu *vcpu)
3495{
7972995b 3496 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3497 goto data_avail;
3498
3499 trace_kvm_pio(1, port, size, 1);
3500
3501 vcpu->arch.pio.port = port;
3502 vcpu->arch.pio.in = 1;
7972995b 3503 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3504 vcpu->arch.pio.size = size;
3505
3506 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3507 data_avail:
3508 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3509 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3510 return 1;
3511 }
3512
3513 vcpu->run->exit_reason = KVM_EXIT_IO;
3514 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3515 vcpu->run->io.size = size;
3516 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3517 vcpu->run->io.count = count;
3518 vcpu->run->io.port = port;
3519
3520 return 0;
3521}
3522
3523static int emulator_pio_out_emulated(int size, unsigned short port,
3524 const void *val, unsigned int count,
3525 struct kvm_vcpu *vcpu)
3526{
3527 trace_kvm_pio(0, port, size, 1);
3528
3529 vcpu->arch.pio.port = port;
3530 vcpu->arch.pio.in = 0;
7972995b 3531 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3532 vcpu->arch.pio.size = size;
3533
3534 memcpy(vcpu->arch.pio_data, val, size * count);
3535
3536 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3537 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3538 return 1;
3539 }
3540
3541 vcpu->run->exit_reason = KVM_EXIT_IO;
3542 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3543 vcpu->run->io.size = size;
3544 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3545 vcpu->run->io.count = count;
3546 vcpu->run->io.port = port;
3547
3548 return 0;
3549}
3550
bbd9b64e
CO		 3551static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3552{
3553 return kvm_x86_ops->get_segment_base(vcpu, seg);
3554}
3555
3556int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3557{
a7052897 3558 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3559 return X86EMUL_CONTINUE;
3560}
3561
3562int emulate_clts(struct kvm_vcpu *vcpu)
3563{
4d4ec087 3564 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3565 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3566 return X86EMUL_CONTINUE;
3567}
3568
3569int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3570{
020df079 3571 return kvm_get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3572}
3573
3574int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3575{
3576 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3577
020df079 3578 return kvm_set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3579}
3580
3581void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3582{
bbd9b64e 3583 u8 opcodes[4];
5fdbf976 3584 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3585 unsigned long rip_linear;
3586
f76c710d 3587 if (!printk_ratelimit())
bbd9b64e
CO		 3588 return;
3589
25be4608
GC		 3590 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3591
1871c602 3592 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3593
3594 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3595 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3596}
3597EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3598
52a46617
GN		 3599static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3600{
3601 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3602}
3603
3604static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
3605{
3606 unsigned long value;
3607
3608 switch (cr) {
3609 case 0:
3610 value = kvm_read_cr0(vcpu);
3611 break;
3612 case 2:
3613 value = vcpu->arch.cr2;
3614 break;
3615 case 3:
3616 value = vcpu->arch.cr3;
3617 break;
3618 case 4:
3619 value = kvm_read_cr4(vcpu);
3620 break;
3621 case 8:
3622 value = kvm_get_cr8(vcpu);
3623 break;
3624 default:
3625 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3626 return 0;
3627 }
3628
3629 return value;
3630}
3631
3632static void emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
3633{
3634 switch (cr) {
3635 case 0:
3636 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
3637 break;
3638 case 2:
3639 vcpu->arch.cr2 = val;
3640 break;
3641 case 3:
3642 kvm_set_cr3(vcpu, val);
3643 break;
3644 case 4:
3645 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3646 break;
3647 case 8:
3648 kvm_set_cr8(vcpu, val & 0xfUL);
3649 break;
3650 default:
3651 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3652 }
3653}
3654
9c537244
GN		 3655static int emulator_get_cpl(struct kvm_vcpu *vcpu)
3656{
3657 return kvm_x86_ops->get_cpl(vcpu);
3658}
3659
2dafc6c2
GN		 3660static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
3661{
3662 kvm_x86_ops->get_gdt(vcpu, dt);
3663}
3664
3665static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
3666 struct kvm_vcpu *vcpu)
3667{
3668 struct kvm_segment var;
3669
3670 kvm_get_segment(vcpu, &var, seg);
3671
3672 if (var.unusable)
3673 return false;
3674
3675 if (var.g)
3676 var.limit >>= 12;
3677 set_desc_limit(desc, var.limit);
3678 set_desc_base(desc, (unsigned long)var.base);
3679 desc->type = var.type;
3680 desc->s = var.s;
3681 desc->dpl = var.dpl;
3682 desc->p = var.present;
3683 desc->avl = var.avl;
3684 desc->l = var.l;
3685 desc->d = var.db;
3686 desc->g = var.g;
3687
3688 return true;
3689}
3690
3691static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
3692 struct kvm_vcpu *vcpu)
3693{
3694 struct kvm_segment var;
3695
3696 /* needed to preserve selector */
3697 kvm_get_segment(vcpu, &var, seg);
3698
3699 var.base = get_desc_base(desc);
3700 var.limit = get_desc_limit(desc);
3701 if (desc->g)
3702 var.limit = (var.limit << 12) | 0xfff;
3703 var.type = desc->type;
3704 var.present = desc->p;
3705 var.dpl = desc->dpl;
3706 var.db = desc->d;
3707 var.s = desc->s;
3708 var.l = desc->l;
3709 var.g = desc->g;
3710 var.avl = desc->avl;
3711 var.present = desc->p;
3712 var.unusable = !var.present;
3713 var.padding = 0;
3714
3715 kvm_set_segment(vcpu, &var, seg);
3716 return;
3717}
3718
3719static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
3720{
3721 struct kvm_segment kvm_seg;
3722
3723 kvm_get_segment(vcpu, &kvm_seg, seg);
3724 return kvm_seg.selector;
3725}
3726
3727static void emulator_set_segment_selector(u16 sel, int seg,
3728 struct kvm_vcpu *vcpu)
3729{
3730 struct kvm_segment kvm_seg;
3731
3732 kvm_get_segment(vcpu, &kvm_seg, seg);
3733 kvm_seg.selector = sel;
3734 kvm_set_segment(vcpu, &kvm_seg, seg);
3735}
3736
482ac18a
GN		 3737static void emulator_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
3738{
3739 kvm_x86_ops->set_rflags(vcpu, rflags);
3740}
3741
14af3f3c 3742static struct x86_emulate_ops emulate_ops = {
1871c602 3743 .read_std = kvm_read_guest_virt_system,
2dafc6c2 3744 .write_std = kvm_write_guest_virt_system,
1871c602 3745 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3746 .read_emulated = emulator_read_emulated,
3747 .write_emulated = emulator_write_emulated,
3748 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 3749 .pio_in_emulated = emulator_pio_in_emulated,
3750 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 3751 .get_cached_descriptor = emulator_get_cached_descriptor,
3752 .set_cached_descriptor = emulator_set_cached_descriptor,
3753 .get_segment_selector = emulator_get_segment_selector,
3754 .set_segment_selector = emulator_set_segment_selector,
3755 .get_gdt = emulator_get_gdt,
52a46617
GN		 3756 .get_cr = emulator_get_cr,
3757 .set_cr = emulator_set_cr,
9c537244 3758 .cpl = emulator_get_cpl,
482ac18a 3759 .set_rflags = emulator_set_rflags,
bbd9b64e
CO		 3760};
3761
5fdbf976
MT		 3762static void cache_all_regs(struct kvm_vcpu *vcpu)
3763{
3764 kvm_register_read(vcpu, VCPU_REGS_RAX);
3765 kvm_register_read(vcpu, VCPU_REGS_RSP);
3766 kvm_register_read(vcpu, VCPU_REGS_RIP);
3767 vcpu->arch.regs_dirty = ~0;
3768}
3769
bbd9b64e 3770int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3771 unsigned long cr2,
3772 u16 error_code,
571008da 3773 int emulation_type)
bbd9b64e 3774{
310b5d30 3775 int r, shadow_mask;
571008da 3776 struct decode_cache *c;
851ba692 3777 struct kvm_run *run = vcpu->run;
bbd9b64e 3778
26eef70c 3779 kvm_clear_exception_queue(vcpu);
ad312c7c 3780 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3781 /*
56e82318 3782 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3783 * instead of direct ->regs accesses, can save hundred cycles
3784 * on Intel for instructions that don't read/change RSP, for
3785 * for example.
3786 */
3787 cache_all_regs(vcpu);
bbd9b64e
CO		 3788
3789 vcpu->mmio_is_write = 0;
bbd9b64e 3790
571008da 3791 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3792 int cs_db, cs_l;
3793 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3794
ad312c7c 3795 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3796 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
063db061 3797 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
ad312c7c 3798 vcpu->arch.emulate_ctxt.mode =
a0044755 3799 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3800 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3801 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3802 ? X86EMUL_MODE_PROT64 : cs_db
3803 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3804
ad312c7c 3805 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
e46479f8 3806 trace_kvm_emulate_insn_start(vcpu);
571008da 3807
0cb5762e
AP		 3808 /* Only allow emulation of specific instructions on #UD
3809 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3810 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3811 if (emulation_type & EMULTYPE_TRAP_UD) {
3812 if (!c->twobyte)
3813 return EMULATE_FAIL;
3814 switch (c->b) {
3815 case 0x01: /* VMMCALL */
3816 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3817 return EMULATE_FAIL;
3818 break;
3819 case 0x34: /* sysenter */
3820 case 0x35: /* sysexit */
3821 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3822 return EMULATE_FAIL;
3823 break;
3824 case 0x05: /* syscall */
3825 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3826 return EMULATE_FAIL;
3827 break;
3828 default:
3829 return EMULATE_FAIL;
3830 }
3831
3832 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3833 return EMULATE_FAIL;
3834 }
571008da 3835
f2b5756b 3836 ++vcpu->stat.insn_emulation;
bbd9b64e 3837 if (r) {
f2b5756b 3838 ++vcpu->stat.insn_emulation_fail;
e46479f8 3839 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3840 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3841 return EMULATE_DONE;
3842 return EMULATE_FAIL;
3843 }
3844 }
3845
ba8afb6b
GN		 3846 if (emulation_type & EMULTYPE_SKIP) {
3847 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3848 return EMULATE_DONE;
3849 }
3850
5cd21917 3851restart:
ad312c7c 3852 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3853 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3854
3855 if (r == 0)
3856 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3857
7972995b 3858 if (vcpu->arch.pio.count) {
cf8f70bf 3859 if (!vcpu->arch.pio.in)
7972995b 3860 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3861 return EMULATE_DO_MMIO;
3862 }
3863
112592da 3864 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3865 run->exit_reason = KVM_EXIT_MMIO;
3866 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3867 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3868 run->mmio.len = vcpu->mmio_size;
3869 run->mmio.is_write = vcpu->mmio_is_write;
3870 }
3871
3872 if (r) {
3873 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
5cd21917 3874 goto done;
bbd9b64e 3875 if (!vcpu->mmio_needed) {
e46479f8
AK		 3876 ++vcpu->stat.insn_emulation_fail;
3877 trace_kvm_emulate_insn_failed(vcpu);
bbd9b64e
CO		 3878 kvm_report_emulation_failure(vcpu, "mmio");
3879 return EMULATE_FAIL;
3880 }
3881 return EMULATE_DO_MMIO;
3882 }
3883
bbd9b64e
CO		 3884 if (vcpu->mmio_is_write) {
3885 vcpu->mmio_needed = 0;
3886 return EMULATE_DO_MMIO;
3887 }
3888
5cd21917
GN		 3889done:
3890 if (vcpu->arch.exception.pending)
3891 vcpu->arch.emulate_ctxt.restart = false;
3892
3893 if (vcpu->arch.emulate_ctxt.restart)
3894 goto restart;
3895
bbd9b64e
CO		 3896 return EMULATE_DONE;
3897}
3898EXPORT_SYMBOL_GPL(emulate_instruction);
3899
cf8f70bf
GN		 3900int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
3901{
3902 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3903 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
3904 /* do not return to emulator after return from userspace */
7972995b 3905 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3906 return ret;
3907}
3908EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
3909
c8076604
GH		 3910static void bounce_off(void *info)
3911{
3912 /* nothing */
3913}
3914
c8076604
GH		 3915static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3916 void *data)
3917{
3918 struct cpufreq_freqs *freq = data;
3919 struct kvm *kvm;
3920 struct kvm_vcpu *vcpu;
3921 int i, send_ipi = 0;
3922
c8076604
GH		 3923 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3924 return 0;
3925 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3926 return 0;
0cca7907 3927 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3928
3929 spin_lock(&kvm_lock);
3930 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3931 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3932 if (vcpu->cpu != freq->cpu)
3933 continue;
3934 if (!kvm_request_guest_time_update(vcpu))
3935 continue;
3936 if (vcpu->cpu != smp_processor_id())
3937 send_ipi++;
3938 }
3939 }
3940 spin_unlock(&kvm_lock);
3941
3942 if (freq->old < freq->new && send_ipi) {
3943 /*
3944 * We upscale the frequency. Must make the guest
3945 * doesn't see old kvmclock values while running with
3946 * the new frequency, otherwise we risk the guest sees
3947 * time go backwards.
3948 *
3949 * In case we update the frequency for another cpu
3950 * (which might be in guest context) send an interrupt
3951 * to kick the cpu out of guest context. Next time
3952 * guest context is entered kvmclock will be updated,
3953 * so the guest will not see stale values.
3954 */
3955 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3956 }
3957 return 0;
3958}
3959
3960static struct notifier_block kvmclock_cpufreq_notifier_block = {
3961 .notifier_call = kvmclock_cpufreq_notifier
3962};
3963
b820cc0c
ZA		 3964static void kvm_timer_init(void)
3965{
3966 int cpu;
3967
b820cc0c 3968 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3969 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3970 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3971 for_each_online_cpu(cpu) {
3972 unsigned long khz = cpufreq_get(cpu);
3973 if (!khz)
3974 khz = tsc_khz;
3975 per_cpu(cpu_tsc_khz, cpu) = khz;
3976 }
0cca7907
ZA		 3977 } else {
3978 for_each_possible_cpu(cpu)
3979 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3980 }
3981}
3982
ff9d07a0
ZY		 3983static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
3984
3985static int kvm_is_in_guest(void)
3986{
3987 return percpu_read(current_vcpu) != NULL;
3988}
3989
3990static int kvm_is_user_mode(void)
3991{
3992 int user_mode = 3;
dcf46b94 3993
ff9d07a0
ZY		 3994 if (percpu_read(current_vcpu))
3995 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 3996
ff9d07a0
ZY		 3997 return user_mode != 0;
3998}
3999
4000static unsigned long kvm_get_guest_ip(void)
4001{
4002 unsigned long ip = 0;
dcf46b94 4003
ff9d07a0
ZY		 4004 if (percpu_read(current_vcpu))
4005 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4006
ff9d07a0
ZY		 4007 return ip;
4008}
4009
4010static struct perf_guest_info_callbacks kvm_guest_cbs = {
4011 .is_in_guest = kvm_is_in_guest,
4012 .is_user_mode = kvm_is_user_mode,
4013 .get_guest_ip = kvm_get_guest_ip,
4014};
4015
4016void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4017{
4018 percpu_write(current_vcpu, vcpu);
4019}
4020EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4021
4022void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4023{
4024 percpu_write(current_vcpu, NULL);
4025}
4026EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4027
f8c16bba 4028int kvm_arch_init(void *opaque)
043405e1 4029{
b820cc0c 4030 int r;
f8c16bba
ZX		 4031 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4032
f8c16bba
ZX		 4033 if (kvm_x86_ops) {
4034 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4035 r = -EEXIST;
4036 goto out;
f8c16bba
ZX		 4037 }
4038
4039 if (!ops->cpu_has_kvm_support()) {
4040 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4041 r = -EOPNOTSUPP;
4042 goto out;
f8c16bba
ZX		 4043 }
4044 if (ops->disabled_by_bios()) {
4045 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4046 r = -EOPNOTSUPP;
4047 goto out;
f8c16bba
ZX		 4048 }
4049
97db56ce
AK		 4050 r = kvm_mmu_module_init();
4051 if (r)
4052 goto out;
4053
4054 kvm_init_msr_list();
4055
f8c16bba 4056 kvm_x86_ops = ops;
56c6d28a 4057 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4058 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4059 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4060 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4061
b820cc0c 4062 kvm_timer_init();
c8076604 4063
ff9d07a0
ZY		 4064 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4065
f8c16bba 4066 return 0;
56c6d28a
ZX		 4067
4068out:
56c6d28a 4069 return r;
043405e1 4070}
8776e519 4071
f8c16bba
ZX		 4072void kvm_arch_exit(void)
4073{
ff9d07a0
ZY		 4074 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4075
888d256e
JK		 4076 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4077 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4078 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 4079 kvm_x86_ops = NULL;
56c6d28a
ZX		 4080 kvm_mmu_module_exit();
4081}
f8c16bba 4082
8776e519
HB		 4083int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4084{
4085 ++vcpu->stat.halt_exits;
4086 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4087 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4088 return 1;
4089 } else {
4090 vcpu->run->exit_reason = KVM_EXIT_HLT;
4091 return 0;
4092 }
4093}
4094EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4095
2f333bcb
MT		 4096static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4097 unsigned long a1)
4098{
4099 if (is_long_mode(vcpu))
4100 return a0;
4101 else
4102 return a0 | ((gpa_t)a1 << 32);
4103}
4104
55cd8e5a
GN		 4105int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4106{
4107 u64 param, ingpa, outgpa, ret;
4108 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4109 bool fast, longmode;
4110 int cs_db, cs_l;
4111
4112 /*
4113 * hypercall generates UD from non zero cpl and real mode
4114 * per HYPER-V spec
4115 */
3eeb3288 4116 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4117 kvm_queue_exception(vcpu, UD_VECTOR);
4118 return 0;
4119 }
4120
4121 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4122 longmode = is_long_mode(vcpu) && cs_l == 1;
4123
4124 if (!longmode) {
ccd46936
GN		 4125 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4126 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4127 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4128 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4129 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4130 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4131 }
4132#ifdef CONFIG_X86_64
4133 else {
4134 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4135 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4136 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4137 }
4138#endif
4139
4140 code = param & 0xffff;
4141 fast = (param >> 16) & 0x1;
4142 rep_cnt = (param >> 32) & 0xfff;
4143 rep_idx = (param >> 48) & 0xfff;
4144
4145 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4146
c25bc163
GN		 4147 switch (code) {
4148 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4149 kvm_vcpu_on_spin(vcpu);
4150 break;
4151 default:
4152 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4153 break;
4154 }
55cd8e5a
GN		 4155
4156 ret = res | (((u64)rep_done & 0xfff) << 32);
4157 if (longmode) {
4158 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4159 } else {
4160 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4161 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4162 }
4163
4164 return 1;
4165}
4166
8776e519
HB		 4167int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4168{
4169 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4170 int r = 1;
8776e519 4171
55cd8e5a
GN		 4172 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4173 return kvm_hv_hypercall(vcpu);
4174
5fdbf976
MT		 4175 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4176 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4177 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4178 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4179 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4180
229456fc 4181 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4182
8776e519
HB		 4183 if (!is_long_mode(vcpu)) {
4184 nr &= 0xFFFFFFFF;
4185 a0 &= 0xFFFFFFFF;
4186 a1 &= 0xFFFFFFFF;
4187 a2 &= 0xFFFFFFFF;
4188 a3 &= 0xFFFFFFFF;
4189 }
4190
07708c4a
JK		 4191 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4192 ret = -KVM_EPERM;
4193 goto out;
4194 }
4195
8776e519 4196 switch (nr) {
b93463aa
AK		 4197 case KVM_HC_VAPIC_POLL_IRQ:
4198 ret = 0;
4199 break;
2f333bcb
MT		 4200 case KVM_HC_MMU_OP:
4201 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4202 break;
8776e519
HB		 4203 default:
4204 ret = -KVM_ENOSYS;
4205 break;
4206 }
07708c4a 4207out:
5fdbf976 4208 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4209 ++vcpu->stat.hypercalls;
2f333bcb 4210 return r;
8776e519
HB		 4211}
4212EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4213
4214int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4215{
4216 char instruction[3];
5fdbf976 4217 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4218
8776e519
HB		 4219 /*
4220 * Blow out the MMU to ensure that no other VCPU has an active mapping
4221 * to ensure that the updated hypercall appears atomically across all
4222 * VCPUs.
4223 */
4224 kvm_mmu_zap_all(vcpu->kvm);
4225
8776e519 4226 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4227
8f6abd06 4228 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4229}
4230
8776e519
HB		 4231void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4232{
89a27f4d 4233 struct desc_ptr dt = { limit, base };
8776e519
HB		 4234
4235 kvm_x86_ops->set_gdt(vcpu, &dt);
4236}
4237
4238void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4239{
89a27f4d 4240 struct desc_ptr dt = { limit, base };
8776e519
HB		 4241
4242 kvm_x86_ops->set_idt(vcpu, &dt);
4243}
4244
07716717
DK		 4245static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4246{
ad312c7c
ZX		 4247 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4248 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4249
4250 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4251 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4252 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4253 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4254 if (ej->function == e->function) {
4255 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4256 return j;
4257 }
4258 }
4259 return 0; /* silence gcc, even though control never reaches here */
4260}
4261
4262/* find an entry with matching function, matching index (if needed), and that
4263 * should be read next (if it's stateful) */
4264static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4265 u32 function, u32 index)
4266{
4267 if (e->function != function)
4268 return 0;
4269 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4270 return 0;
4271 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4272 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4273 return 0;
4274 return 1;
4275}
4276
d8017474
AG		 4277struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4278 u32 function, u32 index)
8776e519
HB		 4279{
4280 int i;
d8017474 4281 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4282
ad312c7c 4283 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4284 struct kvm_cpuid_entry2 *e;
4285
ad312c7c 4286 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4287 if (is_matching_cpuid_entry(e, function, index)) {
4288 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4289 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4290 best = e;
4291 break;
4292 }
4293 /*
4294 * Both basic or both extended?
4295 */
4296 if (((e->function ^ function) & 0x80000000) == 0)
4297 if (!best || e->function > best->function)
4298 best = e;
4299 }
d8017474
AG		 4300 return best;
4301}
0e851880 4302EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4303
82725b20
DE		 4304int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4305{
4306 struct kvm_cpuid_entry2 *best;
4307
f7a71197
AK		 4308 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4309 if (!best || best->eax < 0x80000008)
4310 goto not_found;
82725b20
DE		 4311 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4312 if (best)
4313 return best->eax & 0xff;
f7a71197 4314not_found:
82725b20
DE		 4315 return 36;
4316}
4317
d8017474
AG		 4318void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4319{
4320 u32 function, index;
4321 struct kvm_cpuid_entry2 *best;
4322
4323 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4324 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4325 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4326 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4327 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4328 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4329 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4330 if (best) {
5fdbf976
MT		 4331 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4332 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4333 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4334 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4335 }
8776e519 4336 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4337 trace_kvm_cpuid(function,
4338 kvm_register_read(vcpu, VCPU_REGS_RAX),
4339 kvm_register_read(vcpu, VCPU_REGS_RBX),
4340 kvm_register_read(vcpu, VCPU_REGS_RCX),
4341 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4342}
4343EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4344
b6c7a5dc
HB		 4345/*
4346 * Check if userspace requested an interrupt window, and that the
4347 * interrupt window is open.
4348 *
4349 * No need to exit to userspace if we already have an interrupt queued.
4350 */
851ba692 4351static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4352{
8061823a 4353 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4354 vcpu->run->request_interrupt_window &&
5df56646 4355 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4356}
4357
851ba692 4358static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4359{
851ba692
AK		 4360 struct kvm_run *kvm_run = vcpu->run;
4361
91586a3b 4362 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4363 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4364 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4365 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4366 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4367 else
b6c7a5dc 4368 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4369 kvm_arch_interrupt_allowed(vcpu) &&
4370 !kvm_cpu_has_interrupt(vcpu) &&
4371 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4372}
4373
b93463aa
AK		 4374static void vapic_enter(struct kvm_vcpu *vcpu)
4375{
4376 struct kvm_lapic *apic = vcpu->arch.apic;
4377 struct page *page;
4378
4379 if (!apic || !apic->vapic_addr)
4380 return;
4381
4382 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4383
4384 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4385}
4386
4387static void vapic_exit(struct kvm_vcpu *vcpu)
4388{
4389 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4390 int idx;
b93463aa
AK		 4391
4392 if (!apic || !apic->vapic_addr)
4393 return;
4394
f656ce01 4395 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4396 kvm_release_page_dirty(apic->vapic_page);
4397 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4398 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4399}
4400
95ba8273
GN		 4401static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4402{
4403 int max_irr, tpr;
4404
4405 if (!kvm_x86_ops->update_cr8_intercept)
4406 return;
4407
88c808fd
AK		 4408 if (!vcpu->arch.apic)
4409 return;
4410
8db3baa2
GN		 4411 if (!vcpu->arch.apic->vapic_addr)
4412 max_irr = kvm_lapic_find_highest_irr(vcpu);
4413 else
4414 max_irr = -1;
95ba8273
GN		 4415
4416 if (max_irr != -1)
4417 max_irr >>= 4;
4418
4419 tpr = kvm_lapic_get_cr8(vcpu);
4420
4421 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4422}
4423
851ba692 4424static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4425{
4426 /* try to reinject previous events if any */
b59bb7bd 4427 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 4428 trace_kvm_inj_exception(vcpu->arch.exception.nr,
4429 vcpu->arch.exception.has_error_code,
4430 vcpu->arch.exception.error_code);
b59bb7bd
GN		 4431 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4432 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 4433 vcpu->arch.exception.error_code,
4434 vcpu->arch.exception.reinject);
b59bb7bd
GN		 4435 return;
4436 }
4437
95ba8273
GN		 4438 if (vcpu->arch.nmi_injected) {
4439 kvm_x86_ops->set_nmi(vcpu);
4440 return;
4441 }
4442
4443 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4444 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4445 return;
4446 }
4447
4448 /* try to inject new event if pending */
4449 if (vcpu->arch.nmi_pending) {
4450 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4451 vcpu->arch.nmi_pending = false;
4452 vcpu->arch.nmi_injected = true;
4453 kvm_x86_ops->set_nmi(vcpu);
4454 }
4455 } else if (kvm_cpu_has_interrupt(vcpu)) {
4456 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4457 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4458 false);
4459 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4460 }
4461 }
4462}
4463
851ba692 4464static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4465{
4466 int r;
6a8b1d13 4467 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4468 vcpu->run->request_interrupt_window;
b6c7a5dc 4469
2e53d63a
MT		 4470 if (vcpu->requests)
4471 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4472 kvm_mmu_unload(vcpu);
4473
b6c7a5dc
HB		 4474 r = kvm_mmu_reload(vcpu);
4475 if (unlikely(r))
4476 goto out;
4477
2f52d58c
AK		 4478 if (vcpu->requests) {
4479 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4480 __kvm_migrate_timers(vcpu);
c8076604
GH		 4481 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4482 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4483 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4484 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4485 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4486 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4487 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4488 &vcpu->requests)) {
851ba692 4489 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4490 r = 0;
4491 goto out;
4492 }
71c4dfaf 4493 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4494 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4495 r = 0;
4496 goto out;
4497 }
02daab21
AK		 4498 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4499 vcpu->fpu_active = 0;
4500 kvm_x86_ops->fpu_deactivate(vcpu);
4501 }
2f52d58c 4502 }
b93463aa 4503
b6c7a5dc
HB		 4504 preempt_disable();
4505
4506 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4507 if (vcpu->fpu_active)
4508 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4509
4510 local_irq_disable();
4511
32f88400
MT		 4512 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4513 smp_mb__after_clear_bit();
4514
d7690175 4515 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4516 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4517 local_irq_enable();
4518 preempt_enable();
4519 r = 1;
4520 goto out;
4521 }
4522
851ba692 4523 inject_pending_event(vcpu);
b6c7a5dc 4524
6a8b1d13
GN		 4525 /* enable NMI/IRQ window open exits if needed */
4526 if (vcpu->arch.nmi_pending)
4527 kvm_x86_ops->enable_nmi_window(vcpu);
4528 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4529 kvm_x86_ops->enable_irq_window(vcpu);
4530
95ba8273 4531 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4532 update_cr8_intercept(vcpu);
4533 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4534 }
b93463aa 4535
f656ce01 4536 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4537
b6c7a5dc
HB		 4538 kvm_guest_enter();
4539
42dbaa5a 4540 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4541 set_debugreg(0, 7);
4542 set_debugreg(vcpu->arch.eff_db[0], 0);
4543 set_debugreg(vcpu->arch.eff_db[1], 1);
4544 set_debugreg(vcpu->arch.eff_db[2], 2);
4545 set_debugreg(vcpu->arch.eff_db[3], 3);
4546 }
b6c7a5dc 4547
229456fc 4548 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4549 kvm_x86_ops->run(vcpu);
b6c7a5dc 4550
24f1e32c
FW		 4551 /*
4552 * If the guest has used debug registers, at least dr7
4553 * will be disabled while returning to the host.
4554 * If we don't have active breakpoints in the host, we don't
4555 * care about the messed up debug address registers. But if
4556 * we have some of them active, restore the old state.
4557 */
59d8eb53 4558 if (hw_breakpoint_active())
24f1e32c 4559 hw_breakpoint_restore();
42dbaa5a 4560
32f88400 4561 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4562 local_irq_enable();
4563
4564 ++vcpu->stat.exits;
4565
4566 /*
4567 * We must have an instruction between local_irq_enable() and
4568 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4569 * the interrupt shadow. The stat.exits increment will do nicely.
4570 * But we need to prevent reordering, hence this barrier():
4571 */
4572 barrier();
4573
4574 kvm_guest_exit();
4575
4576 preempt_enable();
4577
f656ce01 4578 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4579
b6c7a5dc
HB		 4580 /*
4581 * Profile KVM exit RIPs:
4582 */
4583 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4584 unsigned long rip = kvm_rip_read(vcpu);
4585 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4586 }
4587
298101da 4588
b93463aa
AK		 4589 kvm_lapic_sync_from_vapic(vcpu);
4590
851ba692 4591 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4592out:
4593 return r;
4594}
b6c7a5dc 4595
09cec754 4596
851ba692 4597static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4598{
4599 int r;
f656ce01 4600 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4601
4602 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4603 pr_debug("vcpu %d received sipi with vector # %x\n",
4604 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4605 kvm_lapic_reset(vcpu);
5f179287 4606 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4607 if (r)
4608 return r;
4609 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4610 }
4611
f656ce01 4612 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4613 vapic_enter(vcpu);
4614
4615 r = 1;
4616 while (r > 0) {
af2152f5 4617 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4618 r = vcpu_enter_guest(vcpu);
d7690175 4619 else {
f656ce01 4620 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4621 kvm_vcpu_block(vcpu);
f656ce01 4622 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4623 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4624 {
4625 switch(vcpu->arch.mp_state) {
4626 case KVM_MP_STATE_HALTED:
d7690175 4627 vcpu->arch.mp_state =
09cec754
GN		 4628 KVM_MP_STATE_RUNNABLE;
4629 case KVM_MP_STATE_RUNNABLE:
4630 break;
4631 case KVM_MP_STATE_SIPI_RECEIVED:
4632 default:
4633 r = -EINTR;
4634 break;
4635 }
4636 }
d7690175
MT		 4637 }
4638
09cec754
GN		 4639 if (r <= 0)
4640 break;
4641
4642 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4643 if (kvm_cpu_has_pending_timer(vcpu))
4644 kvm_inject_pending_timer_irqs(vcpu);
4645
851ba692 4646 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4647 r = -EINTR;
851ba692 4648 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4649 ++vcpu->stat.request_irq_exits;
4650 }
4651 if (signal_pending(current)) {
4652 r = -EINTR;
851ba692 4653 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4654 ++vcpu->stat.signal_exits;
4655 }
4656 if (need_resched()) {
f656ce01 4657 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4658 kvm_resched(vcpu);
f656ce01 4659 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4660 }
b6c7a5dc
HB		 4661 }
4662
f656ce01 4663 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 4664
b93463aa
AK		 4665 vapic_exit(vcpu);
4666
b6c7a5dc
HB		 4667 return r;
4668}
4669
4670int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4671{
4672 int r;
4673 sigset_t sigsaved;
4674
4675 vcpu_load(vcpu);
4676
ac9f6dc0
AK		 4677 if (vcpu->sigset_active)
4678 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4679
a4535290 4680 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4681 kvm_vcpu_block(vcpu);
d7690175 4682 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4683 r = -EAGAIN;
4684 goto out;
b6c7a5dc
HB		 4685 }
4686
b6c7a5dc
HB		 4687 /* re-sync apic's tpr */
4688 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4689 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4690
92bf9748
GN		 4691 if (vcpu->arch.pio.count || vcpu->mmio_needed ||
4692 vcpu->arch.emulate_ctxt.restart) {
4693 if (vcpu->mmio_needed) {
4694 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4695 vcpu->mmio_read_completed = 1;
4696 vcpu->mmio_needed = 0;
b6c7a5dc 4697 }
5cd21917
GN		 4698 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4699 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
4700 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4701 if (r == EMULATE_DO_MMIO) {
4702 r = 0;
4703 goto out;
4704 }
4705 }
5fdbf976
MT		 4706 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4707 kvm_register_write(vcpu, VCPU_REGS_RAX,
4708 kvm_run->hypercall.ret);
b6c7a5dc 4709
851ba692 4710 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4711
4712out:
f1d86e46 4713 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 4714 if (vcpu->sigset_active)
4715 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4716
4717 vcpu_put(vcpu);
4718 return r;
4719}
4720
4721int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4722{
4723 vcpu_load(vcpu);
4724
5fdbf976
MT		 4725 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4726 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4727 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4728 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4729 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4730 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4731 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4732 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4733#ifdef CONFIG_X86_64
5fdbf976
MT		 4734 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4735 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4736 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4737 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4738 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4739 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4740 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4741 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4742#endif
4743
5fdbf976 4744 regs->rip = kvm_rip_read(vcpu);
91586a3b 4745 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4746
4747 vcpu_put(vcpu);
4748
4749 return 0;
4750}
4751
4752int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4753{
4754 vcpu_load(vcpu);
4755
5fdbf976
MT		 4756 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4757 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4758 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4759 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4760 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4761 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4762 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4763 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4764#ifdef CONFIG_X86_64
5fdbf976
MT		 4765 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4766 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4767 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4768 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4769 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4770 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4771 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4772 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4773#endif
4774
5fdbf976 4775 kvm_rip_write(vcpu, regs->rip);
91586a3b 4776 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4777
b4f14abd
JK		 4778 vcpu->arch.exception.pending = false;
4779
b6c7a5dc
HB		 4780 vcpu_put(vcpu);
4781
4782 return 0;
4783}
4784
b6c7a5dc
HB		 4785void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4786{
4787 struct kvm_segment cs;
4788
3e6e0aab 4789 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4790 *db = cs.db;
4791 *l = cs.l;
4792}
4793EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4794
4795int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4796 struct kvm_sregs *sregs)
4797{
89a27f4d 4798 struct desc_ptr dt;
b6c7a5dc
HB		 4799
4800 vcpu_load(vcpu);
4801
3e6e0aab
GT		 4802 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4803 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4804 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4805 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4806 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4807 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4808
3e6e0aab
GT		 4809 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4810 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4811
4812 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4813 sregs->idt.limit = dt.size;
4814 sregs->idt.base = dt.address;
b6c7a5dc 4815 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4816 sregs->gdt.limit = dt.size;
4817 sregs->gdt.base = dt.address;
b6c7a5dc 4818
4d4ec087 4819 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4820 sregs->cr2 = vcpu->arch.cr2;
4821 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4822 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4823 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4824 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4825 sregs->apic_base = kvm_get_apic_base(vcpu);
4826
923c61bb 4827 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4828
36752c9b 4829 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4830 set_bit(vcpu->arch.interrupt.nr,
4831 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4832
b6c7a5dc
HB		 4833 vcpu_put(vcpu);
4834
4835 return 0;
4836}
4837
62d9f0db
MT		 4838int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4839 struct kvm_mp_state *mp_state)
4840{
4841 vcpu_load(vcpu);
4842 mp_state->mp_state = vcpu->arch.mp_state;
4843 vcpu_put(vcpu);
4844 return 0;
4845}
4846
4847int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4848 struct kvm_mp_state *mp_state)
4849{
4850 vcpu_load(vcpu);
4851 vcpu->arch.mp_state = mp_state->mp_state;
4852 vcpu_put(vcpu);
4853 return 0;
4854}
4855
e269fb21
JK		 4856int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
4857 bool has_error_code, u32 error_code)
37817f29 4858{
ceffb459
GN		 4859 int cs_db, cs_l, ret;
4860 cache_all_regs(vcpu);
37817f29 4861
ceffb459 4862 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
b237ac37 4863
ceffb459
GN		 4864 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4865 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4866 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4867 vcpu->arch.emulate_ctxt.mode =
4868 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4869 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4870 ? X86EMUL_MODE_VM86 : cs_l
4871 ? X86EMUL_MODE_PROT64 : cs_db
4872 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
37817f29 4873
ceffb459 4874 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt, &emulate_ops,
e269fb21
JK		 4875 tss_selector, reason, has_error_code,
4876 error_code);
37817f29 4877
19d04437
GN		 4878 if (ret)
4879 return EMULATE_FAIL;
37817f29 4880
19d04437
GN		 4881 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4882 return EMULATE_DONE;
37817f29
IE		 4883}
4884EXPORT_SYMBOL_GPL(kvm_task_switch);
4885
b6c7a5dc
HB		 4886int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4887 struct kvm_sregs *sregs)
4888{
4889 int mmu_reset_needed = 0;
923c61bb 4890 int pending_vec, max_bits;
89a27f4d 4891 struct desc_ptr dt;
b6c7a5dc
HB		 4892
4893 vcpu_load(vcpu);
4894
89a27f4d
GN		 4895 dt.size = sregs->idt.limit;
4896 dt.address = sregs->idt.base;
b6c7a5dc 4897 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 4898 dt.size = sregs->gdt.limit;
4899 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 4900 kvm_x86_ops->set_gdt(vcpu, &dt);
4901
ad312c7c
ZX		 4902 vcpu->arch.cr2 = sregs->cr2;
4903 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 4904 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 4905
2d3ad1f4 4906 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4907
f6801dff 4908 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 4909 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4910 kvm_set_apic_base(vcpu, sregs->apic_base);
4911
4d4ec087 4912 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 4913 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4914 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4915
fc78f519 4916 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 4917 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 4918 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 4919 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 4920 mmu_reset_needed = 1;
4921 }
b6c7a5dc
HB		 4922
4923 if (mmu_reset_needed)
4924 kvm_mmu_reset_context(vcpu);
4925
923c61bb
GN		 4926 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4927 pending_vec = find_first_bit(
4928 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4929 if (pending_vec < max_bits) {
66fd3f7f 4930 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4931 pr_debug("Set back pending irq %d\n", pending_vec);
4932 if (irqchip_in_kernel(vcpu->kvm))
4933 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4934 }
4935
3e6e0aab
GT		 4936 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4937 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4938 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4939 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4940 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4941 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4942
3e6e0aab
GT		 4943 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4944 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4945
5f0269f5
ME		 4946 update_cr8_intercept(vcpu);
4947
9c3e4aab 4948 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4949 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 4950 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 4951 !is_protmode(vcpu))
9c3e4aab
MT		 4952 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4953
b6c7a5dc
HB		 4954 vcpu_put(vcpu);
4955
4956 return 0;
4957}
4958
d0bfb940
JK		 4959int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4960 struct kvm_guest_debug *dbg)
b6c7a5dc 4961{
355be0b9 4962 unsigned long rflags;
ae675ef0 4963 int i, r;
b6c7a5dc
HB		 4964
4965 vcpu_load(vcpu);
4966
4f926bf2
JK		 4967 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
4968 r = -EBUSY;
4969 if (vcpu->arch.exception.pending)
4970 goto unlock_out;
4971 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4972 kvm_queue_exception(vcpu, DB_VECTOR);
4973 else
4974 kvm_queue_exception(vcpu, BP_VECTOR);
4975 }
4976
91586a3b
JK		 4977 /*
4978 * Read rflags as long as potentially injected trace flags are still
4979 * filtered out.
4980 */
4981 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 4982
4983 vcpu->guest_debug = dbg->control;
4984 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
4985 vcpu->guest_debug = 0;
4986
4987 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 4988 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4989 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4990 vcpu->arch.switch_db_regs =
4991 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4992 } else {
4993 for (i = 0; i < KVM_NR_DB_REGS; i++)
4994 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4995 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4996 }
4997
f92653ee
JK		 4998 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4999 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5000 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5001
91586a3b
JK		 5002 /*
5003 * Trigger an rflags update that will inject or remove the trace
5004 * flags.
5005 */
5006 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5007
355be0b9 5008 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5009
4f926bf2 5010 r = 0;
d0bfb940 5011
4f926bf2 5012unlock_out:
b6c7a5dc
HB		 5013 vcpu_put(vcpu);
5014
5015 return r;
5016}
5017
d0752060
HB		 5018/*
5019 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5020 * we have asm/x86/processor.h
5021 */
5022struct fxsave {
5023 u16 cwd;
5024 u16 swd;
5025 u16 twd;
5026 u16 fop;
5027 u64 rip;
5028 u64 rdp;
5029 u32 mxcsr;
5030 u32 mxcsr_mask;
5031 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5032#ifdef CONFIG_X86_64
5033 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5034#else
5035 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5036#endif
5037};
5038
8b006791
ZX		 5039/*
5040 * Translate a guest virtual address to a guest physical address.
5041 */
5042int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5043 struct kvm_translation *tr)
5044{
5045 unsigned long vaddr = tr->linear_address;
5046 gpa_t gpa;
f656ce01 5047 int idx;
8b006791
ZX		 5048
5049 vcpu_load(vcpu);
f656ce01 5050 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5051 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5052 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5053 tr->physical_address = gpa;
5054 tr->valid = gpa != UNMAPPED_GVA;
5055 tr->writeable = 1;
5056 tr->usermode = 0;
8b006791
ZX		 5057 vcpu_put(vcpu);
5058
5059 return 0;
5060}
5061
d0752060
HB		 5062int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5063{
ad312c7c 5064 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5065
5066 vcpu_load(vcpu);
5067
5068 memcpy(fpu->fpr, fxsave->st_space, 128);
5069 fpu->fcw = fxsave->cwd;
5070 fpu->fsw = fxsave->swd;
5071 fpu->ftwx = fxsave->twd;
5072 fpu->last_opcode = fxsave->fop;
5073 fpu->last_ip = fxsave->rip;
5074 fpu->last_dp = fxsave->rdp;
5075 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5076
5077 vcpu_put(vcpu);
5078
5079 return 0;
5080}
5081
5082int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5083{
ad312c7c 5084 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5085
5086 vcpu_load(vcpu);
5087
5088 memcpy(fxsave->st_space, fpu->fpr, 128);
5089 fxsave->cwd = fpu->fcw;
5090 fxsave->swd = fpu->fsw;
5091 fxsave->twd = fpu->ftwx;
5092 fxsave->fop = fpu->last_opcode;
5093 fxsave->rip = fpu->last_ip;
5094 fxsave->rdp = fpu->last_dp;
5095 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5096
5097 vcpu_put(vcpu);
5098
5099 return 0;
5100}
5101
5102void fx_init(struct kvm_vcpu *vcpu)
5103{
5104 unsigned after_mxcsr_mask;
5105
bc1a34f1
AA		 5106 /*
5107 * Touch the fpu the first time in non atomic context as if
5108 * this is the first fpu instruction the exception handler
5109 * will fire before the instruction returns and it'll have to
5110 * allocate ram with GFP_KERNEL.
5111 */
5112 if (!used_math())
d6e88aec 5113 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5114
d0752060
HB		 5115 /* Initialize guest FPU by resetting ours and saving into guest's */
5116 preempt_disable();
d6e88aec
AK		 5117 kvm_fx_save(&vcpu->arch.host_fx_image);
5118 kvm_fx_finit();
5119 kvm_fx_save(&vcpu->arch.guest_fx_image);
5120 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5121 preempt_enable();
5122
ad312c7c 5123 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5124 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5125 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5126 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5127 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5128}
5129EXPORT_SYMBOL_GPL(fx_init);
5130
5131void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5132{
2608d7a1 5133 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5134 return;
5135
5136 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5137 kvm_fx_save(&vcpu->arch.host_fx_image);
5138 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5139 trace_kvm_fpu(1);
d0752060 5140}
d0752060
HB		 5141
5142void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5143{
5144 if (!vcpu->guest_fpu_loaded)
5145 return;
5146
5147 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5148 kvm_fx_save(&vcpu->arch.guest_fx_image);
5149 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5150 ++vcpu->stat.fpu_reload;
02daab21 5151 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5152 trace_kvm_fpu(0);
d0752060 5153}
e9b11c17
ZX		 5154
5155void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5156{
7f1ea208
JR		 5157 if (vcpu->arch.time_page) {
5158 kvm_release_page_dirty(vcpu->arch.time_page);
5159 vcpu->arch.time_page = NULL;
5160 }
5161
e9b11c17
ZX		 5162 kvm_x86_ops->vcpu_free(vcpu);
5163}
5164
5165struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5166 unsigned int id)
5167{
26e5215f
AK		 5168 return kvm_x86_ops->vcpu_create(kvm, id);
5169}
e9b11c17 5170
26e5215f
AK		 5171int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5172{
5173 int r;
e9b11c17
ZX		 5174
5175 /* We do fxsave: this must be aligned. */
ad312c7c 5176 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5177
0bed3b56 5178 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5179 vcpu_load(vcpu);
5180 r = kvm_arch_vcpu_reset(vcpu);
5181 if (r == 0)
5182 r = kvm_mmu_setup(vcpu);
5183 vcpu_put(vcpu);
5184 if (r < 0)
5185 goto free_vcpu;
5186
26e5215f 5187 return 0;
e9b11c17
ZX		 5188free_vcpu:
5189 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5190 return r;
e9b11c17
ZX		 5191}
5192
d40ccc62 5193void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5194{
5195 vcpu_load(vcpu);
5196 kvm_mmu_unload(vcpu);
5197 vcpu_put(vcpu);
5198
5199 kvm_x86_ops->vcpu_free(vcpu);
5200}
5201
5202int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5203{
448fa4a9
JK		 5204 vcpu->arch.nmi_pending = false;
5205 vcpu->arch.nmi_injected = false;
5206
42dbaa5a
JK		 5207 vcpu->arch.switch_db_regs = 0;
5208 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5209 vcpu->arch.dr6 = DR6_FIXED_1;
5210 vcpu->arch.dr7 = DR7_FIXED_1;
5211
e9b11c17
ZX		 5212 return kvm_x86_ops->vcpu_reset(vcpu);
5213}
5214
10474ae8 5215int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5216{
0cca7907
ZA		 5217 /*
5218 * Since this may be called from a hotplug notifcation,
5219 * we can't get the CPU frequency directly.
5220 */
5221 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5222 int cpu = raw_smp_processor_id();
5223 per_cpu(cpu_tsc_khz, cpu) = 0;
5224 }
18863bdd
AK		 5225
5226 kvm_shared_msr_cpu_online();
5227
10474ae8 5228 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5229}
5230
5231void kvm_arch_hardware_disable(void *garbage)
5232{
5233 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5234 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5235}
5236
5237int kvm_arch_hardware_setup(void)
5238{
5239 return kvm_x86_ops->hardware_setup();
5240}
5241
5242void kvm_arch_hardware_unsetup(void)
5243{
5244 kvm_x86_ops->hardware_unsetup();
5245}
5246
5247void kvm_arch_check_processor_compat(void *rtn)
5248{
5249 kvm_x86_ops->check_processor_compatibility(rtn);
5250}
5251
5252int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5253{
5254 struct page *page;
5255 struct kvm *kvm;
5256 int r;
5257
5258 BUG_ON(vcpu->kvm == NULL);
5259 kvm = vcpu->kvm;
5260
ad312c7c 5261 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5262 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5263 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5264 else
a4535290 5265 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5266
5267 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5268 if (!page) {
5269 r = -ENOMEM;
5270 goto fail;
5271 }
ad312c7c 5272 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5273
5274 r = kvm_mmu_create(vcpu);
5275 if (r < 0)
5276 goto fail_free_pio_data;
5277
5278 if (irqchip_in_kernel(kvm)) {
5279 r = kvm_create_lapic(vcpu);
5280 if (r < 0)
5281 goto fail_mmu_destroy;
5282 }
5283
890ca9ae
HY		 5284 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5285 GFP_KERNEL);
5286 if (!vcpu->arch.mce_banks) {
5287 r = -ENOMEM;
443c39bc 5288 goto fail_free_lapic;
890ca9ae
HY		 5289 }
5290 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5291
e9b11c17 5292 return 0;
443c39bc
WY		 5293fail_free_lapic:
5294 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5295fail_mmu_destroy:
5296 kvm_mmu_destroy(vcpu);
5297fail_free_pio_data:
ad312c7c 5298 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5299fail:
5300 return r;
5301}
5302
5303void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5304{
f656ce01
MT		 5305 int idx;
5306
36cb93fd 5307 kfree(vcpu->arch.mce_banks);
e9b11c17 5308 kvm_free_lapic(vcpu);
f656ce01 5309 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5310 kvm_mmu_destroy(vcpu);
f656ce01 5311 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5312 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5313}
d19a9cd2
ZX		 5314
5315struct kvm *kvm_arch_create_vm(void)
5316{
5317 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5318
5319 if (!kvm)
5320 return ERR_PTR(-ENOMEM);
5321
fef9cce0
MT		 5322 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5323 if (!kvm->arch.aliases) {
5324 kfree(kvm);
5325 return ERR_PTR(-ENOMEM);
5326 }
5327
f05e70ac 5328 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5329 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5330
5550af4d
SY		 5331 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5332 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5333
53f658b3
MT		 5334 rdtscll(kvm->arch.vm_init_tsc);
5335
d19a9cd2
ZX		 5336 return kvm;
5337}
5338
5339static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5340{
5341 vcpu_load(vcpu);
5342 kvm_mmu_unload(vcpu);
5343 vcpu_put(vcpu);
5344}
5345
5346static void kvm_free_vcpus(struct kvm *kvm)
5347{
5348 unsigned int i;
988a2cae 5349 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5350
5351 /*
5352 * Unpin any mmu pages first.
5353 */
988a2cae
GN		 5354 kvm_for_each_vcpu(i, vcpu, kvm)
5355 kvm_unload_vcpu_mmu(vcpu);
5356 kvm_for_each_vcpu(i, vcpu, kvm)
5357 kvm_arch_vcpu_free(vcpu);
5358
5359 mutex_lock(&kvm->lock);
5360 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5361 kvm->vcpus[i] = NULL;
d19a9cd2 5362
988a2cae
GN		 5363 atomic_set(&kvm->online_vcpus, 0);
5364 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5365}
5366
ad8ba2cd
SY		 5367void kvm_arch_sync_events(struct kvm *kvm)
5368{
ba4cef31 5369 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5370}
5371
d19a9cd2
ZX		 5372void kvm_arch_destroy_vm(struct kvm *kvm)
5373{
6eb55818 5374 kvm_iommu_unmap_guest(kvm);
7837699f 5375 kvm_free_pit(kvm);
d7deeeb0
ZX		 5376 kfree(kvm->arch.vpic);
5377 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5378 kvm_free_vcpus(kvm);
5379 kvm_free_physmem(kvm);
3d45830c
AK		 5380 if (kvm->arch.apic_access_page)
5381 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5382 if (kvm->arch.ept_identity_pagetable)
5383 put_page(kvm->arch.ept_identity_pagetable);
64749204 5384 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5385 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5386 kfree(kvm);
5387}
0de10343 5388
f7784b8e
MT		 5389int kvm_arch_prepare_memory_region(struct kvm *kvm,
5390 struct kvm_memory_slot *memslot,
0de10343 5391 struct kvm_memory_slot old,
f7784b8e 5392 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5393 int user_alloc)
5394{
f7784b8e 5395 int npages = memslot->npages;
0de10343
ZX		 5396
5397 /*To keep backward compatibility with older userspace,
5398 *x86 needs to hanlde !user_alloc case.
5399 */
5400 if (!user_alloc) {
5401 if (npages && !old.rmap) {
604b38ac
AA		 5402 unsigned long userspace_addr;
5403
72dc67a6 5404 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5405 userspace_addr = do_mmap(NULL, 0,
5406 npages * PAGE_SIZE,
5407 PROT_READ | PROT_WRITE,
acee3c04 5408 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5409 0);
72dc67a6 5410 up_write(&current->mm->mmap_sem);
0de10343 5411
604b38ac
AA		 5412 if (IS_ERR((void *)userspace_addr))
5413 return PTR_ERR((void *)userspace_addr);
5414
604b38ac 5415 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5416 }
5417 }
5418
f7784b8e
MT		 5419
5420 return 0;
5421}
5422
5423void kvm_arch_commit_memory_region(struct kvm *kvm,
5424 struct kvm_userspace_memory_region *mem,
5425 struct kvm_memory_slot old,
5426 int user_alloc)
5427{
5428
5429 int npages = mem->memory_size >> PAGE_SHIFT;
5430
5431 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5432 int ret;
5433
5434 down_write(&current->mm->mmap_sem);
5435 ret = do_munmap(current->mm, old.userspace_addr,
5436 old.npages * PAGE_SIZE);
5437 up_write(&current->mm->mmap_sem);
5438 if (ret < 0)
5439 printk(KERN_WARNING
5440 "kvm_vm_ioctl_set_memory_region: "
5441 "failed to munmap memory\n");
5442 }
5443
7c8a83b7 5444 spin_lock(&kvm->mmu_lock);
f05e70ac 5445 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5446 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5447 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5448 }
5449
5450 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5451 spin_unlock(&kvm->mmu_lock);
0de10343 5452}
1d737c8a 5453
34d4cb8f
MT		 5454void kvm_arch_flush_shadow(struct kvm *kvm)
5455{
5456 kvm_mmu_zap_all(kvm);
8986ecc0 5457 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5458}
5459
1d737c8a
ZX		 5460int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5461{
a4535290 5462 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5463 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5464 || vcpu->arch.nmi_pending ||
5465 (kvm_arch_interrupt_allowed(vcpu) &&
5466 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5467}
5736199a 5468
5736199a
ZX		 5469void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5470{
32f88400
MT		 5471 int me;
5472 int cpu = vcpu->cpu;
5736199a
ZX		 5473
5474 if (waitqueue_active(&vcpu->wq)) {
5475 wake_up_interruptible(&vcpu->wq);
5476 ++vcpu->stat.halt_wakeup;
5477 }
32f88400
MT		 5478
5479 me = get_cpu();
5480 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5481 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5482 smp_send_reschedule(cpu);
e9571ed5 5483 put_cpu();
5736199a 5484}
78646121
GN		 5485
5486int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5487{
5488 return kvm_x86_ops->interrupt_allowed(vcpu);
5489}
229456fc 5490
f92653ee
JK		 5491bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5492{
5493 unsigned long current_rip = kvm_rip_read(vcpu) +
5494 get_segment_base(vcpu, VCPU_SREG_CS);
5495
5496 return current_rip == linear_rip;
5497}
5498EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5499
94fe45da
JK		 5500unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5501{
5502 unsigned long rflags;
5503
5504 rflags = kvm_x86_ops->get_rflags(vcpu);
5505 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5506 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5507 return rflags;
5508}
5509EXPORT_SYMBOL_GPL(kvm_get_rflags);
5510
5511void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5512{
5513 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5514 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5515 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5516 kvm_x86_ops->set_rflags(vcpu, rflags);
5517}
5518EXPORT_SYMBOL_GPL(kvm_set_rflags);
5519
229456fc
MT		 5520EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5521EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5522EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5523EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5524EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5525EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5526EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5527EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5528EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5529EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5530EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5531EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git