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drm/edid: Parse and handle HDMI deep color modes.
[thirdparty/kernel/stable.git] / drivers / gpu / drm / drm_edid.c
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f453ba04
DA		 1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
61e57a8d 5 * Copyright 2010 Red Hat, Inc.
f453ba04
DA		 6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
10a85120 32#include <linux/hdmi.h>
f453ba04 33#include <linux/i2c.h>
47819ba2 34#include <linux/module.h>
760285e7
DH		 35#include <drm/drmP.h>
36#include <drm/drm_edid.h>
f453ba04 37
13931579
AJ		 38#define version_greater(edid, maj, min) \
39 (((edid)->version > (maj)) || \
40 ((edid)->version == (maj) && (edid)->revision > (min)))
f453ba04 41
d1ff6409
AJ		 42#define EDID_EST_TIMINGS 16
43#define EDID_STD_TIMINGS 8
44#define EDID_DETAILED_TIMINGS 4
f453ba04
DA		 45
46/*
47 * EDID blocks out in the wild have a variety of bugs, try to collect
48 * them here (note that userspace may work around broken monitors first,
49 * but fixes should make their way here so that the kernel "just works"
50 * on as many displays as possible).
51 */
52
53/* First detailed mode wrong, use largest 60Hz mode */
54#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
55/* Reported 135MHz pixel clock is too high, needs adjustment */
56#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
57/* Prefer the largest mode at 75 Hz */
58#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
59/* Detail timing is in cm not mm */
60#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
61/* Detailed timing descriptors have bogus size values, so just take the
62 * maximum size and use that.
63 */
64#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
65/* Monitor forgot to set the first detailed is preferred bit. */
66#define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
67/* use +hsync +vsync for detailed mode */
68#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
bc42aabc
AJ		 69/* Force reduced-blanking timings for detailed modes */
70#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
49d45a31
RM		 71/* Force 8bpc */
72#define EDID_QUIRK_FORCE_8BPC (1 << 8)
3c537889 73
13931579
AJ		 74struct detailed_mode_closure {
75 struct drm_connector *connector;
76 struct edid *edid;
77 bool preferred;
78 u32 quirks;
79 int modes;
80};
f453ba04 81
5c61259e
ZY		 82#define LEVEL_DMT 0
83#define LEVEL_GTF 1
7a374350
AJ		 84#define LEVEL_GTF2 2
85#define LEVEL_CVT 3
5c61259e 86
f453ba04 87static struct edid_quirk {
c51a3fd6 88 char vendor[4];
f453ba04
DA		 89 int product_id;
90 u32 quirks;
91} edid_quirk_list[] = {
92 /* Acer AL1706 */
93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
94 /* Acer F51 */
95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
96 /* Unknown Acer */
97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
98
99 /* Belinea 10 15 55 */
100 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
101 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
102
103 /* Envision Peripherals, Inc. EN-7100e */
104 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
ba1163de
AJ		 105 /* Envision EN2028 */
106 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
f453ba04
DA		 107
108 /* Funai Electronics PM36B */
109 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
110 EDID_QUIRK_DETAILED_IN_CM },
111
112 /* LG Philips LCD LP154W01-A5 */
113 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
114 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
115
116 /* Philips 107p5 CRT */
117 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
118
119 /* Proview AY765C */
120 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
121
122 /* Samsung SyncMaster 205BW. Note: irony */
123 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
124 /* Samsung SyncMaster 22[5-6]BW */
125 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
126 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
bc42aabc
AJ		 127
128 /* ViewSonic VA2026w */
129 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
118bdbd8
AD		 130
131 /* Medion MD 30217 PG */
132 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
49d45a31
RM		 133
134 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
135 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
f453ba04
DA		 136};
137
a6b21831
TR		 138/*
139 * Autogenerated from the DMT spec.
140 * This table is copied from xfree86/modes/xf86EdidModes.c.
141 */
142static const struct drm_display_mode drm_dmt_modes[] = {
143 /* 640x350@85Hz */
144 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
145 736, 832, 0, 350, 382, 385, 445, 0,
146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
147 /* 640x400@85Hz */
148 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
149 736, 832, 0, 400, 401, 404, 445, 0,
150 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
151 /* 720x400@85Hz */
152 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
153 828, 936, 0, 400, 401, 404, 446, 0,
154 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
155 /* 640x480@60Hz */
156 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
157 752, 800, 0, 480, 489, 492, 525, 0,
158 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
159 /* 640x480@72Hz */
160 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
161 704, 832, 0, 480, 489, 492, 520, 0,
162 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
163 /* 640x480@75Hz */
164 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
165 720, 840, 0, 480, 481, 484, 500, 0,
166 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
167 /* 640x480@85Hz */
168 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
169 752, 832, 0, 480, 481, 484, 509, 0,
170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
171 /* 800x600@56Hz */
172 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
173 896, 1024, 0, 600, 601, 603, 625, 0,
174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
175 /* 800x600@60Hz */
176 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
177 968, 1056, 0, 600, 601, 605, 628, 0,
178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
179 /* 800x600@72Hz */
180 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
181 976, 1040, 0, 600, 637, 643, 666, 0,
182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
183 /* 800x600@75Hz */
184 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
185 896, 1056, 0, 600, 601, 604, 625, 0,
186 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
187 /* 800x600@85Hz */
188 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
189 896, 1048, 0, 600, 601, 604, 631, 0,
190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
191 /* 800x600@120Hz RB */
192 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
193 880, 960, 0, 600, 603, 607, 636, 0,
194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
195 /* 848x480@60Hz */
196 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
197 976, 1088, 0, 480, 486, 494, 517, 0,
198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
199 /* 1024x768@43Hz, interlace */
200 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
201 1208, 1264, 0, 768, 768, 772, 817, 0,
202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
203 DRM_MODE_FLAG_INTERLACE) },
204 /* 1024x768@60Hz */
205 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
206 1184, 1344, 0, 768, 771, 777, 806, 0,
207 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
208 /* 1024x768@70Hz */
209 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
210 1184, 1328, 0, 768, 771, 777, 806, 0,
211 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
212 /* 1024x768@75Hz */
213 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
214 1136, 1312, 0, 768, 769, 772, 800, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
216 /* 1024x768@85Hz */
217 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
218 1168, 1376, 0, 768, 769, 772, 808, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
220 /* 1024x768@120Hz RB */
221 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
222 1104, 1184, 0, 768, 771, 775, 813, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
224 /* 1152x864@75Hz */
225 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
226 1344, 1600, 0, 864, 865, 868, 900, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228 /* 1280x768@60Hz RB */
229 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
230 1360, 1440, 0, 768, 771, 778, 790, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
232 /* 1280x768@60Hz */
233 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
234 1472, 1664, 0, 768, 771, 778, 798, 0,
235 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 1280x768@75Hz */
237 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
238 1488, 1696, 0, 768, 771, 778, 805, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
240 /* 1280x768@85Hz */
241 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
242 1496, 1712, 0, 768, 771, 778, 809, 0,
243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
244 /* 1280x768@120Hz RB */
245 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
246 1360, 1440, 0, 768, 771, 778, 813, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
248 /* 1280x800@60Hz RB */
249 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
250 1360, 1440, 0, 800, 803, 809, 823, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
252 /* 1280x800@60Hz */
253 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
254 1480, 1680, 0, 800, 803, 809, 831, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 1280x800@75Hz */
257 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
258 1488, 1696, 0, 800, 803, 809, 838, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 1280x800@85Hz */
261 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
262 1496, 1712, 0, 800, 803, 809, 843, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 1280x800@120Hz RB */
265 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
266 1360, 1440, 0, 800, 803, 809, 847, 0,
267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
268 /* 1280x960@60Hz */
269 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
270 1488, 1800, 0, 960, 961, 964, 1000, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
272 /* 1280x960@85Hz */
273 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
274 1504, 1728, 0, 960, 961, 964, 1011, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
276 /* 1280x960@120Hz RB */
277 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
278 1360, 1440, 0, 960, 963, 967, 1017, 0,
279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
280 /* 1280x1024@60Hz */
281 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
282 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 1280x1024@75Hz */
285 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
286 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 1280x1024@85Hz */
289 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
290 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
292 /* 1280x1024@120Hz RB */
293 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
294 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
296 /* 1360x768@60Hz */
297 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
298 1536, 1792, 0, 768, 771, 777, 795, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 1360x768@120Hz RB */
301 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
302 1440, 1520, 0, 768, 771, 776, 813, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
304 /* 1400x1050@60Hz RB */
305 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
306 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
308 /* 1400x1050@60Hz */
309 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
310 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 1400x1050@75Hz */
313 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
314 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
316 /* 1400x1050@85Hz */
317 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
318 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
319 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 1400x1050@120Hz RB */
321 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
322 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
324 /* 1440x900@60Hz RB */
325 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
326 1520, 1600, 0, 900, 903, 909, 926, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 1440x900@60Hz */
329 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
330 1672, 1904, 0, 900, 903, 909, 934, 0,
331 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 1440x900@75Hz */
333 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
334 1688, 1936, 0, 900, 903, 909, 942, 0,
335 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 1440x900@85Hz */
337 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
338 1696, 1952, 0, 900, 903, 909, 948, 0,
339 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
340 /* 1440x900@120Hz RB */
341 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
342 1520, 1600, 0, 900, 903, 909, 953, 0,
343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
344 /* 1600x1200@60Hz */
345 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
346 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 1600x1200@65Hz */
349 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
350 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 1600x1200@70Hz */
353 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
354 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
356 /* 1600x1200@75Hz */
357 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
358 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
360 /* 1600x1200@85Hz */
361 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
362 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 1600x1200@120Hz RB */
365 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
366 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
368 /* 1680x1050@60Hz RB */
369 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
370 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
372 /* 1680x1050@60Hz */
373 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
374 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
376 /* 1680x1050@75Hz */
377 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
378 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 1680x1050@85Hz */
381 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
382 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 1680x1050@120Hz RB */
385 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
386 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 1792x1344@60Hz */
389 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
390 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
391 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 1792x1344@75Hz */
393 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
394 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 1792x1344@120Hz RB */
397 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
398 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
400 /* 1856x1392@60Hz */
401 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
402 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
403 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
404 /* 1856x1392@75Hz */
405 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
406 2208, 2560, 0, 1392, 1395, 1399, 1500, 0,
407 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 1856x1392@120Hz RB */
409 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
410 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 1920x1200@60Hz RB */
413 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
414 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
416 /* 1920x1200@60Hz */
417 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
418 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 1920x1200@75Hz */
421 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
422 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
424 /* 1920x1200@85Hz */
425 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
426 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 1920x1200@120Hz RB */
429 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
430 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
432 /* 1920x1440@60Hz */
433 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
434 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 1920x1440@75Hz */
437 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
438 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 1920x1440@120Hz RB */
441 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
442 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 2560x1600@60Hz RB */
445 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
446 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 2560x1600@60Hz */
449 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
450 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 2560x1600@75HZ */
453 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
454 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 2560x1600@85HZ */
457 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
458 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 2560x1600@120Hz RB */
461 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
462 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
464};
465
e7bfa5c4
VS		 466/*
467 * These more or less come from the DMT spec. The 720x400 modes are
468 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
469 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
470 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
471 * mode.
472 *
473 * The DMT modes have been fact-checked; the rest are mild guesses.
474 */
a6b21831
TR		 475static const struct drm_display_mode edid_est_modes[] = {
476 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
477 968, 1056, 0, 600, 601, 605, 628, 0,
478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
479 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
480 896, 1024, 0, 600, 601, 603, 625, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
482 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
483 720, 840, 0, 480, 481, 484, 500, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
485 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
486 704, 832, 0, 480, 489, 491, 520, 0,
487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
488 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
489 768, 864, 0, 480, 483, 486, 525, 0,
490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
492 752, 800, 0, 480, 490, 492, 525, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
494 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
495 846, 900, 0, 400, 421, 423, 449, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
497 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
498 846, 900, 0, 400, 412, 414, 449, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
500 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
501 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
503 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
504 1136, 1312, 0, 768, 769, 772, 800, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
506 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
507 1184, 1328, 0, 768, 771, 777, 806, 0,
508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
509 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
510 1184, 1344, 0, 768, 771, 777, 806, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
512 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
513 1208, 1264, 0, 768, 768, 776, 817, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
515 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
516 928, 1152, 0, 624, 625, 628, 667, 0,
517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
518 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
519 896, 1056, 0, 600, 601, 604, 625, 0,
520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
521 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
522 976, 1040, 0, 600, 637, 643, 666, 0,
523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
524 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
525 1344, 1600, 0, 864, 865, 868, 900, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
527};
528
529struct minimode {
530 short w;
531 short h;
532 short r;
533 short rb;
534};
535
536static const struct minimode est3_modes[] = {
537 /* byte 6 */
538 { 640, 350, 85, 0 },
539 { 640, 400, 85, 0 },
540 { 720, 400, 85, 0 },
541 { 640, 480, 85, 0 },
542 { 848, 480, 60, 0 },
543 { 800, 600, 85, 0 },
544 { 1024, 768, 85, 0 },
545 { 1152, 864, 75, 0 },
546 /* byte 7 */
547 { 1280, 768, 60, 1 },
548 { 1280, 768, 60, 0 },
549 { 1280, 768, 75, 0 },
550 { 1280, 768, 85, 0 },
551 { 1280, 960, 60, 0 },
552 { 1280, 960, 85, 0 },
553 { 1280, 1024, 60, 0 },
554 { 1280, 1024, 85, 0 },
555 /* byte 8 */
556 { 1360, 768, 60, 0 },
557 { 1440, 900, 60, 1 },
558 { 1440, 900, 60, 0 },
559 { 1440, 900, 75, 0 },
560 { 1440, 900, 85, 0 },
561 { 1400, 1050, 60, 1 },
562 { 1400, 1050, 60, 0 },
563 { 1400, 1050, 75, 0 },
564 /* byte 9 */
565 { 1400, 1050, 85, 0 },
566 { 1680, 1050, 60, 1 },
567 { 1680, 1050, 60, 0 },
568 { 1680, 1050, 75, 0 },
569 { 1680, 1050, 85, 0 },
570 { 1600, 1200, 60, 0 },
571 { 1600, 1200, 65, 0 },
572 { 1600, 1200, 70, 0 },
573 /* byte 10 */
574 { 1600, 1200, 75, 0 },
575 { 1600, 1200, 85, 0 },
576 { 1792, 1344, 60, 0 },
c068b32a 577 { 1792, 1344, 75, 0 },
a6b21831
TR		 578 { 1856, 1392, 60, 0 },
579 { 1856, 1392, 75, 0 },
580 { 1920, 1200, 60, 1 },
581 { 1920, 1200, 60, 0 },
582 /* byte 11 */
583 { 1920, 1200, 75, 0 },
584 { 1920, 1200, 85, 0 },
585 { 1920, 1440, 60, 0 },
586 { 1920, 1440, 75, 0 },
587};
588
589static const struct minimode extra_modes[] = {
590 { 1024, 576, 60, 0 },
591 { 1366, 768, 60, 0 },
592 { 1600, 900, 60, 0 },
593 { 1680, 945, 60, 0 },
594 { 1920, 1080, 60, 0 },
595 { 2048, 1152, 60, 0 },
596 { 2048, 1536, 60, 0 },
597};
598
599/*
600 * Probably taken from CEA-861 spec.
601 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
602 */
603static const struct drm_display_mode edid_cea_modes[] = {
604 /* 1 - 640x480@60Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
ee7925bb 607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 608 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 609 /* 2 - 720x480@60Hz */
610 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
611 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 612 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 613 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 614 /* 3 - 720x480@60Hz */
615 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
616 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 618 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 619 /* 4 - 1280x720@60Hz */
620 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
621 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 622 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 623 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 624 /* 5 - 1920x1080i@60Hz */
625 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
626 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 628 DRM_MODE_FLAG_INTERLACE),
985e5dc2 629 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 630 /* 6 - 1440x480i@60Hz */
631 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
632 1602, 1716, 0, 480, 488, 494, 525, 0,
633 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 634 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 636 /* 7 - 1440x480i@60Hz */
637 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
638 1602, 1716, 0, 480, 488, 494, 525, 0,
639 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 640 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 641 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 642 /* 8 - 1440x240@60Hz */
643 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
644 1602, 1716, 0, 240, 244, 247, 262, 0,
645 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 646 DRM_MODE_FLAG_DBLCLK),
985e5dc2 647 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 648 /* 9 - 1440x240@60Hz */
649 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478,
650 1602, 1716, 0, 240, 244, 247, 262, 0,
651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 652 DRM_MODE_FLAG_DBLCLK),
985e5dc2 653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 654 /* 10 - 2880x480i@60Hz */
655 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
656 3204, 3432, 0, 480, 488, 494, 525, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 658 DRM_MODE_FLAG_INTERLACE),
985e5dc2 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 660 /* 11 - 2880x480i@60Hz */
661 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
662 3204, 3432, 0, 480, 488, 494, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 664 DRM_MODE_FLAG_INTERLACE),
985e5dc2 665 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 666 /* 12 - 2880x240@60Hz */
667 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
668 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 669 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 671 /* 13 - 2880x240@60Hz */
672 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
673 3204, 3432, 0, 240, 244, 247, 262, 0,
ee7925bb 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 675 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 676 /* 14 - 1440x480@60Hz */
677 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
678 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 679 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 681 /* 15 - 1440x480@60Hz */
682 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
683 1596, 1716, 0, 480, 489, 495, 525, 0,
ee7925bb 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 686 /* 16 - 1920x1080@60Hz */
687 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
688 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 691 /* 17 - 720x576@50Hz */
692 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
693 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 695 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 696 /* 18 - 720x576@50Hz */
697 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
698 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 700 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 701 /* 19 - 1280x720@50Hz */
702 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
703 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 705 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 706 /* 20 - 1920x1080i@50Hz */
707 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
708 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 710 DRM_MODE_FLAG_INTERLACE),
985e5dc2 711 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 712 /* 21 - 1440x576i@50Hz */
713 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
714 1590, 1728, 0, 576, 580, 586, 625, 0,
715 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 716 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 717 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 718 /* 22 - 1440x576i@50Hz */
719 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
720 1590, 1728, 0, 576, 580, 586, 625, 0,
721 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 722 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 723 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 724 /* 23 - 1440x288@50Hz */
725 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
726 1590, 1728, 0, 288, 290, 293, 312, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 728 DRM_MODE_FLAG_DBLCLK),
985e5dc2 729 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 730 /* 24 - 1440x288@50Hz */
731 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464,
732 1590, 1728, 0, 288, 290, 293, 312, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 734 DRM_MODE_FLAG_DBLCLK),
985e5dc2 735 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 736 /* 25 - 2880x576i@50Hz */
737 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
738 3180, 3456, 0, 576, 580, 586, 625, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 740 DRM_MODE_FLAG_INTERLACE),
985e5dc2 741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 742 /* 26 - 2880x576i@50Hz */
743 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
744 3180, 3456, 0, 576, 580, 586, 625, 0,
745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 746 DRM_MODE_FLAG_INTERLACE),
985e5dc2 747 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 748 /* 27 - 2880x288@50Hz */
749 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
750 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 751 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 753 /* 28 - 2880x288@50Hz */
754 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
755 3180, 3456, 0, 288, 290, 293, 312, 0,
ee7925bb 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 757 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 758 /* 29 - 1440x576@50Hz */
759 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
760 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 763 /* 30 - 1440x576@50Hz */
764 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
765 1592, 1728, 0, 576, 581, 586, 625, 0,
ee7925bb 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 768 /* 31 - 1920x1080@50Hz */
769 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
770 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 773 /* 32 - 1920x1080@24Hz */
774 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
775 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 776 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 777 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 778 /* 33 - 1920x1080@25Hz */
779 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
780 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 782 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 783 /* 34 - 1920x1080@30Hz */
784 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
785 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 787 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 788 /* 35 - 2880x480@60Hz */
789 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
790 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 793 /* 36 - 2880x480@60Hz */
794 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
795 3192, 3432, 0, 480, 489, 495, 525, 0,
ee7925bb 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 798 /* 37 - 2880x576@50Hz */
799 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
800 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 803 /* 38 - 2880x576@50Hz */
804 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
805 3184, 3456, 0, 576, 581, 586, 625, 0,
ee7925bb 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 808 /* 39 - 1920x1080i@50Hz */
809 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
810 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 812 DRM_MODE_FLAG_INTERLACE),
985e5dc2 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 814 /* 40 - 1920x1080i@100Hz */
815 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
816 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 818 DRM_MODE_FLAG_INTERLACE),
985e5dc2 819 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 820 /* 41 - 1280x720@100Hz */
821 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
822 1760, 1980, 0, 720, 725, 730, 750, 0,
ee7925bb 823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 824 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 825 /* 42 - 720x576@100Hz */
826 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
827 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 828 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 829 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 830 /* 43 - 720x576@100Hz */
831 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
832 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 833 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 834 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 835 /* 44 - 1440x576i@100Hz */
836 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
837 1590, 1728, 0, 576, 580, 586, 625, 0,
838 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 839 DRM_MODE_FLAG_DBLCLK),
985e5dc2 840 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 841 /* 45 - 1440x576i@100Hz */
842 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
843 1590, 1728, 0, 576, 580, 586, 625, 0,
844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 845 DRM_MODE_FLAG_DBLCLK),
985e5dc2 846 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 847 /* 46 - 1920x1080i@120Hz */
848 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
849 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
ee7925bb 851 DRM_MODE_FLAG_INTERLACE),
985e5dc2 852 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 853 /* 47 - 1280x720@120Hz */
854 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
855 1430, 1650, 0, 720, 725, 730, 750, 0,
ee7925bb 856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 857 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 858 /* 48 - 720x480@120Hz */
859 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
860 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 862 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 863 /* 49 - 720x480@120Hz */
864 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
865 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 867 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 868 /* 50 - 1440x480i@120Hz */
869 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
870 1602, 1716, 0, 480, 488, 494, 525, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 872 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 873 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 874 /* 51 - 1440x480i@120Hz */
875 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478,
876 1602, 1716, 0, 480, 488, 494, 525, 0,
877 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 878 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 879 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 880 /* 52 - 720x576@200Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 884 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 885 /* 53 - 720x576@200Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
ee7925bb 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 889 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 890 /* 54 - 1440x576i@200Hz */
891 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
892 1590, 1728, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 895 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 896 /* 55 - 1440x576i@200Hz */
897 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464,
898 1590, 1728, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 901 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 902 /* 56 - 720x480@240Hz */
903 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
904 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 905 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 906 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 907 /* 57 - 720x480@240Hz */
908 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
909 798, 858, 0, 480, 489, 495, 525, 0,
ee7925bb 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
985e5dc2 911 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 912 /* 58 - 1440x480i@240 */
913 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
914 1602, 1716, 0, 480, 488, 494, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 916 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 917 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
a6b21831
TR		 918 /* 59 - 1440x480i@240 */
919 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478,
920 1602, 1716, 0, 480, 488, 494, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
ee7925bb 922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
985e5dc2 923 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 924 /* 60 - 1280x720@24Hz */
925 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
926 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 928 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 929 /* 61 - 1280x720@25Hz */
930 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
931 3740, 3960, 0, 720, 725, 730, 750, 0,
ee7925bb 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 933 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 934 /* 62 - 1280x720@30Hz */
935 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
936 3080, 3300, 0, 720, 725, 730, 750, 0,
ee7925bb 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 938 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 939 /* 63 - 1920x1080@120Hz */
940 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
941 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
ee7925bb 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 943 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 944 /* 64 - 1920x1080@100Hz */
945 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
946 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
ee7925bb 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
985e5dc2 948 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
a6b21831
TR		 949};
950
7ebe1963
LD		 951/*
952 * HDMI 1.4 4k modes.
953 */
954static const struct drm_display_mode edid_4k_modes[] = {
955 /* 1 - 3840x2160@30Hz */
956 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
957 3840, 4016, 4104, 4400, 0,
958 2160, 2168, 2178, 2250, 0,
959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
960 .vrefresh = 30, },
961 /* 2 - 3840x2160@25Hz */
962 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
963 3840, 4896, 4984, 5280, 0,
964 2160, 2168, 2178, 2250, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
966 .vrefresh = 25, },
967 /* 3 - 3840x2160@24Hz */
968 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
969 3840, 5116, 5204, 5500, 0,
970 2160, 2168, 2178, 2250, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .vrefresh = 24, },
973 /* 4 - 4096x2160@24Hz (SMPTE) */
974 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
975 4096, 5116, 5204, 5500, 0,
976 2160, 2168, 2178, 2250, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 24, },
979};
980
61e57a8d 981/*** DDC fetch and block validation ***/
f453ba04 982
083ae056
AJ		 983static const u8 edid_header[] = {
984 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
985};
f453ba04 986
db6cf833
TR		 987/**
988 * drm_edid_header_is_valid - sanity check the header of the base EDID block
989 * @raw_edid: pointer to raw base EDID block
990 *
991 * Sanity check the header of the base EDID block.
992 *
993 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
051963d4
TR		 994 */
995int drm_edid_header_is_valid(const u8 *raw_edid)
996{
997 int i, score = 0;
998
999 for (i = 0; i < sizeof(edid_header); i++)
1000 if (raw_edid[i] == edid_header[i])
1001 score++;
1002
1003 return score;
1004}
1005EXPORT_SYMBOL(drm_edid_header_is_valid);
1006
47819ba2
AJ		 1007static int edid_fixup __read_mostly = 6;
1008module_param_named(edid_fixup, edid_fixup, int, 0400);
1009MODULE_PARM_DESC(edid_fixup,
1010 "Minimum number of valid EDID header bytes (0-8, default 6)");
051963d4 1011
db6cf833
TR		 1012/**
1013 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1014 * @raw_edid: pointer to raw EDID block
1015 * @block: type of block to validate (0 for base, extension otherwise)
1016 * @print_bad_edid: if true, dump bad EDID blocks to the console
1017 *
1018 * Validate a base or extension EDID block and optionally dump bad blocks to
1019 * the console.
1020 *
1021 * Return: True if the block is valid, false otherwise.
f453ba04 1022 */
0b2443ed 1023bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid)
f453ba04 1024{
61e57a8d 1025 int i;
f453ba04 1026 u8 csum = 0;
61e57a8d 1027 struct edid *edid = (struct edid *)raw_edid;
f453ba04 1028
fe2ef780
SWK		 1029 if (WARN_ON(!raw_edid))
1030 return false;
1031
47819ba2
AJ		 1032 if (edid_fixup > 8 || edid_fixup < 0)
1033 edid_fixup = 6;
1034
f89ec8a4 1035 if (block == 0) {
051963d4 1036 int score = drm_edid_header_is_valid(raw_edid);
61e57a8d 1037 if (score == 8) ;
47819ba2 1038 else if (score >= edid_fixup) {
61e57a8d
AJ		 1039 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1040 memcpy(raw_edid, edid_header, sizeof(edid_header));
1041 } else {
1042 goto bad;
1043 }
1044 }
f453ba04
DA		 1045
1046 for (i = 0; i < EDID_LENGTH; i++)
1047 csum += raw_edid[i];
1048 if (csum) {
0b2443ed
JG		 1049 if (print_bad_edid) {
1050 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1051 }
4a638b4e
AJ		 1052
1053 /* allow CEA to slide through, switches mangle this */
1054 if (raw_edid[0] != 0x02)
1055 goto bad;
f453ba04
DA		 1056 }
1057
61e57a8d
AJ		 1058 /* per-block-type checks */
1059 switch (raw_edid[0]) {
1060 case 0: /* base */
1061 if (edid->version != 1) {
1062 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1063 goto bad;
1064 }
862b89c0 1065
61e57a8d
AJ		 1066 if (edid->revision > 4)
1067 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1068 break;
862b89c0 1069
61e57a8d
AJ		 1070 default:
1071 break;
1072 }
47ee4ccf 1073
fe2ef780 1074 return true;
f453ba04
DA		 1075
1076bad:
fe2ef780 1077 if (print_bad_edid) {
f49dadb8 1078 printk(KERN_ERR "Raw EDID:\n");
0aff47f2
TV		 1079 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1080 raw_edid, EDID_LENGTH, false);
f453ba04 1081 }
fe2ef780 1082 return false;
f453ba04 1083}
da0df92b 1084EXPORT_SYMBOL(drm_edid_block_valid);
61e57a8d
AJ		 1085
1086/**
1087 * drm_edid_is_valid - sanity check EDID data
1088 * @edid: EDID data
1089 *
1090 * Sanity-check an entire EDID record (including extensions)
db6cf833
TR		 1091 *
1092 * Return: True if the EDID data is valid, false otherwise.
61e57a8d
AJ		 1093 */
1094bool drm_edid_is_valid(struct edid *edid)
1095{
1096 int i;
1097 u8 *raw = (u8 *)edid;
1098
1099 if (!edid)
1100 return false;
1101
1102 for (i = 0; i <= edid->extensions; i++)
0b2443ed 1103 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true))
61e57a8d
AJ		 1104 return false;
1105
1106 return true;
1107}
3c537889 1108EXPORT_SYMBOL(drm_edid_is_valid);
f453ba04 1109
61e57a8d
AJ		 1110#define DDC_SEGMENT_ADDR 0x30
1111/**
db6cf833
TR		 1112 * drm_do_probe_ddc_edid() - get EDID information via I2C
1113 * @adapter: I2C device adaptor
fc66811c
DV		 1114 * @buf: EDID data buffer to be filled
1115 * @block: 128 byte EDID block to start fetching from
1116 * @len: EDID data buffer length to fetch
1117 *
db6cf833 1118 * Try to fetch EDID information by calling I2C driver functions.
61e57a8d 1119 *
db6cf833 1120 * Return: 0 on success or -1 on failure.
61e57a8d
AJ		 1121 */
1122static int
1123drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
1124 int block, int len)
1125{
1126 unsigned char start = block * EDID_LENGTH;
cd004b3f
S		 1127 unsigned char segment = block >> 1;
1128 unsigned char xfers = segment ? 3 : 2;
4819d2e4
CW		 1129 int ret, retries = 5;
1130
db6cf833
TR		 1131 /*
1132 * The core I2C driver will automatically retry the transfer if the
4819d2e4
CW		 1133 * adapter reports EAGAIN. However, we find that bit-banging transfers
1134 * are susceptible to errors under a heavily loaded machine and
1135 * generate spurious NAKs and timeouts. Retrying the transfer
1136 * of the individual block a few times seems to overcome this.
1137 */
1138 do {
1139 struct i2c_msg msgs[] = {
1140 {
cd004b3f
S		 1141 .addr = DDC_SEGMENT_ADDR,
1142 .flags = 0,
1143 .len = 1,
1144 .buf = &segment,
1145 }, {
4819d2e4
CW		 1146 .addr = DDC_ADDR,
1147 .flags = 0,
1148 .len = 1,
1149 .buf = &start,
1150 }, {
1151 .addr = DDC_ADDR,
1152 .flags = I2C_M_RD,
1153 .len = len,
1154 .buf = buf,
1155 }
1156 };
cd004b3f 1157
db6cf833
TR		 1158 /*
1159 * Avoid sending the segment addr to not upset non-compliant
1160 * DDC monitors.
1161 */
cd004b3f
S		 1162 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1163
9292f37e
ED		 1164 if (ret == -ENXIO) {
1165 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1166 adapter->name);
1167 break;
1168 }
cd004b3f 1169 } while (ret != xfers && --retries);
4819d2e4 1170
cd004b3f 1171 return ret == xfers ? 0 : -1;
61e57a8d
AJ		 1172}
1173
4a9a8b71
DA		 1174static bool drm_edid_is_zero(u8 *in_edid, int length)
1175{
6311803b
AM		 1176 if (memchr_inv(in_edid, 0, length))
1177 return false;
4a9a8b71 1178
4a9a8b71
DA		 1179 return true;
1180}
1181
61e57a8d
AJ		 1182static u8 *
1183drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1184{
0ea75e23 1185 int i, j = 0, valid_extensions = 0;
61e57a8d 1186 u8 *block, *new;
0b2443ed 1187 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
61e57a8d
AJ		 1188
1189 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1190 return NULL;
1191
1192 /* base block fetch */
1193 for (i = 0; i < 4; i++) {
1194 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH))
1195 goto out;
0b2443ed 1196 if (drm_edid_block_valid(block, 0, print_bad_edid))
61e57a8d 1197 break;
4a9a8b71
DA		 1198 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1199 connector->null_edid_counter++;
1200 goto carp;
1201 }
61e57a8d
AJ		 1202 }
1203 if (i == 4)
1204 goto carp;
1205
1206 /* if there's no extensions, we're done */
1207 if (block[0x7e] == 0)
1208 return block;
1209
1210 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1211 if (!new)
1212 goto out;
1213 block = new;
1214
1215 for (j = 1; j <= block[0x7e]; j++) {
1216 for (i = 0; i < 4; i++) {
0ea75e23
ST		 1217 if (drm_do_probe_ddc_edid(adapter,
1218 block + (valid_extensions + 1) * EDID_LENGTH,
1219 j, EDID_LENGTH))
61e57a8d 1220 goto out;
0b2443ed 1221 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) {
0ea75e23 1222 valid_extensions++;
61e57a8d 1223 break;
0ea75e23 1224 }
61e57a8d 1225 }
f934ec8c
ML		 1226
1227 if (i == 4 && print_bad_edid) {
0ea75e23
ST		 1228 dev_warn(connector->dev->dev,
1229 "%s: Ignoring invalid EDID block %d.\n",
1230 drm_get_connector_name(connector), j);
f934ec8c
ML		 1231
1232 connector->bad_edid_counter++;
1233 }
0ea75e23
ST		 1234 }
1235
1236 if (valid_extensions != block[0x7e]) {
1237 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1238 block[0x7e] = valid_extensions;
1239 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1240 if (!new)
1241 goto out;
1242 block = new;
61e57a8d
AJ		 1243 }
1244
1245 return block;
1246
1247carp:
0b2443ed
JG		 1248 if (print_bad_edid) {
1249 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1250 drm_get_connector_name(connector), j);
1251 }
1252 connector->bad_edid_counter++;
61e57a8d
AJ		 1253
1254out:
1255 kfree(block);
1256 return NULL;
1257}
1258
1259/**
db6cf833
TR		 1260 * drm_probe_ddc() - probe DDC presence
1261 * @adapter: I2C adapter to probe
fc66811c 1262 *
db6cf833 1263 * Return: True on success, false on failure.
61e57a8d 1264 */
fbff4690 1265bool
61e57a8d
AJ		 1266drm_probe_ddc(struct i2c_adapter *adapter)
1267{
1268 unsigned char out;
1269
1270 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1271}
fbff4690 1272EXPORT_SYMBOL(drm_probe_ddc);
61e57a8d
AJ		 1273
1274/**
1275 * drm_get_edid - get EDID data, if available
1276 * @connector: connector we're probing
db6cf833 1277 * @adapter: I2C adapter to use for DDC
61e57a8d 1278 *
db6cf833 1279 * Poke the given I2C channel to grab EDID data if possible. If found,
61e57a8d
AJ		 1280 * attach it to the connector.
1281 *
db6cf833 1282 * Return: Pointer to valid EDID or NULL if we couldn't find any.
61e57a8d
AJ		 1283 */
1284struct edid *drm_get_edid(struct drm_connector *connector,
1285 struct i2c_adapter *adapter)
1286{
1287 struct edid *edid = NULL;
1288
1289 if (drm_probe_ddc(adapter))
1290 edid = (struct edid *)drm_do_get_edid(connector, adapter);
1291
61e57a8d 1292 return edid;
61e57a8d
AJ		 1293}
1294EXPORT_SYMBOL(drm_get_edid);
1295
51f8da59
JN		 1296/**
1297 * drm_edid_duplicate - duplicate an EDID and the extensions
1298 * @edid: EDID to duplicate
1299 *
db6cf833 1300 * Return: Pointer to duplicated EDID or NULL on allocation failure.
51f8da59
JN		 1301 */
1302struct edid *drm_edid_duplicate(const struct edid *edid)
1303{
1304 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1305}
1306EXPORT_SYMBOL(drm_edid_duplicate);
1307
61e57a8d
AJ		 1308/*** EDID parsing ***/
1309
f453ba04
DA		 1310/**
1311 * edid_vendor - match a string against EDID's obfuscated vendor field
1312 * @edid: EDID to match
1313 * @vendor: vendor string
1314 *
1315 * Returns true if @vendor is in @edid, false otherwise
1316 */
1317static bool edid_vendor(struct edid *edid, char *vendor)
1318{
1319 char edid_vendor[3];
1320
1321 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1322 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1323 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
16456c87 1324 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
f453ba04
DA		 1325
1326 return !strncmp(edid_vendor, vendor, 3);
1327}
1328
1329/**
1330 * edid_get_quirks - return quirk flags for a given EDID
1331 * @edid: EDID to process
1332 *
1333 * This tells subsequent routines what fixes they need to apply.
1334 */
1335static u32 edid_get_quirks(struct edid *edid)
1336{
1337 struct edid_quirk *quirk;
1338 int i;
1339
1340 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1341 quirk = &edid_quirk_list[i];
1342
1343 if (edid_vendor(edid, quirk->vendor) &&
1344 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1345 return quirk->quirks;
1346 }
1347
1348 return 0;
1349}
1350
1351#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
339d202c 1352#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
f453ba04 1353
f453ba04
DA		 1354/**
1355 * edid_fixup_preferred - set preferred modes based on quirk list
1356 * @connector: has mode list to fix up
1357 * @quirks: quirks list
1358 *
1359 * Walk the mode list for @connector, clearing the preferred status
1360 * on existing modes and setting it anew for the right mode ala @quirks.
1361 */
1362static void edid_fixup_preferred(struct drm_connector *connector,
1363 u32 quirks)
1364{
1365 struct drm_display_mode *t, *cur_mode, *preferred_mode;
f890607b 1366 int target_refresh = 0;
339d202c 1367 int cur_vrefresh, preferred_vrefresh;
f453ba04
DA		 1368
1369 if (list_empty(&connector->probed_modes))
1370 return;
1371
1372 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1373 target_refresh = 60;
1374 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1375 target_refresh = 75;
1376
1377 preferred_mode = list_first_entry(&connector->probed_modes,
1378 struct drm_display_mode, head);
1379
1380 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1381 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1382
1383 if (cur_mode == preferred_mode)
1384 continue;
1385
1386 /* Largest mode is preferred */
1387 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1388 preferred_mode = cur_mode;
1389
339d202c
AD		 1390 cur_vrefresh = cur_mode->vrefresh ?
1391 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1392 preferred_vrefresh = preferred_mode->vrefresh ?
1393 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
f453ba04
DA		 1394 /* At a given size, try to get closest to target refresh */
1395 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
339d202c
AD		 1396 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1397 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
f453ba04
DA		 1398 preferred_mode = cur_mode;
1399 }
1400 }
1401
1402 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1403}
1404
f6e252ba
AJ		 1405static bool
1406mode_is_rb(const struct drm_display_mode *mode)
1407{
1408 return (mode->htotal - mode->hdisplay == 160) &&
1409 (mode->hsync_end - mode->hdisplay == 80) &&
1410 (mode->hsync_end - mode->hsync_start == 32) &&
1411 (mode->vsync_start - mode->vdisplay == 3);
1412}
1413
33c7531d
AJ		 1414/*
1415 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1416 * @dev: Device to duplicate against
1417 * @hsize: Mode width
1418 * @vsize: Mode height
1419 * @fresh: Mode refresh rate
f6e252ba 1420 * @rb: Mode reduced-blanking-ness
33c7531d
AJ		 1421 *
1422 * Walk the DMT mode list looking for a match for the given parameters.
db6cf833
TR		 1423 *
1424 * Return: A newly allocated copy of the mode, or NULL if not found.
33c7531d 1425 */
1d42bbc8 1426struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
f6e252ba
AJ		 1427 int hsize, int vsize, int fresh,
1428 bool rb)
559ee21d 1429{
07a5e632 1430 int i;
559ee21d 1431
a6b21831 1432 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
b1f559ec 1433 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f8b46a05
AJ		 1434 if (hsize != ptr->hdisplay)
1435 continue;
1436 if (vsize != ptr->vdisplay)
1437 continue;
1438 if (fresh != drm_mode_vrefresh(ptr))
1439 continue;
f6e252ba
AJ		 1440 if (rb != mode_is_rb(ptr))
1441 continue;
f8b46a05
AJ		 1442
1443 return drm_mode_duplicate(dev, ptr);
559ee21d 1444 }
f8b46a05
AJ		 1445
1446 return NULL;
559ee21d 1447}
1d42bbc8 1448EXPORT_SYMBOL(drm_mode_find_dmt);
23425cae 1449
d1ff6409
AJ		 1450typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1451
4d76a221
AJ		 1452static void
1453cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1454{
1455 int i, n = 0;
4966b2a9 1456 u8 d = ext[0x02];
4d76a221
AJ		 1457 u8 *det_base = ext + d;
1458
4966b2a9 1459 n = (127 - d) / 18;
4d76a221
AJ		 1460 for (i = 0; i < n; i++)
1461 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1462}
1463
cbba98f8
AJ		 1464static void
1465vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1466{
1467 unsigned int i, n = min((int)ext[0x02], 6);
1468 u8 *det_base = ext + 5;
1469
1470 if (ext[0x01] != 1)
1471 return; /* unknown version */
1472
1473 for (i = 0; i < n; i++)
1474 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1475}
1476
d1ff6409
AJ		 1477static void
1478drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1479{
1480 int i;
1481 struct edid *edid = (struct edid *)raw_edid;
1482
1483 if (edid == NULL)
1484 return;
1485
1486 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1487 cb(&(edid->detailed_timings[i]), closure);
1488
4d76a221
AJ		 1489 for (i = 1; i <= raw_edid[0x7e]; i++) {
1490 u8 *ext = raw_edid + (i * EDID_LENGTH);
1491 switch (*ext) {
1492 case CEA_EXT:
1493 cea_for_each_detailed_block(ext, cb, closure);
1494 break;
cbba98f8
AJ		 1495 case VTB_EXT:
1496 vtb_for_each_detailed_block(ext, cb, closure);
1497 break;
4d76a221
AJ		 1498 default:
1499 break;
1500 }
1501 }
d1ff6409
AJ		 1502}
1503
1504static void
1505is_rb(struct detailed_timing *t, void *data)
1506{
1507 u8 *r = (u8 *)t;
1508 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1509 if (r[15] & 0x10)
1510 *(bool *)data = true;
1511}
1512
1513/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1514static bool
1515drm_monitor_supports_rb(struct edid *edid)
1516{
1517 if (edid->revision >= 4) {
b196a498 1518 bool ret = false;
d1ff6409
AJ		 1519 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1520 return ret;
1521 }
1522
1523 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1524}
1525
7a374350
AJ		 1526static void
1527find_gtf2(struct detailed_timing *t, void *data)
1528{
1529 u8 *r = (u8 *)t;
1530 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1531 *(u8 **)data = r;
1532}
1533
1534/* Secondary GTF curve kicks in above some break frequency */
1535static int
1536drm_gtf2_hbreak(struct edid *edid)
1537{
1538 u8 *r = NULL;
1539 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1540 return r ? (r[12] * 2) : 0;
1541}
1542
1543static int
1544drm_gtf2_2c(struct edid *edid)
1545{
1546 u8 *r = NULL;
1547 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1548 return r ? r[13] : 0;
1549}
1550
1551static int
1552drm_gtf2_m(struct edid *edid)
1553{
1554 u8 *r = NULL;
1555 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1556 return r ? (r[15] << 8) + r[14] : 0;
1557}
1558
1559static int
1560drm_gtf2_k(struct edid *edid)
1561{
1562 u8 *r = NULL;
1563 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1564 return r ? r[16] : 0;
1565}
1566
1567static int
1568drm_gtf2_2j(struct edid *edid)
1569{
1570 u8 *r = NULL;
1571 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1572 return r ? r[17] : 0;
1573}
1574
1575/**
1576 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1577 * @edid: EDID block to scan
1578 */
1579static int standard_timing_level(struct edid *edid)
1580{
1581 if (edid->revision >= 2) {
1582 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1583 return LEVEL_CVT;
1584 if (drm_gtf2_hbreak(edid))
1585 return LEVEL_GTF2;
1586 return LEVEL_GTF;
1587 }
1588 return LEVEL_DMT;
1589}
1590
23425cae
AJ		 1591/*
1592 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1593 * monitors fill with ascii space (0x20) instead.
1594 */
1595static int
1596bad_std_timing(u8 a, u8 b)
1597{
1598 return (a == 0x00 && b == 0x00) ||
1599 (a == 0x01 && b == 0x01) ||
1600 (a == 0x20 && b == 0x20);
1601}
1602
f453ba04
DA		 1603/**
1604 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
fc66811c
DV		 1605 * @connector: connector of for the EDID block
1606 * @edid: EDID block to scan
f453ba04
DA		 1607 * @t: standard timing params
1608 *
1609 * Take the standard timing params (in this case width, aspect, and refresh)
5c61259e 1610 * and convert them into a real mode using CVT/GTF/DMT.
f453ba04 1611 */
7ca6adb3 1612static struct drm_display_mode *
7a374350 1613drm_mode_std(struct drm_connector *connector, struct edid *edid,
464fdeca 1614 struct std_timing *t)
f453ba04 1615{
7ca6adb3
AJ		 1616 struct drm_device *dev = connector->dev;
1617 struct drm_display_mode *m, *mode = NULL;
5c61259e
ZY		 1618 int hsize, vsize;
1619 int vrefresh_rate;
0454beab
MD		 1620 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1621 >> EDID_TIMING_ASPECT_SHIFT;
5c61259e
ZY		 1622 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1623 >> EDID_TIMING_VFREQ_SHIFT;
7a374350 1624 int timing_level = standard_timing_level(edid);
5c61259e 1625
23425cae
AJ		 1626 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1627 return NULL;
1628
5c61259e
ZY		 1629 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1630 hsize = t->hsize * 8 + 248;
1631 /* vrefresh_rate = vfreq + 60 */
1632 vrefresh_rate = vfreq + 60;
1633 /* the vdisplay is calculated based on the aspect ratio */
f066a17d 1634 if (aspect_ratio == 0) {
464fdeca 1635 if (edid->revision < 3)
f066a17d
AJ		 1636 vsize = hsize;
1637 else
1638 vsize = (hsize * 10) / 16;
1639 } else if (aspect_ratio == 1)
f453ba04 1640 vsize = (hsize * 3) / 4;
0454beab 1641 else if (aspect_ratio == 2)
f453ba04
DA		 1642 vsize = (hsize * 4) / 5;
1643 else
1644 vsize = (hsize * 9) / 16;
a0910c8e
AJ		 1645
1646 /* HDTV hack, part 1 */
1647 if (vrefresh_rate == 60 &&
1648 ((hsize == 1360 && vsize == 765) ||
1649 (hsize == 1368 && vsize == 769))) {
1650 hsize = 1366;
1651 vsize = 768;
1652 }
1653
7ca6adb3
AJ		 1654 /*
1655 * If this connector already has a mode for this size and refresh
1656 * rate (because it came from detailed or CVT info), use that
1657 * instead. This way we don't have to guess at interlace or
1658 * reduced blanking.
1659 */
522032da 1660 list_for_each_entry(m, &connector->probed_modes, head)
7ca6adb3
AJ		 1661 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1662 drm_mode_vrefresh(m) == vrefresh_rate)
1663 return NULL;
1664
a0910c8e
AJ		 1665 /* HDTV hack, part 2 */
1666 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1667 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
d50ba256 1668 false);
559ee21d 1669 mode->hdisplay = 1366;
a4967de6
AJ		 1670 mode->hsync_start = mode->hsync_start - 1;
1671 mode->hsync_end = mode->hsync_end - 1;
559ee21d
ZY		 1672 return mode;
1673 }
a0910c8e 1674
559ee21d 1675 /* check whether it can be found in default mode table */
f6e252ba
AJ		 1676 if (drm_monitor_supports_rb(edid)) {
1677 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1678 true);
1679 if (mode)
1680 return mode;
1681 }
1682 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
559ee21d
ZY		 1683 if (mode)
1684 return mode;
1685
f6e252ba 1686 /* okay, generate it */
5c61259e
ZY		 1687 switch (timing_level) {
1688 case LEVEL_DMT:
5c61259e
ZY		 1689 break;
1690 case LEVEL_GTF:
1691 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1692 break;
7a374350
AJ		 1693 case LEVEL_GTF2:
1694 /*
1695 * This is potentially wrong if there's ever a monitor with
1696 * more than one ranges section, each claiming a different
1697 * secondary GTF curve. Please don't do that.
1698 */
1699 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
fc48f169
TI		 1700 if (!mode)
1701 return NULL;
7a374350 1702 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
aefd330e 1703 drm_mode_destroy(dev, mode);
7a374350
AJ		 1704 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1705 vrefresh_rate, 0, 0,
1706 drm_gtf2_m(edid),
1707 drm_gtf2_2c(edid),
1708 drm_gtf2_k(edid),
1709 drm_gtf2_2j(edid));
1710 }
1711 break;
5c61259e 1712 case LEVEL_CVT:
d50ba256
DA		 1713 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1714 false);
5c61259e
ZY		 1715 break;
1716 }
f453ba04
DA		 1717 return mode;
1718}
1719
b58db2c6
AJ		 1720/*
1721 * EDID is delightfully ambiguous about how interlaced modes are to be
1722 * encoded. Our internal representation is of frame height, but some
1723 * HDTV detailed timings are encoded as field height.
1724 *
1725 * The format list here is from CEA, in frame size. Technically we
1726 * should be checking refresh rate too. Whatever.
1727 */
1728static void
1729drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1730 struct detailed_pixel_timing *pt)
1731{
1732 int i;
1733 static const struct {
1734 int w, h;
1735 } cea_interlaced[] = {
1736 { 1920, 1080 },
1737 { 720, 480 },
1738 { 1440, 480 },
1739 { 2880, 480 },
1740 { 720, 576 },
1741 { 1440, 576 },
1742 { 2880, 576 },
1743 };
b58db2c6
AJ		 1744
1745 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1746 return;
1747
3c581411 1748 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
b58db2c6
AJ		 1749 if ((mode->hdisplay == cea_interlaced[i].w) &&
1750 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1751 mode->vdisplay *= 2;
1752 mode->vsync_start *= 2;
1753 mode->vsync_end *= 2;
1754 mode->vtotal *= 2;
1755 mode->vtotal |= 1;
1756 }
1757 }
1758
1759 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1760}
1761
f453ba04
DA		 1762/**
1763 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1764 * @dev: DRM device (needed to create new mode)
1765 * @edid: EDID block
1766 * @timing: EDID detailed timing info
1767 * @quirks: quirks to apply
1768 *
1769 * An EDID detailed timing block contains enough info for us to create and
1770 * return a new struct drm_display_mode.
1771 */
1772static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1773 struct edid *edid,
1774 struct detailed_timing *timing,
1775 u32 quirks)
1776{
1777 struct drm_display_mode *mode;
1778 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
0454beab
MD		 1779 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1780 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1781 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1782 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
e14cbee4
MD		 1783 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1784 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
16dad1d7 1785 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
e14cbee4 1786 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
f453ba04 1787
fc438966 1788 /* ignore tiny modes */
0454beab 1789 if (hactive < 64 || vactive < 64)
fc438966
AJ		 1790 return NULL;
1791
0454beab 1792 if (pt->misc & DRM_EDID_PT_STEREO) {
c7d015f3 1793 DRM_DEBUG_KMS("stereo mode not supported\n");
f453ba04
DA		 1794 return NULL;
1795 }
0454beab 1796 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
c7d015f3 1797 DRM_DEBUG_KMS("composite sync not supported\n");
f453ba04
DA		 1798 }
1799
fcb45611
ZY		 1800 /* it is incorrect if hsync/vsync width is zero */
1801 if (!hsync_pulse_width || !vsync_pulse_width) {
1802 DRM_DEBUG_KMS("Incorrect Detailed timing. "
1803 "Wrong Hsync/Vsync pulse width\n");
1804 return NULL;
1805 }
bc42aabc
AJ		 1806
1807 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
1808 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
1809 if (!mode)
1810 return NULL;
1811
1812 goto set_size;
1813 }
1814
f453ba04
DA		 1815 mode = drm_mode_create(dev);
1816 if (!mode)
1817 return NULL;
1818
f453ba04 1819 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
0454beab
MD		 1820 timing->pixel_clock = cpu_to_le16(1088);
1821
1822 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
1823
1824 mode->hdisplay = hactive;
1825 mode->hsync_start = mode->hdisplay + hsync_offset;
1826 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
1827 mode->htotal = mode->hdisplay + hblank;
1828
1829 mode->vdisplay = vactive;
1830 mode->vsync_start = mode->vdisplay + vsync_offset;
1831 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
1832 mode->vtotal = mode->vdisplay + vblank;
f453ba04 1833
7064fef5
JB		 1834 /* Some EDIDs have bogus h/vtotal values */
1835 if (mode->hsync_end > mode->htotal)
1836 mode->htotal = mode->hsync_end + 1;
1837 if (mode->vsync_end > mode->vtotal)
1838 mode->vtotal = mode->vsync_end + 1;
1839
b58db2c6 1840 drm_mode_do_interlace_quirk(mode, pt);
f453ba04
DA		 1841
1842 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
0454beab 1843 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
f453ba04
DA		 1844 }
1845
0454beab
MD		 1846 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
1847 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
1848 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
1849 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
f453ba04 1850
bc42aabc 1851set_size:
e14cbee4
MD		 1852 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
1853 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
f453ba04
DA		 1854
1855 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
1856 mode->width_mm *= 10;
1857 mode->height_mm *= 10;
1858 }
1859
1860 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
1861 mode->width_mm = edid->width_cm * 10;
1862 mode->height_mm = edid->height_cm * 10;
1863 }
1864
bc42aabc 1865 mode->type = DRM_MODE_TYPE_DRIVER;
c19b3b0f 1866 mode->vrefresh = drm_mode_vrefresh(mode);
bc42aabc
AJ		 1867 drm_mode_set_name(mode);
1868
f453ba04
DA		 1869 return mode;
1870}
1871
b17e52ef 1872static bool
b1f559ec
CW		 1873mode_in_hsync_range(const struct drm_display_mode *mode,
1874 struct edid *edid, u8 *t)
b17e52ef
AJ		 1875{
1876 int hsync, hmin, hmax;
1877
1878 hmin = t[7];
1879 if (edid->revision >= 4)
1880 hmin += ((t[4] & 0x04) ? 255 : 0);
1881 hmax = t[8];
1882 if (edid->revision >= 4)
1883 hmax += ((t[4] & 0x08) ? 255 : 0);
07a5e632 1884 hsync = drm_mode_hsync(mode);
07a5e632 1885
b17e52ef
AJ		 1886 return (hsync <= hmax && hsync >= hmin);
1887}
1888
1889static bool
b1f559ec
CW		 1890mode_in_vsync_range(const struct drm_display_mode *mode,
1891 struct edid *edid, u8 *t)
b17e52ef
AJ		 1892{
1893 int vsync, vmin, vmax;
1894
1895 vmin = t[5];
1896 if (edid->revision >= 4)
1897 vmin += ((t[4] & 0x01) ? 255 : 0);
1898 vmax = t[6];
1899 if (edid->revision >= 4)
1900 vmax += ((t[4] & 0x02) ? 255 : 0);
1901 vsync = drm_mode_vrefresh(mode);
1902
1903 return (vsync <= vmax && vsync >= vmin);
1904}
1905
1906static u32
1907range_pixel_clock(struct edid *edid, u8 *t)
1908{
1909 /* unspecified */
1910 if (t[9] == 0 || t[9] == 255)
1911 return 0;
1912
1913 /* 1.4 with CVT support gives us real precision, yay */
1914 if (edid->revision >= 4 && t[10] == 0x04)
1915 return (t[9] * 10000) - ((t[12] >> 2) * 250);
1916
1917 /* 1.3 is pathetic, so fuzz up a bit */
1918 return t[9] * 10000 + 5001;
1919}
1920
b17e52ef 1921static bool
b1f559ec 1922mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
b17e52ef
AJ		 1923 struct detailed_timing *timing)
1924{
1925 u32 max_clock;
1926 u8 *t = (u8 *)timing;
1927
1928 if (!mode_in_hsync_range(mode, edid, t))
07a5e632
AJ		 1929 return false;
1930
b17e52ef 1931 if (!mode_in_vsync_range(mode, edid, t))
07a5e632
AJ		 1932 return false;
1933
b17e52ef 1934 if ((max_clock = range_pixel_clock(edid, t)))
07a5e632
AJ		 1935 if (mode->clock > max_clock)
1936 return false;
b17e52ef
AJ		 1937
1938 /* 1.4 max horizontal check */
1939 if (edid->revision >= 4 && t[10] == 0x04)
1940 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
1941 return false;
1942
1943 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
1944 return false;
07a5e632
AJ		 1945
1946 return true;
1947}
1948
7b668ebe
TI		 1949static bool valid_inferred_mode(const struct drm_connector *connector,
1950 const struct drm_display_mode *mode)
1951{
1952 struct drm_display_mode *m;
1953 bool ok = false;
1954
1955 list_for_each_entry(m, &connector->probed_modes, head) {
1956 if (mode->hdisplay == m->hdisplay &&
1957 mode->vdisplay == m->vdisplay &&
1958 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1959 return false; /* duplicated */
1960 if (mode->hdisplay <= m->hdisplay &&
1961 mode->vdisplay <= m->vdisplay)
1962 ok = true;
1963 }
1964 return ok;
1965}
1966
b17e52ef 1967static int
cd4cd3de 1968drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
b17e52ef 1969 struct detailed_timing *timing)
07a5e632
AJ		 1970{
1971 int i, modes = 0;
1972 struct drm_display_mode *newmode;
1973 struct drm_device *dev = connector->dev;
1974
a6b21831 1975 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
7b668ebe
TI		 1976 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
1977 valid_inferred_mode(connector, drm_dmt_modes + i)) {
07a5e632
AJ		 1978 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1979 if (newmode) {
1980 drm_mode_probed_add(connector, newmode);
1981 modes++;
1982 }
1983 }
1984 }
1985
1986 return modes;
1987}
1988
c09dedb7
TI		 1989/* fix up 1366x768 mode from 1368x768;
1990 * GFT/CVT can't express 1366 width which isn't dividable by 8
1991 */
1992static void fixup_mode_1366x768(struct drm_display_mode *mode)
1993{
1994 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
1995 mode->hdisplay = 1366;
1996 mode->hsync_start--;
1997 mode->hsync_end--;
1998 drm_mode_set_name(mode);
1999 }
2000}
2001
b309bd37
AJ		 2002static int
2003drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2004 struct detailed_timing *timing)
2005{
2006 int i, modes = 0;
2007 struct drm_display_mode *newmode;
2008 struct drm_device *dev = connector->dev;
2009
a6b21831 2010 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2011 const struct minimode *m = &extra_modes[i];
2012 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
fc48f169
TI		 2013 if (!newmode)
2014 return modes;
b309bd37 2015
c09dedb7 2016 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2017 if (!mode_in_range(newmode, edid, timing) ||
2018 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2019 drm_mode_destroy(dev, newmode);
2020 continue;
2021 }
2022
2023 drm_mode_probed_add(connector, newmode);
2024 modes++;
2025 }
2026
2027 return modes;
2028}
2029
2030static int
2031drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2032 struct detailed_timing *timing)
2033{
2034 int i, modes = 0;
2035 struct drm_display_mode *newmode;
2036 struct drm_device *dev = connector->dev;
2037 bool rb = drm_monitor_supports_rb(edid);
2038
a6b21831 2039 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
b309bd37
AJ		 2040 const struct minimode *m = &extra_modes[i];
2041 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
fc48f169
TI		 2042 if (!newmode)
2043 return modes;
b309bd37 2044
c09dedb7 2045 fixup_mode_1366x768(newmode);
7b668ebe
TI		 2046 if (!mode_in_range(newmode, edid, timing) ||
2047 !valid_inferred_mode(connector, newmode)) {
b309bd37
AJ		 2048 drm_mode_destroy(dev, newmode);
2049 continue;
2050 }
2051
2052 drm_mode_probed_add(connector, newmode);
2053 modes++;
2054 }
2055
2056 return modes;
2057}
2058
13931579
AJ		 2059static void
2060do_inferred_modes(struct detailed_timing *timing, void *c)
9340d8cf 2061{
13931579
AJ		 2062 struct detailed_mode_closure *closure = c;
2063 struct detailed_non_pixel *data = &timing->data.other_data;
b309bd37 2064 struct detailed_data_monitor_range *range = &data->data.range;
9340d8cf 2065
cb21aafe
AJ		 2066 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2067 return;
2068
2069 closure->modes += drm_dmt_modes_for_range(closure->connector,
2070 closure->edid,
2071 timing);
b309bd37
AJ		 2072
2073 if (!version_greater(closure->edid, 1, 1))
2074 return; /* GTF not defined yet */
2075
2076 switch (range->flags) {
2077 case 0x02: /* secondary gtf, XXX could do more */
2078 case 0x00: /* default gtf */
2079 closure->modes += drm_gtf_modes_for_range(closure->connector,
2080 closure->edid,
2081 timing);
2082 break;
2083 case 0x04: /* cvt, only in 1.4+ */
2084 if (!version_greater(closure->edid, 1, 3))
2085 break;
2086
2087 closure->modes += drm_cvt_modes_for_range(closure->connector,
2088 closure->edid,
2089 timing);
2090 break;
2091 case 0x01: /* just the ranges, no formula */
2092 default:
2093 break;
2094 }
13931579 2095}
69da3015 2096
13931579
AJ		 2097static int
2098add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2099{
2100 struct detailed_mode_closure closure = {
2101 connector, edid, 0, 0, 0
2102 };
9340d8cf 2103
13931579
AJ		 2104 if (version_greater(edid, 1, 0))
2105 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2106 &closure);
9340d8cf 2107
13931579 2108 return closure.modes;
9340d8cf
AJ		 2109}
2110
2255be14
AJ		 2111static int
2112drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2113{
2114 int i, j, m, modes = 0;
2115 struct drm_display_mode *mode;
2116 u8 *est = ((u8 *)timing) + 5;
2117
2118 for (i = 0; i < 6; i++) {
891a7469 2119 for (j = 7; j >= 0; j--) {
2255be14 2120 m = (i * 8) + (7 - j);
3c581411 2121 if (m >= ARRAY_SIZE(est3_modes))
2255be14
AJ		 2122 break;
2123 if (est[i] & (1 << j)) {
1d42bbc8
DA		 2124 mode = drm_mode_find_dmt(connector->dev,
2125 est3_modes[m].w,
2126 est3_modes[m].h,
f6e252ba
AJ		 2127 est3_modes[m].r,
2128 est3_modes[m].rb);
2255be14
AJ		 2129 if (mode) {
2130 drm_mode_probed_add(connector, mode);
2131 modes++;
2132 }
2133 }
2134 }
2135 }
2136
2137 return modes;
2138}
2139
13931579
AJ		 2140static void
2141do_established_modes(struct detailed_timing *timing, void *c)
9cf00977 2142{
13931579 2143 struct detailed_mode_closure *closure = c;
9cf00977 2144 struct detailed_non_pixel *data = &timing->data.other_data;
9cf00977 2145
13931579
AJ		 2146 if (data->type == EDID_DETAIL_EST_TIMINGS)
2147 closure->modes += drm_est3_modes(closure->connector, timing);
2148}
9cf00977 2149
13931579
AJ		 2150/**
2151 * add_established_modes - get est. modes from EDID and add them
db6cf833 2152 * @connector: connector to add mode(s) to
13931579
AJ		 2153 * @edid: EDID block to scan
2154 *
2155 * Each EDID block contains a bitmap of the supported "established modes" list
2156 * (defined above). Tease them out and add them to the global modes list.
2157 */
2158static int
2159add_established_modes(struct drm_connector *connector, struct edid *edid)
2160{
2161 struct drm_device *dev = connector->dev;
2162 unsigned long est_bits = edid->established_timings.t1 |
2163 (edid->established_timings.t2 << 8) |
2164 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2165 int i, modes = 0;
2166 struct detailed_mode_closure closure = {
2167 connector, edid, 0, 0, 0
2168 };
9cf00977 2169
13931579
AJ		 2170 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2171 if (est_bits & (1<<i)) {
2172 struct drm_display_mode *newmode;
2173 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2174 if (newmode) {
2175 drm_mode_probed_add(connector, newmode);
2176 modes++;
2177 }
2178 }
9cf00977
AJ		 2179 }
2180
13931579
AJ		 2181 if (version_greater(edid, 1, 0))
2182 drm_for_each_detailed_block((u8 *)edid,
2183 do_established_modes, &closure);
2184
2185 return modes + closure.modes;
2186}
2187
2188static void
2189do_standard_modes(struct detailed_timing *timing, void *c)
2190{
2191 struct detailed_mode_closure *closure = c;
2192 struct detailed_non_pixel *data = &timing->data.other_data;
2193 struct drm_connector *connector = closure->connector;
2194 struct edid *edid = closure->edid;
2195
2196 if (data->type == EDID_DETAIL_STD_MODES) {
2197 int i;
9cf00977
AJ		 2198 for (i = 0; i < 6; i++) {
2199 struct std_timing *std;
2200 struct drm_display_mode *newmode;
2201
2202 std = &data->data.timings[i];
464fdeca 2203 newmode = drm_mode_std(connector, edid, std);
9cf00977
AJ		 2204 if (newmode) {
2205 drm_mode_probed_add(connector, newmode);
13931579 2206 closure->modes++;
9cf00977
AJ		 2207 }
2208 }
9cf00977 2209 }
9cf00977
AJ		 2210}
2211
f453ba04 2212/**
13931579 2213 * add_standard_modes - get std. modes from EDID and add them
db6cf833 2214 * @connector: connector to add mode(s) to
f453ba04 2215 * @edid: EDID block to scan
f453ba04 2216 *
13931579
AJ		 2217 * Standard modes can be calculated using the appropriate standard (DMT,
2218 * GTF or CVT. Grab them from @edid and add them to the list.
f453ba04 2219 */
13931579
AJ		 2220static int
2221add_standard_modes(struct drm_connector *connector, struct edid *edid)
f453ba04 2222{
9cf00977 2223 int i, modes = 0;
13931579
AJ		 2224 struct detailed_mode_closure closure = {
2225 connector, edid, 0, 0, 0
2226 };
2227
2228 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2229 struct drm_display_mode *newmode;
2230
2231 newmode = drm_mode_std(connector, edid,
464fdeca 2232 &edid->standard_timings[i]);
13931579
AJ		 2233 if (newmode) {
2234 drm_mode_probed_add(connector, newmode);
2235 modes++;
2236 }
2237 }
2238
2239 if (version_greater(edid, 1, 0))
2240 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2241 &closure);
2242
2243 /* XXX should also look for standard codes in VTB blocks */
2244
2245 return modes + closure.modes;
2246}
f453ba04 2247
13931579
AJ		 2248static int drm_cvt_modes(struct drm_connector *connector,
2249 struct detailed_timing *timing)
2250{
2251 int i, j, modes = 0;
2252 struct drm_display_mode *newmode;
2253 struct drm_device *dev = connector->dev;
2254 struct cvt_timing *cvt;
2255 const int rates[] = { 60, 85, 75, 60, 50 };
2256 const u8 empty[3] = { 0, 0, 0 };
a327f6b8 2257
13931579
AJ		 2258 for (i = 0; i < 4; i++) {
2259 int uninitialized_var(width), height;
2260 cvt = &(timing->data.other_data.data.cvt[i]);
f453ba04 2261
13931579 2262 if (!memcmp(cvt->code, empty, 3))
9cf00977 2263 continue;
f453ba04 2264
13931579
AJ		 2265 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2266 switch (cvt->code[1] & 0x0c) {
2267 case 0x00:
2268 width = height * 4 / 3;
2269 break;
2270 case 0x04:
2271 width = height * 16 / 9;
2272 break;
2273 case 0x08:
2274 width = height * 16 / 10;
2275 break;
2276 case 0x0c:
2277 width = height * 15 / 9;
2278 break;
2279 }
2280
2281 for (j = 1; j < 5; j++) {
2282 if (cvt->code[2] & (1 << j)) {
2283 newmode = drm_cvt_mode(dev, width, height,
2284 rates[j], j == 0,
2285 false, false);
2286 if (newmode) {
2287 drm_mode_probed_add(connector, newmode);
2288 modes++;
2289 }
2290 }
2291 }
f453ba04
DA		 2292 }
2293
2294 return modes;
2295}
9cf00977 2296
13931579
AJ		 2297static void
2298do_cvt_mode(struct detailed_timing *timing, void *c)
882f0219 2299{
13931579
AJ		 2300 struct detailed_mode_closure *closure = c;
2301 struct detailed_non_pixel *data = &timing->data.other_data;
882f0219 2302
13931579
AJ		 2303 if (data->type == EDID_DETAIL_CVT_3BYTE)
2304 closure->modes += drm_cvt_modes(closure->connector, timing);
2305}
882f0219 2306
13931579
AJ		 2307static int
2308add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2309{
2310 struct detailed_mode_closure closure = {
2311 connector, edid, 0, 0, 0
2312 };
882f0219 2313
13931579
AJ		 2314 if (version_greater(edid, 1, 2))
2315 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
882f0219 2316
13931579 2317 /* XXX should also look for CVT codes in VTB blocks */
882f0219 2318
13931579
AJ		 2319 return closure.modes;
2320}
2321
2322static void
2323do_detailed_mode(struct detailed_timing *timing, void *c)
2324{
2325 struct detailed_mode_closure *closure = c;
2326 struct drm_display_mode *newmode;
2327
2328 if (timing->pixel_clock) {
2329 newmode = drm_mode_detailed(closure->connector->dev,
2330 closure->edid, timing,
2331 closure->quirks);
2332 if (!newmode)
2333 return;
2334
2335 if (closure->preferred)
2336 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2337
2338 drm_mode_probed_add(closure->connector, newmode);
2339 closure->modes++;
2340 closure->preferred = 0;
882f0219 2341 }
13931579 2342}
882f0219 2343
13931579
AJ		 2344/*
2345 * add_detailed_modes - Add modes from detailed timings
2346 * @connector: attached connector
2347 * @edid: EDID block to scan
2348 * @quirks: quirks to apply
2349 */
2350static int
2351add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2352 u32 quirks)
2353{
2354 struct detailed_mode_closure closure = {
2355 connector,
2356 edid,
2357 1,
2358 quirks,
2359 0
2360 };
2361
2362 if (closure.preferred && !version_greater(edid, 1, 3))
2363 closure.preferred =
2364 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2365
2366 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2367
2368 return closure.modes;
882f0219 2369}
f453ba04 2370
8fe9790d 2371#define AUDIO_BLOCK 0x01
54ac76f8 2372#define VIDEO_BLOCK 0x02
f23c20c8 2373#define VENDOR_BLOCK 0x03
76adaa34 2374#define SPEAKER_BLOCK 0x04
b1edd6a6 2375#define VIDEO_CAPABILITY_BLOCK 0x07
8fe9790d 2376#define EDID_BASIC_AUDIO (1 << 6)
a988bc72
LPC		 2377#define EDID_CEA_YCRCB444 (1 << 5)
2378#define EDID_CEA_YCRCB422 (1 << 4)
b1edd6a6 2379#define EDID_CEA_VCDB_QS (1 << 6)
8fe9790d 2380
d4e4a31d 2381/*
8fe9790d 2382 * Search EDID for CEA extension block.
f23c20c8 2383 */
d4e4a31d 2384static u8 *drm_find_cea_extension(struct edid *edid)
f23c20c8 2385{
8fe9790d
ZW		 2386 u8 *edid_ext = NULL;
2387 int i;
f23c20c8
ML		 2388
2389 /* No EDID or EDID extensions */
2390 if (edid == NULL || edid->extensions == 0)
8fe9790d 2391 return NULL;
f23c20c8 2392
f23c20c8 2393 /* Find CEA extension */
7466f4cc 2394 for (i = 0; i < edid->extensions; i++) {
8fe9790d
ZW		 2395 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2396 if (edid_ext[0] == CEA_EXT)
f23c20c8
ML		 2397 break;
2398 }
2399
7466f4cc 2400 if (i == edid->extensions)
8fe9790d
ZW		 2401 return NULL;
2402
2403 return edid_ext;
2404}
2405
e6e79209
VS		 2406/*
2407 * Calculate the alternate clock for the CEA mode
2408 * (60Hz vs. 59.94Hz etc.)
2409 */
2410static unsigned int
2411cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2412{
2413 unsigned int clock = cea_mode->clock;
2414
2415 if (cea_mode->vrefresh % 6 != 0)
2416 return clock;
2417
2418 /*
2419 * edid_cea_modes contains the 59.94Hz
2420 * variant for 240 and 480 line modes,
2421 * and the 60Hz variant otherwise.
2422 */
2423 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2424 clock = clock * 1001 / 1000;
2425 else
2426 clock = DIV_ROUND_UP(clock * 1000, 1001);
2427
2428 return clock;
2429}
2430
18316c8c
TR		 2431/**
2432 * drm_match_cea_mode - look for a CEA mode matching given mode
2433 * @to_match: display mode
2434 *
db6cf833 2435 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
18316c8c 2436 * mode.
a4799037 2437 */
18316c8c 2438u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
a4799037 2439{
a4799037
SM		 2440 u8 mode;
2441
a90b590e
VS		 2442 if (!to_match->clock)
2443 return 0;
2444
a6b21831 2445 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) {
a90b590e
VS		 2446 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode];
2447 unsigned int clock1, clock2;
2448
a90b590e 2449 /* Check both 60Hz and 59.94Hz */
e6e79209
VS		 2450 clock1 = cea_mode->clock;
2451 clock2 = cea_mode_alternate_clock(cea_mode);
a4799037 2452
a90b590e
VS		 2453 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2454 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2455 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
a4799037
SM		 2456 return mode + 1;
2457 }
2458 return 0;
2459}
2460EXPORT_SYMBOL(drm_match_cea_mode);
2461
0967e6a5
VK		 2462/**
2463 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2464 * the input VIC from the CEA mode list
2465 * @video_code: ID given to each of the CEA modes
2466 *
2467 * Returns picture aspect ratio
2468 */
2469enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2470{
2471 /* return picture aspect ratio for video_code - 1 to access the
2472 * right array element
2473 */
2474 return edid_cea_modes[video_code-1].picture_aspect_ratio;
2475}
2476EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2477
3f2f6533
LD		 2478/*
2479 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2480 * specific block).
2481 *
2482 * It's almost like cea_mode_alternate_clock(), we just need to add an
2483 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2484 * one.
2485 */
2486static unsigned int
2487hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2488{
2489 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2490 return hdmi_mode->clock;
2491
2492 return cea_mode_alternate_clock(hdmi_mode);
2493}
2494
2495/*
2496 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2497 * @to_match: display mode
2498 *
2499 * An HDMI mode is one defined in the HDMI vendor specific block.
2500 *
2501 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2502 */
2503static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2504{
2505 u8 mode;
2506
2507 if (!to_match->clock)
2508 return 0;
2509
2510 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) {
2511 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode];
2512 unsigned int clock1, clock2;
2513
2514 /* Make sure to also match alternate clocks */
2515 clock1 = hdmi_mode->clock;
2516 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2517
2518 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2519 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
f2ecf2e3 2520 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3f2f6533
LD		 2521 return mode + 1;
2522 }
2523 return 0;
2524}
2525
e6e79209
VS		 2526static int
2527add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2528{
2529 struct drm_device *dev = connector->dev;
2530 struct drm_display_mode *mode, *tmp;
2531 LIST_HEAD(list);
2532 int modes = 0;
2533
2534 /* Don't add CEA modes if the CEA extension block is missing */
2535 if (!drm_find_cea_extension(edid))
2536 return 0;
2537
2538 /*
2539 * Go through all probed modes and create a new mode
2540 * with the alternate clock for certain CEA modes.
2541 */
2542 list_for_each_entry(mode, &connector->probed_modes, head) {
3f2f6533 2543 const struct drm_display_mode *cea_mode = NULL;
e6e79209 2544 struct drm_display_mode *newmode;
3f2f6533 2545 u8 mode_idx = drm_match_cea_mode(mode) - 1;
e6e79209
VS		 2546 unsigned int clock1, clock2;
2547
3f2f6533
LD		 2548 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) {
2549 cea_mode = &edid_cea_modes[mode_idx];
2550 clock2 = cea_mode_alternate_clock(cea_mode);
2551 } else {
2552 mode_idx = drm_match_hdmi_mode(mode) - 1;
2553 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) {
2554 cea_mode = &edid_4k_modes[mode_idx];
2555 clock2 = hdmi_mode_alternate_clock(cea_mode);
2556 }
2557 }
e6e79209 2558
3f2f6533
LD		 2559 if (!cea_mode)
2560 continue;
e6e79209
VS		 2561
2562 clock1 = cea_mode->clock;
e6e79209
VS		 2563
2564 if (clock1 == clock2)
2565 continue;
2566
2567 if (mode->clock != clock1 && mode->clock != clock2)
2568 continue;
2569
2570 newmode = drm_mode_duplicate(dev, cea_mode);
2571 if (!newmode)
2572 continue;
2573
27130212
DL		 2574 /* Carry over the stereo flags */
2575 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2576
e6e79209
VS		 2577 /*
2578 * The current mode could be either variant. Make
2579 * sure to pick the "other" clock for the new mode.
2580 */
2581 if (mode->clock != clock1)
2582 newmode->clock = clock1;
2583 else
2584 newmode->clock = clock2;
2585
2586 list_add_tail(&newmode->head, &list);
2587 }
2588
2589 list_for_each_entry_safe(mode, tmp, &list, head) {
2590 list_del(&mode->head);
2591 drm_mode_probed_add(connector, mode);
2592 modes++;
2593 }
2594
2595 return modes;
2596}
a4799037 2597
aff04ace
TW		 2598static struct drm_display_mode *
2599drm_display_mode_from_vic_index(struct drm_connector *connector,
2600 const u8 *video_db, u8 video_len,
2601 u8 video_index)
54ac76f8
CS		 2602{
2603 struct drm_device *dev = connector->dev;
aff04ace 2604 struct drm_display_mode *newmode;
13ac3f55 2605 u8 cea_mode;
54ac76f8 2606
aff04ace
TW		 2607 if (video_db == NULL || video_index >= video_len)
2608 return NULL;
2609
2610 /* CEA modes are numbered 1..127 */
2611 cea_mode = (video_db[video_index] & 127) - 1;
2612 if (cea_mode >= ARRAY_SIZE(edid_cea_modes))
2613 return NULL;
2614
2615 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]);
409bbf1e
DL		 2616 if (!newmode)
2617 return NULL;
2618
aff04ace
TW		 2619 newmode->vrefresh = 0;
2620
2621 return newmode;
2622}
2623
2624static int
2625do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2626{
2627 int i, modes = 0;
2628
2629 for (i = 0; i < len; i++) {
2630 struct drm_display_mode *mode;
2631 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2632 if (mode) {
2633 drm_mode_probed_add(connector, mode);
2634 modes++;
54ac76f8
CS		 2635 }
2636 }
2637
2638 return modes;
2639}
2640
c858cfca
DL		 2641struct stereo_mandatory_mode {
2642 int width, height, vrefresh;
2643 unsigned int flags;
2644};
2645
2646static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
f7e121b7
DL		 2647 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2648 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
c858cfca
DL		 2649 { 1920, 1080, 50,
2650 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2651 { 1920, 1080, 60,
2652 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
f7e121b7
DL		 2653 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2654 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2655 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2656 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
c858cfca
DL		 2657};
2658
2659static bool
2660stereo_match_mandatory(const struct drm_display_mode *mode,
2661 const struct stereo_mandatory_mode *stereo_mode)
2662{
2663 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2664
2665 return mode->hdisplay == stereo_mode->width &&
2666 mode->vdisplay == stereo_mode->height &&
2667 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2668 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2669}
2670
c858cfca
DL		 2671static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2672{
2673 struct drm_device *dev = connector->dev;
2674 const struct drm_display_mode *mode;
2675 struct list_head stereo_modes;
f7e121b7 2676 int modes = 0, i;
c858cfca
DL		 2677
2678 INIT_LIST_HEAD(&stereo_modes);
2679
2680 list_for_each_entry(mode, &connector->probed_modes, head) {
f7e121b7
DL		 2681 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2682 const struct stereo_mandatory_mode *mandatory;
c858cfca
DL		 2683 struct drm_display_mode *new_mode;
2684
f7e121b7
DL		 2685 if (!stereo_match_mandatory(mode,
2686 &stereo_mandatory_modes[i]))
2687 continue;
c858cfca 2688
f7e121b7 2689 mandatory = &stereo_mandatory_modes[i];
c858cfca
DL		 2690 new_mode = drm_mode_duplicate(dev, mode);
2691 if (!new_mode)
2692 continue;
2693
f7e121b7 2694 new_mode->flags |= mandatory->flags;
c858cfca
DL		 2695 list_add_tail(&new_mode->head, &stereo_modes);
2696 modes++;
f7e121b7 2697 }
c858cfca
DL		 2698 }
2699
2700 list_splice_tail(&stereo_modes, &connector->probed_modes);
2701
2702 return modes;
2703}
2704
1deee8d7
DL		 2705static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2706{
2707 struct drm_device *dev = connector->dev;
2708 struct drm_display_mode *newmode;
2709
2710 vic--; /* VICs start at 1 */
2711 if (vic >= ARRAY_SIZE(edid_4k_modes)) {
2712 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2713 return 0;
2714 }
2715
2716 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2717 if (!newmode)
2718 return 0;
2719
2720 drm_mode_probed_add(connector, newmode);
2721
2722 return 1;
2723}
2724
fbf46025
TW		 2725static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
2726 const u8 *video_db, u8 video_len, u8 video_index)
2727{
fbf46025
TW		 2728 struct drm_display_mode *newmode;
2729 int modes = 0;
fbf46025
TW		 2730
2731 if (structure & (1 << 0)) {
aff04ace
TW		 2732 newmode = drm_display_mode_from_vic_index(connector, video_db,
2733 video_len,
2734 video_index);
fbf46025
TW		 2735 if (newmode) {
2736 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
2737 drm_mode_probed_add(connector, newmode);
2738 modes++;
2739 }
2740 }
2741 if (structure & (1 << 6)) {
aff04ace
TW		 2742 newmode = drm_display_mode_from_vic_index(connector, video_db,
2743 video_len,
2744 video_index);
fbf46025
TW		 2745 if (newmode) {
2746 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2747 drm_mode_probed_add(connector, newmode);
2748 modes++;
2749 }
2750 }
2751 if (structure & (1 << 8)) {
aff04ace
TW		 2752 newmode = drm_display_mode_from_vic_index(connector, video_db,
2753 video_len,
2754 video_index);
fbf46025 2755 if (newmode) {
89570eeb 2756 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
fbf46025
TW		 2757 drm_mode_probed_add(connector, newmode);
2758 modes++;
2759 }
2760 }
2761
2762 return modes;
2763}
2764
7ebe1963
LD		 2765/*
2766 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
2767 * @connector: connector corresponding to the HDMI sink
2768 * @db: start of the CEA vendor specific block
2769 * @len: length of the CEA block payload, ie. one can access up to db[len]
2770 *
c858cfca
DL		 2771 * Parses the HDMI VSDB looking for modes to add to @connector. This function
2772 * also adds the stereo 3d modes when applicable.
7ebe1963
LD		 2773 */
2774static int
fbf46025
TW		 2775do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
2776 const u8 *video_db, u8 video_len)
7ebe1963 2777{
0e5083aa 2778 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
fbf46025
TW		 2779 u8 vic_len, hdmi_3d_len = 0;
2780 u16 mask;
2781 u16 structure_all;
7ebe1963
LD		 2782
2783 if (len < 8)
2784 goto out;
2785
2786 /* no HDMI_Video_Present */
2787 if (!(db[8] & (1 << 5)))
2788 goto out;
2789
2790 /* Latency_Fields_Present */
2791 if (db[8] & (1 << 7))
2792 offset += 2;
2793
2794 /* I_Latency_Fields_Present */
2795 if (db[8] & (1 << 6))
2796 offset += 2;
2797
2798 /* the declared length is not long enough for the 2 first bytes
2799 * of additional video format capabilities */
c858cfca 2800 if (len < (8 + offset + 2))
7ebe1963
LD		 2801 goto out;
2802
c858cfca
DL		 2803 /* 3D_Present */
2804 offset++;
fbf46025 2805 if (db[8 + offset] & (1 << 7)) {
c858cfca
DL		 2806 modes += add_hdmi_mandatory_stereo_modes(connector);
2807
fbf46025
TW		 2808 /* 3D_Multi_present */
2809 multi_present = (db[8 + offset] & 0x60) >> 5;
2810 }
2811
c858cfca 2812 offset++;
7ebe1963 2813 vic_len = db[8 + offset] >> 5;
fbf46025 2814 hdmi_3d_len = db[8 + offset] & 0x1f;
7ebe1963
LD		 2815
2816 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
7ebe1963
LD		 2817 u8 vic;
2818
2819 vic = db[9 + offset + i];
1deee8d7 2820 modes += add_hdmi_mode(connector, vic);
7ebe1963 2821 }
fbf46025
TW		 2822 offset += 1 + vic_len;
2823
0e5083aa
TW		 2824 if (multi_present == 1)
2825 multi_len = 2;
2826 else if (multi_present == 2)
2827 multi_len = 4;
2828 else
2829 multi_len = 0;
fbf46025 2830
0e5083aa 2831 if (len < (8 + offset + hdmi_3d_len - 1))
fbf46025
TW		 2832 goto out;
2833
0e5083aa 2834 if (hdmi_3d_len < multi_len)
fbf46025
TW		 2835 goto out;
2836
0e5083aa
TW		 2837 if (multi_present == 1 || multi_present == 2) {
2838 /* 3D_Structure_ALL */
2839 structure_all = (db[8 + offset] << 8) | db[9 + offset];
fbf46025 2840
0e5083aa
TW		 2841 /* check if 3D_MASK is present */
2842 if (multi_present == 2)
2843 mask = (db[10 + offset] << 8) | db[11 + offset];
2844 else
2845 mask = 0xffff;
2846
2847 for (i = 0; i < 16; i++) {
2848 if (mask & (1 << i))
2849 modes += add_3d_struct_modes(connector,
2850 structure_all,
2851 video_db,
2852 video_len, i);
2853 }
2854 }
2855
2856 offset += multi_len;
2857
2858 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
2859 int vic_index;
2860 struct drm_display_mode *newmode = NULL;
2861 unsigned int newflag = 0;
2862 bool detail_present;
2863
2864 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
2865
2866 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
2867 break;
2868
2869 /* 2D_VIC_order_X */
2870 vic_index = db[8 + offset + i] >> 4;
2871
2872 /* 3D_Structure_X */
2873 switch (db[8 + offset + i] & 0x0f) {
2874 case 0:
2875 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
2876 break;
2877 case 6:
2878 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
2879 break;
2880 case 8:
2881 /* 3D_Detail_X */
2882 if ((db[9 + offset + i] >> 4) == 1)
2883 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
2884 break;
2885 }
2886
2887 if (newflag != 0) {
2888 newmode = drm_display_mode_from_vic_index(connector,
2889 video_db,
2890 video_len,
2891 vic_index);
2892
2893 if (newmode) {
2894 newmode->flags |= newflag;
2895 drm_mode_probed_add(connector, newmode);
2896 modes++;
2897 }
2898 }
2899
2900 if (detail_present)
2901 i++;
fbf46025 2902 }
7ebe1963
LD		 2903
2904out:
2905 return modes;
2906}
2907
9e50b9d5
VS		 2908static int
2909cea_db_payload_len(const u8 *db)
2910{
2911 return db[0] & 0x1f;
2912}
2913
2914static int
2915cea_db_tag(const u8 *db)
2916{
2917 return db[0] >> 5;
2918}
2919
2920static int
2921cea_revision(const u8 *cea)
2922{
2923 return cea[1];
2924}
2925
2926static int
2927cea_db_offsets(const u8 *cea, int *start, int *end)
2928{
2929 /* Data block offset in CEA extension block */
2930 *start = 4;
2931 *end = cea[2];
2932 if (*end == 0)
2933 *end = 127;
2934 if (*end < 4 || *end > 127)
2935 return -ERANGE;
2936 return 0;
2937}
2938
7ebe1963
LD		 2939static bool cea_db_is_hdmi_vsdb(const u8 *db)
2940{
2941 int hdmi_id;
2942
2943 if (cea_db_tag(db) != VENDOR_BLOCK)
2944 return false;
2945
2946 if (cea_db_payload_len(db) < 5)
2947 return false;
2948
2949 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
2950
6cb3b7f1 2951 return hdmi_id == HDMI_IEEE_OUI;
7ebe1963
LD		 2952}
2953
9e50b9d5
VS		 2954#define for_each_cea_db(cea, i, start, end) \
2955 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
2956
54ac76f8
CS		 2957static int
2958add_cea_modes(struct drm_connector *connector, struct edid *edid)
2959{
13ac3f55 2960 const u8 *cea = drm_find_cea_extension(edid);
fbf46025
TW		 2961 const u8 *db, *hdmi = NULL, *video = NULL;
2962 u8 dbl, hdmi_len, video_len = 0;
54ac76f8
CS		 2963 int modes = 0;
2964
9e50b9d5
VS		 2965 if (cea && cea_revision(cea) >= 3) {
2966 int i, start, end;
2967
2968 if (cea_db_offsets(cea, &start, &end))
2969 return 0;
2970
2971 for_each_cea_db(cea, i, start, end) {
2972 db = &cea[i];
2973 dbl = cea_db_payload_len(db);
2974
fbf46025
TW		 2975 if (cea_db_tag(db) == VIDEO_BLOCK) {
2976 video = db + 1;
2977 video_len = dbl;
2978 modes += do_cea_modes(connector, video, dbl);
2979 }
c858cfca
DL		 2980 else if (cea_db_is_hdmi_vsdb(db)) {
2981 hdmi = db;
2982 hdmi_len = dbl;
2983 }
54ac76f8
CS		 2984 }
2985 }
2986
c858cfca
DL		 2987 /*
2988 * We parse the HDMI VSDB after having added the cea modes as we will
2989 * be patching their flags when the sink supports stereo 3D.
2990 */
2991 if (hdmi)
fbf46025
TW		 2992 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
2993 video_len);
c858cfca 2994
54ac76f8
CS		 2995 return modes;
2996}
2997
76adaa34 2998static void
8504072a 2999parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
76adaa34 3000{
8504072a 3001 u8 len = cea_db_payload_len(db);
76adaa34 3002
8504072a
VS		 3003 if (len >= 6) {
3004 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3005 connector->dvi_dual = db[6] & 1;
3006 }
3007 if (len >= 7)
3008 connector->max_tmds_clock = db[7] * 5;
3009 if (len >= 8) {
3010 connector->latency_present[0] = db[8] >> 7;
3011 connector->latency_present[1] = (db[8] >> 6) & 1;
3012 }
3013 if (len >= 9)
3014 connector->video_latency[0] = db[9];
3015 if (len >= 10)
3016 connector->audio_latency[0] = db[10];
3017 if (len >= 11)
3018 connector->video_latency[1] = db[11];
3019 if (len >= 12)
3020 connector->audio_latency[1] = db[12];
76adaa34 3021
670c1ef6 3022 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
76adaa34
WF		 3023 "max TMDS clock %d, "
3024 "latency present %d %d, "
3025 "video latency %d %d, "
3026 "audio latency %d %d\n",
3027 connector->dvi_dual,
3028 connector->max_tmds_clock,
3029 (int) connector->latency_present[0],
3030 (int) connector->latency_present[1],
3031 connector->video_latency[0],
3032 connector->video_latency[1],
3033 connector->audio_latency[0],
3034 connector->audio_latency[1]);
3035}
3036
3037static void
3038monitor_name(struct detailed_timing *t, void *data)
3039{
3040 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3041 *(u8 **)data = t->data.other_data.data.str.str;
14f77fdd
VS		 3042}
3043
76adaa34
WF		 3044/**
3045 * drm_edid_to_eld - build ELD from EDID
3046 * @connector: connector corresponding to the HDMI/DP sink
3047 * @edid: EDID to parse
3048 *
db6cf833
TR		 3049 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3050 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3051 * fill in.
76adaa34
WF		 3052 */
3053void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3054{
3055 uint8_t *eld = connector->eld;
3056 u8 *cea;
3057 u8 *name;
3058 u8 *db;
3059 int sad_count = 0;
3060 int mnl;
3061 int dbl;
3062
3063 memset(eld, 0, sizeof(connector->eld));
3064
3065 cea = drm_find_cea_extension(edid);
3066 if (!cea) {
3067 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3068 return;
3069 }
3070
3071 name = NULL;
3072 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3073 for (mnl = 0; name && mnl < 13; mnl++) {
3074 if (name[mnl] == 0x0a)
3075 break;
3076 eld[20 + mnl] = name[mnl];
3077 }
3078 eld[4] = (cea[1] << 5) | mnl;
3079 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3080
3081 eld[0] = 2 << 3; /* ELD version: 2 */
3082
3083 eld[16] = edid->mfg_id[0];
3084 eld[17] = edid->mfg_id[1];
3085 eld[18] = edid->prod_code[0];
3086 eld[19] = edid->prod_code[1];
3087
9e50b9d5
VS		 3088 if (cea_revision(cea) >= 3) {
3089 int i, start, end;
3090
3091 if (cea_db_offsets(cea, &start, &end)) {
3092 start = 0;
3093 end = 0;
3094 }
3095
3096 for_each_cea_db(cea, i, start, end) {
3097 db = &cea[i];
3098 dbl = cea_db_payload_len(db);
3099
3100 switch (cea_db_tag(db)) {
a0ab734d
CS		 3101 case AUDIO_BLOCK:
3102 /* Audio Data Block, contains SADs */
3103 sad_count = dbl / 3;
9e50b9d5
VS		 3104 if (dbl >= 1)
3105 memcpy(eld + 20 + mnl, &db[1], dbl);
a0ab734d
CS		 3106 break;
3107 case SPEAKER_BLOCK:
9e50b9d5
VS		 3108 /* Speaker Allocation Data Block */
3109 if (dbl >= 1)
3110 eld[7] = db[1];
a0ab734d
CS		 3111 break;
3112 case VENDOR_BLOCK:
3113 /* HDMI Vendor-Specific Data Block */
14f77fdd 3114 if (cea_db_is_hdmi_vsdb(db))
a0ab734d
CS		 3115 parse_hdmi_vsdb(connector, db);
3116 break;
3117 default:
3118 break;
3119 }
76adaa34 3120 }
9e50b9d5 3121 }
76adaa34
WF		 3122 eld[5] |= sad_count << 4;
3123 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
3124
3125 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count);
3126}
3127EXPORT_SYMBOL(drm_edid_to_eld);
3128
fe214163
RM		 3129/**
3130 * drm_edid_to_sad - extracts SADs from EDID
3131 * @edid: EDID to parse
3132 * @sads: pointer that will be set to the extracted SADs
3133 *
3134 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
fe214163 3135 *
db6cf833
TR		 3136 * Note: The returned pointer needs to be freed using kfree().
3137 *
3138 * Return: The number of found SADs or negative number on error.
fe214163
RM		 3139 */
3140int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3141{
3142 int count = 0;
3143 int i, start, end, dbl;
3144 u8 *cea;
3145
3146 cea = drm_find_cea_extension(edid);
3147 if (!cea) {
3148 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3149 return -ENOENT;
3150 }
3151
3152 if (cea_revision(cea) < 3) {
3153 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3154 return -ENOTSUPP;
3155 }
3156
3157 if (cea_db_offsets(cea, &start, &end)) {
3158 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3159 return -EPROTO;
3160 }
3161
3162 for_each_cea_db(cea, i, start, end) {
3163 u8 *db = &cea[i];
3164
3165 if (cea_db_tag(db) == AUDIO_BLOCK) {
3166 int j;
3167 dbl = cea_db_payload_len(db);
3168
3169 count = dbl / 3; /* SAD is 3B */
3170 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3171 if (!*sads)
3172 return -ENOMEM;
3173 for (j = 0; j < count; j++) {
3174 u8 *sad = &db[1 + j * 3];
3175
3176 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3177 (*sads)[j].channels = sad[0] & 0x7;
3178 (*sads)[j].freq = sad[1] & 0x7F;
3179 (*sads)[j].byte2 = sad[2];
3180 }
3181 break;
3182 }
3183 }
3184
3185 return count;
3186}
3187EXPORT_SYMBOL(drm_edid_to_sad);
3188
d105f476
AD		 3189/**
3190 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3191 * @edid: EDID to parse
3192 * @sadb: pointer to the speaker block
3193 *
3194 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
d105f476 3195 *
db6cf833
TR		 3196 * Note: The returned pointer needs to be freed using kfree().
3197 *
3198 * Return: The number of found Speaker Allocation Blocks or negative number on
3199 * error.
d105f476
AD		 3200 */
3201int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3202{
3203 int count = 0;
3204 int i, start, end, dbl;
3205 const u8 *cea;
3206
3207 cea = drm_find_cea_extension(edid);
3208 if (!cea) {
3209 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3210 return -ENOENT;
3211 }
3212
3213 if (cea_revision(cea) < 3) {
3214 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3215 return -ENOTSUPP;
3216 }
3217
3218 if (cea_db_offsets(cea, &start, &end)) {
3219 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3220 return -EPROTO;
3221 }
3222
3223 for_each_cea_db(cea, i, start, end) {
3224 const u8 *db = &cea[i];
3225
3226 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3227 dbl = cea_db_payload_len(db);
3228
3229 /* Speaker Allocation Data Block */
3230 if (dbl == 3) {
89086bca 3231 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
618e3776
AD		 3232 if (!*sadb)
3233 return -ENOMEM;
d105f476
AD		 3234 count = dbl;
3235 break;
3236 }
3237 }
3238 }
3239
3240 return count;
3241}
3242EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3243
76adaa34 3244/**
db6cf833 3245 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
76adaa34
WF		 3246 * @connector: connector associated with the HDMI/DP sink
3247 * @mode: the display mode
db6cf833
TR		 3248 *
3249 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3250 * the sink doesn't support audio or video.
76adaa34
WF		 3251 */
3252int drm_av_sync_delay(struct drm_connector *connector,
3253 struct drm_display_mode *mode)
3254{
3255 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3256 int a, v;
3257
3258 if (!connector->latency_present[0])
3259 return 0;
3260 if (!connector->latency_present[1])
3261 i = 0;
3262
3263 a = connector->audio_latency[i];
3264 v = connector->video_latency[i];
3265
3266 /*
3267 * HDMI/DP sink doesn't support audio or video?
3268 */
3269 if (a == 255 || v == 255)
3270 return 0;
3271
3272 /*
3273 * Convert raw EDID values to millisecond.
3274 * Treat unknown latency as 0ms.
3275 */
3276 if (a)
3277 a = min(2 * (a - 1), 500);
3278 if (v)
3279 v = min(2 * (v - 1), 500);
3280
3281 return max(v - a, 0);
3282}
3283EXPORT_SYMBOL(drm_av_sync_delay);
3284
3285/**
3286 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3287 * @encoder: the encoder just changed display mode
3288 * @mode: the adjusted display mode
3289 *
3290 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3291 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
db6cf833
TR		 3292 *
3293 * Return: The connector associated with the first HDMI/DP sink that has ELD
3294 * attached to it.
76adaa34
WF		 3295 */
3296struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
3297 struct drm_display_mode *mode)
3298{
3299 struct drm_connector *connector;
3300 struct drm_device *dev = encoder->dev;
3301
3302 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
3303 if (connector->encoder == encoder && connector->eld[0])
3304 return connector;
3305
3306 return NULL;
3307}
3308EXPORT_SYMBOL(drm_select_eld);
3309
8fe9790d 3310/**
db6cf833 3311 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
8fe9790d
ZW		 3312 * @edid: monitor EDID information
3313 *
3314 * Parse the CEA extension according to CEA-861-B.
db6cf833
TR		 3315 *
3316 * Return: True if the monitor is HDMI, false if not or unknown.
8fe9790d
ZW		 3317 */
3318bool drm_detect_hdmi_monitor(struct edid *edid)
3319{
3320 u8 *edid_ext;
14f77fdd 3321 int i;
8fe9790d 3322 int start_offset, end_offset;
8fe9790d
ZW		 3323
3324 edid_ext = drm_find_cea_extension(edid);
3325 if (!edid_ext)
14f77fdd 3326 return false;
f23c20c8 3327
9e50b9d5 3328 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
14f77fdd 3329 return false;
f23c20c8
ML		 3330
3331 /*
3332 * Because HDMI identifier is in Vendor Specific Block,
3333 * search it from all data blocks of CEA extension.
3334 */
9e50b9d5 3335 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
14f77fdd
VS		 3336 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3337 return true;
f23c20c8
ML		 3338 }
3339
14f77fdd 3340 return false;
f23c20c8
ML		 3341}
3342EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3343
8fe9790d
ZW		 3344/**
3345 * drm_detect_monitor_audio - check monitor audio capability
fc66811c 3346 * @edid: EDID block to scan
8fe9790d
ZW		 3347 *
3348 * Monitor should have CEA extension block.
3349 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3350 * audio' only. If there is any audio extension block and supported
3351 * audio format, assume at least 'basic audio' support, even if 'basic
3352 * audio' is not defined in EDID.
3353 *
db6cf833 3354 * Return: True if the monitor supports audio, false otherwise.
8fe9790d
ZW		 3355 */
3356bool drm_detect_monitor_audio(struct edid *edid)
3357{
3358 u8 *edid_ext;
3359 int i, j;
3360 bool has_audio = false;
3361 int start_offset, end_offset;
3362
3363 edid_ext = drm_find_cea_extension(edid);
3364 if (!edid_ext)
3365 goto end;
3366
3367 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3368
3369 if (has_audio) {
3370 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3371 goto end;
3372 }
3373
9e50b9d5
VS		 3374 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3375 goto end;
8fe9790d 3376
9e50b9d5
VS		 3377 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3378 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
8fe9790d 3379 has_audio = true;
9e50b9d5 3380 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
8fe9790d
ZW		 3381 DRM_DEBUG_KMS("CEA audio format %d\n",
3382 (edid_ext[i + j] >> 3) & 0xf);
3383 goto end;
3384 }
3385 }
3386end:
3387 return has_audio;
3388}
3389EXPORT_SYMBOL(drm_detect_monitor_audio);
3390
b1edd6a6
VS		 3391/**
3392 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
fc66811c 3393 * @edid: EDID block to scan
b1edd6a6
VS		 3394 *
3395 * Check whether the monitor reports the RGB quantization range selection
3396 * as supported. The AVI infoframe can then be used to inform the monitor
3397 * which quantization range (full or limited) is used.
db6cf833
TR		 3398 *
3399 * Return: True if the RGB quantization range is selectable, false otherwise.
b1edd6a6
VS		 3400 */
3401bool drm_rgb_quant_range_selectable(struct edid *edid)
3402{
3403 u8 *edid_ext;
3404 int i, start, end;
3405
3406 edid_ext = drm_find_cea_extension(edid);
3407 if (!edid_ext)
3408 return false;
3409
3410 if (cea_db_offsets(edid_ext, &start, &end))
3411 return false;
3412
3413 for_each_cea_db(edid_ext, i, start, end) {
3414 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3415 cea_db_payload_len(&edid_ext[i]) == 2) {
3416 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3417 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3418 }
3419 }
3420
3421 return false;
3422}
3423EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3424
d0c94692
MK		 3425/**
3426 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3427 * hdmi deep color modes and update drm_display_info if so.
3428 *
3429 * @edid: monitor EDID information
3430 * @info: Updated with maximum supported deep color bpc and color format
3431 * if deep color supported.
3432 *
3433 * Parse the CEA extension according to CEA-861-B.
3434 * Return true if HDMI deep color supported, false if not or unknown.
3435 */
3436static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3437 struct drm_display_info *info,
3438 struct drm_connector *connector)
3439{
3440 u8 *edid_ext, *hdmi;
3441 int i;
3442 int start_offset, end_offset;
3443 unsigned int dc_bpc = 0;
3444
3445 edid_ext = drm_find_cea_extension(edid);
3446 if (!edid_ext)
3447 return false;
3448
3449 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3450 return false;
3451
3452 /*
3453 * Because HDMI identifier is in Vendor Specific Block,
3454 * search it from all data blocks of CEA extension.
3455 */
3456 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3457 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3458 /* HDMI supports at least 8 bpc */
3459 info->bpc = 8;
3460
3461 hdmi = &edid_ext[i];
3462 if (cea_db_payload_len(hdmi) < 6)
3463 return false;
3464
3465 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3466 dc_bpc = 10;
3467 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3468 drm_get_connector_name(connector));
3469 }
3470
3471 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3472 dc_bpc = 12;
3473 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3474 drm_get_connector_name(connector));
3475 }
3476
3477 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3478 dc_bpc = 16;
3479 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3480 drm_get_connector_name(connector));
3481 }
3482
3483 if (dc_bpc > 0) {
3484 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3485 drm_get_connector_name(connector), dc_bpc);
3486 info->bpc = dc_bpc;
3487
3488 /*
3489 * Deep color support mandates RGB444 support for all video
3490 * modes and forbids YCRCB422 support for all video modes per
3491 * HDMI 1.3 spec.
3492 */
3493 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3494
3495 /* YCRCB444 is optional according to spec. */
3496 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3497 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3498 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3499 drm_get_connector_name(connector));
3500 }
3501
3502 /*
3503 * Spec says that if any deep color mode is supported at all,
3504 * then deep color 36 bit must be supported.
3505 */
3506 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3507 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3508 drm_get_connector_name(connector));
3509 }
3510
3511 return true;
3512 }
3513 else {
3514 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3515 drm_get_connector_name(connector));
3516 }
3517 }
3518 }
3519
3520 return false;
3521}
3522
3b11228b
JB		 3523/**
3524 * drm_add_display_info - pull display info out if present
3525 * @edid: EDID data
3526 * @info: display info (attached to connector)
d0c94692 3527 * @connector: connector whose edid is used to build display info
3b11228b
JB		 3528 *
3529 * Grab any available display info and stuff it into the drm_display_info
3530 * structure that's part of the connector. Useful for tracking bpp and
3531 * color spaces.
3532 */
3533static void drm_add_display_info(struct edid *edid,
d0c94692
MK		 3534 struct drm_display_info *info,
3535 struct drm_connector *connector)
3b11228b 3536{
ebec9a7b
JB		 3537 u8 *edid_ext;
3538
3b11228b
JB		 3539 info->width_mm = edid->width_cm * 10;
3540 info->height_mm = edid->height_cm * 10;
3541
3542 /* driver figures it out in this case */
3543 info->bpc = 0;
da05a5a7 3544 info->color_formats = 0;
3b11228b 3545
a988bc72 3546 if (edid->revision < 3)
3b11228b
JB		 3547 return;
3548
3549 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3550 return;
3551
a988bc72
LPC		 3552 /* Get data from CEA blocks if present */
3553 edid_ext = drm_find_cea_extension(edid);
3554 if (edid_ext) {
3555 info->cea_rev = edid_ext[1];
3556
3557 /* The existence of a CEA block should imply RGB support */
3558 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3559 if (edid_ext[3] & EDID_CEA_YCRCB444)
3560 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3561 if (edid_ext[3] & EDID_CEA_YCRCB422)
3562 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3563 }
3564
d0c94692
MK		 3565 /* HDMI deep color modes supported? Assign to info, if so */
3566 drm_assign_hdmi_deep_color_info(edid, info, connector);
3567
a988bc72
LPC		 3568 /* Only defined for 1.4 with digital displays */
3569 if (edid->revision < 4)
3570 return;
3571
3b11228b
JB		 3572 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3573 case DRM_EDID_DIGITAL_DEPTH_6:
3574 info->bpc = 6;
3575 break;
3576 case DRM_EDID_DIGITAL_DEPTH_8:
3577 info->bpc = 8;
3578 break;
3579 case DRM_EDID_DIGITAL_DEPTH_10:
3580 info->bpc = 10;
3581 break;
3582 case DRM_EDID_DIGITAL_DEPTH_12:
3583 info->bpc = 12;
3584 break;
3585 case DRM_EDID_DIGITAL_DEPTH_14:
3586 info->bpc = 14;
3587 break;
3588 case DRM_EDID_DIGITAL_DEPTH_16:
3589 info->bpc = 16;
3590 break;
3591 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3592 default:
3593 info->bpc = 0;
3594 break;
3595 }
da05a5a7 3596
d0c94692
MK		 3597 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3598 drm_get_connector_name(connector), info->bpc);
3599
a988bc72 3600 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
ee58808d
LPC		 3601 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3602 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3603 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3604 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3b11228b
JB		 3605}
3606
f453ba04
DA		 3607/**
3608 * drm_add_edid_modes - add modes from EDID data, if available
3609 * @connector: connector we're probing
db6cf833 3610 * @edid: EDID data
f453ba04
DA		 3611 *
3612 * Add the specified modes to the connector's mode list.
3613 *
db6cf833 3614 * Return: The number of modes added or 0 if we couldn't find any.
f453ba04
DA		 3615 */
3616int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3617{
3618 int num_modes = 0;
3619 u32 quirks;
3620
3621 if (edid == NULL) {
3622 return 0;
3623 }
3c537889 3624 if (!drm_edid_is_valid(edid)) {
dcdb1674 3625 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
f453ba04
DA		 3626 drm_get_connector_name(connector));
3627 return 0;
3628 }
3629
3630 quirks = edid_get_quirks(edid);
3631
c867df70
AJ		 3632 /*
3633 * EDID spec says modes should be preferred in this order:
3634 * - preferred detailed mode
3635 * - other detailed modes from base block
3636 * - detailed modes from extension blocks
3637 * - CVT 3-byte code modes
3638 * - standard timing codes
3639 * - established timing codes
3640 * - modes inferred from GTF or CVT range information
3641 *
13931579 3642 * We get this pretty much right.
c867df70
AJ		 3643 *
3644 * XXX order for additional mode types in extension blocks?
3645 */
13931579
AJ		 3646 num_modes += add_detailed_modes(connector, edid, quirks);
3647 num_modes += add_cvt_modes(connector, edid);
c867df70
AJ		 3648 num_modes += add_standard_modes(connector, edid);
3649 num_modes += add_established_modes(connector, edid);
196e077d
PZ		 3650 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3651 num_modes += add_inferred_modes(connector, edid);
54ac76f8 3652 num_modes += add_cea_modes(connector, edid);
e6e79209 3653 num_modes += add_alternate_cea_modes(connector, edid);
f453ba04
DA		 3654
3655 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3656 edid_fixup_preferred(connector, quirks);
3657
d0c94692 3658 drm_add_display_info(edid, &connector->display_info, connector);
f453ba04 3659
49d45a31
RM		 3660 if (quirks & EDID_QUIRK_FORCE_8BPC)
3661 connector->display_info.bpc = 8;
3662
f453ba04
DA		 3663 return num_modes;
3664}
3665EXPORT_SYMBOL(drm_add_edid_modes);
f0fda0a4
ZY		 3666
3667/**
3668 * drm_add_modes_noedid - add modes for the connectors without EDID
3669 * @connector: connector we're probing
3670 * @hdisplay: the horizontal display limit
3671 * @vdisplay: the vertical display limit
3672 *
3673 * Add the specified modes to the connector's mode list. Only when the
3674 * hdisplay/vdisplay is not beyond the given limit, it will be added.
3675 *
db6cf833 3676 * Return: The number of modes added or 0 if we couldn't find any.
f0fda0a4
ZY		 3677 */
3678int drm_add_modes_noedid(struct drm_connector *connector,
3679 int hdisplay, int vdisplay)
3680{
3681 int i, count, num_modes = 0;
b1f559ec 3682 struct drm_display_mode *mode;
f0fda0a4
ZY		 3683 struct drm_device *dev = connector->dev;
3684
3685 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode);
3686 if (hdisplay < 0)
3687 hdisplay = 0;
3688 if (vdisplay < 0)
3689 vdisplay = 0;
3690
3691 for (i = 0; i < count; i++) {
b1f559ec 3692 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
f0fda0a4
ZY		 3693 if (hdisplay && vdisplay) {
3694 /*
3695 * Only when two are valid, they will be used to check
3696 * whether the mode should be added to the mode list of
3697 * the connector.
3698 */
3699 if (ptr->hdisplay > hdisplay ||
3700 ptr->vdisplay > vdisplay)
3701 continue;
3702 }
f985dedb
AJ		 3703 if (drm_mode_vrefresh(ptr) > 61)
3704 continue;
f0fda0a4
ZY		 3705 mode = drm_mode_duplicate(dev, ptr);
3706 if (mode) {
3707 drm_mode_probed_add(connector, mode);
3708 num_modes++;
3709 }
3710 }
3711 return num_modes;
3712}
3713EXPORT_SYMBOL(drm_add_modes_noedid);
10a85120 3714
db6cf833
TR		 3715/**
3716 * drm_set_preferred_mode - Sets the preferred mode of a connector
3717 * @connector: connector whose mode list should be processed
3718 * @hpref: horizontal resolution of preferred mode
3719 * @vpref: vertical resolution of preferred mode
3720 *
3721 * Marks a mode as preferred if it matches the resolution specified by @hpref
3722 * and @vpref.
3723 */
3cf70daf
GH		 3724void drm_set_preferred_mode(struct drm_connector *connector,
3725 int hpref, int vpref)
3726{
3727 struct drm_display_mode *mode;
3728
3729 list_for_each_entry(mode, &connector->probed_modes, head) {
db6cf833 3730 if (mode->hdisplay == hpref &&
9d3de138 3731 mode->vdisplay == vpref)
3cf70daf
GH		 3732 mode->type |= DRM_MODE_TYPE_PREFERRED;
3733 }
3734}
3735EXPORT_SYMBOL(drm_set_preferred_mode);
3736
10a85120
TR		 3737/**
3738 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
3739 * data from a DRM display mode
3740 * @frame: HDMI AVI infoframe
3741 * @mode: DRM display mode
3742 *
db6cf833 3743 * Return: 0 on success or a negative error code on failure.
10a85120
TR		 3744 */
3745int
3746drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
3747 const struct drm_display_mode *mode)
3748{
3749 int err;
3750
3751 if (!frame || !mode)
3752 return -EINVAL;
3753
3754 err = hdmi_avi_infoframe_init(frame);
3755 if (err < 0)
3756 return err;
3757
bf02db99
DL		 3758 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
3759 frame->pixel_repeat = 1;
3760
10a85120 3761 frame->video_code = drm_match_cea_mode(mode);
10a85120
TR		 3762
3763 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
0967e6a5
VK		 3764
3765 /* Populate picture aspect ratio from CEA mode list */
3766 if (frame->video_code > 0)
3767 frame->picture_aspect = drm_get_cea_aspect_ratio(
3768 frame->video_code);
3769
10a85120 3770 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
24d01805 3771 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
10a85120
TR		 3772
3773 return 0;
3774}
3775EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
83dd0008 3776
4eed4a0a
DL		 3777static enum hdmi_3d_structure
3778s3d_structure_from_display_mode(const struct drm_display_mode *mode)
3779{
3780 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
3781
3782 switch (layout) {
3783 case DRM_MODE_FLAG_3D_FRAME_PACKING:
3784 return HDMI_3D_STRUCTURE_FRAME_PACKING;
3785 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
3786 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
3787 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
3788 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
3789 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
3790 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
3791 case DRM_MODE_FLAG_3D_L_DEPTH:
3792 return HDMI_3D_STRUCTURE_L_DEPTH;
3793 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
3794 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
3795 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
3796 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
3797 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
3798 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
3799 default:
3800 return HDMI_3D_STRUCTURE_INVALID;
3801 }
3802}
3803
83dd0008
LD		 3804/**
3805 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
3806 * data from a DRM display mode
3807 * @frame: HDMI vendor infoframe
3808 * @mode: DRM display mode
3809 *
3810 * Note that there's is a need to send HDMI vendor infoframes only when using a
3811 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
3812 * function will return -EINVAL, error that can be safely ignored.
3813 *
db6cf833 3814 * Return: 0 on success or a negative error code on failure.
83dd0008
LD		 3815 */
3816int
3817drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
3818 const struct drm_display_mode *mode)
3819{
3820 int err;
4eed4a0a 3821 u32 s3d_flags;
83dd0008
LD		 3822 u8 vic;
3823
3824 if (!frame || !mode)
3825 return -EINVAL;
3826
3827 vic = drm_match_hdmi_mode(mode);
4eed4a0a
DL		 3828 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
3829
3830 if (!vic && !s3d_flags)
3831 return -EINVAL;
3832
3833 if (vic && s3d_flags)
83dd0008
LD		 3834 return -EINVAL;
3835
3836 err = hdmi_vendor_infoframe_init(frame);
3837 if (err < 0)
3838 return err;
3839
4eed4a0a
DL		 3840 if (vic)
3841 frame->vic = vic;
3842 else
3843 frame->s3d_struct = s3d_structure_from_display_mode(mode);
83dd0008
LD		 3844
3845 return 0;
3846}
3847EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git