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ac1bdbf2 TR |
1 | /* |
2 | * Tegra host1x Register Offsets for Tegra194 | |
3 | * | |
4 | * Copyright (c) 2018 NVIDIA Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #ifndef __HOST1X_HOST1X07_HARDWARE_H | |
20 | #define __HOST1X_HOST1X07_HARDWARE_H | |
21 | ||
22 | #include <linux/types.h> | |
23 | #include <linux/bitops.h> | |
24 | ||
de5469c2 | 25 | #include "hw_host1x07_channel.h" |
ac1bdbf2 TR |
26 | #include "hw_host1x07_uclass.h" |
27 | #include "hw_host1x07_vm.h" | |
28 | #include "hw_host1x07_hypervisor.h" | |
29 | ||
30 | static inline u32 host1x_class_host_wait_syncpt( | |
31 | unsigned indx, unsigned threshold) | |
32 | { | |
33 | return host1x_uclass_wait_syncpt_indx_f(indx) | |
34 | | host1x_uclass_wait_syncpt_thresh_f(threshold); | |
35 | } | |
36 | ||
37 | static inline u32 host1x_class_host_load_syncpt_base( | |
38 | unsigned indx, unsigned threshold) | |
39 | { | |
40 | return host1x_uclass_load_syncpt_base_base_indx_f(indx) | |
41 | | host1x_uclass_load_syncpt_base_value_f(threshold); | |
42 | } | |
43 | ||
44 | static inline u32 host1x_class_host_wait_syncpt_base( | |
45 | unsigned indx, unsigned base_indx, unsigned offset) | |
46 | { | |
47 | return host1x_uclass_wait_syncpt_base_indx_f(indx) | |
48 | | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx) | |
49 | | host1x_uclass_wait_syncpt_base_offset_f(offset); | |
50 | } | |
51 | ||
52 | static inline u32 host1x_class_host_incr_syncpt_base( | |
53 | unsigned base_indx, unsigned offset) | |
54 | { | |
55 | return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx) | |
56 | | host1x_uclass_incr_syncpt_base_offset_f(offset); | |
57 | } | |
58 | ||
59 | static inline u32 host1x_class_host_incr_syncpt( | |
60 | unsigned cond, unsigned indx) | |
61 | { | |
62 | return host1x_uclass_incr_syncpt_cond_f(cond) | |
63 | | host1x_uclass_incr_syncpt_indx_f(indx); | |
64 | } | |
65 | ||
66 | static inline u32 host1x_class_host_indoff_reg_write( | |
67 | unsigned mod_id, unsigned offset, bool auto_inc) | |
68 | { | |
69 | u32 v = host1x_uclass_indoff_indbe_f(0xf) | |
70 | | host1x_uclass_indoff_indmodid_f(mod_id) | |
71 | | host1x_uclass_indoff_indroffset_f(offset); | |
72 | if (auto_inc) | |
73 | v |= host1x_uclass_indoff_autoinc_f(1); | |
74 | return v; | |
75 | } | |
76 | ||
77 | static inline u32 host1x_class_host_indoff_reg_read( | |
78 | unsigned mod_id, unsigned offset, bool auto_inc) | |
79 | { | |
80 | u32 v = host1x_uclass_indoff_indmodid_f(mod_id) | |
81 | | host1x_uclass_indoff_indroffset_f(offset) | |
82 | | host1x_uclass_indoff_rwn_read_v(); | |
83 | if (auto_inc) | |
84 | v |= host1x_uclass_indoff_autoinc_f(1); | |
85 | return v; | |
86 | } | |
87 | ||
88 | /* cdma opcodes */ | |
89 | static inline u32 host1x_opcode_setclass( | |
90 | unsigned class_id, unsigned offset, unsigned mask) | |
91 | { | |
92 | return (0 << 28) | (offset << 16) | (class_id << 6) | mask; | |
93 | } | |
94 | ||
95 | static inline u32 host1x_opcode_incr(unsigned offset, unsigned count) | |
96 | { | |
97 | return (1 << 28) | (offset << 16) | count; | |
98 | } | |
99 | ||
100 | static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count) | |
101 | { | |
102 | return (2 << 28) | (offset << 16) | count; | |
103 | } | |
104 | ||
105 | static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) | |
106 | { | |
107 | return (3 << 28) | (offset << 16) | mask; | |
108 | } | |
109 | ||
110 | static inline u32 host1x_opcode_imm(unsigned offset, unsigned value) | |
111 | { | |
112 | return (4 << 28) | (offset << 16) | value; | |
113 | } | |
114 | ||
115 | static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx) | |
116 | { | |
117 | return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(), | |
118 | host1x_class_host_incr_syncpt(cond, indx)); | |
119 | } | |
120 | ||
121 | static inline u32 host1x_opcode_restart(unsigned address) | |
122 | { | |
123 | return (5 << 28) | (address >> 4); | |
124 | } | |
125 | ||
126 | static inline u32 host1x_opcode_gather(unsigned count) | |
127 | { | |
128 | return (6 << 28) | count; | |
129 | } | |
130 | ||
131 | static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count) | |
132 | { | |
133 | return (6 << 28) | (offset << 16) | BIT(15) | count; | |
134 | } | |
135 | ||
136 | static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count) | |
137 | { | |
138 | return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; | |
139 | } | |
140 | ||
141 | #define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0) | |
142 | ||
143 | #endif |