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e126ba97 | 1 | /* |
6cf0a15f | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <rdma/ib_umem.h> | |
2811ba51 | 35 | #include <rdma/ib_cache.h> |
cfb5e088 | 36 | #include <rdma/ib_user_verbs.h> |
c2e53b2c | 37 | #include <linux/mlx5/fs.h> |
e126ba97 | 38 | #include "mlx5_ib.h" |
b96c9dde | 39 | #include "ib_rep.h" |
443c1cf9 | 40 | #include "cmd.h" |
e126ba97 EC |
41 | |
42 | /* not supported currently */ | |
43 | static int wq_signature; | |
44 | ||
45 | enum { | |
46 | MLX5_IB_ACK_REQ_FREQ = 8, | |
47 | }; | |
48 | ||
49 | enum { | |
50 | MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83, | |
51 | MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, | |
52 | MLX5_IB_LINK_TYPE_IB = 0, | |
53 | MLX5_IB_LINK_TYPE_ETH = 1 | |
54 | }; | |
55 | ||
56 | enum { | |
57 | MLX5_IB_SQ_STRIDE = 6, | |
064e5262 | 58 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64, |
e126ba97 EC |
59 | }; |
60 | ||
61 | static const u32 mlx5_ib_opcode[] = { | |
62 | [IB_WR_SEND] = MLX5_OPCODE_SEND, | |
f0313965 | 63 | [IB_WR_LSO] = MLX5_OPCODE_LSO, |
e126ba97 EC |
64 | [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM, |
65 | [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE, | |
66 | [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM, | |
67 | [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ, | |
68 | [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS, | |
69 | [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA, | |
70 | [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL, | |
71 | [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR, | |
8a187ee5 | 72 | [IB_WR_REG_MR] = MLX5_OPCODE_UMR, |
e126ba97 EC |
73 | [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS, |
74 | [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA, | |
75 | [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR, | |
76 | }; | |
77 | ||
f0313965 ES |
78 | struct mlx5_wqe_eth_pad { |
79 | u8 rsvd0[16]; | |
80 | }; | |
e126ba97 | 81 | |
eb49ab0c AV |
82 | enum raw_qp_set_mask_map { |
83 | MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0, | |
7d29f349 | 84 | MLX5_RAW_QP_RATE_LIMIT = 1UL << 1, |
eb49ab0c AV |
85 | }; |
86 | ||
0680efa2 AV |
87 | struct mlx5_modify_raw_qp_param { |
88 | u16 operation; | |
eb49ab0c AV |
89 | |
90 | u32 set_mask; /* raw_qp_set_mask_map */ | |
61147f39 BW |
91 | |
92 | struct mlx5_rate_limit rl; | |
93 | ||
eb49ab0c | 94 | u8 rq_q_ctr_id; |
0680efa2 AV |
95 | }; |
96 | ||
89ea94a7 MG |
97 | static void get_cqs(enum ib_qp_type qp_type, |
98 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
99 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq); | |
100 | ||
e126ba97 EC |
101 | static int is_qp0(enum ib_qp_type qp_type) |
102 | { | |
103 | return qp_type == IB_QPT_SMI; | |
104 | } | |
105 | ||
e126ba97 EC |
106 | static int is_sqp(enum ib_qp_type qp_type) |
107 | { | |
108 | return is_qp0(qp_type) || is_qp1(qp_type); | |
109 | } | |
110 | ||
c1395a2a | 111 | /** |
fbeb4075 MS |
112 | * mlx5_ib_read_user_wqe_common() - Copy a WQE (or part of) from user WQ |
113 | * to kernel buffer | |
c1395a2a | 114 | * |
fbeb4075 MS |
115 | * @umem: User space memory where the WQ is |
116 | * @buffer: buffer to copy to | |
117 | * @buflen: buffer length | |
118 | * @wqe_index: index of WQE to copy from | |
119 | * @wq_offset: offset to start of WQ | |
120 | * @wq_wqe_cnt: number of WQEs in WQ | |
121 | * @wq_wqe_shift: log2 of WQE size | |
122 | * @bcnt: number of bytes to copy | |
123 | * @bytes_copied: number of bytes to copy (return value) | |
c1395a2a | 124 | * |
fbeb4075 MS |
125 | * Copies from start of WQE bcnt or less bytes. |
126 | * Does not gurantee to copy the entire WQE. | |
c1395a2a | 127 | * |
fbeb4075 | 128 | * Return: zero on success, or an error code. |
c1395a2a | 129 | */ |
fbeb4075 MS |
130 | static int mlx5_ib_read_user_wqe_common(struct ib_umem *umem, |
131 | void *buffer, | |
132 | u32 buflen, | |
133 | int wqe_index, | |
134 | int wq_offset, | |
135 | int wq_wqe_cnt, | |
136 | int wq_wqe_shift, | |
137 | int bcnt, | |
138 | size_t *bytes_copied) | |
c1395a2a | 139 | { |
fbeb4075 MS |
140 | size_t offset = wq_offset + ((wqe_index % wq_wqe_cnt) << wq_wqe_shift); |
141 | size_t wq_end = wq_offset + (wq_wqe_cnt << wq_wqe_shift); | |
142 | size_t copy_length; | |
c1395a2a HE |
143 | int ret; |
144 | ||
fbeb4075 MS |
145 | /* don't copy more than requested, more than buffer length or |
146 | * beyond WQ end | |
147 | */ | |
148 | copy_length = min_t(u32, buflen, wq_end - offset); | |
149 | copy_length = min_t(u32, copy_length, bcnt); | |
150 | ||
151 | ret = ib_umem_copy_from(buffer, umem, offset, copy_length); | |
152 | if (ret) | |
153 | return ret; | |
c1395a2a | 154 | |
fbeb4075 MS |
155 | if (!ret && bytes_copied) |
156 | *bytes_copied = copy_length; | |
c1395a2a | 157 | |
fbeb4075 MS |
158 | return 0; |
159 | } | |
c1395a2a | 160 | |
fbeb4075 MS |
161 | int mlx5_ib_read_user_wqe_sq(struct mlx5_ib_qp *qp, |
162 | int wqe_index, | |
163 | void *buffer, | |
164 | int buflen, | |
165 | size_t *bc) | |
166 | { | |
167 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
168 | struct ib_umem *umem = base->ubuffer.umem; | |
169 | struct mlx5_ib_wq *wq = &qp->sq; | |
170 | struct mlx5_wqe_ctrl_seg *ctrl; | |
171 | size_t bytes_copied; | |
172 | size_t bytes_copied2; | |
173 | size_t wqe_length; | |
174 | int ret; | |
175 | int ds; | |
176 | ||
177 | if (buflen < sizeof(*ctrl)) | |
c1395a2a HE |
178 | return -EINVAL; |
179 | ||
fbeb4075 MS |
180 | /* at first read as much as possible */ |
181 | ret = mlx5_ib_read_user_wqe_common(umem, | |
182 | buffer, | |
183 | buflen, | |
184 | wqe_index, | |
185 | wq->offset, | |
186 | wq->wqe_cnt, | |
187 | wq->wqe_shift, | |
188 | buflen, | |
189 | &bytes_copied); | |
c1395a2a HE |
190 | if (ret) |
191 | return ret; | |
192 | ||
fbeb4075 MS |
193 | /* we need at least control segment size to proceed */ |
194 | if (bytes_copied < sizeof(*ctrl)) | |
195 | return -EINVAL; | |
196 | ||
197 | ctrl = buffer; | |
198 | ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK; | |
199 | wqe_length = ds * MLX5_WQE_DS_UNITS; | |
c1395a2a | 200 | |
fbeb4075 MS |
201 | /* if we copied enough then we are done */ |
202 | if (bytes_copied >= wqe_length) { | |
203 | *bc = bytes_copied; | |
204 | return 0; | |
c1395a2a HE |
205 | } |
206 | ||
fbeb4075 MS |
207 | /* otherwise this a wrapped around wqe |
208 | * so read the remaining bytes starting | |
209 | * from wqe_index 0 | |
210 | */ | |
211 | ret = mlx5_ib_read_user_wqe_common(umem, | |
212 | buffer + bytes_copied, | |
213 | buflen - bytes_copied, | |
214 | 0, | |
215 | wq->offset, | |
216 | wq->wqe_cnt, | |
217 | wq->wqe_shift, | |
218 | wqe_length - bytes_copied, | |
219 | &bytes_copied2); | |
220 | ||
221 | if (ret) | |
222 | return ret; | |
223 | *bc = bytes_copied + bytes_copied2; | |
224 | return 0; | |
225 | } | |
226 | ||
227 | int mlx5_ib_read_user_wqe_rq(struct mlx5_ib_qp *qp, | |
228 | int wqe_index, | |
229 | void *buffer, | |
230 | int buflen, | |
231 | size_t *bc) | |
232 | { | |
233 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; | |
234 | struct ib_umem *umem = base->ubuffer.umem; | |
235 | struct mlx5_ib_wq *wq = &qp->rq; | |
236 | size_t bytes_copied; | |
237 | int ret; | |
238 | ||
239 | ret = mlx5_ib_read_user_wqe_common(umem, | |
240 | buffer, | |
241 | buflen, | |
242 | wqe_index, | |
243 | wq->offset, | |
244 | wq->wqe_cnt, | |
245 | wq->wqe_shift, | |
246 | buflen, | |
247 | &bytes_copied); | |
c1395a2a | 248 | |
c1395a2a HE |
249 | if (ret) |
250 | return ret; | |
fbeb4075 MS |
251 | *bc = bytes_copied; |
252 | return 0; | |
253 | } | |
254 | ||
255 | int mlx5_ib_read_user_wqe_srq(struct mlx5_ib_srq *srq, | |
256 | int wqe_index, | |
257 | void *buffer, | |
258 | int buflen, | |
259 | size_t *bc) | |
260 | { | |
261 | struct ib_umem *umem = srq->umem; | |
262 | size_t bytes_copied; | |
263 | int ret; | |
c1395a2a | 264 | |
fbeb4075 MS |
265 | ret = mlx5_ib_read_user_wqe_common(umem, |
266 | buffer, | |
267 | buflen, | |
268 | wqe_index, | |
269 | 0, | |
270 | srq->msrq.max, | |
271 | srq->msrq.wqe_shift, | |
272 | buflen, | |
273 | &bytes_copied); | |
274 | ||
275 | if (ret) | |
276 | return ret; | |
277 | *bc = bytes_copied; | |
278 | return 0; | |
c1395a2a HE |
279 | } |
280 | ||
e126ba97 EC |
281 | static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type) |
282 | { | |
283 | struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; | |
284 | struct ib_event event; | |
285 | ||
19098df2 | 286 | if (type == MLX5_EVENT_TYPE_PATH_MIG) { |
287 | /* This event is only valid for trans_qps */ | |
288 | to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port; | |
289 | } | |
e126ba97 EC |
290 | |
291 | if (ibqp->event_handler) { | |
292 | event.device = ibqp->device; | |
293 | event.element.qp = ibqp; | |
294 | switch (type) { | |
295 | case MLX5_EVENT_TYPE_PATH_MIG: | |
296 | event.event = IB_EVENT_PATH_MIG; | |
297 | break; | |
298 | case MLX5_EVENT_TYPE_COMM_EST: | |
299 | event.event = IB_EVENT_COMM_EST; | |
300 | break; | |
301 | case MLX5_EVENT_TYPE_SQ_DRAINED: | |
302 | event.event = IB_EVENT_SQ_DRAINED; | |
303 | break; | |
304 | case MLX5_EVENT_TYPE_SRQ_LAST_WQE: | |
305 | event.event = IB_EVENT_QP_LAST_WQE_REACHED; | |
306 | break; | |
307 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
308 | event.event = IB_EVENT_QP_FATAL; | |
309 | break; | |
310 | case MLX5_EVENT_TYPE_PATH_MIG_FAILED: | |
311 | event.event = IB_EVENT_PATH_MIG_ERR; | |
312 | break; | |
313 | case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: | |
314 | event.event = IB_EVENT_QP_REQ_ERR; | |
315 | break; | |
316 | case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: | |
317 | event.event = IB_EVENT_QP_ACCESS_ERR; | |
318 | break; | |
319 | default: | |
320 | pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn); | |
321 | return; | |
322 | } | |
323 | ||
324 | ibqp->event_handler(&event, ibqp->qp_context); | |
325 | } | |
326 | } | |
327 | ||
328 | static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap, | |
329 | int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd) | |
330 | { | |
331 | int wqe_size; | |
332 | int wq_size; | |
333 | ||
334 | /* Sanity check RQ size before proceeding */ | |
938fe83c | 335 | if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) |
e126ba97 EC |
336 | return -EINVAL; |
337 | ||
338 | if (!has_rq) { | |
339 | qp->rq.max_gs = 0; | |
340 | qp->rq.wqe_cnt = 0; | |
341 | qp->rq.wqe_shift = 0; | |
0540d814 NO |
342 | cap->max_recv_wr = 0; |
343 | cap->max_recv_sge = 0; | |
e126ba97 EC |
344 | } else { |
345 | if (ucmd) { | |
346 | qp->rq.wqe_cnt = ucmd->rq_wqe_count; | |
002bf228 LR |
347 | if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift)) |
348 | return -EINVAL; | |
e126ba97 | 349 | qp->rq.wqe_shift = ucmd->rq_wqe_shift; |
002bf228 LR |
350 | if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig) |
351 | return -EINVAL; | |
e126ba97 EC |
352 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; |
353 | qp->rq.max_post = qp->rq.wqe_cnt; | |
354 | } else { | |
355 | wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0; | |
356 | wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg); | |
357 | wqe_size = roundup_pow_of_two(wqe_size); | |
358 | wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size; | |
359 | wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB); | |
360 | qp->rq.wqe_cnt = wq_size / wqe_size; | |
938fe83c | 361 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) { |
e126ba97 EC |
362 | mlx5_ib_dbg(dev, "wqe_size %d, max %d\n", |
363 | wqe_size, | |
938fe83c SM |
364 | MLX5_CAP_GEN(dev->mdev, |
365 | max_wqe_sz_rq)); | |
e126ba97 EC |
366 | return -EINVAL; |
367 | } | |
368 | qp->rq.wqe_shift = ilog2(wqe_size); | |
369 | qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig; | |
370 | qp->rq.max_post = qp->rq.wqe_cnt; | |
371 | } | |
372 | } | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
f0313965 | 377 | static int sq_overhead(struct ib_qp_init_attr *attr) |
e126ba97 | 378 | { |
618af384 | 379 | int size = 0; |
e126ba97 | 380 | |
f0313965 | 381 | switch (attr->qp_type) { |
e126ba97 | 382 | case IB_QPT_XRC_INI: |
b125a54b | 383 | size += sizeof(struct mlx5_wqe_xrc_seg); |
e126ba97 EC |
384 | /* fall through */ |
385 | case IB_QPT_RC: | |
386 | size += sizeof(struct mlx5_wqe_ctrl_seg) + | |
75c1657e LR |
387 | max(sizeof(struct mlx5_wqe_atomic_seg) + |
388 | sizeof(struct mlx5_wqe_raddr_seg), | |
389 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
064e5262 IB |
390 | sizeof(struct mlx5_mkey_seg) + |
391 | MLX5_IB_SQ_UMR_INLINE_THRESHOLD / | |
392 | MLX5_IB_UMR_OCTOWORD); | |
e126ba97 EC |
393 | break; |
394 | ||
b125a54b EC |
395 | case IB_QPT_XRC_TGT: |
396 | return 0; | |
397 | ||
e126ba97 | 398 | case IB_QPT_UC: |
b125a54b | 399 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
75c1657e LR |
400 | max(sizeof(struct mlx5_wqe_raddr_seg), |
401 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + | |
402 | sizeof(struct mlx5_mkey_seg)); | |
e126ba97 EC |
403 | break; |
404 | ||
405 | case IB_QPT_UD: | |
f0313965 ES |
406 | if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) |
407 | size += sizeof(struct mlx5_wqe_eth_pad) + | |
408 | sizeof(struct mlx5_wqe_eth_seg); | |
409 | /* fall through */ | |
e126ba97 | 410 | case IB_QPT_SMI: |
d16e91da | 411 | case MLX5_IB_QPT_HW_GSI: |
b125a54b | 412 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
413 | sizeof(struct mlx5_wqe_datagram_seg); |
414 | break; | |
415 | ||
416 | case MLX5_IB_QPT_REG_UMR: | |
b125a54b | 417 | size += sizeof(struct mlx5_wqe_ctrl_seg) + |
e126ba97 EC |
418 | sizeof(struct mlx5_wqe_umr_ctrl_seg) + |
419 | sizeof(struct mlx5_mkey_seg); | |
420 | break; | |
421 | ||
422 | default: | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | return size; | |
427 | } | |
428 | ||
429 | static int calc_send_wqe(struct ib_qp_init_attr *attr) | |
430 | { | |
431 | int inl_size = 0; | |
432 | int size; | |
433 | ||
f0313965 | 434 | size = sq_overhead(attr); |
e126ba97 EC |
435 | if (size < 0) |
436 | return size; | |
437 | ||
438 | if (attr->cap.max_inline_data) { | |
439 | inl_size = size + sizeof(struct mlx5_wqe_inline_seg) + | |
440 | attr->cap.max_inline_data; | |
441 | } | |
442 | ||
443 | size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg); | |
e1e66cc2 SG |
444 | if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN && |
445 | ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE) | |
446 | return MLX5_SIG_WQE_SIZE; | |
447 | else | |
448 | return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB); | |
e126ba97 EC |
449 | } |
450 | ||
288c01b7 EC |
451 | static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size) |
452 | { | |
453 | int max_sge; | |
454 | ||
455 | if (attr->qp_type == IB_QPT_RC) | |
456 | max_sge = (min_t(int, wqe_size, 512) - | |
457 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
458 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
459 | sizeof(struct mlx5_wqe_data_seg); | |
460 | else if (attr->qp_type == IB_QPT_XRC_INI) | |
461 | max_sge = (min_t(int, wqe_size, 512) - | |
462 | sizeof(struct mlx5_wqe_ctrl_seg) - | |
463 | sizeof(struct mlx5_wqe_xrc_seg) - | |
464 | sizeof(struct mlx5_wqe_raddr_seg)) / | |
465 | sizeof(struct mlx5_wqe_data_seg); | |
466 | else | |
467 | max_sge = (wqe_size - sq_overhead(attr)) / | |
468 | sizeof(struct mlx5_wqe_data_seg); | |
469 | ||
470 | return min_t(int, max_sge, wqe_size - sq_overhead(attr) / | |
471 | sizeof(struct mlx5_wqe_data_seg)); | |
472 | } | |
473 | ||
e126ba97 EC |
474 | static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr, |
475 | struct mlx5_ib_qp *qp) | |
476 | { | |
477 | int wqe_size; | |
478 | int wq_size; | |
479 | ||
480 | if (!attr->cap.max_send_wr) | |
481 | return 0; | |
482 | ||
483 | wqe_size = calc_send_wqe(attr); | |
484 | mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size); | |
485 | if (wqe_size < 0) | |
486 | return wqe_size; | |
487 | ||
938fe83c | 488 | if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
b125a54b | 489 | mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n", |
938fe83c | 490 | wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
491 | return -EINVAL; |
492 | } | |
493 | ||
f0313965 ES |
494 | qp->max_inline_data = wqe_size - sq_overhead(attr) - |
495 | sizeof(struct mlx5_wqe_inline_seg); | |
e126ba97 EC |
496 | attr->cap.max_inline_data = qp->max_inline_data; |
497 | ||
e1e66cc2 SG |
498 | if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN) |
499 | qp->signature_en = true; | |
500 | ||
e126ba97 EC |
501 | wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size); |
502 | qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB; | |
938fe83c | 503 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
1974ab9d BVA |
504 | mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n", |
505 | attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB, | |
938fe83c SM |
506 | qp->sq.wqe_cnt, |
507 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
b125a54b EC |
508 | return -ENOMEM; |
509 | } | |
e126ba97 | 510 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); |
288c01b7 EC |
511 | qp->sq.max_gs = get_send_sge(attr, wqe_size); |
512 | if (qp->sq.max_gs < attr->cap.max_send_sge) | |
513 | return -ENOMEM; | |
514 | ||
515 | attr->cap.max_send_sge = qp->sq.max_gs; | |
b125a54b EC |
516 | qp->sq.max_post = wq_size / wqe_size; |
517 | attr->cap.max_send_wr = qp->sq.max_post; | |
e126ba97 EC |
518 | |
519 | return wq_size; | |
520 | } | |
521 | ||
522 | static int set_user_buf_size(struct mlx5_ib_dev *dev, | |
523 | struct mlx5_ib_qp *qp, | |
19098df2 | 524 | struct mlx5_ib_create_qp *ucmd, |
0fb2ed66 | 525 | struct mlx5_ib_qp_base *base, |
526 | struct ib_qp_init_attr *attr) | |
e126ba97 EC |
527 | { |
528 | int desc_sz = 1 << qp->sq.wqe_shift; | |
529 | ||
938fe83c | 530 | if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) { |
e126ba97 | 531 | mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n", |
938fe83c | 532 | desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)); |
e126ba97 EC |
533 | return -EINVAL; |
534 | } | |
535 | ||
af8b38ed GP |
536 | if (ucmd->sq_wqe_count && !is_power_of_2(ucmd->sq_wqe_count)) { |
537 | mlx5_ib_warn(dev, "sq_wqe_count %d is not a power of two\n", | |
538 | ucmd->sq_wqe_count); | |
e126ba97 EC |
539 | return -EINVAL; |
540 | } | |
541 | ||
542 | qp->sq.wqe_cnt = ucmd->sq_wqe_count; | |
543 | ||
938fe83c | 544 | if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) { |
e126ba97 | 545 | mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n", |
938fe83c SM |
546 | qp->sq.wqe_cnt, |
547 | 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)); | |
e126ba97 EC |
548 | return -EINVAL; |
549 | } | |
550 | ||
c2e53b2c YH |
551 | if (attr->qp_type == IB_QPT_RAW_PACKET || |
552 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 553 | base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift; |
554 | qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6; | |
555 | } else { | |
556 | base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + | |
557 | (qp->sq.wqe_cnt << 6); | |
558 | } | |
e126ba97 EC |
559 | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static int qp_has_rq(struct ib_qp_init_attr *attr) | |
564 | { | |
565 | if (attr->qp_type == IB_QPT_XRC_INI || | |
566 | attr->qp_type == IB_QPT_XRC_TGT || attr->srq || | |
567 | attr->qp_type == MLX5_IB_QPT_REG_UMR || | |
568 | !attr->cap.max_recv_wr) | |
569 | return 0; | |
570 | ||
571 | return 1; | |
572 | } | |
573 | ||
0b80c14f EC |
574 | enum { |
575 | /* this is the first blue flame register in the array of bfregs assigned | |
576 | * to a processes. Since we do not use it for blue flame but rather | |
577 | * regular 64 bit doorbells, we do not need a lock for maintaiing | |
578 | * "odd/even" order | |
579 | */ | |
580 | NUM_NON_BLUE_FLAME_BFREGS = 1, | |
581 | }; | |
582 | ||
b037c29a EC |
583 | static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi) |
584 | { | |
31a78a5a | 585 | return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a EC |
586 | } |
587 | ||
588 | static int num_med_bfreg(struct mlx5_ib_dev *dev, | |
589 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
590 | { |
591 | int n; | |
592 | ||
b037c29a EC |
593 | n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs - |
594 | NUM_NON_BLUE_FLAME_BFREGS; | |
c1be5232 EC |
595 | |
596 | return n >= 0 ? n : 0; | |
597 | } | |
598 | ||
18b0362e YH |
599 | static int first_med_bfreg(struct mlx5_ib_dev *dev, |
600 | struct mlx5_bfreg_info *bfregi) | |
601 | { | |
602 | return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM; | |
603 | } | |
604 | ||
b037c29a EC |
605 | static int first_hi_bfreg(struct mlx5_ib_dev *dev, |
606 | struct mlx5_bfreg_info *bfregi) | |
c1be5232 EC |
607 | { |
608 | int med; | |
c1be5232 | 609 | |
b037c29a EC |
610 | med = num_med_bfreg(dev, bfregi); |
611 | return ++med; | |
c1be5232 EC |
612 | } |
613 | ||
b037c29a EC |
614 | static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev, |
615 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 616 | { |
e126ba97 EC |
617 | int i; |
618 | ||
b037c29a EC |
619 | for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) { |
620 | if (!bfregi->count[i]) { | |
2f5ff264 | 621 | bfregi->count[i]++; |
e126ba97 EC |
622 | return i; |
623 | } | |
624 | } | |
625 | ||
626 | return -ENOMEM; | |
627 | } | |
628 | ||
b037c29a EC |
629 | static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev, |
630 | struct mlx5_bfreg_info *bfregi) | |
e126ba97 | 631 | { |
18b0362e | 632 | int minidx = first_med_bfreg(dev, bfregi); |
e126ba97 EC |
633 | int i; |
634 | ||
18b0362e YH |
635 | if (minidx < 0) |
636 | return minidx; | |
637 | ||
638 | for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) { | |
2f5ff264 | 639 | if (bfregi->count[i] < bfregi->count[minidx]) |
e126ba97 | 640 | minidx = i; |
0b80c14f EC |
641 | if (!bfregi->count[minidx]) |
642 | break; | |
e126ba97 EC |
643 | } |
644 | ||
2f5ff264 | 645 | bfregi->count[minidx]++; |
e126ba97 EC |
646 | return minidx; |
647 | } | |
648 | ||
b037c29a | 649 | static int alloc_bfreg(struct mlx5_ib_dev *dev, |
ffaf58de | 650 | struct mlx5_bfreg_info *bfregi) |
e126ba97 | 651 | { |
ffaf58de | 652 | int bfregn = -ENOMEM; |
e126ba97 | 653 | |
2f5ff264 | 654 | mutex_lock(&bfregi->lock); |
ffaf58de LR |
655 | if (bfregi->ver >= 2) { |
656 | bfregn = alloc_high_class_bfreg(dev, bfregi); | |
657 | if (bfregn < 0) | |
658 | bfregn = alloc_med_class_bfreg(dev, bfregi); | |
659 | } | |
660 | ||
661 | if (bfregn < 0) { | |
0b80c14f | 662 | BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1); |
2f5ff264 EC |
663 | bfregn = 0; |
664 | bfregi->count[bfregn]++; | |
e126ba97 | 665 | } |
2f5ff264 | 666 | mutex_unlock(&bfregi->lock); |
e126ba97 | 667 | |
2f5ff264 | 668 | return bfregn; |
e126ba97 EC |
669 | } |
670 | ||
4ed131d0 | 671 | void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn) |
e126ba97 | 672 | { |
2f5ff264 | 673 | mutex_lock(&bfregi->lock); |
b037c29a | 674 | bfregi->count[bfregn]--; |
2f5ff264 | 675 | mutex_unlock(&bfregi->lock); |
e126ba97 EC |
676 | } |
677 | ||
678 | static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state) | |
679 | { | |
680 | switch (state) { | |
681 | case IB_QPS_RESET: return MLX5_QP_STATE_RST; | |
682 | case IB_QPS_INIT: return MLX5_QP_STATE_INIT; | |
683 | case IB_QPS_RTR: return MLX5_QP_STATE_RTR; | |
684 | case IB_QPS_RTS: return MLX5_QP_STATE_RTS; | |
685 | case IB_QPS_SQD: return MLX5_QP_STATE_SQD; | |
686 | case IB_QPS_SQE: return MLX5_QP_STATE_SQER; | |
687 | case IB_QPS_ERR: return MLX5_QP_STATE_ERR; | |
688 | default: return -1; | |
689 | } | |
690 | } | |
691 | ||
692 | static int to_mlx5_st(enum ib_qp_type type) | |
693 | { | |
694 | switch (type) { | |
695 | case IB_QPT_RC: return MLX5_QP_ST_RC; | |
696 | case IB_QPT_UC: return MLX5_QP_ST_UC; | |
697 | case IB_QPT_UD: return MLX5_QP_ST_UD; | |
698 | case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR; | |
699 | case IB_QPT_XRC_INI: | |
700 | case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC; | |
701 | case IB_QPT_SMI: return MLX5_QP_ST_QP0; | |
d16e91da | 702 | case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1; |
c32a4f29 | 703 | case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI; |
e126ba97 | 704 | case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6; |
e126ba97 | 705 | case IB_QPT_RAW_PACKET: |
0fb2ed66 | 706 | case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE; |
e126ba97 EC |
707 | case IB_QPT_MAX: |
708 | default: return -EINVAL; | |
709 | } | |
710 | } | |
711 | ||
89ea94a7 MG |
712 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, |
713 | struct mlx5_ib_cq *recv_cq); | |
714 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, | |
715 | struct mlx5_ib_cq *recv_cq); | |
716 | ||
7c043e90 | 717 | int bfregn_to_uar_index(struct mlx5_ib_dev *dev, |
05f58ceb | 718 | struct mlx5_bfreg_info *bfregi, u32 bfregn, |
7c043e90 | 719 | bool dyn_bfreg) |
e126ba97 | 720 | { |
05f58ceb LR |
721 | unsigned int bfregs_per_sys_page; |
722 | u32 index_of_sys_page; | |
723 | u32 offset; | |
b037c29a EC |
724 | |
725 | bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * | |
726 | MLX5_NON_FP_BFREGS_PER_UAR; | |
727 | index_of_sys_page = bfregn / bfregs_per_sys_page; | |
728 | ||
1ee47ab3 YH |
729 | if (dyn_bfreg) { |
730 | index_of_sys_page += bfregi->num_static_sys_pages; | |
05f58ceb LR |
731 | |
732 | if (index_of_sys_page >= bfregi->num_sys_pages) | |
733 | return -EINVAL; | |
734 | ||
1ee47ab3 YH |
735 | if (bfregn > bfregi->num_dyn_bfregs || |
736 | bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) { | |
737 | mlx5_ib_dbg(dev, "Invalid dynamic uar index\n"); | |
738 | return -EINVAL; | |
739 | } | |
740 | } | |
b037c29a | 741 | |
1ee47ab3 | 742 | offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR; |
b037c29a | 743 | return bfregi->sys_pages[index_of_sys_page] + offset; |
e126ba97 EC |
744 | } |
745 | ||
b0ea0fa5 | 746 | static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata, |
19098df2 | 747 | unsigned long addr, size_t size, |
b0ea0fa5 JG |
748 | struct ib_umem **umem, int *npages, int *page_shift, |
749 | int *ncont, u32 *offset) | |
19098df2 | 750 | { |
751 | int err; | |
752 | ||
b0ea0fa5 | 753 | *umem = ib_umem_get(udata, addr, size, 0, 0); |
19098df2 | 754 | if (IS_ERR(*umem)) { |
755 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
756 | return PTR_ERR(*umem); | |
757 | } | |
758 | ||
762f899a | 759 | mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL); |
19098df2 | 760 | |
761 | err = mlx5_ib_get_buf_offset(addr, *page_shift, offset); | |
762 | if (err) { | |
763 | mlx5_ib_warn(dev, "bad offset\n"); | |
764 | goto err_umem; | |
765 | } | |
766 | ||
767 | mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n", | |
768 | addr, size, *npages, *page_shift, *ncont, *offset); | |
769 | ||
770 | return 0; | |
771 | ||
772 | err_umem: | |
773 | ib_umem_release(*umem); | |
774 | *umem = NULL; | |
775 | ||
776 | return err; | |
777 | } | |
778 | ||
fe248c3a MG |
779 | static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
780 | struct mlx5_ib_rwq *rwq) | |
79b20a6c YH |
781 | { |
782 | struct mlx5_ib_ucontext *context; | |
783 | ||
fe248c3a MG |
784 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP) |
785 | atomic_dec(&dev->delay_drop.rqs_cnt); | |
786 | ||
79b20a6c YH |
787 | context = to_mucontext(pd->uobject->context); |
788 | mlx5_ib_db_unmap_user(context, &rwq->db); | |
789 | if (rwq->umem) | |
790 | ib_umem_release(rwq->umem); | |
791 | } | |
792 | ||
793 | static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd, | |
b0ea0fa5 | 794 | struct ib_udata *udata, struct mlx5_ib_rwq *rwq, |
79b20a6c YH |
795 | struct mlx5_ib_create_wq *ucmd) |
796 | { | |
89944450 SR |
797 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
798 | udata, struct mlx5_ib_ucontext, ibucontext); | |
79b20a6c YH |
799 | int page_shift = 0; |
800 | int npages; | |
801 | u32 offset = 0; | |
802 | int ncont = 0; | |
803 | int err; | |
804 | ||
805 | if (!ucmd->buf_addr) | |
806 | return -EINVAL; | |
807 | ||
b0ea0fa5 | 808 | rwq->umem = ib_umem_get(udata, ucmd->buf_addr, rwq->buf_size, 0, 0); |
79b20a6c YH |
809 | if (IS_ERR(rwq->umem)) { |
810 | mlx5_ib_dbg(dev, "umem_get failed\n"); | |
811 | err = PTR_ERR(rwq->umem); | |
812 | return err; | |
813 | } | |
814 | ||
762f899a | 815 | mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift, |
79b20a6c YH |
816 | &ncont, NULL); |
817 | err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift, | |
818 | &rwq->rq_page_offset); | |
819 | if (err) { | |
820 | mlx5_ib_warn(dev, "bad offset\n"); | |
821 | goto err_umem; | |
822 | } | |
823 | ||
824 | rwq->rq_num_pas = ncont; | |
825 | rwq->page_shift = page_shift; | |
826 | rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT; | |
827 | rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE); | |
828 | ||
829 | mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n", | |
830 | (unsigned long long)ucmd->buf_addr, rwq->buf_size, | |
831 | npages, page_shift, ncont, offset); | |
832 | ||
89944450 | 833 | err = mlx5_ib_db_map_user(ucontext, udata, ucmd->db_addr, &rwq->db); |
79b20a6c YH |
834 | if (err) { |
835 | mlx5_ib_dbg(dev, "map failed\n"); | |
836 | goto err_umem; | |
837 | } | |
838 | ||
839 | rwq->create_type = MLX5_WQ_USER; | |
840 | return 0; | |
841 | ||
842 | err_umem: | |
843 | ib_umem_release(rwq->umem); | |
844 | return err; | |
845 | } | |
846 | ||
b037c29a EC |
847 | static int adjust_bfregn(struct mlx5_ib_dev *dev, |
848 | struct mlx5_bfreg_info *bfregi, int bfregn) | |
849 | { | |
850 | return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR + | |
851 | bfregn % MLX5_NON_FP_BFREGS_PER_UAR; | |
852 | } | |
853 | ||
e126ba97 EC |
854 | static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
855 | struct mlx5_ib_qp *qp, struct ib_udata *udata, | |
0fb2ed66 | 856 | struct ib_qp_init_attr *attr, |
09a7d9ec | 857 | u32 **in, |
19098df2 | 858 | struct mlx5_ib_create_qp_resp *resp, int *inlen, |
859 | struct mlx5_ib_qp_base *base) | |
e126ba97 EC |
860 | { |
861 | struct mlx5_ib_ucontext *context; | |
862 | struct mlx5_ib_create_qp ucmd; | |
19098df2 | 863 | struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer; |
9e9c47d0 | 864 | int page_shift = 0; |
1ee47ab3 | 865 | int uar_index = 0; |
e126ba97 | 866 | int npages; |
9e9c47d0 | 867 | u32 offset = 0; |
2f5ff264 | 868 | int bfregn; |
9e9c47d0 | 869 | int ncont = 0; |
09a7d9ec SM |
870 | __be64 *pas; |
871 | void *qpc; | |
e126ba97 | 872 | int err; |
5aa3771d | 873 | u16 uid; |
e126ba97 EC |
874 | |
875 | err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd)); | |
876 | if (err) { | |
877 | mlx5_ib_dbg(dev, "copy failed\n"); | |
878 | return err; | |
879 | } | |
880 | ||
89944450 SR |
881 | context = rdma_udata_to_drv_context(udata, struct mlx5_ib_ucontext, |
882 | ibucontext); | |
1ee47ab3 YH |
883 | if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) { |
884 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, | |
885 | ucmd.bfreg_index, true); | |
886 | if (uar_index < 0) | |
887 | return uar_index; | |
888 | ||
889 | bfregn = MLX5_IB_INVALID_BFREG; | |
890 | } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) { | |
891 | /* | |
892 | * TBD: should come from the verbs when we have the API | |
893 | */ | |
051f2630 | 894 | /* In CROSS_CHANNEL CQ and QP must use the same UAR */ |
2f5ff264 | 895 | bfregn = MLX5_CROSS_CHANNEL_BFREG; |
1ee47ab3 | 896 | } |
051f2630 | 897 | else { |
ffaf58de LR |
898 | bfregn = alloc_bfreg(dev, &context->bfregi); |
899 | if (bfregn < 0) | |
900 | return bfregn; | |
e126ba97 EC |
901 | } |
902 | ||
2f5ff264 | 903 | mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index); |
1ee47ab3 YH |
904 | if (bfregn != MLX5_IB_INVALID_BFREG) |
905 | uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn, | |
906 | false); | |
e126ba97 | 907 | |
48fea837 HE |
908 | qp->rq.offset = 0; |
909 | qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB); | |
910 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
911 | ||
0fb2ed66 | 912 | err = set_user_buf_size(dev, qp, &ucmd, base, attr); |
e126ba97 | 913 | if (err) |
2f5ff264 | 914 | goto err_bfreg; |
e126ba97 | 915 | |
19098df2 | 916 | if (ucmd.buf_addr && ubuffer->buf_size) { |
917 | ubuffer->buf_addr = ucmd.buf_addr; | |
b0ea0fa5 JG |
918 | err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, |
919 | ubuffer->buf_size, &ubuffer->umem, | |
920 | &npages, &page_shift, &ncont, &offset); | |
19098df2 | 921 | if (err) |
2f5ff264 | 922 | goto err_bfreg; |
9e9c47d0 | 923 | } else { |
19098df2 | 924 | ubuffer->umem = NULL; |
e126ba97 | 925 | } |
e126ba97 | 926 | |
09a7d9ec SM |
927 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
928 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont; | |
1b9a07ee | 929 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
930 | if (!*in) { |
931 | err = -ENOMEM; | |
932 | goto err_umem; | |
933 | } | |
09a7d9ec | 934 | |
7422edce YH |
935 | uid = (attr->qp_type != IB_QPT_XRC_TGT && |
936 | attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0; | |
5aa3771d | 937 | MLX5_SET(create_qp_in, *in, uid, uid); |
09a7d9ec | 938 | pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas); |
19098df2 | 939 | if (ubuffer->umem) |
09a7d9ec SM |
940 | mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0); |
941 | ||
942 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
943 | ||
944 | MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
945 | MLX5_SET(qpc, qpc, page_offset, offset); | |
e126ba97 | 946 | |
09a7d9ec | 947 | MLX5_SET(qpc, qpc, uar_page, uar_index); |
1ee47ab3 YH |
948 | if (bfregn != MLX5_IB_INVALID_BFREG) |
949 | resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn); | |
950 | else | |
951 | resp->bfreg_index = MLX5_IB_INVALID_BFREG; | |
2f5ff264 | 952 | qp->bfregn = bfregn; |
e126ba97 | 953 | |
b0ea0fa5 | 954 | err = mlx5_ib_db_map_user(context, udata, ucmd.db_addr, &qp->db); |
e126ba97 EC |
955 | if (err) { |
956 | mlx5_ib_dbg(dev, "map failed\n"); | |
957 | goto err_free; | |
958 | } | |
959 | ||
41d902cb | 960 | err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); |
e126ba97 EC |
961 | if (err) { |
962 | mlx5_ib_dbg(dev, "copy failed\n"); | |
963 | goto err_unmap; | |
964 | } | |
965 | qp->create_type = MLX5_QP_USER; | |
966 | ||
967 | return 0; | |
968 | ||
969 | err_unmap: | |
970 | mlx5_ib_db_unmap_user(context, &qp->db); | |
971 | ||
972 | err_free: | |
479163f4 | 973 | kvfree(*in); |
e126ba97 EC |
974 | |
975 | err_umem: | |
19098df2 | 976 | if (ubuffer->umem) |
977 | ib_umem_release(ubuffer->umem); | |
e126ba97 | 978 | |
2f5ff264 | 979 | err_bfreg: |
1ee47ab3 YH |
980 | if (bfregn != MLX5_IB_INVALID_BFREG) |
981 | mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn); | |
e126ba97 EC |
982 | return err; |
983 | } | |
984 | ||
b037c29a EC |
985 | static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
986 | struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base) | |
e126ba97 EC |
987 | { |
988 | struct mlx5_ib_ucontext *context; | |
989 | ||
990 | context = to_mucontext(pd->uobject->context); | |
991 | mlx5_ib_db_unmap_user(context, &qp->db); | |
19098df2 | 992 | if (base->ubuffer.umem) |
993 | ib_umem_release(base->ubuffer.umem); | |
1ee47ab3 YH |
994 | |
995 | /* | |
996 | * Free only the BFREGs which are handled by the kernel. | |
997 | * BFREGs of UARs allocated dynamically are handled by user. | |
998 | */ | |
999 | if (qp->bfregn != MLX5_IB_INVALID_BFREG) | |
1000 | mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn); | |
e126ba97 EC |
1001 | } |
1002 | ||
34f4c955 GL |
1003 | /* get_sq_edge - Get the next nearby edge. |
1004 | * | |
1005 | * An 'edge' is defined as the first following address after the end | |
1006 | * of the fragment or the SQ. Accordingly, during the WQE construction | |
1007 | * which repetitively increases the pointer to write the next data, it | |
1008 | * simply should check if it gets to an edge. | |
1009 | * | |
1010 | * @sq - SQ buffer. | |
1011 | * @idx - Stride index in the SQ buffer. | |
1012 | * | |
1013 | * Return: | |
1014 | * The new edge. | |
1015 | */ | |
1016 | static void *get_sq_edge(struct mlx5_ib_wq *sq, u32 idx) | |
1017 | { | |
1018 | void *fragment_end; | |
1019 | ||
1020 | fragment_end = mlx5_frag_buf_get_wqe | |
1021 | (&sq->fbc, | |
1022 | mlx5_frag_buf_get_idx_last_contig_stride(&sq->fbc, idx)); | |
1023 | ||
1024 | return fragment_end + MLX5_SEND_WQE_BB; | |
1025 | } | |
1026 | ||
e126ba97 EC |
1027 | static int create_kernel_qp(struct mlx5_ib_dev *dev, |
1028 | struct ib_qp_init_attr *init_attr, | |
1029 | struct mlx5_ib_qp *qp, | |
09a7d9ec | 1030 | u32 **in, int *inlen, |
19098df2 | 1031 | struct mlx5_ib_qp_base *base) |
e126ba97 | 1032 | { |
e126ba97 | 1033 | int uar_index; |
09a7d9ec | 1034 | void *qpc; |
e126ba97 EC |
1035 | int err; |
1036 | ||
f0313965 ES |
1037 | if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | |
1038 | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK | | |
b11a4f9c | 1039 | IB_QP_CREATE_IPOIB_UD_LSO | |
93d576af | 1040 | IB_QP_CREATE_NETIF_QP | |
b11a4f9c | 1041 | mlx5_ib_create_qp_sqpn_qp1())) |
1a4c3a3d | 1042 | return -EINVAL; |
e126ba97 EC |
1043 | |
1044 | if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR) | |
5fe9dec0 EC |
1045 | qp->bf.bfreg = &dev->fp_bfreg; |
1046 | else | |
1047 | qp->bf.bfreg = &dev->bfreg; | |
e126ba97 | 1048 | |
d8030b0d EC |
1049 | /* We need to divide by two since each register is comprised of |
1050 | * two buffers of identical size, namely odd and even | |
1051 | */ | |
1052 | qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2; | |
5fe9dec0 | 1053 | uar_index = qp->bf.bfreg->index; |
e126ba97 EC |
1054 | |
1055 | err = calc_sq_size(dev, init_attr, qp); | |
1056 | if (err < 0) { | |
1057 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 1058 | return err; |
e126ba97 EC |
1059 | } |
1060 | ||
1061 | qp->rq.offset = 0; | |
1062 | qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; | |
19098df2 | 1063 | base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift); |
e126ba97 | 1064 | |
34f4c955 GL |
1065 | err = mlx5_frag_buf_alloc_node(dev->mdev, base->ubuffer.buf_size, |
1066 | &qp->buf, dev->mdev->priv.numa_node); | |
e126ba97 EC |
1067 | if (err) { |
1068 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5fe9dec0 | 1069 | return err; |
e126ba97 EC |
1070 | } |
1071 | ||
34f4c955 GL |
1072 | if (qp->rq.wqe_cnt) |
1073 | mlx5_init_fbc(qp->buf.frags, qp->rq.wqe_shift, | |
1074 | ilog2(qp->rq.wqe_cnt), &qp->rq.fbc); | |
1075 | ||
1076 | if (qp->sq.wqe_cnt) { | |
1077 | int sq_strides_offset = (qp->sq.offset & (PAGE_SIZE - 1)) / | |
1078 | MLX5_SEND_WQE_BB; | |
1079 | mlx5_init_fbc_offset(qp->buf.frags + | |
1080 | (qp->sq.offset / PAGE_SIZE), | |
1081 | ilog2(MLX5_SEND_WQE_BB), | |
1082 | ilog2(qp->sq.wqe_cnt), | |
1083 | sq_strides_offset, &qp->sq.fbc); | |
1084 | ||
1085 | qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); | |
1086 | } | |
1087 | ||
09a7d9ec SM |
1088 | *inlen = MLX5_ST_SZ_BYTES(create_qp_in) + |
1089 | MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages; | |
1b9a07ee | 1090 | *in = kvzalloc(*inlen, GFP_KERNEL); |
e126ba97 EC |
1091 | if (!*in) { |
1092 | err = -ENOMEM; | |
1093 | goto err_buf; | |
1094 | } | |
09a7d9ec SM |
1095 | |
1096 | qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc); | |
1097 | MLX5_SET(qpc, qpc, uar_page, uar_index); | |
1098 | MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1099 | ||
e126ba97 | 1100 | /* Set "fast registration enabled" for all kernel QPs */ |
09a7d9ec SM |
1101 | MLX5_SET(qpc, qpc, fre, 1); |
1102 | MLX5_SET(qpc, qpc, rlky, 1); | |
e126ba97 | 1103 | |
b11a4f9c | 1104 | if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) { |
09a7d9ec | 1105 | MLX5_SET(qpc, qpc, deth_sqpn, 1); |
b11a4f9c HE |
1106 | qp->flags |= MLX5_IB_QP_SQPN_QP1; |
1107 | } | |
1108 | ||
34f4c955 GL |
1109 | mlx5_fill_page_frag_array(&qp->buf, |
1110 | (__be64 *)MLX5_ADDR_OF(create_qp_in, | |
1111 | *in, pas)); | |
e126ba97 | 1112 | |
9603b61d | 1113 | err = mlx5_db_alloc(dev->mdev, &qp->db); |
e126ba97 EC |
1114 | if (err) { |
1115 | mlx5_ib_dbg(dev, "err %d\n", err); | |
1116 | goto err_free; | |
1117 | } | |
1118 | ||
b5883008 LD |
1119 | qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt, |
1120 | sizeof(*qp->sq.wrid), GFP_KERNEL); | |
1121 | qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt, | |
1122 | sizeof(*qp->sq.wr_data), GFP_KERNEL); | |
1123 | qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt, | |
1124 | sizeof(*qp->rq.wrid), GFP_KERNEL); | |
1125 | qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt, | |
1126 | sizeof(*qp->sq.w_list), GFP_KERNEL); | |
1127 | qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt, | |
1128 | sizeof(*qp->sq.wqe_head), GFP_KERNEL); | |
e126ba97 EC |
1129 | |
1130 | if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid || | |
1131 | !qp->sq.w_list || !qp->sq.wqe_head) { | |
1132 | err = -ENOMEM; | |
1133 | goto err_wrid; | |
1134 | } | |
1135 | qp->create_type = MLX5_QP_KERNEL; | |
1136 | ||
1137 | return 0; | |
1138 | ||
1139 | err_wrid: | |
b5883008 LD |
1140 | kvfree(qp->sq.wqe_head); |
1141 | kvfree(qp->sq.w_list); | |
1142 | kvfree(qp->sq.wrid); | |
1143 | kvfree(qp->sq.wr_data); | |
1144 | kvfree(qp->rq.wrid); | |
f4044dac | 1145 | mlx5_db_free(dev->mdev, &qp->db); |
e126ba97 EC |
1146 | |
1147 | err_free: | |
479163f4 | 1148 | kvfree(*in); |
e126ba97 EC |
1149 | |
1150 | err_buf: | |
34f4c955 | 1151 | mlx5_frag_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1152 | return err; |
1153 | } | |
1154 | ||
1155 | static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) | |
1156 | { | |
b5883008 LD |
1157 | kvfree(qp->sq.wqe_head); |
1158 | kvfree(qp->sq.w_list); | |
1159 | kvfree(qp->sq.wrid); | |
1160 | kvfree(qp->sq.wr_data); | |
1161 | kvfree(qp->rq.wrid); | |
f4044dac | 1162 | mlx5_db_free(dev->mdev, &qp->db); |
34f4c955 | 1163 | mlx5_frag_buf_free(dev->mdev, &qp->buf); |
e126ba97 EC |
1164 | } |
1165 | ||
09a7d9ec | 1166 | static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr) |
e126ba97 EC |
1167 | { |
1168 | if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) || | |
c32a4f29 | 1169 | (attr->qp_type == MLX5_IB_QPT_DCI) || |
e126ba97 | 1170 | (attr->qp_type == IB_QPT_XRC_INI)) |
09a7d9ec | 1171 | return MLX5_SRQ_RQ; |
e126ba97 | 1172 | else if (!qp->has_rq) |
09a7d9ec | 1173 | return MLX5_ZERO_LEN_RQ; |
e126ba97 | 1174 | else |
09a7d9ec | 1175 | return MLX5_NON_ZERO_RQ; |
e126ba97 EC |
1176 | } |
1177 | ||
1178 | static int is_connected(enum ib_qp_type qp_type) | |
1179 | { | |
5d6ff1ba YC |
1180 | if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC || |
1181 | qp_type == MLX5_IB_QPT_DCI) | |
e126ba97 EC |
1182 | return 1; |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
0fb2ed66 | 1187 | static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev, |
c2e53b2c | 1188 | struct mlx5_ib_qp *qp, |
1cd6dbd3 YH |
1189 | struct mlx5_ib_sq *sq, u32 tdn, |
1190 | struct ib_pd *pd) | |
0fb2ed66 | 1191 | { |
c4f287c4 | 1192 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
0fb2ed66 | 1193 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
1194 | ||
1cd6dbd3 | 1195 | MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1196 | MLX5_SET(tisc, tisc, transport_domain, tdn); |
c2e53b2c YH |
1197 | if (qp->flags & MLX5_IB_QP_UNDERLAY) |
1198 | MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn); | |
1199 | ||
0fb2ed66 | 1200 | return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn); |
1201 | } | |
1202 | ||
1203 | static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev, | |
1cd6dbd3 | 1204 | struct mlx5_ib_sq *sq, struct ib_pd *pd) |
0fb2ed66 | 1205 | { |
1cd6dbd3 | 1206 | mlx5_cmd_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid); |
0fb2ed66 | 1207 | } |
1208 | ||
b96c9dde MB |
1209 | static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev, |
1210 | struct mlx5_ib_sq *sq) | |
1211 | { | |
1212 | if (sq->flow_rule) | |
1213 | mlx5_del_flow_rules(sq->flow_rule); | |
1214 | } | |
1215 | ||
0fb2ed66 | 1216 | static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev, |
b0ea0fa5 | 1217 | struct ib_udata *udata, |
0fb2ed66 | 1218 | struct mlx5_ib_sq *sq, void *qpin, |
1219 | struct ib_pd *pd) | |
1220 | { | |
1221 | struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer; | |
1222 | __be64 *pas; | |
1223 | void *in; | |
1224 | void *sqc; | |
1225 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
1226 | void *wq; | |
1227 | int inlen; | |
1228 | int err; | |
1229 | int page_shift = 0; | |
1230 | int npages; | |
1231 | int ncont = 0; | |
1232 | u32 offset = 0; | |
1233 | ||
b0ea0fa5 JG |
1234 | err = mlx5_ib_umem_get(dev, udata, ubuffer->buf_addr, ubuffer->buf_size, |
1235 | &sq->ubuffer.umem, &npages, &page_shift, &ncont, | |
1236 | &offset); | |
0fb2ed66 | 1237 | if (err) |
1238 | return err; | |
1239 | ||
1240 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont; | |
1b9a07ee | 1241 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1242 | if (!in) { |
1243 | err = -ENOMEM; | |
1244 | goto err_umem; | |
1245 | } | |
1246 | ||
c14003f0 | 1247 | MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1248 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); |
1249 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); | |
795b609c BW |
1250 | if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) |
1251 | MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1); | |
0fb2ed66 | 1252 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
1253 | MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1254 | MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd)); | |
1255 | MLX5_SET(sqc, sqc, tis_lst_sz, 1); | |
1256 | MLX5_SET(sqc, sqc, tis_num_0, sq->tisn); | |
96dc3fc5 NO |
1257 | if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && |
1258 | MLX5_CAP_ETH(dev->mdev, swp)) | |
1259 | MLX5_SET(sqc, sqc, allow_swp, 1); | |
0fb2ed66 | 1260 | |
1261 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1262 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
1263 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1264 | MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page)); | |
1265 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1266 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1267 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size)); | |
1268 | MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT); | |
1269 | MLX5_SET(wq, wq, page_offset, offset); | |
1270 | ||
1271 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1272 | mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0); | |
1273 | ||
1274 | err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp); | |
1275 | ||
1276 | kvfree(in); | |
1277 | ||
1278 | if (err) | |
1279 | goto err_umem; | |
1280 | ||
b96c9dde MB |
1281 | err = create_flow_rule_vport_sq(dev, sq); |
1282 | if (err) | |
1283 | goto err_flow; | |
1284 | ||
0fb2ed66 | 1285 | return 0; |
1286 | ||
b96c9dde MB |
1287 | err_flow: |
1288 | mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); | |
1289 | ||
0fb2ed66 | 1290 | err_umem: |
1291 | ib_umem_release(sq->ubuffer.umem); | |
1292 | sq->ubuffer.umem = NULL; | |
1293 | ||
1294 | return err; | |
1295 | } | |
1296 | ||
1297 | static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev, | |
1298 | struct mlx5_ib_sq *sq) | |
1299 | { | |
b96c9dde | 1300 | destroy_flow_rule_vport_sq(dev, sq); |
0fb2ed66 | 1301 | mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp); |
1302 | ib_umem_release(sq->ubuffer.umem); | |
1303 | } | |
1304 | ||
2c292dbb | 1305 | static size_t get_rq_pas_size(void *qpc) |
0fb2ed66 | 1306 | { |
1307 | u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12; | |
1308 | u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride); | |
1309 | u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size); | |
1310 | u32 page_offset = MLX5_GET(qpc, qpc, page_offset); | |
1311 | u32 po_quanta = 1 << (log_page_size - 6); | |
1312 | u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride); | |
1313 | u32 page_size = 1 << log_page_size; | |
1314 | u32 rq_sz_po = rq_sz + (page_offset * po_quanta); | |
1315 | u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size; | |
1316 | ||
1317 | return rq_num_pas * sizeof(u64); | |
1318 | } | |
1319 | ||
1320 | static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
2c292dbb | 1321 | struct mlx5_ib_rq *rq, void *qpin, |
34d57585 | 1322 | size_t qpinlen, struct ib_pd *pd) |
0fb2ed66 | 1323 | { |
358e42ea | 1324 | struct mlx5_ib_qp *mqp = rq->base.container_mibqp; |
0fb2ed66 | 1325 | __be64 *pas; |
1326 | __be64 *qp_pas; | |
1327 | void *in; | |
1328 | void *rqc; | |
1329 | void *wq; | |
1330 | void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc); | |
2c292dbb BP |
1331 | size_t rq_pas_size = get_rq_pas_size(qpc); |
1332 | size_t inlen; | |
0fb2ed66 | 1333 | int err; |
2c292dbb BP |
1334 | |
1335 | if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas)) | |
1336 | return -EINVAL; | |
0fb2ed66 | 1337 | |
1338 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size; | |
1b9a07ee | 1339 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1340 | if (!in) |
1341 | return -ENOMEM; | |
1342 | ||
34d57585 | 1343 | MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1344 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); |
e4cc4fa7 NO |
1345 | if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING)) |
1346 | MLX5_SET(rqc, rqc, vsd, 1); | |
0fb2ed66 | 1347 | MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); |
1348 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
1349 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
1350 | MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index)); | |
1351 | MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv)); | |
1352 | ||
358e42ea MD |
1353 | if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS) |
1354 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
1355 | ||
0fb2ed66 | 1356 | wq = MLX5_ADDR_OF(rqc, rqc, wq); |
1357 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
1358 | if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING) |
1359 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
0fb2ed66 | 1360 | MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset)); |
1361 | MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd)); | |
1362 | MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr)); | |
1363 | MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4); | |
1364 | MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size)); | |
1365 | MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size)); | |
1366 | ||
1367 | pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); | |
1368 | qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas); | |
1369 | memcpy(pas, qp_pas, rq_pas_size); | |
1370 | ||
1371 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp); | |
1372 | ||
1373 | kvfree(in); | |
1374 | ||
1375 | return err; | |
1376 | } | |
1377 | ||
1378 | static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev, | |
1379 | struct mlx5_ib_rq *rq) | |
1380 | { | |
1381 | mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp); | |
1382 | } | |
1383 | ||
f95ef6cb MG |
1384 | static bool tunnel_offload_supported(struct mlx5_core_dev *dev) |
1385 | { | |
1386 | return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) || | |
1387 | MLX5_CAP_ETH(dev, tunnel_stateless_gre) || | |
1388 | MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx)); | |
1389 | } | |
1390 | ||
0042f9e4 MB |
1391 | static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev, |
1392 | struct mlx5_ib_rq *rq, | |
443c1cf9 YH |
1393 | u32 qp_flags_en, |
1394 | struct ib_pd *pd) | |
0042f9e4 MB |
1395 | { |
1396 | if (qp_flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
1397 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) | |
1398 | mlx5_ib_disable_lb(dev, false, true); | |
443c1cf9 | 1399 | mlx5_cmd_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid); |
0042f9e4 MB |
1400 | } |
1401 | ||
0fb2ed66 | 1402 | static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev, |
f95ef6cb | 1403 | struct mlx5_ib_rq *rq, u32 tdn, |
443c1cf9 YH |
1404 | u32 *qp_flags_en, |
1405 | struct ib_pd *pd) | |
0fb2ed66 | 1406 | { |
175edba8 | 1407 | u8 lb_flag = 0; |
0fb2ed66 | 1408 | u32 *in; |
1409 | void *tirc; | |
1410 | int inlen; | |
1411 | int err; | |
1412 | ||
1413 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 1414 | in = kvzalloc(inlen, GFP_KERNEL); |
0fb2ed66 | 1415 | if (!in) |
1416 | return -ENOMEM; | |
1417 | ||
443c1cf9 | 1418 | MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); |
0fb2ed66 | 1419 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
1420 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); | |
1421 | MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn); | |
1422 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
175edba8 | 1423 | if (*qp_flags_en & MLX5_QP_FLAG_TUNNEL_OFFLOADS) |
f95ef6cb | 1424 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); |
0fb2ed66 | 1425 | |
175edba8 MB |
1426 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) |
1427 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1428 | ||
1429 | if (*qp_flags_en & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) | |
1430 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1431 | ||
1432 | if (dev->rep) { | |
1433 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1434 | *qp_flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1435 | } | |
1436 | ||
1437 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); | |
ec9c2fb8 | 1438 | |
0fb2ed66 | 1439 | err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn); |
1440 | ||
0042f9e4 MB |
1441 | if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { |
1442 | err = mlx5_ib_enable_lb(dev, false, true); | |
1443 | ||
1444 | if (err) | |
443c1cf9 | 1445 | destroy_raw_packet_qp_tir(dev, rq, 0, pd); |
0042f9e4 | 1446 | } |
0fb2ed66 | 1447 | kvfree(in); |
1448 | ||
1449 | return err; | |
1450 | } | |
1451 | ||
0fb2ed66 | 1452 | static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
2c292dbb | 1453 | u32 *in, size_t inlen, |
7f72052c YH |
1454 | struct ib_pd *pd, |
1455 | struct ib_udata *udata, | |
1456 | struct mlx5_ib_create_qp_resp *resp) | |
0fb2ed66 | 1457 | { |
1458 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1459 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1460 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
89944450 SR |
1461 | struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( |
1462 | udata, struct mlx5_ib_ucontext, ibucontext); | |
0fb2ed66 | 1463 | int err; |
1464 | u32 tdn = mucontext->tdn; | |
7f72052c | 1465 | u16 uid = to_mpd(pd)->uid; |
0fb2ed66 | 1466 | |
1467 | if (qp->sq.wqe_cnt) { | |
1cd6dbd3 | 1468 | err = create_raw_packet_qp_tis(dev, qp, sq, tdn, pd); |
0fb2ed66 | 1469 | if (err) |
1470 | return err; | |
1471 | ||
b0ea0fa5 | 1472 | err = create_raw_packet_qp_sq(dev, udata, sq, in, pd); |
0fb2ed66 | 1473 | if (err) |
1474 | goto err_destroy_tis; | |
1475 | ||
7f72052c YH |
1476 | if (uid) { |
1477 | resp->tisn = sq->tisn; | |
1478 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TISN; | |
1479 | resp->sqn = sq->base.mqp.qpn; | |
1480 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_SQN; | |
1481 | } | |
1482 | ||
0fb2ed66 | 1483 | sq->base.container_mibqp = qp; |
1d31e9c0 | 1484 | sq->base.mqp.event = mlx5_ib_qp_event; |
0fb2ed66 | 1485 | } |
1486 | ||
1487 | if (qp->rq.wqe_cnt) { | |
358e42ea MD |
1488 | rq->base.container_mibqp = qp; |
1489 | ||
e4cc4fa7 NO |
1490 | if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING) |
1491 | rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING; | |
b1383aa6 NO |
1492 | if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING) |
1493 | rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING; | |
34d57585 | 1494 | err = create_raw_packet_qp_rq(dev, rq, in, inlen, pd); |
0fb2ed66 | 1495 | if (err) |
1496 | goto err_destroy_sq; | |
1497 | ||
443c1cf9 | 1498 | err = create_raw_packet_qp_tir(dev, rq, tdn, &qp->flags_en, pd); |
0fb2ed66 | 1499 | if (err) |
1500 | goto err_destroy_rq; | |
7f72052c YH |
1501 | |
1502 | if (uid) { | |
1503 | resp->rqn = rq->base.mqp.qpn; | |
1504 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_RQN; | |
1505 | resp->tirn = rq->tirn; | |
1506 | resp->comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; | |
1507 | } | |
0fb2ed66 | 1508 | } |
1509 | ||
1510 | qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn : | |
1511 | rq->base.mqp.qpn; | |
7f72052c YH |
1512 | err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp))); |
1513 | if (err) | |
1514 | goto err_destroy_tir; | |
0fb2ed66 | 1515 | |
1516 | return 0; | |
1517 | ||
7f72052c YH |
1518 | err_destroy_tir: |
1519 | destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, pd); | |
0fb2ed66 | 1520 | err_destroy_rq: |
1521 | destroy_raw_packet_qp_rq(dev, rq); | |
1522 | err_destroy_sq: | |
1523 | if (!qp->sq.wqe_cnt) | |
1524 | return err; | |
1525 | destroy_raw_packet_qp_sq(dev, sq); | |
1526 | err_destroy_tis: | |
1cd6dbd3 | 1527 | destroy_raw_packet_qp_tis(dev, sq, pd); |
0fb2ed66 | 1528 | |
1529 | return err; | |
1530 | } | |
1531 | ||
1532 | static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev, | |
1533 | struct mlx5_ib_qp *qp) | |
1534 | { | |
1535 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
1536 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1537 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1538 | ||
1539 | if (qp->rq.wqe_cnt) { | |
443c1cf9 | 1540 | destroy_raw_packet_qp_tir(dev, rq, qp->flags_en, qp->ibqp.pd); |
0fb2ed66 | 1541 | destroy_raw_packet_qp_rq(dev, rq); |
1542 | } | |
1543 | ||
1544 | if (qp->sq.wqe_cnt) { | |
1545 | destroy_raw_packet_qp_sq(dev, sq); | |
1cd6dbd3 | 1546 | destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd); |
0fb2ed66 | 1547 | } |
1548 | } | |
1549 | ||
1550 | static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp, | |
1551 | struct mlx5_ib_raw_packet_qp *raw_packet_qp) | |
1552 | { | |
1553 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
1554 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
1555 | ||
1556 | sq->sq = &qp->sq; | |
1557 | rq->rq = &qp->rq; | |
1558 | sq->doorbell = &qp->db; | |
1559 | rq->doorbell = &qp->db; | |
1560 | } | |
1561 | ||
28d61370 YH |
1562 | static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) |
1563 | { | |
0042f9e4 MB |
1564 | if (qp->flags_en & (MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | |
1565 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) | |
1566 | mlx5_ib_disable_lb(dev, false, true); | |
443c1cf9 YH |
1567 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, |
1568 | to_mpd(qp->ibqp.pd)->uid); | |
28d61370 YH |
1569 | } |
1570 | ||
1571 | static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
1572 | struct ib_pd *pd, | |
1573 | struct ib_qp_init_attr *init_attr, | |
1574 | struct ib_udata *udata) | |
1575 | { | |
89944450 SR |
1576 | struct mlx5_ib_ucontext *mucontext = rdma_udata_to_drv_context( |
1577 | udata, struct mlx5_ib_ucontext, ibucontext); | |
28d61370 YH |
1578 | struct mlx5_ib_create_qp_resp resp = {}; |
1579 | int inlen; | |
1580 | int err; | |
1581 | u32 *in; | |
1582 | void *tirc; | |
1583 | void *hfso; | |
1584 | u32 selected_fields = 0; | |
2d93fc85 | 1585 | u32 outer_l4; |
28d61370 YH |
1586 | size_t min_resp_len; |
1587 | u32 tdn = mucontext->tdn; | |
1588 | struct mlx5_ib_create_qp_rss ucmd = {}; | |
1589 | size_t required_cmd_sz; | |
175edba8 | 1590 | u8 lb_flag = 0; |
28d61370 YH |
1591 | |
1592 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) | |
1593 | return -EOPNOTSUPP; | |
1594 | ||
1595 | if (init_attr->create_flags || init_attr->send_cq) | |
1596 | return -EINVAL; | |
1597 | ||
2f5ff264 | 1598 | min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index); |
28d61370 YH |
1599 | if (udata->outlen < min_resp_len) |
1600 | return -EINVAL; | |
1601 | ||
f95ef6cb | 1602 | required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags); |
28d61370 YH |
1603 | if (udata->inlen < required_cmd_sz) { |
1604 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
1605 | return -EINVAL; | |
1606 | } | |
1607 | ||
1608 | if (udata->inlen > sizeof(ucmd) && | |
1609 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
1610 | udata->inlen - sizeof(ucmd))) { | |
1611 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
1612 | return -EOPNOTSUPP; | |
1613 | } | |
1614 | ||
1615 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
1616 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1617 | return -EFAULT; | |
1618 | } | |
1619 | ||
1620 | if (ucmd.comp_mask) { | |
1621 | mlx5_ib_dbg(dev, "invalid comp mask\n"); | |
1622 | return -EOPNOTSUPP; | |
1623 | } | |
1624 | ||
175edba8 MB |
1625 | if (ucmd.flags & ~(MLX5_QP_FLAG_TUNNEL_OFFLOADS | |
1626 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
1627 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC)) { | |
f95ef6cb MG |
1628 | mlx5_ib_dbg(dev, "invalid flags\n"); |
1629 | return -EOPNOTSUPP; | |
1630 | } | |
1631 | ||
1632 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS && | |
1633 | !tunnel_offload_supported(dev->mdev)) { | |
1634 | mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n"); | |
28d61370 YH |
1635 | return -EOPNOTSUPP; |
1636 | } | |
1637 | ||
309fa347 MG |
1638 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER && |
1639 | !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) { | |
1640 | mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n"); | |
1641 | return -EOPNOTSUPP; | |
1642 | } | |
1643 | ||
175edba8 MB |
1644 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC || dev->rep) { |
1645 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; | |
1646 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
1647 | } | |
1648 | ||
1649 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
1650 | lb_flag |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; | |
1651 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
1652 | } | |
1653 | ||
41d902cb | 1654 | err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); |
28d61370 YH |
1655 | if (err) { |
1656 | mlx5_ib_dbg(dev, "copy failed\n"); | |
1657 | return -EINVAL; | |
1658 | } | |
1659 | ||
1660 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 1661 | in = kvzalloc(inlen, GFP_KERNEL); |
28d61370 YH |
1662 | if (!in) |
1663 | return -ENOMEM; | |
1664 | ||
443c1cf9 | 1665 | MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid); |
28d61370 YH |
1666 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
1667 | MLX5_SET(tirc, tirc, disp_type, | |
1668 | MLX5_TIRC_DISP_TYPE_INDIRECT); | |
1669 | MLX5_SET(tirc, tirc, indirect_table, | |
1670 | init_attr->rwq_ind_tbl->ind_tbl_num); | |
1671 | MLX5_SET(tirc, tirc, transport_domain, tdn); | |
1672 | ||
1673 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
f95ef6cb MG |
1674 | |
1675 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) | |
1676 | MLX5_SET(tirc, tirc, tunneled_offload_en, 1); | |
1677 | ||
175edba8 MB |
1678 | MLX5_SET(tirc, tirc, self_lb_block, lb_flag); |
1679 | ||
309fa347 MG |
1680 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER) |
1681 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner); | |
1682 | else | |
1683 | hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1684 | ||
28d61370 YH |
1685 | switch (ucmd.rx_hash_function) { |
1686 | case MLX5_RX_HASH_FUNC_TOEPLITZ: | |
1687 | { | |
1688 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key); | |
1689 | size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key); | |
1690 | ||
1691 | if (len != ucmd.rx_key_len) { | |
1692 | err = -EINVAL; | |
1693 | goto err; | |
1694 | } | |
1695 | ||
1696 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ); | |
1697 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1698 | memcpy(rss_key, ucmd.rx_hash_key, len); | |
1699 | break; | |
1700 | } | |
1701 | default: | |
1702 | err = -EOPNOTSUPP; | |
1703 | goto err; | |
1704 | } | |
1705 | ||
1706 | if (!ucmd.rx_hash_fields_mask) { | |
1707 | /* special case when this TIR serves as steering entry without hashing */ | |
1708 | if (!init_attr->rwq_ind_tbl->log_ind_tbl_size) | |
1709 | goto create_tir; | |
1710 | err = -EINVAL; | |
1711 | goto err; | |
1712 | } | |
1713 | ||
1714 | if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1715 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) && | |
1716 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1717 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) { | |
1718 | err = -EINVAL; | |
1719 | goto err; | |
1720 | } | |
1721 | ||
1722 | /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */ | |
1723 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1724 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) | |
1725 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1726 | MLX5_L3_PROT_TYPE_IPV4); | |
1727 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) || | |
1728 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1729 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1730 | MLX5_L3_PROT_TYPE_IPV6); | |
1731 | ||
2d93fc85 MB |
1732 | outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || |
1733 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 | | |
1734 | ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1735 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 | | |
1736 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2; | |
1737 | ||
1738 | /* Check that only one l4 protocol is set */ | |
1739 | if (outer_l4 & (outer_l4 - 1)) { | |
28d61370 YH |
1740 | err = -EINVAL; |
1741 | goto err; | |
1742 | } | |
1743 | ||
1744 | /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */ | |
1745 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1746 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) | |
1747 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1748 | MLX5_L4_PROT_TYPE_TCP); | |
1749 | else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) || | |
1750 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1751 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1752 | MLX5_L4_PROT_TYPE_UDP); | |
1753 | ||
1754 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) || | |
1755 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6)) | |
1756 | selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP; | |
1757 | ||
1758 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) || | |
1759 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6)) | |
1760 | selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP; | |
1761 | ||
1762 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) || | |
1763 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP)) | |
1764 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT; | |
1765 | ||
1766 | if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) || | |
1767 | (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) | |
1768 | selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT; | |
1769 | ||
2d93fc85 MB |
1770 | if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) |
1771 | selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI; | |
1772 | ||
28d61370 YH |
1773 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields); |
1774 | ||
1775 | create_tir: | |
1776 | err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn); | |
1777 | ||
0042f9e4 MB |
1778 | if (!err && MLX5_GET(tirc, tirc, self_lb_block)) { |
1779 | err = mlx5_ib_enable_lb(dev, false, true); | |
1780 | ||
1781 | if (err) | |
443c1cf9 YH |
1782 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, |
1783 | to_mpd(pd)->uid); | |
0042f9e4 MB |
1784 | } |
1785 | ||
28d61370 YH |
1786 | if (err) |
1787 | goto err; | |
1788 | ||
7f72052c YH |
1789 | if (mucontext->devx_uid) { |
1790 | resp.comp_mask |= MLX5_IB_CREATE_QP_RESP_MASK_TIRN; | |
1791 | resp.tirn = qp->rss_qp.tirn; | |
1792 | } | |
1793 | ||
1794 | err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); | |
1795 | if (err) | |
1796 | goto err_copy; | |
1797 | ||
28d61370 YH |
1798 | kvfree(in); |
1799 | /* qpn is reserved for that QP */ | |
1800 | qp->trans_qp.base.mqp.qpn = 0; | |
d9f88e5a | 1801 | qp->flags |= MLX5_IB_QP_RSS; |
28d61370 YH |
1802 | return 0; |
1803 | ||
7f72052c YH |
1804 | err_copy: |
1805 | mlx5_cmd_destroy_tir(dev->mdev, qp->rss_qp.tirn, mucontext->devx_uid); | |
28d61370 YH |
1806 | err: |
1807 | kvfree(in); | |
1808 | return err; | |
1809 | } | |
1810 | ||
5d6ff1ba YC |
1811 | static void configure_responder_scat_cqe(struct ib_qp_init_attr *init_attr, |
1812 | void *qpc) | |
1813 | { | |
1814 | int rcqe_sz; | |
1815 | ||
1816 | if (init_attr->qp_type == MLX5_IB_QPT_DCI) | |
1817 | return; | |
1818 | ||
1819 | rcqe_sz = mlx5_ib_get_cqe_size(init_attr->recv_cq); | |
1820 | ||
1821 | if (rcqe_sz == 128) { | |
1822 | MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE); | |
1823 | return; | |
1824 | } | |
1825 | ||
1826 | if (init_attr->qp_type != MLX5_IB_QPT_DCT) | |
1827 | MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE); | |
1828 | } | |
1829 | ||
1830 | static void configure_requester_scat_cqe(struct mlx5_ib_dev *dev, | |
1831 | struct ib_qp_init_attr *init_attr, | |
6f4bc0ea | 1832 | struct mlx5_ib_create_qp *ucmd, |
5d6ff1ba YC |
1833 | void *qpc) |
1834 | { | |
1835 | enum ib_qp_type qpt = init_attr->qp_type; | |
1836 | int scqe_sz; | |
6f4bc0ea | 1837 | bool allow_scat_cqe = 0; |
5d6ff1ba YC |
1838 | |
1839 | if (qpt == IB_QPT_UC || qpt == IB_QPT_UD) | |
1840 | return; | |
1841 | ||
6f4bc0ea YC |
1842 | if (ucmd) |
1843 | allow_scat_cqe = ucmd->flags & MLX5_QP_FLAG_ALLOW_SCATTER_CQE; | |
1844 | ||
1845 | if (!allow_scat_cqe && init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) | |
5d6ff1ba YC |
1846 | return; |
1847 | ||
1848 | scqe_sz = mlx5_ib_get_cqe_size(init_attr->send_cq); | |
1849 | if (scqe_sz == 128) { | |
1850 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE); | |
1851 | return; | |
1852 | } | |
1853 | ||
1854 | if (init_attr->qp_type != MLX5_IB_QPT_DCI || | |
1855 | MLX5_CAP_GEN(dev->mdev, dc_req_scat_data_cqe)) | |
1856 | MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE); | |
1857 | } | |
1858 | ||
a60109dc YC |
1859 | static int atomic_size_to_mode(int size_mask) |
1860 | { | |
1861 | /* driver does not support atomic_size > 256B | |
1862 | * and does not know how to translate bigger sizes | |
1863 | */ | |
1864 | int supported_size_mask = size_mask & 0x1ff; | |
1865 | int log_max_size; | |
1866 | ||
1867 | if (!supported_size_mask) | |
1868 | return -EOPNOTSUPP; | |
1869 | ||
1870 | log_max_size = __fls(supported_size_mask); | |
1871 | ||
1872 | if (log_max_size > 3) | |
1873 | return log_max_size; | |
1874 | ||
1875 | return MLX5_ATOMIC_MODE_8B; | |
1876 | } | |
1877 | ||
1878 | static int get_atomic_mode(struct mlx5_ib_dev *dev, | |
1879 | enum ib_qp_type qp_type) | |
1880 | { | |
1881 | u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); | |
1882 | u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic); | |
1883 | int atomic_mode = -EOPNOTSUPP; | |
1884 | int atomic_size_mask; | |
1885 | ||
1886 | if (!atomic) | |
1887 | return -EOPNOTSUPP; | |
1888 | ||
1889 | if (qp_type == MLX5_IB_QPT_DCT) | |
1890 | atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc); | |
1891 | else | |
1892 | atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); | |
1893 | ||
1894 | if ((atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP) || | |
1895 | (atomic_operations & MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD)) | |
1896 | atomic_mode = atomic_size_to_mode(atomic_size_mask); | |
1897 | ||
1898 | if (atomic_mode <= 0 && | |
1899 | (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP && | |
1900 | atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD)) | |
1901 | atomic_mode = MLX5_ATOMIC_MODE_IB_COMP; | |
1902 | ||
1903 | return atomic_mode; | |
1904 | } | |
1905 | ||
2e43bb31 YC |
1906 | static inline bool check_flags_mask(uint64_t input, uint64_t supported) |
1907 | { | |
1908 | return (input & ~supported) == 0; | |
1909 | } | |
1910 | ||
e126ba97 EC |
1911 | static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd, |
1912 | struct ib_qp_init_attr *init_attr, | |
1913 | struct ib_udata *udata, struct mlx5_ib_qp *qp) | |
1914 | { | |
1915 | struct mlx5_ib_resources *devr = &dev->devr; | |
09a7d9ec | 1916 | int inlen = MLX5_ST_SZ_BYTES(create_qp_in); |
938fe83c | 1917 | struct mlx5_core_dev *mdev = dev->mdev; |
0625b4ba | 1918 | struct mlx5_ib_create_qp_resp resp = {}; |
89944450 SR |
1919 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
1920 | udata, struct mlx5_ib_ucontext, ibucontext); | |
89ea94a7 MG |
1921 | struct mlx5_ib_cq *send_cq; |
1922 | struct mlx5_ib_cq *recv_cq; | |
1923 | unsigned long flags; | |
cfb5e088 | 1924 | u32 uidx = MLX5_IB_DEFAULT_UIDX; |
09a7d9ec SM |
1925 | struct mlx5_ib_create_qp ucmd; |
1926 | struct mlx5_ib_qp_base *base; | |
e7b169f3 | 1927 | int mlx5_st; |
cfb5e088 | 1928 | void *qpc; |
09a7d9ec SM |
1929 | u32 *in; |
1930 | int err; | |
e126ba97 EC |
1931 | |
1932 | mutex_init(&qp->mutex); | |
1933 | spin_lock_init(&qp->sq.lock); | |
1934 | spin_lock_init(&qp->rq.lock); | |
1935 | ||
e7b169f3 NO |
1936 | mlx5_st = to_mlx5_st(init_attr->qp_type); |
1937 | if (mlx5_st < 0) | |
1938 | return -EINVAL; | |
1939 | ||
28d61370 YH |
1940 | if (init_attr->rwq_ind_tbl) { |
1941 | if (!udata) | |
1942 | return -ENOSYS; | |
1943 | ||
1944 | err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata); | |
1945 | return err; | |
1946 | } | |
1947 | ||
f360d88a | 1948 | if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) { |
938fe83c | 1949 | if (!MLX5_CAP_GEN(mdev, block_lb_mc)) { |
f360d88a EC |
1950 | mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n"); |
1951 | return -EINVAL; | |
1952 | } else { | |
1953 | qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK; | |
1954 | } | |
1955 | } | |
1956 | ||
051f2630 LR |
1957 | if (init_attr->create_flags & |
1958 | (IB_QP_CREATE_CROSS_CHANNEL | | |
1959 | IB_QP_CREATE_MANAGED_SEND | | |
1960 | IB_QP_CREATE_MANAGED_RECV)) { | |
1961 | if (!MLX5_CAP_GEN(mdev, cd)) { | |
1962 | mlx5_ib_dbg(dev, "cross-channel isn't supported\n"); | |
1963 | return -EINVAL; | |
1964 | } | |
1965 | if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL) | |
1966 | qp->flags |= MLX5_IB_QP_CROSS_CHANNEL; | |
1967 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND) | |
1968 | qp->flags |= MLX5_IB_QP_MANAGED_SEND; | |
1969 | if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV) | |
1970 | qp->flags |= MLX5_IB_QP_MANAGED_RECV; | |
1971 | } | |
f0313965 ES |
1972 | |
1973 | if (init_attr->qp_type == IB_QPT_UD && | |
1974 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) | |
1975 | if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { | |
1976 | mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n"); | |
1977 | return -EOPNOTSUPP; | |
1978 | } | |
1979 | ||
358e42ea MD |
1980 | if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) { |
1981 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
1982 | mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs"); | |
1983 | return -EOPNOTSUPP; | |
1984 | } | |
1985 | if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) || | |
1986 | !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) { | |
1987 | mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n"); | |
1988 | return -EOPNOTSUPP; | |
1989 | } | |
1990 | qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS; | |
1991 | } | |
1992 | ||
e126ba97 EC |
1993 | if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) |
1994 | qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE; | |
1995 | ||
e4cc4fa7 NO |
1996 | if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) { |
1997 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
1998 | MLX5_CAP_ETH(dev->mdev, vlan_cap)) || | |
1999 | (init_attr->qp_type != IB_QPT_RAW_PACKET)) | |
2000 | return -EOPNOTSUPP; | |
2001 | qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING; | |
2002 | } | |
2003 | ||
e00b64f7 | 2004 | if (udata) { |
e126ba97 EC |
2005 | if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) { |
2006 | mlx5_ib_dbg(dev, "copy failed\n"); | |
2007 | return -EFAULT; | |
2008 | } | |
2009 | ||
2e43bb31 | 2010 | if (!check_flags_mask(ucmd.flags, |
8af526e0 MB |
2011 | MLX5_QP_FLAG_ALLOW_SCATTER_CQE | |
2012 | MLX5_QP_FLAG_BFREG_INDEX | | |
2013 | MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE | | |
2014 | MLX5_QP_FLAG_SCATTER_CQE | | |
2e43bb31 | 2015 | MLX5_QP_FLAG_SIGNATURE | |
8af526e0 MB |
2016 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC | |
2017 | MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC | | |
2018 | MLX5_QP_FLAG_TUNNEL_OFFLOADS | | |
2019 | MLX5_QP_FLAG_TYPE_DCI | | |
2020 | MLX5_QP_FLAG_TYPE_DCT)) | |
2e43bb31 YC |
2021 | return -EINVAL; |
2022 | ||
89944450 | 2023 | err = get_qp_user_index(ucontext, &ucmd, udata->inlen, &uidx); |
cfb5e088 HA |
2024 | if (err) |
2025 | return err; | |
2026 | ||
e126ba97 | 2027 | qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE); |
5d6ff1ba YC |
2028 | if (MLX5_CAP_GEN(dev->mdev, sctr_data_cqe)) |
2029 | qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE); | |
f95ef6cb MG |
2030 | if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) { |
2031 | if (init_attr->qp_type != IB_QPT_RAW_PACKET || | |
2032 | !tunnel_offload_supported(mdev)) { | |
2033 | mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n"); | |
2034 | return -EOPNOTSUPP; | |
2035 | } | |
175edba8 MB |
2036 | qp->flags_en |= MLX5_QP_FLAG_TUNNEL_OFFLOADS; |
2037 | } | |
2038 | ||
2039 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC) { | |
2040 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2041 | mlx5_ib_dbg(dev, "Self-LB UC isn't supported\n"); | |
2042 | return -EOPNOTSUPP; | |
2043 | } | |
2044 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC; | |
2045 | } | |
2046 | ||
2047 | if (ucmd.flags & MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC) { | |
2048 | if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2049 | mlx5_ib_dbg(dev, "Self-LB UM isn't supported\n"); | |
2050 | return -EOPNOTSUPP; | |
2051 | } | |
2052 | qp->flags_en |= MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC; | |
f95ef6cb | 2053 | } |
c2e53b2c | 2054 | |
569c6651 DG |
2055 | if (ucmd.flags & MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE) { |
2056 | if (init_attr->qp_type != IB_QPT_RC || | |
2057 | !MLX5_CAP_GEN(dev->mdev, qp_packet_based)) { | |
2058 | mlx5_ib_dbg(dev, "packet based credit mode isn't supported\n"); | |
2059 | return -EOPNOTSUPP; | |
2060 | } | |
2061 | qp->flags |= MLX5_IB_QP_PACKET_BASED_CREDIT; | |
2062 | } | |
2063 | ||
c2e53b2c YH |
2064 | if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) { |
2065 | if (init_attr->qp_type != IB_QPT_UD || | |
2066 | (MLX5_CAP_GEN(dev->mdev, port_type) != | |
2067 | MLX5_CAP_PORT_TYPE_IB) || | |
2068 | !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) { | |
2069 | mlx5_ib_dbg(dev, "Source QP option isn't supported\n"); | |
2070 | return -EOPNOTSUPP; | |
2071 | } | |
2072 | ||
2073 | qp->flags |= MLX5_IB_QP_UNDERLAY; | |
2074 | qp->underlay_qpn = init_attr->source_qpn; | |
2075 | } | |
e126ba97 EC |
2076 | } else { |
2077 | qp->wq_sig = !!wq_signature; | |
2078 | } | |
2079 | ||
c2e53b2c YH |
2080 | base = (init_attr->qp_type == IB_QPT_RAW_PACKET || |
2081 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
2082 | &qp->raw_packet_qp.rq.base : | |
2083 | &qp->trans_qp.base; | |
2084 | ||
e126ba97 EC |
2085 | qp->has_rq = qp_has_rq(init_attr); |
2086 | err = set_rq_size(dev, &init_attr->cap, qp->has_rq, | |
e00b64f7 | 2087 | qp, udata ? &ucmd : NULL); |
e126ba97 EC |
2088 | if (err) { |
2089 | mlx5_ib_dbg(dev, "err %d\n", err); | |
2090 | return err; | |
2091 | } | |
2092 | ||
2093 | if (pd) { | |
e00b64f7 | 2094 | if (udata) { |
938fe83c SM |
2095 | __u32 max_wqes = |
2096 | 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); | |
e126ba97 EC |
2097 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count); |
2098 | if (ucmd.rq_wqe_shift != qp->rq.wqe_shift || | |
2099 | ucmd.rq_wqe_count != qp->rq.wqe_cnt) { | |
2100 | mlx5_ib_dbg(dev, "invalid rq params\n"); | |
2101 | return -EINVAL; | |
2102 | } | |
938fe83c | 2103 | if (ucmd.sq_wqe_count > max_wqes) { |
e126ba97 | 2104 | mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n", |
938fe83c | 2105 | ucmd.sq_wqe_count, max_wqes); |
e126ba97 EC |
2106 | return -EINVAL; |
2107 | } | |
b11a4f9c HE |
2108 | if (init_attr->create_flags & |
2109 | mlx5_ib_create_qp_sqpn_qp1()) { | |
2110 | mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n"); | |
2111 | return -EINVAL; | |
2112 | } | |
0fb2ed66 | 2113 | err = create_user_qp(dev, pd, qp, udata, init_attr, &in, |
2114 | &resp, &inlen, base); | |
e126ba97 EC |
2115 | if (err) |
2116 | mlx5_ib_dbg(dev, "err %d\n", err); | |
2117 | } else { | |
19098df2 | 2118 | err = create_kernel_qp(dev, init_attr, qp, &in, &inlen, |
2119 | base); | |
e126ba97 EC |
2120 | if (err) |
2121 | mlx5_ib_dbg(dev, "err %d\n", err); | |
e126ba97 EC |
2122 | } |
2123 | ||
2124 | if (err) | |
2125 | return err; | |
2126 | } else { | |
1b9a07ee | 2127 | in = kvzalloc(inlen, GFP_KERNEL); |
e126ba97 EC |
2128 | if (!in) |
2129 | return -ENOMEM; | |
2130 | ||
2131 | qp->create_type = MLX5_QP_EMPTY; | |
2132 | } | |
2133 | ||
2134 | if (is_sqp(init_attr->qp_type)) | |
2135 | qp->port = init_attr->port_num; | |
2136 | ||
09a7d9ec SM |
2137 | qpc = MLX5_ADDR_OF(create_qp_in, in, qpc); |
2138 | ||
e7b169f3 | 2139 | MLX5_SET(qpc, qpc, st, mlx5_st); |
09a7d9ec | 2140 | MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); |
e126ba97 EC |
2141 | |
2142 | if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR) | |
09a7d9ec | 2143 | MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn); |
e126ba97 | 2144 | else |
09a7d9ec SM |
2145 | MLX5_SET(qpc, qpc, latency_sensitive, 1); |
2146 | ||
e126ba97 EC |
2147 | |
2148 | if (qp->wq_sig) | |
09a7d9ec | 2149 | MLX5_SET(qpc, qpc, wq_signature, 1); |
e126ba97 | 2150 | |
f360d88a | 2151 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) |
09a7d9ec | 2152 | MLX5_SET(qpc, qpc, block_lb_mc, 1); |
f360d88a | 2153 | |
051f2630 | 2154 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
09a7d9ec | 2155 | MLX5_SET(qpc, qpc, cd_master, 1); |
051f2630 | 2156 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) |
09a7d9ec | 2157 | MLX5_SET(qpc, qpc, cd_slave_send, 1); |
051f2630 | 2158 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) |
09a7d9ec | 2159 | MLX5_SET(qpc, qpc, cd_slave_receive, 1); |
569c6651 DG |
2160 | if (qp->flags & MLX5_IB_QP_PACKET_BASED_CREDIT) |
2161 | MLX5_SET(qpc, qpc, req_e2e_credit_mode, 1); | |
e126ba97 | 2162 | if (qp->scat_cqe && is_connected(init_attr->qp_type)) { |
5d6ff1ba | 2163 | configure_responder_scat_cqe(init_attr, qpc); |
6f4bc0ea | 2164 | configure_requester_scat_cqe(dev, init_attr, |
e00b64f7 | 2165 | udata ? &ucmd : NULL, |
6f4bc0ea | 2166 | qpc); |
e126ba97 EC |
2167 | } |
2168 | ||
2169 | if (qp->rq.wqe_cnt) { | |
09a7d9ec SM |
2170 | MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4); |
2171 | MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt)); | |
e126ba97 EC |
2172 | } |
2173 | ||
09a7d9ec | 2174 | MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr)); |
e126ba97 | 2175 | |
3fd3307e | 2176 | if (qp->sq.wqe_cnt) { |
09a7d9ec | 2177 | MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt)); |
3fd3307e | 2178 | } else { |
09a7d9ec | 2179 | MLX5_SET(qpc, qpc, no_sq, 1); |
3fd3307e AK |
2180 | if (init_attr->srq && |
2181 | init_attr->srq->srq_type == IB_SRQT_TM) | |
2182 | MLX5_SET(qpc, qpc, offload_type, | |
2183 | MLX5_QPC_OFFLOAD_TYPE_RNDV); | |
2184 | } | |
e126ba97 EC |
2185 | |
2186 | /* Set default resources */ | |
2187 | switch (init_attr->qp_type) { | |
2188 | case IB_QPT_XRC_TGT: | |
09a7d9ec SM |
2189 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
2190 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn); | |
2191 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
2192 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn); | |
e126ba97 EC |
2193 | break; |
2194 | case IB_QPT_XRC_INI: | |
09a7d9ec SM |
2195 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn); |
2196 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); | |
2197 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn); | |
e126ba97 EC |
2198 | break; |
2199 | default: | |
2200 | if (init_attr->srq) { | |
09a7d9ec SM |
2201 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn); |
2202 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn); | |
e126ba97 | 2203 | } else { |
09a7d9ec SM |
2204 | MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn); |
2205 | MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn); | |
e126ba97 EC |
2206 | } |
2207 | } | |
2208 | ||
2209 | if (init_attr->send_cq) | |
09a7d9ec | 2210 | MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn); |
e126ba97 EC |
2211 | |
2212 | if (init_attr->recv_cq) | |
09a7d9ec | 2213 | MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn); |
e126ba97 | 2214 | |
09a7d9ec | 2215 | MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma); |
e126ba97 | 2216 | |
09a7d9ec SM |
2217 | /* 0xffffff means we ask to work with cqe version 0 */ |
2218 | if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) | |
cfb5e088 | 2219 | MLX5_SET(qpc, qpc, user_index, uidx); |
09a7d9ec | 2220 | |
f0313965 ES |
2221 | /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */ |
2222 | if (init_attr->qp_type == IB_QPT_UD && | |
2223 | (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) { | |
f0313965 ES |
2224 | MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1); |
2225 | qp->flags |= MLX5_IB_QP_LSO; | |
2226 | } | |
cfb5e088 | 2227 | |
b1383aa6 NO |
2228 | if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) { |
2229 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
2230 | mlx5_ib_dbg(dev, "scatter end padding is not supported\n"); | |
2231 | err = -EOPNOTSUPP; | |
2232 | goto err; | |
2233 | } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) { | |
2234 | MLX5_SET(qpc, qpc, end_padding_mode, | |
2235 | MLX5_WQ_END_PAD_MODE_ALIGN); | |
2236 | } else { | |
2237 | qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING; | |
2238 | } | |
2239 | } | |
2240 | ||
2c292dbb BP |
2241 | if (inlen < 0) { |
2242 | err = -EINVAL; | |
2243 | goto err; | |
2244 | } | |
2245 | ||
c2e53b2c YH |
2246 | if (init_attr->qp_type == IB_QPT_RAW_PACKET || |
2247 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 2248 | qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr; |
2249 | raw_packet_qp_copy_info(qp, &qp->raw_packet_qp); | |
7f72052c YH |
2250 | err = create_raw_packet_qp(dev, qp, in, inlen, pd, udata, |
2251 | &resp); | |
0fb2ed66 | 2252 | } else { |
2253 | err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen); | |
2254 | } | |
2255 | ||
e126ba97 EC |
2256 | if (err) { |
2257 | mlx5_ib_dbg(dev, "create qp failed\n"); | |
2258 | goto err_create; | |
2259 | } | |
2260 | ||
479163f4 | 2261 | kvfree(in); |
e126ba97 | 2262 | |
19098df2 | 2263 | base->container_mibqp = qp; |
2264 | base->mqp.event = mlx5_ib_qp_event; | |
e126ba97 | 2265 | |
89ea94a7 MG |
2266 | get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq, |
2267 | &send_cq, &recv_cq); | |
2268 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
2269 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
2270 | /* Maintain device to QPs access, needed for further handling via reset | |
2271 | * flow | |
2272 | */ | |
2273 | list_add_tail(&qp->qps_list, &dev->qp_list); | |
2274 | /* Maintain CQ to QPs access, needed for further handling via reset flow | |
2275 | */ | |
2276 | if (send_cq) | |
2277 | list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp); | |
2278 | if (recv_cq) | |
2279 | list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp); | |
2280 | mlx5_ib_unlock_cqs(send_cq, recv_cq); | |
2281 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
2282 | ||
e126ba97 EC |
2283 | return 0; |
2284 | ||
2285 | err_create: | |
2286 | if (qp->create_type == MLX5_QP_USER) | |
b037c29a | 2287 | destroy_qp_user(dev, pd, qp, base); |
e126ba97 EC |
2288 | else if (qp->create_type == MLX5_QP_KERNEL) |
2289 | destroy_qp_kernel(dev, qp); | |
2290 | ||
b1383aa6 | 2291 | err: |
479163f4 | 2292 | kvfree(in); |
e126ba97 EC |
2293 | return err; |
2294 | } | |
2295 | ||
2296 | static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
2297 | __acquires(&send_cq->lock) __acquires(&recv_cq->lock) | |
2298 | { | |
2299 | if (send_cq) { | |
2300 | if (recv_cq) { | |
2301 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
89ea94a7 | 2302 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2303 | spin_lock_nested(&recv_cq->lock, |
2304 | SINGLE_DEPTH_NESTING); | |
2305 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { | |
89ea94a7 | 2306 | spin_lock(&send_cq->lock); |
e126ba97 EC |
2307 | __acquire(&recv_cq->lock); |
2308 | } else { | |
89ea94a7 | 2309 | spin_lock(&recv_cq->lock); |
e126ba97 EC |
2310 | spin_lock_nested(&send_cq->lock, |
2311 | SINGLE_DEPTH_NESTING); | |
2312 | } | |
2313 | } else { | |
89ea94a7 | 2314 | spin_lock(&send_cq->lock); |
6a4f139a | 2315 | __acquire(&recv_cq->lock); |
e126ba97 EC |
2316 | } |
2317 | } else if (recv_cq) { | |
89ea94a7 | 2318 | spin_lock(&recv_cq->lock); |
6a4f139a EC |
2319 | __acquire(&send_cq->lock); |
2320 | } else { | |
2321 | __acquire(&send_cq->lock); | |
2322 | __acquire(&recv_cq->lock); | |
e126ba97 EC |
2323 | } |
2324 | } | |
2325 | ||
2326 | static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq) | |
2327 | __releases(&send_cq->lock) __releases(&recv_cq->lock) | |
2328 | { | |
2329 | if (send_cq) { | |
2330 | if (recv_cq) { | |
2331 | if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { | |
2332 | spin_unlock(&recv_cq->lock); | |
89ea94a7 | 2333 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2334 | } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) { |
2335 | __release(&recv_cq->lock); | |
89ea94a7 | 2336 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2337 | } else { |
2338 | spin_unlock(&send_cq->lock); | |
89ea94a7 | 2339 | spin_unlock(&recv_cq->lock); |
e126ba97 EC |
2340 | } |
2341 | } else { | |
6a4f139a | 2342 | __release(&recv_cq->lock); |
89ea94a7 | 2343 | spin_unlock(&send_cq->lock); |
e126ba97 EC |
2344 | } |
2345 | } else if (recv_cq) { | |
6a4f139a | 2346 | __release(&send_cq->lock); |
89ea94a7 | 2347 | spin_unlock(&recv_cq->lock); |
6a4f139a EC |
2348 | } else { |
2349 | __release(&recv_cq->lock); | |
2350 | __release(&send_cq->lock); | |
e126ba97 EC |
2351 | } |
2352 | } | |
2353 | ||
2354 | static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp) | |
2355 | { | |
2356 | return to_mpd(qp->ibqp.pd); | |
2357 | } | |
2358 | ||
89ea94a7 MG |
2359 | static void get_cqs(enum ib_qp_type qp_type, |
2360 | struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq, | |
e126ba97 EC |
2361 | struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq) |
2362 | { | |
89ea94a7 | 2363 | switch (qp_type) { |
e126ba97 EC |
2364 | case IB_QPT_XRC_TGT: |
2365 | *send_cq = NULL; | |
2366 | *recv_cq = NULL; | |
2367 | break; | |
2368 | case MLX5_IB_QPT_REG_UMR: | |
2369 | case IB_QPT_XRC_INI: | |
89ea94a7 | 2370 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
e126ba97 EC |
2371 | *recv_cq = NULL; |
2372 | break; | |
2373 | ||
2374 | case IB_QPT_SMI: | |
d16e91da | 2375 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 EC |
2376 | case IB_QPT_RC: |
2377 | case IB_QPT_UC: | |
2378 | case IB_QPT_UD: | |
2379 | case IB_QPT_RAW_IPV6: | |
2380 | case IB_QPT_RAW_ETHERTYPE: | |
0fb2ed66 | 2381 | case IB_QPT_RAW_PACKET: |
89ea94a7 MG |
2382 | *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL; |
2383 | *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL; | |
e126ba97 EC |
2384 | break; |
2385 | ||
e126ba97 EC |
2386 | case IB_QPT_MAX: |
2387 | default: | |
2388 | *send_cq = NULL; | |
2389 | *recv_cq = NULL; | |
2390 | break; | |
2391 | } | |
2392 | } | |
2393 | ||
ad5f8e96 | 2394 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
13eab21f AH |
2395 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
2396 | u8 lag_tx_affinity); | |
ad5f8e96 | 2397 | |
e126ba97 EC |
2398 | static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp) |
2399 | { | |
2400 | struct mlx5_ib_cq *send_cq, *recv_cq; | |
c2e53b2c | 2401 | struct mlx5_ib_qp_base *base; |
89ea94a7 | 2402 | unsigned long flags; |
e126ba97 EC |
2403 | int err; |
2404 | ||
28d61370 YH |
2405 | if (qp->ibqp.rwq_ind_tbl) { |
2406 | destroy_rss_raw_qp_tir(dev, qp); | |
2407 | return; | |
2408 | } | |
2409 | ||
c2e53b2c YH |
2410 | base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2411 | qp->flags & MLX5_IB_QP_UNDERLAY) ? | |
0fb2ed66 | 2412 | &qp->raw_packet_qp.rq.base : |
2413 | &qp->trans_qp.base; | |
2414 | ||
6aec21f6 | 2415 | if (qp->state != IB_QPS_RESET) { |
c2e53b2c YH |
2416 | if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET && |
2417 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) { | |
ad5f8e96 | 2418 | err = mlx5_core_qp_modify(dev->mdev, |
1a412fb1 SM |
2419 | MLX5_CMD_OP_2RST_QP, 0, |
2420 | NULL, &base->mqp); | |
ad5f8e96 | 2421 | } else { |
0680efa2 AV |
2422 | struct mlx5_modify_raw_qp_param raw_qp_param = { |
2423 | .operation = MLX5_CMD_OP_2RST_QP | |
2424 | }; | |
2425 | ||
13eab21f | 2426 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0); |
ad5f8e96 | 2427 | } |
2428 | if (err) | |
427c1e7b | 2429 | mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n", |
19098df2 | 2430 | base->mqp.qpn); |
6aec21f6 | 2431 | } |
e126ba97 | 2432 | |
89ea94a7 MG |
2433 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
2434 | &send_cq, &recv_cq); | |
2435 | ||
2436 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
2437 | mlx5_ib_lock_cqs(send_cq, recv_cq); | |
2438 | /* del from lists under both locks above to protect reset flow paths */ | |
2439 | list_del(&qp->qps_list); | |
2440 | if (send_cq) | |
2441 | list_del(&qp->cq_send_list); | |
2442 | ||
2443 | if (recv_cq) | |
2444 | list_del(&qp->cq_recv_list); | |
e126ba97 EC |
2445 | |
2446 | if (qp->create_type == MLX5_QP_KERNEL) { | |
19098df2 | 2447 | __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
2448 | qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL); |
2449 | if (send_cq != recv_cq) | |
19098df2 | 2450 | __mlx5_ib_cq_clean(send_cq, base->mqp.qpn, |
2451 | NULL); | |
e126ba97 | 2452 | } |
89ea94a7 MG |
2453 | mlx5_ib_unlock_cqs(send_cq, recv_cq); |
2454 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
e126ba97 | 2455 | |
c2e53b2c YH |
2456 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
2457 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0fb2ed66 | 2458 | destroy_raw_packet_qp(dev, qp); |
2459 | } else { | |
2460 | err = mlx5_core_destroy_qp(dev->mdev, &base->mqp); | |
2461 | if (err) | |
2462 | mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", | |
2463 | base->mqp.qpn); | |
2464 | } | |
e126ba97 | 2465 | |
e126ba97 EC |
2466 | if (qp->create_type == MLX5_QP_KERNEL) |
2467 | destroy_qp_kernel(dev, qp); | |
2468 | else if (qp->create_type == MLX5_QP_USER) | |
b037c29a | 2469 | destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base); |
e126ba97 EC |
2470 | } |
2471 | ||
2472 | static const char *ib_qp_type_str(enum ib_qp_type type) | |
2473 | { | |
2474 | switch (type) { | |
2475 | case IB_QPT_SMI: | |
2476 | return "IB_QPT_SMI"; | |
2477 | case IB_QPT_GSI: | |
2478 | return "IB_QPT_GSI"; | |
2479 | case IB_QPT_RC: | |
2480 | return "IB_QPT_RC"; | |
2481 | case IB_QPT_UC: | |
2482 | return "IB_QPT_UC"; | |
2483 | case IB_QPT_UD: | |
2484 | return "IB_QPT_UD"; | |
2485 | case IB_QPT_RAW_IPV6: | |
2486 | return "IB_QPT_RAW_IPV6"; | |
2487 | case IB_QPT_RAW_ETHERTYPE: | |
2488 | return "IB_QPT_RAW_ETHERTYPE"; | |
2489 | case IB_QPT_XRC_INI: | |
2490 | return "IB_QPT_XRC_INI"; | |
2491 | case IB_QPT_XRC_TGT: | |
2492 | return "IB_QPT_XRC_TGT"; | |
2493 | case IB_QPT_RAW_PACKET: | |
2494 | return "IB_QPT_RAW_PACKET"; | |
2495 | case MLX5_IB_QPT_REG_UMR: | |
2496 | return "MLX5_IB_QPT_REG_UMR"; | |
b4aaa1f0 MS |
2497 | case IB_QPT_DRIVER: |
2498 | return "IB_QPT_DRIVER"; | |
e126ba97 EC |
2499 | case IB_QPT_MAX: |
2500 | default: | |
2501 | return "Invalid QP type"; | |
2502 | } | |
2503 | } | |
2504 | ||
b4aaa1f0 MS |
2505 | static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd, |
2506 | struct ib_qp_init_attr *attr, | |
89944450 SR |
2507 | struct mlx5_ib_create_qp *ucmd, |
2508 | struct ib_udata *udata) | |
b4aaa1f0 | 2509 | { |
89944450 SR |
2510 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
2511 | udata, struct mlx5_ib_ucontext, ibucontext); | |
b4aaa1f0 MS |
2512 | struct mlx5_ib_qp *qp; |
2513 | int err = 0; | |
2514 | u32 uidx = MLX5_IB_DEFAULT_UIDX; | |
2515 | void *dctc; | |
2516 | ||
2517 | if (!attr->srq || !attr->recv_cq) | |
2518 | return ERR_PTR(-EINVAL); | |
2519 | ||
89944450 | 2520 | err = get_qp_user_index(ucontext, ucmd, sizeof(*ucmd), &uidx); |
b4aaa1f0 MS |
2521 | if (err) |
2522 | return ERR_PTR(err); | |
2523 | ||
2524 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); | |
2525 | if (!qp) | |
2526 | return ERR_PTR(-ENOMEM); | |
2527 | ||
2528 | qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL); | |
2529 | if (!qp->dct.in) { | |
2530 | err = -ENOMEM; | |
2531 | goto err_free; | |
2532 | } | |
2533 | ||
a01a5860 | 2534 | MLX5_SET(create_dct_in, qp->dct.in, uid, to_mpd(pd)->uid); |
b4aaa1f0 | 2535 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); |
776a3906 | 2536 | qp->qp_sub_type = MLX5_IB_QPT_DCT; |
b4aaa1f0 MS |
2537 | MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn); |
2538 | MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn); | |
2539 | MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn); | |
2540 | MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key); | |
2541 | MLX5_SET(dctc, dctc, user_index, uidx); | |
2542 | ||
5d6ff1ba YC |
2543 | if (ucmd->flags & MLX5_QP_FLAG_SCATTER_CQE) |
2544 | configure_responder_scat_cqe(attr, dctc); | |
2545 | ||
b4aaa1f0 MS |
2546 | qp->state = IB_QPS_RESET; |
2547 | ||
2548 | return &qp->ibqp; | |
2549 | err_free: | |
2550 | kfree(qp); | |
2551 | return ERR_PTR(err); | |
2552 | } | |
2553 | ||
2554 | static int set_mlx_qp_type(struct mlx5_ib_dev *dev, | |
2555 | struct ib_qp_init_attr *init_attr, | |
2556 | struct mlx5_ib_create_qp *ucmd, | |
2557 | struct ib_udata *udata) | |
2558 | { | |
2559 | enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI }; | |
2560 | int err; | |
2561 | ||
2562 | if (!udata) | |
2563 | return -EINVAL; | |
2564 | ||
2565 | if (udata->inlen < sizeof(*ucmd)) { | |
2566 | mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n"); | |
2567 | return -EINVAL; | |
2568 | } | |
2569 | err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd)); | |
2570 | if (err) | |
2571 | return err; | |
2572 | ||
2573 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) { | |
2574 | init_attr->qp_type = MLX5_IB_QPT_DCI; | |
2575 | } else { | |
2576 | if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) { | |
2577 | init_attr->qp_type = MLX5_IB_QPT_DCT; | |
2578 | } else { | |
2579 | mlx5_ib_dbg(dev, "Invalid QP flags\n"); | |
2580 | return -EINVAL; | |
2581 | } | |
2582 | } | |
2583 | ||
2584 | if (!MLX5_CAP_GEN(dev->mdev, dct)) { | |
2585 | mlx5_ib_dbg(dev, "DC transport is not supported\n"); | |
2586 | return -EOPNOTSUPP; | |
2587 | } | |
2588 | ||
2589 | return 0; | |
2590 | } | |
2591 | ||
e126ba97 | 2592 | struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, |
b4aaa1f0 | 2593 | struct ib_qp_init_attr *verbs_init_attr, |
e126ba97 EC |
2594 | struct ib_udata *udata) |
2595 | { | |
2596 | struct mlx5_ib_dev *dev; | |
2597 | struct mlx5_ib_qp *qp; | |
2598 | u16 xrcdn = 0; | |
2599 | int err; | |
b4aaa1f0 MS |
2600 | struct ib_qp_init_attr mlx_init_attr; |
2601 | struct ib_qp_init_attr *init_attr = verbs_init_attr; | |
89944450 SR |
2602 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
2603 | udata, struct mlx5_ib_ucontext, ibucontext); | |
e126ba97 EC |
2604 | |
2605 | if (pd) { | |
2606 | dev = to_mdev(pd->device); | |
0fb2ed66 | 2607 | |
2608 | if (init_attr->qp_type == IB_QPT_RAW_PACKET) { | |
89944450 | 2609 | if (!ucontext) { |
0fb2ed66 | 2610 | mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n"); |
2611 | return ERR_PTR(-EINVAL); | |
89944450 | 2612 | } else if (!ucontext->cqe_version) { |
0fb2ed66 | 2613 | mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n"); |
2614 | return ERR_PTR(-EINVAL); | |
2615 | } | |
2616 | } | |
09f16cf5 MD |
2617 | } else { |
2618 | /* being cautious here */ | |
2619 | if (init_attr->qp_type != IB_QPT_XRC_TGT && | |
2620 | init_attr->qp_type != MLX5_IB_QPT_REG_UMR) { | |
2621 | pr_warn("%s: no PD for transport %s\n", __func__, | |
2622 | ib_qp_type_str(init_attr->qp_type)); | |
2623 | return ERR_PTR(-EINVAL); | |
2624 | } | |
2625 | dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device); | |
e126ba97 EC |
2626 | } |
2627 | ||
b4aaa1f0 MS |
2628 | if (init_attr->qp_type == IB_QPT_DRIVER) { |
2629 | struct mlx5_ib_create_qp ucmd; | |
2630 | ||
2631 | init_attr = &mlx_init_attr; | |
2632 | memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr)); | |
2633 | err = set_mlx_qp_type(dev, init_attr, &ucmd, udata); | |
2634 | if (err) | |
2635 | return ERR_PTR(err); | |
c32a4f29 MS |
2636 | |
2637 | if (init_attr->qp_type == MLX5_IB_QPT_DCI) { | |
2638 | if (init_attr->cap.max_recv_wr || | |
2639 | init_attr->cap.max_recv_sge) { | |
2640 | mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n"); | |
2641 | return ERR_PTR(-EINVAL); | |
2642 | } | |
776a3906 | 2643 | } else { |
89944450 | 2644 | return mlx5_ib_create_dct(pd, init_attr, &ucmd, udata); |
c32a4f29 | 2645 | } |
b4aaa1f0 MS |
2646 | } |
2647 | ||
e126ba97 EC |
2648 | switch (init_attr->qp_type) { |
2649 | case IB_QPT_XRC_TGT: | |
2650 | case IB_QPT_XRC_INI: | |
938fe83c | 2651 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) { |
e126ba97 EC |
2652 | mlx5_ib_dbg(dev, "XRC not supported\n"); |
2653 | return ERR_PTR(-ENOSYS); | |
2654 | } | |
2655 | init_attr->recv_cq = NULL; | |
2656 | if (init_attr->qp_type == IB_QPT_XRC_TGT) { | |
2657 | xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; | |
2658 | init_attr->send_cq = NULL; | |
2659 | } | |
2660 | ||
2661 | /* fall through */ | |
0fb2ed66 | 2662 | case IB_QPT_RAW_PACKET: |
e126ba97 EC |
2663 | case IB_QPT_RC: |
2664 | case IB_QPT_UC: | |
2665 | case IB_QPT_UD: | |
2666 | case IB_QPT_SMI: | |
d16e91da | 2667 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 2668 | case MLX5_IB_QPT_REG_UMR: |
c32a4f29 | 2669 | case MLX5_IB_QPT_DCI: |
e126ba97 EC |
2670 | qp = kzalloc(sizeof(*qp), GFP_KERNEL); |
2671 | if (!qp) | |
2672 | return ERR_PTR(-ENOMEM); | |
2673 | ||
2674 | err = create_qp_common(dev, pd, init_attr, udata, qp); | |
2675 | if (err) { | |
2676 | mlx5_ib_dbg(dev, "create_qp_common failed\n"); | |
2677 | kfree(qp); | |
2678 | return ERR_PTR(err); | |
2679 | } | |
2680 | ||
2681 | if (is_qp0(init_attr->qp_type)) | |
2682 | qp->ibqp.qp_num = 0; | |
2683 | else if (is_qp1(init_attr->qp_type)) | |
2684 | qp->ibqp.qp_num = 1; | |
2685 | else | |
19098df2 | 2686 | qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn; |
e126ba97 EC |
2687 | |
2688 | mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n", | |
19098df2 | 2689 | qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn, |
a1ab8402 EC |
2690 | init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1, |
2691 | init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1); | |
e126ba97 | 2692 | |
19098df2 | 2693 | qp->trans_qp.xrcdn = xrcdn; |
e126ba97 EC |
2694 | |
2695 | break; | |
2696 | ||
d16e91da HE |
2697 | case IB_QPT_GSI: |
2698 | return mlx5_ib_gsi_create_qp(pd, init_attr); | |
2699 | ||
e126ba97 EC |
2700 | case IB_QPT_RAW_IPV6: |
2701 | case IB_QPT_RAW_ETHERTYPE: | |
e126ba97 EC |
2702 | case IB_QPT_MAX: |
2703 | default: | |
2704 | mlx5_ib_dbg(dev, "unsupported qp type %d\n", | |
2705 | init_attr->qp_type); | |
2706 | /* Don't support raw QPs */ | |
2707 | return ERR_PTR(-EINVAL); | |
2708 | } | |
2709 | ||
b4aaa1f0 MS |
2710 | if (verbs_init_attr->qp_type == IB_QPT_DRIVER) |
2711 | qp->qp_sub_type = init_attr->qp_type; | |
2712 | ||
e126ba97 EC |
2713 | return &qp->ibqp; |
2714 | } | |
2715 | ||
776a3906 MS |
2716 | static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp) |
2717 | { | |
2718 | struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device); | |
2719 | ||
2720 | if (mqp->state == IB_QPS_RTR) { | |
2721 | int err; | |
2722 | ||
2723 | err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct); | |
2724 | if (err) { | |
2725 | mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err); | |
2726 | return err; | |
2727 | } | |
2728 | } | |
2729 | ||
2730 | kfree(mqp->dct.in); | |
2731 | kfree(mqp); | |
2732 | return 0; | |
2733 | } | |
2734 | ||
e126ba97 EC |
2735 | int mlx5_ib_destroy_qp(struct ib_qp *qp) |
2736 | { | |
2737 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
2738 | struct mlx5_ib_qp *mqp = to_mqp(qp); | |
2739 | ||
d16e91da HE |
2740 | if (unlikely(qp->qp_type == IB_QPT_GSI)) |
2741 | return mlx5_ib_gsi_destroy_qp(qp); | |
2742 | ||
776a3906 MS |
2743 | if (mqp->qp_sub_type == MLX5_IB_QPT_DCT) |
2744 | return mlx5_ib_destroy_dct(mqp); | |
2745 | ||
e126ba97 EC |
2746 | destroy_qp_common(dev, mqp); |
2747 | ||
2748 | kfree(mqp); | |
2749 | ||
2750 | return 0; | |
2751 | } | |
2752 | ||
a60109dc YC |
2753 | static int to_mlx5_access_flags(struct mlx5_ib_qp *qp, |
2754 | const struct ib_qp_attr *attr, | |
bf3b4f06 | 2755 | int attr_mask, __be32 *hw_access_flags_be) |
e126ba97 | 2756 | { |
e126ba97 | 2757 | u8 dest_rd_atomic; |
bf3b4f06 | 2758 | u32 access_flags, hw_access_flags = 0; |
e126ba97 | 2759 | |
a60109dc YC |
2760 | struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device); |
2761 | ||
e126ba97 EC |
2762 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
2763 | dest_rd_atomic = attr->max_dest_rd_atomic; | |
2764 | else | |
19098df2 | 2765 | dest_rd_atomic = qp->trans_qp.resp_depth; |
e126ba97 EC |
2766 | |
2767 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
2768 | access_flags = attr->qp_access_flags; | |
2769 | else | |
19098df2 | 2770 | access_flags = qp->trans_qp.atomic_rd_en; |
e126ba97 EC |
2771 | |
2772 | if (!dest_rd_atomic) | |
2773 | access_flags &= IB_ACCESS_REMOTE_WRITE; | |
2774 | ||
2775 | if (access_flags & IB_ACCESS_REMOTE_READ) | |
bf3b4f06 | 2776 | hw_access_flags |= MLX5_QP_BIT_RRE; |
13f8d9c1 | 2777 | if (access_flags & IB_ACCESS_REMOTE_ATOMIC) { |
a60109dc YC |
2778 | int atomic_mode; |
2779 | ||
2780 | atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type); | |
2781 | if (atomic_mode < 0) | |
2782 | return -EOPNOTSUPP; | |
2783 | ||
bf3b4f06 BVA |
2784 | hw_access_flags |= MLX5_QP_BIT_RAE; |
2785 | hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET; | |
a60109dc YC |
2786 | } |
2787 | ||
e126ba97 | 2788 | if (access_flags & IB_ACCESS_REMOTE_WRITE) |
bf3b4f06 | 2789 | hw_access_flags |= MLX5_QP_BIT_RWE; |
a60109dc | 2790 | |
bf3b4f06 | 2791 | *hw_access_flags_be = cpu_to_be32(hw_access_flags); |
e126ba97 | 2792 | |
a60109dc | 2793 | return 0; |
e126ba97 EC |
2794 | } |
2795 | ||
2796 | enum { | |
2797 | MLX5_PATH_FLAG_FL = 1 << 0, | |
2798 | MLX5_PATH_FLAG_FREE_AR = 1 << 1, | |
2799 | MLX5_PATH_FLAG_COUNTER = 1 << 2, | |
2800 | }; | |
2801 | ||
2802 | static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate) | |
2803 | { | |
4f32ac2e | 2804 | if (rate == IB_RATE_PORT_CURRENT) |
e126ba97 | 2805 | return 0; |
4f32ac2e | 2806 | |
a5a5d199 | 2807 | if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) |
e126ba97 | 2808 | return -EINVAL; |
e126ba97 | 2809 | |
4f32ac2e DG |
2810 | while (rate != IB_RATE_PORT_CURRENT && |
2811 | !(1 << (rate + MLX5_STAT_RATE_OFFSET) & | |
2812 | MLX5_CAP_GEN(dev->mdev, stat_rate_support))) | |
2813 | --rate; | |
2814 | ||
2815 | return rate ? rate + MLX5_STAT_RATE_OFFSET : rate; | |
e126ba97 EC |
2816 | } |
2817 | ||
75850d0b | 2818 | static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev, |
1cd6dbd3 YH |
2819 | struct mlx5_ib_sq *sq, u8 sl, |
2820 | struct ib_pd *pd) | |
75850d0b | 2821 | { |
2822 | void *in; | |
2823 | void *tisc; | |
2824 | int inlen; | |
2825 | int err; | |
2826 | ||
2827 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2828 | in = kvzalloc(inlen, GFP_KERNEL); |
75850d0b | 2829 | if (!in) |
2830 | return -ENOMEM; | |
2831 | ||
2832 | MLX5_SET(modify_tis_in, in, bitmask.prio, 1); | |
1cd6dbd3 | 2833 | MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); |
75850d0b | 2834 | |
2835 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2836 | MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1)); | |
2837 | ||
2838 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2839 | ||
2840 | kvfree(in); | |
2841 | ||
2842 | return err; | |
2843 | } | |
2844 | ||
13eab21f | 2845 | static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev, |
1cd6dbd3 YH |
2846 | struct mlx5_ib_sq *sq, u8 tx_affinity, |
2847 | struct ib_pd *pd) | |
13eab21f AH |
2848 | { |
2849 | void *in; | |
2850 | void *tisc; | |
2851 | int inlen; | |
2852 | int err; | |
2853 | ||
2854 | inlen = MLX5_ST_SZ_BYTES(modify_tis_in); | |
1b9a07ee | 2855 | in = kvzalloc(inlen, GFP_KERNEL); |
13eab21f AH |
2856 | if (!in) |
2857 | return -ENOMEM; | |
2858 | ||
2859 | MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1); | |
1cd6dbd3 | 2860 | MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid); |
13eab21f AH |
2861 | |
2862 | tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx); | |
2863 | MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity); | |
2864 | ||
2865 | err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen); | |
2866 | ||
2867 | kvfree(in); | |
2868 | ||
2869 | return err; | |
2870 | } | |
2871 | ||
75850d0b | 2872 | static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, |
90898850 | 2873 | const struct rdma_ah_attr *ah, |
e126ba97 | 2874 | struct mlx5_qp_path *path, u8 port, int attr_mask, |
f879ee8d AS |
2875 | u32 path_flags, const struct ib_qp_attr *attr, |
2876 | bool alt) | |
e126ba97 | 2877 | { |
d8966fcd | 2878 | const struct ib_global_route *grh = rdma_ah_read_grh(ah); |
e126ba97 | 2879 | int err; |
ed88451e | 2880 | enum ib_gid_type gid_type; |
d8966fcd DC |
2881 | u8 ah_flags = rdma_ah_get_ah_flags(ah); |
2882 | u8 sl = rdma_ah_get_sl(ah); | |
e126ba97 | 2883 | |
e126ba97 | 2884 | if (attr_mask & IB_QP_PKEY_INDEX) |
f879ee8d AS |
2885 | path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index : |
2886 | attr->pkey_index); | |
e126ba97 | 2887 | |
d8966fcd DC |
2888 | if (ah_flags & IB_AH_GRH) { |
2889 | if (grh->sgid_index >= | |
938fe83c | 2890 | dev->mdev->port_caps[port - 1].gid_table_len) { |
f4f01b54 | 2891 | pr_err("sgid_index (%u) too large. max is %d\n", |
d8966fcd | 2892 | grh->sgid_index, |
938fe83c | 2893 | dev->mdev->port_caps[port - 1].gid_table_len); |
f83b4263 EC |
2894 | return -EINVAL; |
2895 | } | |
2811ba51 | 2896 | } |
44c58487 DC |
2897 | |
2898 | if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { | |
d8966fcd | 2899 | if (!(ah_flags & IB_AH_GRH)) |
2811ba51 | 2900 | return -EINVAL; |
47ec3866 | 2901 | |
44c58487 | 2902 | memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac)); |
2b621851 MD |
2903 | if (qp->ibqp.qp_type == IB_QPT_RC || |
2904 | qp->ibqp.qp_type == IB_QPT_UC || | |
2905 | qp->ibqp.qp_type == IB_QPT_XRC_INI || | |
2906 | qp->ibqp.qp_type == IB_QPT_XRC_TGT) | |
47ec3866 PP |
2907 | path->udp_sport = |
2908 | mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr); | |
d8966fcd | 2909 | path->dci_cfi_prio_sl = (sl & 0x7) << 4; |
47ec3866 | 2910 | gid_type = ah->grh.sgid_attr->gid_type; |
ed88451e | 2911 | if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) |
d8966fcd | 2912 | path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f; |
2811ba51 | 2913 | } else { |
d3ae2bde NO |
2914 | path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0; |
2915 | path->fl_free_ar |= | |
2916 | (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0; | |
d8966fcd DC |
2917 | path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); |
2918 | path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f; | |
2919 | if (ah_flags & IB_AH_GRH) | |
2811ba51 | 2920 | path->grh_mlid |= 1 << 7; |
d8966fcd | 2921 | path->dci_cfi_prio_sl = sl & 0xf; |
2811ba51 AS |
2922 | } |
2923 | ||
d8966fcd DC |
2924 | if (ah_flags & IB_AH_GRH) { |
2925 | path->mgid_index = grh->sgid_index; | |
2926 | path->hop_limit = grh->hop_limit; | |
e126ba97 | 2927 | path->tclass_flowlabel = |
d8966fcd DC |
2928 | cpu_to_be32((grh->traffic_class << 20) | |
2929 | (grh->flow_label)); | |
2930 | memcpy(path->rgid, grh->dgid.raw, 16); | |
e126ba97 EC |
2931 | } |
2932 | ||
d8966fcd | 2933 | err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah)); |
e126ba97 EC |
2934 | if (err < 0) |
2935 | return err; | |
2936 | path->static_rate = err; | |
2937 | path->port = port; | |
2938 | ||
e126ba97 | 2939 | if (attr_mask & IB_QP_TIMEOUT) |
f879ee8d | 2940 | path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3; |
e126ba97 | 2941 | |
75850d0b | 2942 | if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt) |
2943 | return modify_raw_packet_eth_prio(dev->mdev, | |
2944 | &qp->raw_packet_qp.sq, | |
1cd6dbd3 | 2945 | sl & 0xf, qp->ibqp.pd); |
75850d0b | 2946 | |
e126ba97 EC |
2947 | return 0; |
2948 | } | |
2949 | ||
2950 | static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = { | |
2951 | [MLX5_QP_STATE_INIT] = { | |
2952 | [MLX5_QP_STATE_INIT] = { | |
2953 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
2954 | MLX5_QP_OPTPAR_RAE | | |
2955 | MLX5_QP_OPTPAR_RWE | | |
2956 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
2957 | MLX5_QP_OPTPAR_PRI_PORT, | |
2958 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | | |
2959 | MLX5_QP_OPTPAR_PKEY_INDEX | | |
2960 | MLX5_QP_OPTPAR_PRI_PORT, | |
2961 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2962 | MLX5_QP_OPTPAR_Q_KEY | | |
2963 | MLX5_QP_OPTPAR_PRI_PORT, | |
2964 | }, | |
2965 | [MLX5_QP_STATE_RTR] = { | |
2966 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2967 | MLX5_QP_OPTPAR_RRE | | |
2968 | MLX5_QP_OPTPAR_RAE | | |
2969 | MLX5_QP_OPTPAR_RWE | | |
2970 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
2971 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2972 | MLX5_QP_OPTPAR_RWE | | |
2973 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
2974 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2975 | MLX5_QP_OPTPAR_Q_KEY, | |
2976 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX | | |
2977 | MLX5_QP_OPTPAR_Q_KEY, | |
a4774e90 EC |
2978 | [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | |
2979 | MLX5_QP_OPTPAR_RRE | | |
2980 | MLX5_QP_OPTPAR_RAE | | |
2981 | MLX5_QP_OPTPAR_RWE | | |
2982 | MLX5_QP_OPTPAR_PKEY_INDEX, | |
e126ba97 EC |
2983 | }, |
2984 | }, | |
2985 | [MLX5_QP_STATE_RTR] = { | |
2986 | [MLX5_QP_STATE_RTS] = { | |
2987 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2988 | MLX5_QP_OPTPAR_RRE | | |
2989 | MLX5_QP_OPTPAR_RAE | | |
2990 | MLX5_QP_OPTPAR_RWE | | |
2991 | MLX5_QP_OPTPAR_PM_STATE | | |
2992 | MLX5_QP_OPTPAR_RNR_TIMEOUT, | |
2993 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH | | |
2994 | MLX5_QP_OPTPAR_RWE | | |
2995 | MLX5_QP_OPTPAR_PM_STATE, | |
2996 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
2997 | }, | |
2998 | }, | |
2999 | [MLX5_QP_STATE_RTS] = { | |
3000 | [MLX5_QP_STATE_RTS] = { | |
3001 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE | | |
3002 | MLX5_QP_OPTPAR_RAE | | |
3003 | MLX5_QP_OPTPAR_RWE | | |
3004 | MLX5_QP_OPTPAR_RNR_TIMEOUT | | |
c2a3431e EC |
3005 | MLX5_QP_OPTPAR_PM_STATE | |
3006 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 | 3007 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE | |
c2a3431e EC |
3008 | MLX5_QP_OPTPAR_PM_STATE | |
3009 | MLX5_QP_OPTPAR_ALT_ADDR_PATH, | |
e126ba97 EC |
3010 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY | |
3011 | MLX5_QP_OPTPAR_SRQN | | |
3012 | MLX5_QP_OPTPAR_CQN_RCV, | |
3013 | }, | |
3014 | }, | |
3015 | [MLX5_QP_STATE_SQER] = { | |
3016 | [MLX5_QP_STATE_RTS] = { | |
3017 | [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY, | |
3018 | [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY, | |
75959f56 | 3019 | [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE, |
a4774e90 EC |
3020 | [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT | |
3021 | MLX5_QP_OPTPAR_RWE | | |
3022 | MLX5_QP_OPTPAR_RAE | | |
3023 | MLX5_QP_OPTPAR_RRE, | |
e126ba97 EC |
3024 | }, |
3025 | }, | |
3026 | }; | |
3027 | ||
3028 | static int ib_nr_to_mlx5_nr(int ib_mask) | |
3029 | { | |
3030 | switch (ib_mask) { | |
3031 | case IB_QP_STATE: | |
3032 | return 0; | |
3033 | case IB_QP_CUR_STATE: | |
3034 | return 0; | |
3035 | case IB_QP_EN_SQD_ASYNC_NOTIFY: | |
3036 | return 0; | |
3037 | case IB_QP_ACCESS_FLAGS: | |
3038 | return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE | | |
3039 | MLX5_QP_OPTPAR_RAE; | |
3040 | case IB_QP_PKEY_INDEX: | |
3041 | return MLX5_QP_OPTPAR_PKEY_INDEX; | |
3042 | case IB_QP_PORT: | |
3043 | return MLX5_QP_OPTPAR_PRI_PORT; | |
3044 | case IB_QP_QKEY: | |
3045 | return MLX5_QP_OPTPAR_Q_KEY; | |
3046 | case IB_QP_AV: | |
3047 | return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH | | |
3048 | MLX5_QP_OPTPAR_PRI_PORT; | |
3049 | case IB_QP_PATH_MTU: | |
3050 | return 0; | |
3051 | case IB_QP_TIMEOUT: | |
3052 | return MLX5_QP_OPTPAR_ACK_TIMEOUT; | |
3053 | case IB_QP_RETRY_CNT: | |
3054 | return MLX5_QP_OPTPAR_RETRY_COUNT; | |
3055 | case IB_QP_RNR_RETRY: | |
3056 | return MLX5_QP_OPTPAR_RNR_RETRY; | |
3057 | case IB_QP_RQ_PSN: | |
3058 | return 0; | |
3059 | case IB_QP_MAX_QP_RD_ATOMIC: | |
3060 | return MLX5_QP_OPTPAR_SRA_MAX; | |
3061 | case IB_QP_ALT_PATH: | |
3062 | return MLX5_QP_OPTPAR_ALT_ADDR_PATH; | |
3063 | case IB_QP_MIN_RNR_TIMER: | |
3064 | return MLX5_QP_OPTPAR_RNR_TIMEOUT; | |
3065 | case IB_QP_SQ_PSN: | |
3066 | return 0; | |
3067 | case IB_QP_MAX_DEST_RD_ATOMIC: | |
3068 | return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE | | |
3069 | MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE; | |
3070 | case IB_QP_PATH_MIG_STATE: | |
3071 | return MLX5_QP_OPTPAR_PM_STATE; | |
3072 | case IB_QP_CAP: | |
3073 | return 0; | |
3074 | case IB_QP_DEST_QPN: | |
3075 | return 0; | |
3076 | } | |
3077 | return 0; | |
3078 | } | |
3079 | ||
3080 | static int ib_mask_to_mlx5_opt(int ib_mask) | |
3081 | { | |
3082 | int result = 0; | |
3083 | int i; | |
3084 | ||
3085 | for (i = 0; i < 8 * sizeof(int); i++) { | |
3086 | if ((1 << i) & ib_mask) | |
3087 | result |= ib_nr_to_mlx5_nr(1 << i); | |
3088 | } | |
3089 | ||
3090 | return result; | |
3091 | } | |
3092 | ||
34d57585 YH |
3093 | static int modify_raw_packet_qp_rq( |
3094 | struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state, | |
3095 | const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) | |
ad5f8e96 | 3096 | { |
3097 | void *in; | |
3098 | void *rqc; | |
3099 | int inlen; | |
3100 | int err; | |
3101 | ||
3102 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 3103 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 3104 | if (!in) |
3105 | return -ENOMEM; | |
3106 | ||
3107 | MLX5_SET(modify_rq_in, in, rq_state, rq->state); | |
34d57585 | 3108 | MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid); |
ad5f8e96 | 3109 | |
3110 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
3111 | MLX5_SET(rqc, rqc, state, new_state); | |
3112 | ||
eb49ab0c AV |
3113 | if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) { |
3114 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { | |
3115 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
23a6964e | 3116 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); |
eb49ab0c AV |
3117 | MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id); |
3118 | } else | |
5a738b5d JG |
3119 | dev_info_once( |
3120 | &dev->ib_dev.dev, | |
3121 | "RAW PACKET QP counters are not supported on current FW\n"); | |
eb49ab0c AV |
3122 | } |
3123 | ||
3124 | err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen); | |
ad5f8e96 | 3125 | if (err) |
3126 | goto out; | |
3127 | ||
3128 | rq->state = new_state; | |
3129 | ||
3130 | out: | |
3131 | kvfree(in); | |
3132 | return err; | |
3133 | } | |
3134 | ||
c14003f0 YH |
3135 | static int modify_raw_packet_qp_sq( |
3136 | struct mlx5_core_dev *dev, struct mlx5_ib_sq *sq, int new_state, | |
3137 | const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd) | |
ad5f8e96 | 3138 | { |
7d29f349 | 3139 | struct mlx5_ib_qp *ibqp = sq->base.container_mibqp; |
61147f39 BW |
3140 | struct mlx5_rate_limit old_rl = ibqp->rl; |
3141 | struct mlx5_rate_limit new_rl = old_rl; | |
3142 | bool new_rate_added = false; | |
7d29f349 | 3143 | u16 rl_index = 0; |
ad5f8e96 | 3144 | void *in; |
3145 | void *sqc; | |
3146 | int inlen; | |
3147 | int err; | |
3148 | ||
3149 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 3150 | in = kvzalloc(inlen, GFP_KERNEL); |
ad5f8e96 | 3151 | if (!in) |
3152 | return -ENOMEM; | |
3153 | ||
c14003f0 | 3154 | MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid); |
ad5f8e96 | 3155 | MLX5_SET(modify_sq_in, in, sq_state, sq->state); |
3156 | ||
3157 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
3158 | MLX5_SET(sqc, sqc, state, new_state); | |
3159 | ||
7d29f349 BW |
3160 | if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) { |
3161 | if (new_state != MLX5_SQC_STATE_RDY) | |
3162 | pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n", | |
3163 | __func__); | |
3164 | else | |
61147f39 | 3165 | new_rl = raw_qp_param->rl; |
7d29f349 BW |
3166 | } |
3167 | ||
61147f39 BW |
3168 | if (!mlx5_rl_are_equal(&old_rl, &new_rl)) { |
3169 | if (new_rl.rate) { | |
3170 | err = mlx5_rl_add_rate(dev, &rl_index, &new_rl); | |
7d29f349 | 3171 | if (err) { |
61147f39 BW |
3172 | pr_err("Failed configuring rate limit(err %d): \ |
3173 | rate %u, max_burst_sz %u, typical_pkt_sz %u\n", | |
3174 | err, new_rl.rate, new_rl.max_burst_sz, | |
3175 | new_rl.typical_pkt_sz); | |
3176 | ||
7d29f349 BW |
3177 | goto out; |
3178 | } | |
61147f39 | 3179 | new_rate_added = true; |
7d29f349 BW |
3180 | } |
3181 | ||
3182 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); | |
61147f39 | 3183 | /* index 0 means no limit */ |
7d29f349 BW |
3184 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index); |
3185 | } | |
3186 | ||
ad5f8e96 | 3187 | err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen); |
7d29f349 BW |
3188 | if (err) { |
3189 | /* Remove new rate from table if failed */ | |
61147f39 BW |
3190 | if (new_rate_added) |
3191 | mlx5_rl_remove_rate(dev, &new_rl); | |
ad5f8e96 | 3192 | goto out; |
7d29f349 BW |
3193 | } |
3194 | ||
3195 | /* Only remove the old rate after new rate was set */ | |
61147f39 BW |
3196 | if ((old_rl.rate && |
3197 | !mlx5_rl_are_equal(&old_rl, &new_rl)) || | |
7d29f349 | 3198 | (new_state != MLX5_SQC_STATE_RDY)) |
61147f39 | 3199 | mlx5_rl_remove_rate(dev, &old_rl); |
ad5f8e96 | 3200 | |
61147f39 | 3201 | ibqp->rl = new_rl; |
ad5f8e96 | 3202 | sq->state = new_state; |
3203 | ||
3204 | out: | |
3205 | kvfree(in); | |
3206 | return err; | |
3207 | } | |
3208 | ||
3209 | static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
13eab21f AH |
3210 | const struct mlx5_modify_raw_qp_param *raw_qp_param, |
3211 | u8 tx_affinity) | |
ad5f8e96 | 3212 | { |
3213 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
3214 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
3215 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
7d29f349 BW |
3216 | int modify_rq = !!qp->rq.wqe_cnt; |
3217 | int modify_sq = !!qp->sq.wqe_cnt; | |
ad5f8e96 | 3218 | int rq_state; |
3219 | int sq_state; | |
3220 | int err; | |
3221 | ||
0680efa2 | 3222 | switch (raw_qp_param->operation) { |
ad5f8e96 | 3223 | case MLX5_CMD_OP_RST2INIT_QP: |
3224 | rq_state = MLX5_RQC_STATE_RDY; | |
3225 | sq_state = MLX5_SQC_STATE_RDY; | |
3226 | break; | |
3227 | case MLX5_CMD_OP_2ERR_QP: | |
3228 | rq_state = MLX5_RQC_STATE_ERR; | |
3229 | sq_state = MLX5_SQC_STATE_ERR; | |
3230 | break; | |
3231 | case MLX5_CMD_OP_2RST_QP: | |
3232 | rq_state = MLX5_RQC_STATE_RST; | |
3233 | sq_state = MLX5_SQC_STATE_RST; | |
3234 | break; | |
ad5f8e96 | 3235 | case MLX5_CMD_OP_RTR2RTS_QP: |
3236 | case MLX5_CMD_OP_RTS2RTS_QP: | |
7d29f349 BW |
3237 | if (raw_qp_param->set_mask == |
3238 | MLX5_RAW_QP_RATE_LIMIT) { | |
3239 | modify_rq = 0; | |
3240 | sq_state = sq->state; | |
3241 | } else { | |
3242 | return raw_qp_param->set_mask ? -EINVAL : 0; | |
3243 | } | |
3244 | break; | |
3245 | case MLX5_CMD_OP_INIT2INIT_QP: | |
3246 | case MLX5_CMD_OP_INIT2RTR_QP: | |
eb49ab0c AV |
3247 | if (raw_qp_param->set_mask) |
3248 | return -EINVAL; | |
3249 | else | |
3250 | return 0; | |
ad5f8e96 | 3251 | default: |
3252 | WARN_ON(1); | |
3253 | return -EINVAL; | |
3254 | } | |
3255 | ||
7d29f349 | 3256 | if (modify_rq) { |
34d57585 YH |
3257 | err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param, |
3258 | qp->ibqp.pd); | |
ad5f8e96 | 3259 | if (err) |
3260 | return err; | |
3261 | } | |
3262 | ||
7d29f349 | 3263 | if (modify_sq) { |
13eab21f AH |
3264 | if (tx_affinity) { |
3265 | err = modify_raw_packet_tx_affinity(dev->mdev, sq, | |
1cd6dbd3 YH |
3266 | tx_affinity, |
3267 | qp->ibqp.pd); | |
13eab21f AH |
3268 | if (err) |
3269 | return err; | |
3270 | } | |
3271 | ||
c14003f0 YH |
3272 | return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, |
3273 | raw_qp_param, qp->ibqp.pd); | |
13eab21f | 3274 | } |
ad5f8e96 | 3275 | |
3276 | return 0; | |
3277 | } | |
3278 | ||
c6a21c38 MD |
3279 | static unsigned int get_tx_affinity(struct mlx5_ib_dev *dev, |
3280 | struct mlx5_ib_pd *pd, | |
3281 | struct mlx5_ib_qp_base *qp_base, | |
89944450 | 3282 | u8 port_num, struct ib_udata *udata) |
c6a21c38 | 3283 | { |
89944450 SR |
3284 | struct mlx5_ib_ucontext *ucontext = rdma_udata_to_drv_context( |
3285 | udata, struct mlx5_ib_ucontext, ibucontext); | |
c6a21c38 MD |
3286 | unsigned int tx_port_affinity; |
3287 | ||
c6a21c38 MD |
3288 | if (ucontext) { |
3289 | tx_port_affinity = (unsigned int)atomic_add_return( | |
3290 | 1, &ucontext->tx_port_affinity) % | |
3291 | MLX5_MAX_PORTS + | |
3292 | 1; | |
3293 | mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x ucontext %p\n", | |
3294 | tx_port_affinity, qp_base->mqp.qpn, ucontext); | |
3295 | } else { | |
3296 | tx_port_affinity = | |
3297 | (unsigned int)atomic_add_return( | |
3298 | 1, &dev->roce[port_num].tx_port_affinity) % | |
3299 | MLX5_MAX_PORTS + | |
3300 | 1; | |
3301 | mlx5_ib_dbg(dev, "Set tx affinity 0x%x to qpn 0x%x\n", | |
3302 | tx_port_affinity, qp_base->mqp.qpn); | |
3303 | } | |
3304 | ||
3305 | return tx_port_affinity; | |
3306 | } | |
3307 | ||
e126ba97 EC |
3308 | static int __mlx5_ib_modify_qp(struct ib_qp *ibqp, |
3309 | const struct ib_qp_attr *attr, int attr_mask, | |
89944450 SR |
3310 | enum ib_qp_state cur_state, |
3311 | enum ib_qp_state new_state, | |
3312 | const struct mlx5_ib_modify_qp *ucmd, | |
3313 | struct ib_udata *udata) | |
e126ba97 | 3314 | { |
427c1e7b | 3315 | static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = { |
3316 | [MLX5_QP_STATE_RST] = { | |
3317 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3318 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3319 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP, | |
3320 | }, | |
3321 | [MLX5_QP_STATE_INIT] = { | |
3322 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3323 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3324 | [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP, | |
3325 | [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP, | |
3326 | }, | |
3327 | [MLX5_QP_STATE_RTR] = { | |
3328 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3329 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3330 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP, | |
3331 | }, | |
3332 | [MLX5_QP_STATE_RTS] = { | |
3333 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3334 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3335 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP, | |
3336 | }, | |
3337 | [MLX5_QP_STATE_SQD] = { | |
3338 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3339 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3340 | }, | |
3341 | [MLX5_QP_STATE_SQER] = { | |
3342 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3343 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3344 | [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP, | |
3345 | }, | |
3346 | [MLX5_QP_STATE_ERR] = { | |
3347 | [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP, | |
3348 | [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP, | |
3349 | } | |
3350 | }; | |
3351 | ||
e126ba97 EC |
3352 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
3353 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
19098df2 | 3354 | struct mlx5_ib_qp_base *base = &qp->trans_qp.base; |
e126ba97 EC |
3355 | struct mlx5_ib_cq *send_cq, *recv_cq; |
3356 | struct mlx5_qp_context *context; | |
e126ba97 | 3357 | struct mlx5_ib_pd *pd; |
eb49ab0c | 3358 | struct mlx5_ib_port *mibport = NULL; |
e126ba97 EC |
3359 | enum mlx5_qp_state mlx5_cur, mlx5_new; |
3360 | enum mlx5_qp_optpar optpar; | |
e126ba97 EC |
3361 | int mlx5_st; |
3362 | int err; | |
427c1e7b | 3363 | u16 op; |
13eab21f | 3364 | u8 tx_affinity = 0; |
e126ba97 | 3365 | |
55de9a77 LR |
3366 | mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ? |
3367 | qp->qp_sub_type : ibqp->qp_type); | |
3368 | if (mlx5_st < 0) | |
3369 | return -EINVAL; | |
3370 | ||
1a412fb1 SM |
3371 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
3372 | if (!context) | |
e126ba97 EC |
3373 | return -ENOMEM; |
3374 | ||
c6a21c38 | 3375 | pd = get_pd(qp); |
55de9a77 | 3376 | context->flags = cpu_to_be32(mlx5_st << 16); |
e126ba97 EC |
3377 | |
3378 | if (!(attr_mask & IB_QP_PATH_MIG_STATE)) { | |
3379 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3380 | } else { | |
3381 | switch (attr->path_mig_state) { | |
3382 | case IB_MIG_MIGRATED: | |
3383 | context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11); | |
3384 | break; | |
3385 | case IB_MIG_REARM: | |
3386 | context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11); | |
3387 | break; | |
3388 | case IB_MIG_ARMED: | |
3389 | context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11); | |
3390 | break; | |
3391 | } | |
3392 | } | |
3393 | ||
13eab21f AH |
3394 | if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { |
3395 | if ((ibqp->qp_type == IB_QPT_RC) || | |
3396 | (ibqp->qp_type == IB_QPT_UD && | |
3397 | !(qp->flags & MLX5_IB_QP_SQPN_QP1)) || | |
3398 | (ibqp->qp_type == IB_QPT_UC) || | |
3399 | (ibqp->qp_type == IB_QPT_RAW_PACKET) || | |
3400 | (ibqp->qp_type == IB_QPT_XRC_INI) || | |
3401 | (ibqp->qp_type == IB_QPT_XRC_TGT)) { | |
7c34ec19 | 3402 | if (dev->lag_active) { |
7fd8aefb | 3403 | u8 p = mlx5_core_native_port_num(dev->mdev); |
89944450 SR |
3404 | tx_affinity = get_tx_affinity(dev, pd, base, p, |
3405 | udata); | |
13eab21f AH |
3406 | context->flags |= cpu_to_be32(tx_affinity << 24); |
3407 | } | |
3408 | } | |
3409 | } | |
3410 | ||
d16e91da | 3411 | if (is_sqp(ibqp->qp_type)) { |
e126ba97 | 3412 | context->mtu_msgmax = (IB_MTU_256 << 5) | 8; |
c2e53b2c YH |
3413 | } else if ((ibqp->qp_type == IB_QPT_UD && |
3414 | !(qp->flags & MLX5_IB_QP_UNDERLAY)) || | |
e126ba97 EC |
3415 | ibqp->qp_type == MLX5_IB_QPT_REG_UMR) { |
3416 | context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; | |
3417 | } else if (attr_mask & IB_QP_PATH_MTU) { | |
3418 | if (attr->path_mtu < IB_MTU_256 || | |
3419 | attr->path_mtu > IB_MTU_4096) { | |
3420 | mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu); | |
3421 | err = -EINVAL; | |
3422 | goto out; | |
3423 | } | |
938fe83c SM |
3424 | context->mtu_msgmax = (attr->path_mtu << 5) | |
3425 | (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg); | |
e126ba97 EC |
3426 | } |
3427 | ||
3428 | if (attr_mask & IB_QP_DEST_QPN) | |
3429 | context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num); | |
3430 | ||
3431 | if (attr_mask & IB_QP_PKEY_INDEX) | |
d3ae2bde | 3432 | context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index); |
e126ba97 EC |
3433 | |
3434 | /* todo implement counter_index functionality */ | |
3435 | ||
3436 | if (is_sqp(ibqp->qp_type)) | |
3437 | context->pri_path.port = qp->port; | |
3438 | ||
3439 | if (attr_mask & IB_QP_PORT) | |
3440 | context->pri_path.port = attr->port_num; | |
3441 | ||
3442 | if (attr_mask & IB_QP_AV) { | |
75850d0b | 3443 | err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path, |
e126ba97 | 3444 | attr_mask & IB_QP_PORT ? attr->port_num : qp->port, |
f879ee8d | 3445 | attr_mask, 0, attr, false); |
e126ba97 EC |
3446 | if (err) |
3447 | goto out; | |
3448 | } | |
3449 | ||
3450 | if (attr_mask & IB_QP_TIMEOUT) | |
3451 | context->pri_path.ackto_lt |= attr->timeout << 3; | |
3452 | ||
3453 | if (attr_mask & IB_QP_ALT_PATH) { | |
75850d0b | 3454 | err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, |
3455 | &context->alt_path, | |
f879ee8d AS |
3456 | attr->alt_port_num, |
3457 | attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT, | |
3458 | 0, attr, true); | |
e126ba97 EC |
3459 | if (err) |
3460 | goto out; | |
3461 | } | |
3462 | ||
89ea94a7 MG |
3463 | get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq, |
3464 | &send_cq, &recv_cq); | |
e126ba97 EC |
3465 | |
3466 | context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn); | |
3467 | context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0; | |
3468 | context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0; | |
3469 | context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28); | |
3470 | ||
3471 | if (attr_mask & IB_QP_RNR_RETRY) | |
3472 | context->params1 |= cpu_to_be32(attr->rnr_retry << 13); | |
3473 | ||
3474 | if (attr_mask & IB_QP_RETRY_CNT) | |
3475 | context->params1 |= cpu_to_be32(attr->retry_cnt << 16); | |
3476 | ||
3477 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | |
3478 | if (attr->max_rd_atomic) | |
3479 | context->params1 |= | |
3480 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); | |
3481 | } | |
3482 | ||
3483 | if (attr_mask & IB_QP_SQ_PSN) | |
3484 | context->next_send_psn = cpu_to_be32(attr->sq_psn); | |
3485 | ||
3486 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { | |
3487 | if (attr->max_dest_rd_atomic) | |
3488 | context->params2 |= | |
3489 | cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); | |
3490 | } | |
3491 | ||
a60109dc | 3492 | if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { |
bf3b4f06 | 3493 | __be32 access_flags; |
a60109dc YC |
3494 | |
3495 | err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags); | |
3496 | if (err) | |
3497 | goto out; | |
3498 | ||
3499 | context->params2 |= access_flags; | |
3500 | } | |
e126ba97 EC |
3501 | |
3502 | if (attr_mask & IB_QP_MIN_RNR_TIMER) | |
3503 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); | |
3504 | ||
3505 | if (attr_mask & IB_QP_RQ_PSN) | |
3506 | context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); | |
3507 | ||
3508 | if (attr_mask & IB_QP_QKEY) | |
3509 | context->qkey = cpu_to_be32(attr->qkey); | |
3510 | ||
3511 | if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) | |
3512 | context->db_rec_addr = cpu_to_be64(qp->db.dma); | |
3513 | ||
0837e86a MB |
3514 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
3515 | u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num : | |
3516 | qp->port) - 1; | |
c2e53b2c YH |
3517 | |
3518 | /* Underlay port should be used - index 0 function per port */ | |
3519 | if (qp->flags & MLX5_IB_QP_UNDERLAY) | |
3520 | port_num = 0; | |
3521 | ||
eb49ab0c | 3522 | mibport = &dev->port[port_num]; |
0837e86a | 3523 | context->qp_counter_set_usr_page |= |
e1f24a79 | 3524 | cpu_to_be32((u32)(mibport->cnts.set_id) << 24); |
0837e86a MB |
3525 | } |
3526 | ||
e126ba97 EC |
3527 | if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) |
3528 | context->sq_crq_size |= cpu_to_be16(1 << 4); | |
3529 | ||
b11a4f9c HE |
3530 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
3531 | context->deth_sqpn = cpu_to_be32(1); | |
e126ba97 EC |
3532 | |
3533 | mlx5_cur = to_mlx5_state(cur_state); | |
3534 | mlx5_new = to_mlx5_state(new_state); | |
e126ba97 | 3535 | |
427c1e7b | 3536 | if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE || |
5d414b17 DC |
3537 | !optab[mlx5_cur][mlx5_new]) { |
3538 | err = -EINVAL; | |
427c1e7b | 3539 | goto out; |
5d414b17 | 3540 | } |
427c1e7b | 3541 | |
3542 | op = optab[mlx5_cur][mlx5_new]; | |
e126ba97 EC |
3543 | optpar = ib_mask_to_mlx5_opt(attr_mask); |
3544 | optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st]; | |
ad5f8e96 | 3545 | |
c2e53b2c YH |
3546 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
3547 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
0680efa2 AV |
3548 | struct mlx5_modify_raw_qp_param raw_qp_param = {}; |
3549 | ||
3550 | raw_qp_param.operation = op; | |
eb49ab0c | 3551 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { |
e1f24a79 | 3552 | raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id; |
eb49ab0c AV |
3553 | raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID; |
3554 | } | |
7d29f349 BW |
3555 | |
3556 | if (attr_mask & IB_QP_RATE_LIMIT) { | |
61147f39 BW |
3557 | raw_qp_param.rl.rate = attr->rate_limit; |
3558 | ||
3559 | if (ucmd->burst_info.max_burst_sz) { | |
3560 | if (attr->rate_limit && | |
3561 | MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) { | |
3562 | raw_qp_param.rl.max_burst_sz = | |
3563 | ucmd->burst_info.max_burst_sz; | |
3564 | } else { | |
3565 | err = -EINVAL; | |
3566 | goto out; | |
3567 | } | |
3568 | } | |
3569 | ||
3570 | if (ucmd->burst_info.typical_pkt_sz) { | |
3571 | if (attr->rate_limit && | |
3572 | MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) { | |
3573 | raw_qp_param.rl.typical_pkt_sz = | |
3574 | ucmd->burst_info.typical_pkt_sz; | |
3575 | } else { | |
3576 | err = -EINVAL; | |
3577 | goto out; | |
3578 | } | |
3579 | } | |
3580 | ||
7d29f349 BW |
3581 | raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT; |
3582 | } | |
3583 | ||
13eab21f | 3584 | err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity); |
0680efa2 | 3585 | } else { |
1a412fb1 | 3586 | err = mlx5_core_qp_modify(dev->mdev, op, optpar, context, |
ad5f8e96 | 3587 | &base->mqp); |
0680efa2 AV |
3588 | } |
3589 | ||
e126ba97 EC |
3590 | if (err) |
3591 | goto out; | |
3592 | ||
3593 | qp->state = new_state; | |
3594 | ||
3595 | if (attr_mask & IB_QP_ACCESS_FLAGS) | |
19098df2 | 3596 | qp->trans_qp.atomic_rd_en = attr->qp_access_flags; |
e126ba97 | 3597 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) |
19098df2 | 3598 | qp->trans_qp.resp_depth = attr->max_dest_rd_atomic; |
e126ba97 EC |
3599 | if (attr_mask & IB_QP_PORT) |
3600 | qp->port = attr->port_num; | |
3601 | if (attr_mask & IB_QP_ALT_PATH) | |
19098df2 | 3602 | qp->trans_qp.alt_port = attr->alt_port_num; |
e126ba97 EC |
3603 | |
3604 | /* | |
3605 | * If we moved a kernel QP to RESET, clean up all old CQ | |
3606 | * entries and reinitialize the QP. | |
3607 | */ | |
75a45982 LR |
3608 | if (new_state == IB_QPS_RESET && |
3609 | !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) { | |
19098df2 | 3610 | mlx5_ib_cq_clean(recv_cq, base->mqp.qpn, |
e126ba97 EC |
3611 | ibqp->srq ? to_msrq(ibqp->srq) : NULL); |
3612 | if (send_cq != recv_cq) | |
19098df2 | 3613 | mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL); |
e126ba97 EC |
3614 | |
3615 | qp->rq.head = 0; | |
3616 | qp->rq.tail = 0; | |
3617 | qp->sq.head = 0; | |
3618 | qp->sq.tail = 0; | |
3619 | qp->sq.cur_post = 0; | |
34f4c955 GL |
3620 | if (qp->sq.wqe_cnt) |
3621 | qp->sq.cur_edge = get_sq_edge(&qp->sq, 0); | |
e126ba97 EC |
3622 | qp->db.db[MLX5_RCV_DBR] = 0; |
3623 | qp->db.db[MLX5_SND_DBR] = 0; | |
3624 | } | |
3625 | ||
3626 | out: | |
1a412fb1 | 3627 | kfree(context); |
e126ba97 EC |
3628 | return err; |
3629 | } | |
3630 | ||
c32a4f29 MS |
3631 | static inline bool is_valid_mask(int mask, int req, int opt) |
3632 | { | |
3633 | if ((mask & req) != req) | |
3634 | return false; | |
3635 | ||
3636 | if (mask & ~(req | opt)) | |
3637 | return false; | |
3638 | ||
3639 | return true; | |
3640 | } | |
3641 | ||
3642 | /* check valid transition for driver QP types | |
3643 | * for now the only QP type that this function supports is DCI | |
3644 | */ | |
3645 | static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state, | |
3646 | enum ib_qp_attr_mask attr_mask) | |
3647 | { | |
3648 | int req = IB_QP_STATE; | |
3649 | int opt = 0; | |
3650 | ||
99ed748e MS |
3651 | if (new_state == IB_QPS_RESET) { |
3652 | return is_valid_mask(attr_mask, req, opt); | |
3653 | } else if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
c32a4f29 MS |
3654 | req |= IB_QP_PKEY_INDEX | IB_QP_PORT; |
3655 | return is_valid_mask(attr_mask, req, opt); | |
3656 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { | |
3657 | opt = IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3658 | return is_valid_mask(attr_mask, req, opt); | |
3659 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3660 | req |= IB_QP_PATH_MTU; | |
5ec0304c | 3661 | opt = IB_QP_PKEY_INDEX | IB_QP_AV; |
c32a4f29 MS |
3662 | return is_valid_mask(attr_mask, req, opt); |
3663 | } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) { | |
3664 | req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY | | |
3665 | IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN; | |
3666 | opt = IB_QP_MIN_RNR_TIMER; | |
3667 | return is_valid_mask(attr_mask, req, opt); | |
3668 | } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) { | |
3669 | opt = IB_QP_MIN_RNR_TIMER; | |
3670 | return is_valid_mask(attr_mask, req, opt); | |
3671 | } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) { | |
3672 | return is_valid_mask(attr_mask, req, opt); | |
3673 | } | |
3674 | return false; | |
3675 | } | |
3676 | ||
776a3906 MS |
3677 | /* mlx5_ib_modify_dct: modify a DCT QP |
3678 | * valid transitions are: | |
3679 | * RESET to INIT: must set access_flags, pkey_index and port | |
3680 | * INIT to RTR : must set min_rnr_timer, tclass, flow_label, | |
3681 | * mtu, gid_index and hop_limit | |
3682 | * Other transitions and attributes are illegal | |
3683 | */ | |
3684 | static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, | |
3685 | int attr_mask, struct ib_udata *udata) | |
3686 | { | |
3687 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
3688 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3689 | enum ib_qp_state cur_state, new_state; | |
3690 | int err = 0; | |
3691 | int required = IB_QP_STATE; | |
3692 | void *dctc; | |
3693 | ||
3694 | if (!(attr_mask & IB_QP_STATE)) | |
3695 | return -EINVAL; | |
3696 | ||
3697 | cur_state = qp->state; | |
3698 | new_state = attr->qp_state; | |
3699 | ||
3700 | dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry); | |
3701 | if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { | |
3702 | required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT; | |
3703 | if (!is_valid_mask(attr_mask, required, 0)) | |
3704 | return -EINVAL; | |
3705 | ||
3706 | if (attr->port_num == 0 || | |
3707 | attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { | |
3708 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", | |
3709 | attr->port_num, dev->num_ports); | |
3710 | return -EINVAL; | |
3711 | } | |
3712 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) | |
3713 | MLX5_SET(dctc, dctc, rre, 1); | |
3714 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) | |
3715 | MLX5_SET(dctc, dctc, rwe, 1); | |
3716 | if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) { | |
a60109dc YC |
3717 | int atomic_mode; |
3718 | ||
3719 | atomic_mode = get_atomic_mode(dev, MLX5_IB_QPT_DCT); | |
3720 | if (atomic_mode < 0) | |
776a3906 | 3721 | return -EOPNOTSUPP; |
a60109dc YC |
3722 | |
3723 | MLX5_SET(dctc, dctc, atomic_mode, atomic_mode); | |
776a3906 | 3724 | MLX5_SET(dctc, dctc, rae, 1); |
776a3906 MS |
3725 | } |
3726 | MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index); | |
3727 | MLX5_SET(dctc, dctc, port, attr->port_num); | |
3728 | MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id); | |
3729 | ||
3730 | } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { | |
3731 | struct mlx5_ib_modify_qp_resp resp = {}; | |
c5ae1954 | 3732 | u32 out[MLX5_ST_SZ_DW(create_dct_out)] = {0}; |
776a3906 MS |
3733 | u32 min_resp_len = offsetof(typeof(resp), dctn) + |
3734 | sizeof(resp.dctn); | |
3735 | ||
3736 | if (udata->outlen < min_resp_len) | |
3737 | return -EINVAL; | |
3738 | resp.response_length = min_resp_len; | |
3739 | ||
3740 | required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU; | |
3741 | if (!is_valid_mask(attr_mask, required, 0)) | |
3742 | return -EINVAL; | |
3743 | MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer); | |
3744 | MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class); | |
3745 | MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label); | |
3746 | MLX5_SET(dctc, dctc, mtu, attr->path_mtu); | |
3747 | MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index); | |
3748 | MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit); | |
3749 | ||
3750 | err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in, | |
c5ae1954 YH |
3751 | MLX5_ST_SZ_BYTES(create_dct_in), out, |
3752 | sizeof(out)); | |
776a3906 MS |
3753 | if (err) |
3754 | return err; | |
3755 | resp.dctn = qp->dct.mdct.mqp.qpn; | |
3756 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
3757 | if (err) { | |
3758 | mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct); | |
3759 | return err; | |
3760 | } | |
3761 | } else { | |
3762 | mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state); | |
3763 | return -EINVAL; | |
3764 | } | |
3765 | if (err) | |
3766 | qp->state = IB_QPS_ERR; | |
3767 | else | |
3768 | qp->state = new_state; | |
3769 | return err; | |
3770 | } | |
3771 | ||
e126ba97 EC |
3772 | int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
3773 | int attr_mask, struct ib_udata *udata) | |
3774 | { | |
3775 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
3776 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
61147f39 | 3777 | struct mlx5_ib_modify_qp ucmd = {}; |
d16e91da | 3778 | enum ib_qp_type qp_type; |
e126ba97 | 3779 | enum ib_qp_state cur_state, new_state; |
61147f39 | 3780 | size_t required_cmd_sz; |
e126ba97 EC |
3781 | int err = -EINVAL; |
3782 | int port; | |
3783 | ||
28d61370 YH |
3784 | if (ibqp->rwq_ind_tbl) |
3785 | return -ENOSYS; | |
3786 | ||
61147f39 BW |
3787 | if (udata && udata->inlen) { |
3788 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + | |
3789 | sizeof(ucmd.reserved); | |
3790 | if (udata->inlen < required_cmd_sz) | |
3791 | return -EINVAL; | |
3792 | ||
3793 | if (udata->inlen > sizeof(ucmd) && | |
3794 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
3795 | udata->inlen - sizeof(ucmd))) | |
3796 | return -EOPNOTSUPP; | |
3797 | ||
3798 | if (ib_copy_from_udata(&ucmd, udata, | |
3799 | min(udata->inlen, sizeof(ucmd)))) | |
3800 | return -EFAULT; | |
3801 | ||
3802 | if (ucmd.comp_mask || | |
3803 | memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) || | |
3804 | memchr_inv(&ucmd.burst_info.reserved, 0, | |
3805 | sizeof(ucmd.burst_info.reserved))) | |
3806 | return -EOPNOTSUPP; | |
3807 | } | |
3808 | ||
d16e91da HE |
3809 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
3810 | return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask); | |
3811 | ||
c32a4f29 MS |
3812 | if (ibqp->qp_type == IB_QPT_DRIVER) |
3813 | qp_type = qp->qp_sub_type; | |
3814 | else | |
3815 | qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ? | |
3816 | IB_QPT_GSI : ibqp->qp_type; | |
3817 | ||
776a3906 MS |
3818 | if (qp_type == MLX5_IB_QPT_DCT) |
3819 | return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata); | |
d16e91da | 3820 | |
e126ba97 EC |
3821 | mutex_lock(&qp->mutex); |
3822 | ||
3823 | cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; | |
3824 | new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; | |
3825 | ||
2811ba51 AS |
3826 | if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) { |
3827 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
2811ba51 AS |
3828 | } |
3829 | ||
c2e53b2c YH |
3830 | if (qp->flags & MLX5_IB_QP_UNDERLAY) { |
3831 | if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) { | |
3832 | mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n", | |
3833 | attr_mask); | |
3834 | goto out; | |
3835 | } | |
3836 | } else if (qp_type != MLX5_IB_QPT_REG_UMR && | |
c32a4f29 | 3837 | qp_type != MLX5_IB_QPT_DCI && |
d31131bb KH |
3838 | !ib_modify_qp_is_ok(cur_state, new_state, qp_type, |
3839 | attr_mask)) { | |
158abf86 HE |
3840 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", |
3841 | cur_state, new_state, ibqp->qp_type, attr_mask); | |
e126ba97 | 3842 | goto out; |
c32a4f29 MS |
3843 | } else if (qp_type == MLX5_IB_QPT_DCI && |
3844 | !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) { | |
3845 | mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n", | |
3846 | cur_state, new_state, qp_type, attr_mask); | |
3847 | goto out; | |
158abf86 | 3848 | } |
e126ba97 EC |
3849 | |
3850 | if ((attr_mask & IB_QP_PORT) && | |
938fe83c | 3851 | (attr->port_num == 0 || |
508562d6 | 3852 | attr->port_num > dev->num_ports)) { |
158abf86 HE |
3853 | mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", |
3854 | attr->port_num, dev->num_ports); | |
e126ba97 | 3855 | goto out; |
158abf86 | 3856 | } |
e126ba97 EC |
3857 | |
3858 | if (attr_mask & IB_QP_PKEY_INDEX) { | |
3859 | port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; | |
938fe83c | 3860 | if (attr->pkey_index >= |
158abf86 HE |
3861 | dev->mdev->port_caps[port - 1].pkey_table_len) { |
3862 | mlx5_ib_dbg(dev, "invalid pkey index %d\n", | |
3863 | attr->pkey_index); | |
e126ba97 | 3864 | goto out; |
158abf86 | 3865 | } |
e126ba97 EC |
3866 | } |
3867 | ||
3868 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && | |
938fe83c | 3869 | attr->max_rd_atomic > |
158abf86 HE |
3870 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) { |
3871 | mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n", | |
3872 | attr->max_rd_atomic); | |
e126ba97 | 3873 | goto out; |
158abf86 | 3874 | } |
e126ba97 EC |
3875 | |
3876 | if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && | |
938fe83c | 3877 | attr->max_dest_rd_atomic > |
158abf86 HE |
3878 | (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) { |
3879 | mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n", | |
3880 | attr->max_dest_rd_atomic); | |
e126ba97 | 3881 | goto out; |
158abf86 | 3882 | } |
e126ba97 EC |
3883 | |
3884 | if (cur_state == new_state && cur_state == IB_QPS_RESET) { | |
3885 | err = 0; | |
3886 | goto out; | |
3887 | } | |
3888 | ||
61147f39 | 3889 | err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, |
89944450 | 3890 | new_state, &ucmd, udata); |
e126ba97 EC |
3891 | |
3892 | out: | |
3893 | mutex_unlock(&qp->mutex); | |
3894 | return err; | |
3895 | } | |
3896 | ||
34f4c955 GL |
3897 | static void _handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, |
3898 | u32 wqe_sz, void **cur_edge) | |
3899 | { | |
3900 | u32 idx; | |
3901 | ||
3902 | idx = (sq->cur_post + (wqe_sz >> 2)) & (sq->wqe_cnt - 1); | |
3903 | *cur_edge = get_sq_edge(sq, idx); | |
3904 | ||
3905 | *seg = mlx5_frag_buf_get_wqe(&sq->fbc, idx); | |
3906 | } | |
3907 | ||
3908 | /* handle_post_send_edge - Check if we get to SQ edge. If yes, update to the | |
3909 | * next nearby edge and get new address translation for current WQE position. | |
3910 | * @sq - SQ buffer. | |
3911 | * @seg: Current WQE position (16B aligned). | |
3912 | * @wqe_sz: Total current WQE size [16B]. | |
3913 | * @cur_edge: Updated current edge. | |
3914 | */ | |
3915 | static inline void handle_post_send_edge(struct mlx5_ib_wq *sq, void **seg, | |
3916 | u32 wqe_sz, void **cur_edge) | |
3917 | { | |
3918 | if (likely(*seg != *cur_edge)) | |
3919 | return; | |
3920 | ||
3921 | _handle_post_send_edge(sq, seg, wqe_sz, cur_edge); | |
3922 | } | |
3923 | ||
3924 | /* memcpy_send_wqe - copy data from src to WQE and update the relevant WQ's | |
3925 | * pointers. At the end @seg is aligned to 16B regardless the copied size. | |
3926 | * @sq - SQ buffer. | |
3927 | * @cur_edge: Updated current edge. | |
3928 | * @seg: Current WQE position (16B aligned). | |
3929 | * @wqe_sz: Total current WQE size [16B]. | |
3930 | * @src: Pointer to copy from. | |
3931 | * @n: Number of bytes to copy. | |
3932 | */ | |
3933 | static inline void memcpy_send_wqe(struct mlx5_ib_wq *sq, void **cur_edge, | |
3934 | void **seg, u32 *wqe_sz, const void *src, | |
3935 | size_t n) | |
3936 | { | |
3937 | while (likely(n)) { | |
3938 | size_t leftlen = *cur_edge - *seg; | |
3939 | size_t copysz = min_t(size_t, leftlen, n); | |
3940 | size_t stride; | |
3941 | ||
3942 | memcpy(*seg, src, copysz); | |
3943 | ||
3944 | n -= copysz; | |
3945 | src += copysz; | |
3946 | stride = !n ? ALIGN(copysz, 16) : copysz; | |
3947 | *seg += stride; | |
3948 | *wqe_sz += stride >> 4; | |
3949 | handle_post_send_edge(sq, seg, *wqe_sz, cur_edge); | |
3950 | } | |
3951 | } | |
3952 | ||
e126ba97 EC |
3953 | static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq) |
3954 | { | |
3955 | struct mlx5_ib_cq *cq; | |
3956 | unsigned cur; | |
3957 | ||
3958 | cur = wq->head - wq->tail; | |
3959 | if (likely(cur + nreq < wq->max_post)) | |
3960 | return 0; | |
3961 | ||
3962 | cq = to_mcq(ib_cq); | |
3963 | spin_lock(&cq->lock); | |
3964 | cur = wq->head - wq->tail; | |
3965 | spin_unlock(&cq->lock); | |
3966 | ||
3967 | return cur + nreq >= wq->max_post; | |
3968 | } | |
3969 | ||
3970 | static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg, | |
3971 | u64 remote_addr, u32 rkey) | |
3972 | { | |
3973 | rseg->raddr = cpu_to_be64(remote_addr); | |
3974 | rseg->rkey = cpu_to_be32(rkey); | |
3975 | rseg->reserved = 0; | |
3976 | } | |
3977 | ||
34f4c955 GL |
3978 | static void set_eth_seg(const struct ib_send_wr *wr, struct mlx5_ib_qp *qp, |
3979 | void **seg, int *size, void **cur_edge) | |
f0313965 | 3980 | { |
34f4c955 | 3981 | struct mlx5_wqe_eth_seg *eseg = *seg; |
f0313965 ES |
3982 | |
3983 | memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg)); | |
3984 | ||
3985 | if (wr->send_flags & IB_SEND_IP_CSUM) | |
3986 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | | |
3987 | MLX5_ETH_WQE_L4_CSUM; | |
3988 | ||
f0313965 ES |
3989 | if (wr->opcode == IB_WR_LSO) { |
3990 | struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr); | |
34f4c955 | 3991 | size_t left, copysz; |
f0313965 | 3992 | void *pdata = ud_wr->header; |
34f4c955 | 3993 | size_t stride; |
f0313965 ES |
3994 | |
3995 | left = ud_wr->hlen; | |
3996 | eseg->mss = cpu_to_be16(ud_wr->mss); | |
2b31f7ae | 3997 | eseg->inline_hdr.sz = cpu_to_be16(left); |
f0313965 | 3998 | |
34f4c955 GL |
3999 | /* memcpy_send_wqe should get a 16B align address. Hence, we |
4000 | * first copy up to the current edge and then, if needed, | |
4001 | * fall-through to memcpy_send_wqe. | |
f0313965 | 4002 | */ |
34f4c955 GL |
4003 | copysz = min_t(u64, *cur_edge - (void *)eseg->inline_hdr.start, |
4004 | left); | |
4005 | memcpy(eseg->inline_hdr.start, pdata, copysz); | |
4006 | stride = ALIGN(sizeof(struct mlx5_wqe_eth_seg) - | |
4007 | sizeof(eseg->inline_hdr.start) + copysz, 16); | |
4008 | *size += stride / 16; | |
4009 | *seg += stride; | |
4010 | ||
4011 | if (copysz < left) { | |
4012 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); | |
f0313965 ES |
4013 | left -= copysz; |
4014 | pdata += copysz; | |
34f4c955 GL |
4015 | memcpy_send_wqe(&qp->sq, cur_edge, seg, size, pdata, |
4016 | left); | |
f0313965 | 4017 | } |
34f4c955 GL |
4018 | |
4019 | return; | |
f0313965 ES |
4020 | } |
4021 | ||
34f4c955 GL |
4022 | *seg += sizeof(struct mlx5_wqe_eth_seg); |
4023 | *size += sizeof(struct mlx5_wqe_eth_seg) / 16; | |
f0313965 ES |
4024 | } |
4025 | ||
e126ba97 | 4026 | static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg, |
f696bf6d | 4027 | const struct ib_send_wr *wr) |
e126ba97 | 4028 | { |
e622f2f4 CH |
4029 | memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av)); |
4030 | dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV); | |
4031 | dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey); | |
e126ba97 EC |
4032 | } |
4033 | ||
4034 | static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg) | |
4035 | { | |
4036 | dseg->byte_count = cpu_to_be32(sg->length); | |
4037 | dseg->lkey = cpu_to_be32(sg->lkey); | |
4038 | dseg->addr = cpu_to_be64(sg->addr); | |
4039 | } | |
4040 | ||
31616255 | 4041 | static u64 get_xlt_octo(u64 bytes) |
e126ba97 | 4042 | { |
31616255 AK |
4043 | return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) / |
4044 | MLX5_IB_UMR_OCTOWORD; | |
e126ba97 EC |
4045 | } |
4046 | ||
4047 | static __be64 frwr_mkey_mask(void) | |
4048 | { | |
4049 | u64 result; | |
4050 | ||
4051 | result = MLX5_MKEY_MASK_LEN | | |
4052 | MLX5_MKEY_MASK_PAGE_SIZE | | |
4053 | MLX5_MKEY_MASK_START_ADDR | | |
4054 | MLX5_MKEY_MASK_EN_RINVAL | | |
4055 | MLX5_MKEY_MASK_KEY | | |
4056 | MLX5_MKEY_MASK_LR | | |
4057 | MLX5_MKEY_MASK_LW | | |
4058 | MLX5_MKEY_MASK_RR | | |
4059 | MLX5_MKEY_MASK_RW | | |
4060 | MLX5_MKEY_MASK_A | | |
4061 | MLX5_MKEY_MASK_SMALL_FENCE | | |
4062 | MLX5_MKEY_MASK_FREE; | |
4063 | ||
4064 | return cpu_to_be64(result); | |
4065 | } | |
4066 | ||
e6631814 SG |
4067 | static __be64 sig_mkey_mask(void) |
4068 | { | |
4069 | u64 result; | |
4070 | ||
4071 | result = MLX5_MKEY_MASK_LEN | | |
4072 | MLX5_MKEY_MASK_PAGE_SIZE | | |
4073 | MLX5_MKEY_MASK_START_ADDR | | |
d5436ba0 | 4074 | MLX5_MKEY_MASK_EN_SIGERR | |
e6631814 SG |
4075 | MLX5_MKEY_MASK_EN_RINVAL | |
4076 | MLX5_MKEY_MASK_KEY | | |
4077 | MLX5_MKEY_MASK_LR | | |
4078 | MLX5_MKEY_MASK_LW | | |
4079 | MLX5_MKEY_MASK_RR | | |
4080 | MLX5_MKEY_MASK_RW | | |
4081 | MLX5_MKEY_MASK_SMALL_FENCE | | |
4082 | MLX5_MKEY_MASK_FREE | | |
4083 | MLX5_MKEY_MASK_BSF_EN; | |
4084 | ||
4085 | return cpu_to_be64(result); | |
4086 | } | |
4087 | ||
8a187ee5 | 4088 | static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr, |
064e5262 | 4089 | struct mlx5_ib_mr *mr, bool umr_inline) |
8a187ee5 | 4090 | { |
31616255 | 4091 | int size = mr->ndescs * mr->desc_size; |
8a187ee5 SG |
4092 | |
4093 | memset(umr, 0, sizeof(*umr)); | |
b005d316 | 4094 | |
8a187ee5 | 4095 | umr->flags = MLX5_UMR_CHECK_NOT_FREE; |
064e5262 IB |
4096 | if (umr_inline) |
4097 | umr->flags |= MLX5_UMR_INLINE; | |
31616255 | 4098 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
8a187ee5 SG |
4099 | umr->mkey_mask = frwr_mkey_mask(); |
4100 | } | |
4101 | ||
dd01e66a | 4102 | static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr) |
e126ba97 EC |
4103 | { |
4104 | memset(umr, 0, sizeof(*umr)); | |
dd01e66a | 4105 | umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); |
2d221588 | 4106 | umr->flags = MLX5_UMR_INLINE; |
e126ba97 EC |
4107 | } |
4108 | ||
31616255 | 4109 | static __be64 get_umr_enable_mr_mask(void) |
968e78dd HE |
4110 | { |
4111 | u64 result; | |
4112 | ||
31616255 | 4113 | result = MLX5_MKEY_MASK_KEY | |
968e78dd HE |
4114 | MLX5_MKEY_MASK_FREE; |
4115 | ||
968e78dd HE |
4116 | return cpu_to_be64(result); |
4117 | } | |
4118 | ||
31616255 | 4119 | static __be64 get_umr_disable_mr_mask(void) |
968e78dd HE |
4120 | { |
4121 | u64 result; | |
4122 | ||
4123 | result = MLX5_MKEY_MASK_FREE; | |
4124 | ||
4125 | return cpu_to_be64(result); | |
4126 | } | |
4127 | ||
56e11d62 NO |
4128 | static __be64 get_umr_update_translation_mask(void) |
4129 | { | |
4130 | u64 result; | |
4131 | ||
4132 | result = MLX5_MKEY_MASK_LEN | | |
4133 | MLX5_MKEY_MASK_PAGE_SIZE | | |
31616255 | 4134 | MLX5_MKEY_MASK_START_ADDR; |
56e11d62 NO |
4135 | |
4136 | return cpu_to_be64(result); | |
4137 | } | |
4138 | ||
31616255 | 4139 | static __be64 get_umr_update_access_mask(int atomic) |
56e11d62 NO |
4140 | { |
4141 | u64 result; | |
4142 | ||
31616255 AK |
4143 | result = MLX5_MKEY_MASK_LR | |
4144 | MLX5_MKEY_MASK_LW | | |
56e11d62 | 4145 | MLX5_MKEY_MASK_RR | |
31616255 AK |
4146 | MLX5_MKEY_MASK_RW; |
4147 | ||
4148 | if (atomic) | |
4149 | result |= MLX5_MKEY_MASK_A; | |
56e11d62 NO |
4150 | |
4151 | return cpu_to_be64(result); | |
4152 | } | |
4153 | ||
4154 | static __be64 get_umr_update_pd_mask(void) | |
4155 | { | |
4156 | u64 result; | |
4157 | ||
31616255 | 4158 | result = MLX5_MKEY_MASK_PD; |
56e11d62 NO |
4159 | |
4160 | return cpu_to_be64(result); | |
4161 | } | |
4162 | ||
c8d75a98 MD |
4163 | static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) |
4164 | { | |
4165 | if ((mask & MLX5_MKEY_MASK_PAGE_SIZE && | |
4166 | MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) || | |
4167 | (mask & MLX5_MKEY_MASK_A && | |
4168 | MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))) | |
4169 | return -EPERM; | |
4170 | return 0; | |
4171 | } | |
4172 | ||
4173 | static int set_reg_umr_segment(struct mlx5_ib_dev *dev, | |
4174 | struct mlx5_wqe_umr_ctrl_seg *umr, | |
f696bf6d | 4175 | const struct ib_send_wr *wr, int atomic) |
e126ba97 | 4176 | { |
f696bf6d | 4177 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
e126ba97 EC |
4178 | |
4179 | memset(umr, 0, sizeof(*umr)); | |
4180 | ||
968e78dd HE |
4181 | if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE) |
4182 | umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */ | |
4183 | else | |
4184 | umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */ | |
4185 | ||
31616255 AK |
4186 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size)); |
4187 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) { | |
4188 | u64 offset = get_xlt_octo(umrwr->offset); | |
4189 | ||
4190 | umr->xlt_offset = cpu_to_be16(offset & 0xffff); | |
4191 | umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16); | |
4192 | umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN; | |
e126ba97 | 4193 | } |
31616255 AK |
4194 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION) |
4195 | umr->mkey_mask |= get_umr_update_translation_mask(); | |
4196 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) { | |
4197 | umr->mkey_mask |= get_umr_update_access_mask(atomic); | |
4198 | umr->mkey_mask |= get_umr_update_pd_mask(); | |
4199 | } | |
4200 | if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR) | |
4201 | umr->mkey_mask |= get_umr_enable_mr_mask(); | |
4202 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) | |
4203 | umr->mkey_mask |= get_umr_disable_mr_mask(); | |
e126ba97 EC |
4204 | |
4205 | if (!wr->num_sge) | |
968e78dd | 4206 | umr->flags |= MLX5_UMR_INLINE; |
c8d75a98 MD |
4207 | |
4208 | return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask)); | |
e126ba97 EC |
4209 | } |
4210 | ||
4211 | static u8 get_umr_flags(int acc) | |
4212 | { | |
4213 | return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) | | |
4214 | (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) | | |
4215 | (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) | | |
4216 | (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) | | |
2ac45934 | 4217 | MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN; |
e126ba97 EC |
4218 | } |
4219 | ||
8a187ee5 SG |
4220 | static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg, |
4221 | struct mlx5_ib_mr *mr, | |
4222 | u32 key, int access) | |
4223 | { | |
4224 | int ndescs = ALIGN(mr->ndescs, 8) >> 1; | |
4225 | ||
4226 | memset(seg, 0, sizeof(*seg)); | |
b005d316 | 4227 | |
ec22eb53 | 4228 | if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT) |
b005d316 | 4229 | seg->log2_page_size = ilog2(mr->ibmr.page_size); |
ec22eb53 | 4230 | else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS) |
b005d316 SG |
4231 | /* KLMs take twice the size of MTTs */ |
4232 | ndescs *= 2; | |
4233 | ||
4234 | seg->flags = get_umr_flags(access) | mr->access_mode; | |
8a187ee5 SG |
4235 | seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00); |
4236 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL); | |
4237 | seg->start_addr = cpu_to_be64(mr->ibmr.iova); | |
4238 | seg->len = cpu_to_be64(mr->ibmr.length); | |
4239 | seg->xlt_oct_size = cpu_to_be32(ndescs); | |
8a187ee5 SG |
4240 | } |
4241 | ||
dd01e66a | 4242 | static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg) |
e126ba97 EC |
4243 | { |
4244 | memset(seg, 0, sizeof(*seg)); | |
dd01e66a | 4245 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 EC |
4246 | } |
4247 | ||
f696bf6d BVA |
4248 | static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, |
4249 | const struct ib_send_wr *wr) | |
e126ba97 | 4250 | { |
f696bf6d | 4251 | const struct mlx5_umr_wr *umrwr = umr_wr(wr); |
968e78dd | 4252 | |
e126ba97 | 4253 | memset(seg, 0, sizeof(*seg)); |
31616255 | 4254 | if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR) |
968e78dd | 4255 | seg->status = MLX5_MKEY_STATUS_FREE; |
e126ba97 | 4256 | |
968e78dd | 4257 | seg->flags = convert_access(umrwr->access_flags); |
31616255 AK |
4258 | if (umrwr->pd) |
4259 | seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn); | |
4260 | if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION && | |
4261 | !umrwr->length) | |
4262 | seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64); | |
4263 | ||
4264 | seg->start_addr = cpu_to_be64(umrwr->virt_addr); | |
968e78dd HE |
4265 | seg->len = cpu_to_be64(umrwr->length); |
4266 | seg->log2_page_size = umrwr->page_shift; | |
746b5583 | 4267 | seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 | |
968e78dd | 4268 | mlx5_mkey_variant(umrwr->mkey)); |
e126ba97 EC |
4269 | } |
4270 | ||
8a187ee5 SG |
4271 | static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg, |
4272 | struct mlx5_ib_mr *mr, | |
4273 | struct mlx5_ib_pd *pd) | |
4274 | { | |
4275 | int bcount = mr->desc_size * mr->ndescs; | |
4276 | ||
4277 | dseg->addr = cpu_to_be64(mr->desc_map); | |
4278 | dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64)); | |
4279 | dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey); | |
4280 | } | |
4281 | ||
f696bf6d | 4282 | static __be32 send_ieth(const struct ib_send_wr *wr) |
e126ba97 EC |
4283 | { |
4284 | switch (wr->opcode) { | |
4285 | case IB_WR_SEND_WITH_IMM: | |
4286 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
4287 | return wr->ex.imm_data; | |
4288 | ||
4289 | case IB_WR_SEND_WITH_INV: | |
4290 | return cpu_to_be32(wr->ex.invalidate_rkey); | |
4291 | ||
4292 | default: | |
4293 | return 0; | |
4294 | } | |
4295 | } | |
4296 | ||
4297 | static u8 calc_sig(void *wqe, int size) | |
4298 | { | |
4299 | u8 *p = wqe; | |
4300 | u8 res = 0; | |
4301 | int i; | |
4302 | ||
4303 | for (i = 0; i < size; i++) | |
4304 | res ^= p[i]; | |
4305 | ||
4306 | return ~res; | |
4307 | } | |
4308 | ||
4309 | static u8 wq_sig(void *wqe) | |
4310 | { | |
4311 | return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); | |
4312 | } | |
4313 | ||
f696bf6d | 4314 | static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr, |
34f4c955 | 4315 | void **wqe, int *wqe_sz, void **cur_edge) |
e126ba97 EC |
4316 | { |
4317 | struct mlx5_wqe_inline_seg *seg; | |
34f4c955 | 4318 | size_t offset; |
e126ba97 | 4319 | int inl = 0; |
e126ba97 EC |
4320 | int i; |
4321 | ||
34f4c955 GL |
4322 | seg = *wqe; |
4323 | *wqe += sizeof(*seg); | |
4324 | offset = sizeof(*seg); | |
4325 | ||
e126ba97 | 4326 | for (i = 0; i < wr->num_sge; i++) { |
34f4c955 GL |
4327 | size_t len = wr->sg_list[i].length; |
4328 | void *addr = (void *)(unsigned long)(wr->sg_list[i].addr); | |
4329 | ||
e126ba97 EC |
4330 | inl += len; |
4331 | ||
4332 | if (unlikely(inl > qp->max_inline_data)) | |
4333 | return -ENOMEM; | |
4334 | ||
34f4c955 GL |
4335 | while (likely(len)) { |
4336 | size_t leftlen; | |
4337 | size_t copysz; | |
4338 | ||
4339 | handle_post_send_edge(&qp->sq, wqe, | |
4340 | *wqe_sz + (offset >> 4), | |
4341 | cur_edge); | |
4342 | ||
4343 | leftlen = *cur_edge - *wqe; | |
4344 | copysz = min_t(size_t, leftlen, len); | |
4345 | ||
4346 | memcpy(*wqe, addr, copysz); | |
4347 | len -= copysz; | |
4348 | addr += copysz; | |
4349 | *wqe += copysz; | |
4350 | offset += copysz; | |
e126ba97 | 4351 | } |
e126ba97 EC |
4352 | } |
4353 | ||
4354 | seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG); | |
4355 | ||
34f4c955 | 4356 | *wqe_sz += ALIGN(inl + sizeof(seg->byte_count), 16) / 16; |
e126ba97 EC |
4357 | |
4358 | return 0; | |
4359 | } | |
4360 | ||
e6631814 SG |
4361 | static u16 prot_field_size(enum ib_signature_type type) |
4362 | { | |
4363 | switch (type) { | |
4364 | case IB_SIG_TYPE_T10_DIF: | |
4365 | return MLX5_DIF_SIZE; | |
4366 | default: | |
4367 | return 0; | |
4368 | } | |
4369 | } | |
4370 | ||
4371 | static u8 bs_selector(int block_size) | |
4372 | { | |
4373 | switch (block_size) { | |
4374 | case 512: return 0x1; | |
4375 | case 520: return 0x2; | |
4376 | case 4096: return 0x3; | |
4377 | case 4160: return 0x4; | |
4378 | case 1073741824: return 0x5; | |
4379 | default: return 0; | |
4380 | } | |
4381 | } | |
4382 | ||
78eda2bb SG |
4383 | static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain, |
4384 | struct mlx5_bsf_inl *inl) | |
e6631814 | 4385 | { |
142537f4 SG |
4386 | /* Valid inline section and allow BSF refresh */ |
4387 | inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID | | |
4388 | MLX5_BSF_REFRESH_DIF); | |
4389 | inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag); | |
4390 | inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag); | |
78eda2bb SG |
4391 | /* repeating block */ |
4392 | inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK; | |
4393 | inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ? | |
4394 | MLX5_DIF_CRC : MLX5_DIF_IPCS; | |
e6631814 | 4395 | |
78eda2bb SG |
4396 | if (domain->sig.dif.ref_remap) |
4397 | inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG; | |
e6631814 | 4398 | |
78eda2bb SG |
4399 | if (domain->sig.dif.app_escape) { |
4400 | if (domain->sig.dif.ref_escape) | |
4401 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE; | |
4402 | else | |
4403 | inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE; | |
e6631814 SG |
4404 | } |
4405 | ||
78eda2bb SG |
4406 | inl->dif_app_bitmask_check = |
4407 | cpu_to_be16(domain->sig.dif.apptag_check_mask); | |
e6631814 SG |
4408 | } |
4409 | ||
4410 | static int mlx5_set_bsf(struct ib_mr *sig_mr, | |
4411 | struct ib_sig_attrs *sig_attrs, | |
4412 | struct mlx5_bsf *bsf, u32 data_size) | |
4413 | { | |
4414 | struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig; | |
4415 | struct mlx5_bsf_basic *basic = &bsf->basic; | |
4416 | struct ib_sig_domain *mem = &sig_attrs->mem; | |
4417 | struct ib_sig_domain *wire = &sig_attrs->wire; | |
e6631814 | 4418 | |
c7f44fbd | 4419 | memset(bsf, 0, sizeof(*bsf)); |
78eda2bb SG |
4420 | |
4421 | /* Basic + Extended + Inline */ | |
4422 | basic->bsf_size_sbs = 1 << 7; | |
4423 | /* Input domain check byte mask */ | |
4424 | basic->check_byte_mask = sig_attrs->check_mask; | |
4425 | basic->raw_data_size = cpu_to_be32(data_size); | |
4426 | ||
4427 | /* Memory domain */ | |
e6631814 | 4428 | switch (sig_attrs->mem.sig_type) { |
78eda2bb SG |
4429 | case IB_SIG_TYPE_NONE: |
4430 | break; | |
e6631814 | 4431 | case IB_SIG_TYPE_T10_DIF: |
78eda2bb SG |
4432 | basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval); |
4433 | basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx); | |
4434 | mlx5_fill_inl_bsf(mem, &bsf->m_inl); | |
4435 | break; | |
4436 | default: | |
4437 | return -EINVAL; | |
4438 | } | |
e6631814 | 4439 | |
78eda2bb SG |
4440 | /* Wire domain */ |
4441 | switch (sig_attrs->wire.sig_type) { | |
4442 | case IB_SIG_TYPE_NONE: | |
4443 | break; | |
4444 | case IB_SIG_TYPE_T10_DIF: | |
e6631814 | 4445 | if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && |
78eda2bb | 4446 | mem->sig_type == wire->sig_type) { |
e6631814 | 4447 | /* Same block structure */ |
142537f4 | 4448 | basic->bsf_size_sbs |= 1 << 4; |
e6631814 | 4449 | if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) |
fd22f78c | 4450 | basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; |
c7f44fbd | 4451 | if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) |
fd22f78c | 4452 | basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; |
c7f44fbd | 4453 | if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) |
fd22f78c | 4454 | basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; |
e6631814 SG |
4455 | } else |
4456 | basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval); | |
4457 | ||
142537f4 | 4458 | basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx); |
78eda2bb | 4459 | mlx5_fill_inl_bsf(wire, &bsf->w_inl); |
e6631814 | 4460 | break; |
e6631814 SG |
4461 | default: |
4462 | return -EINVAL; | |
4463 | } | |
4464 | ||
4465 | return 0; | |
4466 | } | |
4467 | ||
f696bf6d | 4468 | static int set_sig_data_segment(const struct ib_sig_handover_wr *wr, |
34f4c955 GL |
4469 | struct mlx5_ib_qp *qp, void **seg, |
4470 | int *size, void **cur_edge) | |
e6631814 | 4471 | { |
e622f2f4 CH |
4472 | struct ib_sig_attrs *sig_attrs = wr->sig_attrs; |
4473 | struct ib_mr *sig_mr = wr->sig_mr; | |
e6631814 | 4474 | struct mlx5_bsf *bsf; |
e622f2f4 CH |
4475 | u32 data_len = wr->wr.sg_list->length; |
4476 | u32 data_key = wr->wr.sg_list->lkey; | |
4477 | u64 data_va = wr->wr.sg_list->addr; | |
e6631814 SG |
4478 | int ret; |
4479 | int wqe_size; | |
4480 | ||
e622f2f4 CH |
4481 | if (!wr->prot || |
4482 | (data_key == wr->prot->lkey && | |
4483 | data_va == wr->prot->addr && | |
4484 | data_len == wr->prot->length)) { | |
e6631814 SG |
4485 | /** |
4486 | * Source domain doesn't contain signature information | |
5c273b16 | 4487 | * or data and protection are interleaved in memory. |
e6631814 SG |
4488 | * So need construct: |
4489 | * ------------------ | |
4490 | * | data_klm | | |
4491 | * ------------------ | |
4492 | * | BSF | | |
4493 | * ------------------ | |
4494 | **/ | |
4495 | struct mlx5_klm *data_klm = *seg; | |
4496 | ||
4497 | data_klm->bcount = cpu_to_be32(data_len); | |
4498 | data_klm->key = cpu_to_be32(data_key); | |
4499 | data_klm->va = cpu_to_be64(data_va); | |
4500 | wqe_size = ALIGN(sizeof(*data_klm), 64); | |
4501 | } else { | |
4502 | /** | |
4503 | * Source domain contains signature information | |
4504 | * So need construct a strided block format: | |
4505 | * --------------------------- | |
4506 | * | stride_block_ctrl | | |
4507 | * --------------------------- | |
4508 | * | data_klm | | |
4509 | * --------------------------- | |
4510 | * | prot_klm | | |
4511 | * --------------------------- | |
4512 | * | BSF | | |
4513 | * --------------------------- | |
4514 | **/ | |
4515 | struct mlx5_stride_block_ctrl_seg *sblock_ctrl; | |
4516 | struct mlx5_stride_block_entry *data_sentry; | |
4517 | struct mlx5_stride_block_entry *prot_sentry; | |
e622f2f4 CH |
4518 | u32 prot_key = wr->prot->lkey; |
4519 | u64 prot_va = wr->prot->addr; | |
e6631814 SG |
4520 | u16 block_size = sig_attrs->mem.sig.dif.pi_interval; |
4521 | int prot_size; | |
4522 | ||
4523 | sblock_ctrl = *seg; | |
4524 | data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl); | |
4525 | prot_sentry = (void *)data_sentry + sizeof(*data_sentry); | |
4526 | ||
4527 | prot_size = prot_field_size(sig_attrs->mem.sig_type); | |
4528 | if (!prot_size) { | |
4529 | pr_err("Bad block size given: %u\n", block_size); | |
4530 | return -EINVAL; | |
4531 | } | |
4532 | sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size + | |
4533 | prot_size); | |
4534 | sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP); | |
4535 | sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size); | |
4536 | sblock_ctrl->num_entries = cpu_to_be16(2); | |
4537 | ||
4538 | data_sentry->bcount = cpu_to_be16(block_size); | |
4539 | data_sentry->key = cpu_to_be32(data_key); | |
4540 | data_sentry->va = cpu_to_be64(data_va); | |
5c273b16 SG |
4541 | data_sentry->stride = cpu_to_be16(block_size); |
4542 | ||
e6631814 SG |
4543 | prot_sentry->bcount = cpu_to_be16(prot_size); |
4544 | prot_sentry->key = cpu_to_be32(prot_key); | |
5c273b16 SG |
4545 | prot_sentry->va = cpu_to_be64(prot_va); |
4546 | prot_sentry->stride = cpu_to_be16(prot_size); | |
e6631814 | 4547 | |
e6631814 SG |
4548 | wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) + |
4549 | sizeof(*prot_sentry), 64); | |
4550 | } | |
4551 | ||
4552 | *seg += wqe_size; | |
4553 | *size += wqe_size / 16; | |
34f4c955 | 4554 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 SG |
4555 | |
4556 | bsf = *seg; | |
4557 | ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len); | |
4558 | if (ret) | |
4559 | return -EINVAL; | |
4560 | ||
4561 | *seg += sizeof(*bsf); | |
4562 | *size += sizeof(*bsf) / 16; | |
34f4c955 | 4563 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 SG |
4564 | |
4565 | return 0; | |
4566 | } | |
4567 | ||
4568 | static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg, | |
f696bf6d | 4569 | const struct ib_sig_handover_wr *wr, u32 size, |
e6631814 SG |
4570 | u32 length, u32 pdn) |
4571 | { | |
e622f2f4 | 4572 | struct ib_mr *sig_mr = wr->sig_mr; |
e6631814 | 4573 | u32 sig_key = sig_mr->rkey; |
d5436ba0 | 4574 | u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1; |
e6631814 SG |
4575 | |
4576 | memset(seg, 0, sizeof(*seg)); | |
4577 | ||
e622f2f4 | 4578 | seg->flags = get_umr_flags(wr->access_flags) | |
ec22eb53 | 4579 | MLX5_MKC_ACCESS_MODE_KLMS; |
e6631814 | 4580 | seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00); |
d5436ba0 | 4581 | seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 | |
e6631814 SG |
4582 | MLX5_MKEY_BSF_EN | pdn); |
4583 | seg->len = cpu_to_be64(length); | |
31616255 | 4584 | seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size)); |
e6631814 SG |
4585 | seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE); |
4586 | } | |
4587 | ||
4588 | static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr, | |
31616255 | 4589 | u32 size) |
e6631814 SG |
4590 | { |
4591 | memset(umr, 0, sizeof(*umr)); | |
4592 | ||
4593 | umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE; | |
31616255 | 4594 | umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size)); |
e6631814 SG |
4595 | umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE); |
4596 | umr->mkey_mask = sig_mkey_mask(); | |
4597 | } | |
4598 | ||
4599 | ||
f696bf6d | 4600 | static int set_sig_umr_wr(const struct ib_send_wr *send_wr, |
34f4c955 GL |
4601 | struct mlx5_ib_qp *qp, void **seg, int *size, |
4602 | void **cur_edge) | |
e6631814 | 4603 | { |
f696bf6d | 4604 | const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr); |
e622f2f4 | 4605 | struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr); |
e6631814 | 4606 | u32 pdn = get_pd(qp)->pdn; |
31616255 | 4607 | u32 xlt_size; |
e6631814 SG |
4608 | int region_len, ret; |
4609 | ||
e622f2f4 CH |
4610 | if (unlikely(wr->wr.num_sge != 1) || |
4611 | unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) || | |
d5436ba0 SG |
4612 | unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) || |
4613 | unlikely(!sig_mr->sig->sig_status_checked)) | |
e6631814 SG |
4614 | return -EINVAL; |
4615 | ||
4616 | /* length of the protected region, data + protection */ | |
e622f2f4 CH |
4617 | region_len = wr->wr.sg_list->length; |
4618 | if (wr->prot && | |
4619 | (wr->prot->lkey != wr->wr.sg_list->lkey || | |
4620 | wr->prot->addr != wr->wr.sg_list->addr || | |
4621 | wr->prot->length != wr->wr.sg_list->length)) | |
4622 | region_len += wr->prot->length; | |
e6631814 SG |
4623 | |
4624 | /** | |
4625 | * KLM octoword size - if protection was provided | |
4626 | * then we use strided block format (3 octowords), | |
4627 | * else we use single KLM (1 octoword) | |
4628 | **/ | |
31616255 | 4629 | xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm); |
e6631814 | 4630 | |
31616255 | 4631 | set_sig_umr_segment(*seg, xlt_size); |
e6631814 SG |
4632 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4633 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 4634 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 | 4635 | |
31616255 | 4636 | set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn); |
e6631814 SG |
4637 | *seg += sizeof(struct mlx5_mkey_seg); |
4638 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 4639 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e6631814 | 4640 | |
34f4c955 | 4641 | ret = set_sig_data_segment(wr, qp, seg, size, cur_edge); |
e6631814 SG |
4642 | if (ret) |
4643 | return ret; | |
4644 | ||
d5436ba0 | 4645 | sig_mr->sig->sig_status_checked = false; |
e6631814 SG |
4646 | return 0; |
4647 | } | |
4648 | ||
4649 | static int set_psv_wr(struct ib_sig_domain *domain, | |
4650 | u32 psv_idx, void **seg, int *size) | |
4651 | { | |
4652 | struct mlx5_seg_set_psv *psv_seg = *seg; | |
4653 | ||
4654 | memset(psv_seg, 0, sizeof(*psv_seg)); | |
4655 | psv_seg->psv_num = cpu_to_be32(psv_idx); | |
4656 | switch (domain->sig_type) { | |
78eda2bb SG |
4657 | case IB_SIG_TYPE_NONE: |
4658 | break; | |
e6631814 SG |
4659 | case IB_SIG_TYPE_T10_DIF: |
4660 | psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 | | |
4661 | domain->sig.dif.app_tag); | |
4662 | psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag); | |
e6631814 | 4663 | break; |
e6631814 | 4664 | default: |
12bbf1ea LR |
4665 | pr_err("Bad signature type (%d) is given.\n", |
4666 | domain->sig_type); | |
4667 | return -EINVAL; | |
e6631814 SG |
4668 | } |
4669 | ||
78eda2bb SG |
4670 | *seg += sizeof(*psv_seg); |
4671 | *size += sizeof(*psv_seg) / 16; | |
4672 | ||
e6631814 SG |
4673 | return 0; |
4674 | } | |
4675 | ||
8a187ee5 | 4676 | static int set_reg_wr(struct mlx5_ib_qp *qp, |
f696bf6d | 4677 | const struct ib_reg_wr *wr, |
34f4c955 | 4678 | void **seg, int *size, void **cur_edge) |
8a187ee5 SG |
4679 | { |
4680 | struct mlx5_ib_mr *mr = to_mmr(wr->mr); | |
4681 | struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd); | |
34f4c955 | 4682 | size_t mr_list_size = mr->ndescs * mr->desc_size; |
064e5262 | 4683 | bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD; |
8a187ee5 SG |
4684 | |
4685 | if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) { | |
4686 | mlx5_ib_warn(to_mdev(qp->ibqp.device), | |
4687 | "Invalid IB_SEND_INLINE send flag\n"); | |
4688 | return -EINVAL; | |
4689 | } | |
4690 | ||
064e5262 | 4691 | set_reg_umr_seg(*seg, mr, umr_inline); |
8a187ee5 SG |
4692 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4693 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 4694 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
8a187ee5 SG |
4695 | |
4696 | set_reg_mkey_seg(*seg, mr, wr->key, wr->access); | |
4697 | *seg += sizeof(struct mlx5_mkey_seg); | |
4698 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 4699 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
8a187ee5 | 4700 | |
064e5262 | 4701 | if (umr_inline) { |
34f4c955 GL |
4702 | memcpy_send_wqe(&qp->sq, cur_edge, seg, size, mr->descs, |
4703 | mr_list_size); | |
4704 | *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); | |
064e5262 IB |
4705 | } else { |
4706 | set_reg_data_seg(*seg, mr, pd); | |
4707 | *seg += sizeof(struct mlx5_wqe_data_seg); | |
4708 | *size += (sizeof(struct mlx5_wqe_data_seg) / 16); | |
4709 | } | |
8a187ee5 SG |
4710 | return 0; |
4711 | } | |
4712 | ||
34f4c955 GL |
4713 | static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size, |
4714 | void **cur_edge) | |
e126ba97 | 4715 | { |
dd01e66a | 4716 | set_linv_umr_seg(*seg); |
e126ba97 EC |
4717 | *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
4718 | *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 4719 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
dd01e66a | 4720 | set_linv_mkey_seg(*seg); |
e126ba97 EC |
4721 | *seg += sizeof(struct mlx5_mkey_seg); |
4722 | *size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 4723 | handle_post_send_edge(&qp->sq, seg, *size, cur_edge); |
e126ba97 EC |
4724 | } |
4725 | ||
34f4c955 | 4726 | static void dump_wqe(struct mlx5_ib_qp *qp, u32 idx, int size_16) |
e126ba97 EC |
4727 | { |
4728 | __be32 *p = NULL; | |
34f4c955 | 4729 | u32 tidx = idx; |
e126ba97 EC |
4730 | int i, j; |
4731 | ||
34f4c955 | 4732 | pr_debug("dump WQE index %u:\n", idx); |
e126ba97 EC |
4733 | for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { |
4734 | if ((i & 0xf) == 0) { | |
e126ba97 | 4735 | tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1); |
34f4c955 GL |
4736 | p = mlx5_frag_buf_get_wqe(&qp->sq.fbc, tidx); |
4737 | pr_debug("WQBB at %p:\n", (void *)p); | |
e126ba97 EC |
4738 | j = 0; |
4739 | } | |
4740 | pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]), | |
4741 | be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]), | |
4742 | be32_to_cpu(p[j + 3])); | |
4743 | } | |
4744 | } | |
4745 | ||
7bb1fafc | 4746 | static int __begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
34f4c955 GL |
4747 | struct mlx5_wqe_ctrl_seg **ctrl, |
4748 | const struct ib_send_wr *wr, unsigned int *idx, | |
4749 | int *size, void **cur_edge, int nreq, | |
4750 | bool send_signaled, bool solicited) | |
6e5eadac | 4751 | { |
b2a232d2 LR |
4752 | if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) |
4753 | return -ENOMEM; | |
6e5eadac SG |
4754 | |
4755 | *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1); | |
34f4c955 | 4756 | *seg = mlx5_frag_buf_get_wqe(&qp->sq.fbc, *idx); |
6e5eadac SG |
4757 | *ctrl = *seg; |
4758 | *(uint32_t *)(*seg + 8) = 0; | |
4759 | (*ctrl)->imm = send_ieth(wr); | |
4760 | (*ctrl)->fm_ce_se = qp->sq_signal_bits | | |
7bb1fafc BVA |
4761 | (send_signaled ? MLX5_WQE_CTRL_CQ_UPDATE : 0) | |
4762 | (solicited ? MLX5_WQE_CTRL_SOLICITED : 0); | |
6e5eadac SG |
4763 | |
4764 | *seg += sizeof(**ctrl); | |
4765 | *size = sizeof(**ctrl) / 16; | |
34f4c955 | 4766 | *cur_edge = qp->sq.cur_edge; |
6e5eadac | 4767 | |
b2a232d2 | 4768 | return 0; |
6e5eadac SG |
4769 | } |
4770 | ||
7bb1fafc BVA |
4771 | static int begin_wqe(struct mlx5_ib_qp *qp, void **seg, |
4772 | struct mlx5_wqe_ctrl_seg **ctrl, | |
4773 | const struct ib_send_wr *wr, unsigned *idx, | |
34f4c955 | 4774 | int *size, void **cur_edge, int nreq) |
7bb1fafc | 4775 | { |
34f4c955 | 4776 | return __begin_wqe(qp, seg, ctrl, wr, idx, size, cur_edge, nreq, |
7bb1fafc BVA |
4777 | wr->send_flags & IB_SEND_SIGNALED, |
4778 | wr->send_flags & IB_SEND_SOLICITED); | |
4779 | } | |
4780 | ||
6e5eadac SG |
4781 | static void finish_wqe(struct mlx5_ib_qp *qp, |
4782 | struct mlx5_wqe_ctrl_seg *ctrl, | |
34f4c955 GL |
4783 | void *seg, u8 size, void *cur_edge, |
4784 | unsigned int idx, u64 wr_id, int nreq, u8 fence, | |
4785 | u32 mlx5_opcode) | |
6e5eadac SG |
4786 | { |
4787 | u8 opmod = 0; | |
4788 | ||
4789 | ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) | | |
4790 | mlx5_opcode | ((u32)opmod << 24)); | |
19098df2 | 4791 | ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8)); |
6e5eadac | 4792 | ctrl->fm_ce_se |= fence; |
6e5eadac SG |
4793 | if (unlikely(qp->wq_sig)) |
4794 | ctrl->signature = wq_sig(ctrl); | |
4795 | ||
4796 | qp->sq.wrid[idx] = wr_id; | |
4797 | qp->sq.w_list[idx].opcode = mlx5_opcode; | |
4798 | qp->sq.wqe_head[idx] = qp->sq.head + nreq; | |
4799 | qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB); | |
4800 | qp->sq.w_list[idx].next = qp->sq.cur_post; | |
34f4c955 GL |
4801 | |
4802 | /* We save the edge which was possibly updated during the WQE | |
4803 | * construction, into SQ's cache. | |
4804 | */ | |
4805 | seg = PTR_ALIGN(seg, MLX5_SEND_WQE_BB); | |
4806 | qp->sq.cur_edge = (unlikely(seg == cur_edge)) ? | |
4807 | get_sq_edge(&qp->sq, qp->sq.cur_post & | |
4808 | (qp->sq.wqe_cnt - 1)) : | |
4809 | cur_edge; | |
6e5eadac SG |
4810 | } |
4811 | ||
d34ac5cd BVA |
4812 | static int _mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
4813 | const struct ib_send_wr **bad_wr, bool drain) | |
e126ba97 EC |
4814 | { |
4815 | struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */ | |
4816 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
89ea94a7 | 4817 | struct mlx5_core_dev *mdev = dev->mdev; |
d16e91da | 4818 | struct mlx5_ib_qp *qp; |
e6631814 | 4819 | struct mlx5_ib_mr *mr; |
e126ba97 | 4820 | struct mlx5_wqe_xrc_seg *xrc; |
d16e91da | 4821 | struct mlx5_bf *bf; |
34f4c955 | 4822 | void *cur_edge; |
e126ba97 | 4823 | int uninitialized_var(size); |
e126ba97 | 4824 | unsigned long flags; |
e126ba97 EC |
4825 | unsigned idx; |
4826 | int err = 0; | |
e126ba97 EC |
4827 | int num_sge; |
4828 | void *seg; | |
4829 | int nreq; | |
4830 | int i; | |
4831 | u8 next_fence = 0; | |
e126ba97 EC |
4832 | u8 fence; |
4833 | ||
6c75520f PP |
4834 | if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && |
4835 | !drain)) { | |
4836 | *bad_wr = wr; | |
4837 | return -EIO; | |
4838 | } | |
4839 | ||
d16e91da HE |
4840 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
4841 | return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr); | |
4842 | ||
4843 | qp = to_mqp(ibqp); | |
5fe9dec0 | 4844 | bf = &qp->bf; |
d16e91da | 4845 | |
e126ba97 EC |
4846 | spin_lock_irqsave(&qp->sq.lock, flags); |
4847 | ||
4848 | for (nreq = 0; wr; nreq++, wr = wr->next) { | |
a8f731eb | 4849 | if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) { |
e126ba97 EC |
4850 | mlx5_ib_warn(dev, "\n"); |
4851 | err = -EINVAL; | |
4852 | *bad_wr = wr; | |
4853 | goto out; | |
4854 | } | |
4855 | ||
6e5eadac SG |
4856 | num_sge = wr->num_sge; |
4857 | if (unlikely(num_sge > qp->sq.max_gs)) { | |
e126ba97 | 4858 | mlx5_ib_warn(dev, "\n"); |
24be409b | 4859 | err = -EINVAL; |
e126ba97 EC |
4860 | *bad_wr = wr; |
4861 | goto out; | |
4862 | } | |
4863 | ||
34f4c955 GL |
4864 | err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, &cur_edge, |
4865 | nreq); | |
6e5eadac | 4866 | if (err) { |
e126ba97 EC |
4867 | mlx5_ib_warn(dev, "\n"); |
4868 | err = -ENOMEM; | |
4869 | *bad_wr = wr; | |
4870 | goto out; | |
4871 | } | |
4872 | ||
074fca3a | 4873 | if (wr->opcode == IB_WR_REG_MR) { |
6e8484c5 MG |
4874 | fence = dev->umr_fence; |
4875 | next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; | |
074fca3a MD |
4876 | } else { |
4877 | if (wr->send_flags & IB_SEND_FENCE) { | |
4878 | if (qp->next_fence) | |
4879 | fence = MLX5_FENCE_MODE_SMALL_AND_FENCE; | |
4880 | else | |
4881 | fence = MLX5_FENCE_MODE_FENCE; | |
4882 | } else { | |
4883 | fence = qp->next_fence; | |
4884 | } | |
6e8484c5 MG |
4885 | } |
4886 | ||
e126ba97 EC |
4887 | switch (ibqp->qp_type) { |
4888 | case IB_QPT_XRC_INI: | |
4889 | xrc = seg; | |
e126ba97 EC |
4890 | seg += sizeof(*xrc); |
4891 | size += sizeof(*xrc) / 16; | |
4892 | /* fall through */ | |
4893 | case IB_QPT_RC: | |
4894 | switch (wr->opcode) { | |
4895 | case IB_WR_RDMA_READ: | |
4896 | case IB_WR_RDMA_WRITE: | |
4897 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
4898 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
4899 | rdma_wr(wr)->rkey); | |
f241e749 | 4900 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
e126ba97 EC |
4901 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; |
4902 | break; | |
4903 | ||
4904 | case IB_WR_ATOMIC_CMP_AND_SWP: | |
4905 | case IB_WR_ATOMIC_FETCH_AND_ADD: | |
e126ba97 | 4906 | case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: |
81bea28f EC |
4907 | mlx5_ib_warn(dev, "Atomic operations are not supported yet\n"); |
4908 | err = -ENOSYS; | |
4909 | *bad_wr = wr; | |
4910 | goto out; | |
e126ba97 EC |
4911 | |
4912 | case IB_WR_LOCAL_INV: | |
e126ba97 EC |
4913 | qp->sq.wr_data[idx] = IB_WR_LOCAL_INV; |
4914 | ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey); | |
34f4c955 | 4915 | set_linv_wr(qp, &seg, &size, &cur_edge); |
e126ba97 EC |
4916 | num_sge = 0; |
4917 | break; | |
4918 | ||
8a187ee5 | 4919 | case IB_WR_REG_MR: |
8a187ee5 SG |
4920 | qp->sq.wr_data[idx] = IB_WR_REG_MR; |
4921 | ctrl->imm = cpu_to_be32(reg_wr(wr)->key); | |
34f4c955 GL |
4922 | err = set_reg_wr(qp, reg_wr(wr), &seg, &size, |
4923 | &cur_edge); | |
8a187ee5 SG |
4924 | if (err) { |
4925 | *bad_wr = wr; | |
4926 | goto out; | |
4927 | } | |
4928 | num_sge = 0; | |
4929 | break; | |
4930 | ||
e6631814 SG |
4931 | case IB_WR_REG_SIG_MR: |
4932 | qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR; | |
e622f2f4 | 4933 | mr = to_mmr(sig_handover_wr(wr)->sig_mr); |
e6631814 SG |
4934 | |
4935 | ctrl->imm = cpu_to_be32(mr->ibmr.rkey); | |
34f4c955 GL |
4936 | err = set_sig_umr_wr(wr, qp, &seg, &size, |
4937 | &cur_edge); | |
e6631814 SG |
4938 | if (err) { |
4939 | mlx5_ib_warn(dev, "\n"); | |
4940 | *bad_wr = wr; | |
4941 | goto out; | |
4942 | } | |
4943 | ||
34f4c955 GL |
4944 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, |
4945 | wr->wr_id, nreq, fence, | |
4946 | MLX5_OPCODE_UMR); | |
e6631814 SG |
4947 | /* |
4948 | * SET_PSV WQEs are not signaled and solicited | |
4949 | * on error | |
4950 | */ | |
7bb1fafc | 4951 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, |
34f4c955 GL |
4952 | &size, &cur_edge, nreq, false, |
4953 | true); | |
e6631814 SG |
4954 | if (err) { |
4955 | mlx5_ib_warn(dev, "\n"); | |
4956 | err = -ENOMEM; | |
4957 | *bad_wr = wr; | |
4958 | goto out; | |
4959 | } | |
4960 | ||
e622f2f4 | 4961 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem, |
e6631814 SG |
4962 | mr->sig->psv_memory.psv_idx, &seg, |
4963 | &size); | |
4964 | if (err) { | |
4965 | mlx5_ib_warn(dev, "\n"); | |
4966 | *bad_wr = wr; | |
4967 | goto out; | |
4968 | } | |
4969 | ||
34f4c955 GL |
4970 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, |
4971 | wr->wr_id, nreq, fence, | |
4972 | MLX5_OPCODE_SET_PSV); | |
7bb1fafc | 4973 | err = __begin_wqe(qp, &seg, &ctrl, wr, &idx, |
34f4c955 GL |
4974 | &size, &cur_edge, nreq, false, |
4975 | true); | |
e6631814 SG |
4976 | if (err) { |
4977 | mlx5_ib_warn(dev, "\n"); | |
4978 | err = -ENOMEM; | |
4979 | *bad_wr = wr; | |
4980 | goto out; | |
4981 | } | |
4982 | ||
e622f2f4 | 4983 | err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire, |
e6631814 SG |
4984 | mr->sig->psv_wire.psv_idx, &seg, |
4985 | &size); | |
4986 | if (err) { | |
4987 | mlx5_ib_warn(dev, "\n"); | |
4988 | *bad_wr = wr; | |
4989 | goto out; | |
4990 | } | |
4991 | ||
34f4c955 GL |
4992 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, |
4993 | wr->wr_id, nreq, fence, | |
4994 | MLX5_OPCODE_SET_PSV); | |
6e8484c5 | 4995 | qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL; |
e6631814 SG |
4996 | num_sge = 0; |
4997 | goto skip_psv; | |
4998 | ||
e126ba97 EC |
4999 | default: |
5000 | break; | |
5001 | } | |
5002 | break; | |
5003 | ||
5004 | case IB_QPT_UC: | |
5005 | switch (wr->opcode) { | |
5006 | case IB_WR_RDMA_WRITE: | |
5007 | case IB_WR_RDMA_WRITE_WITH_IMM: | |
e622f2f4 CH |
5008 | set_raddr_seg(seg, rdma_wr(wr)->remote_addr, |
5009 | rdma_wr(wr)->rkey); | |
e126ba97 EC |
5010 | seg += sizeof(struct mlx5_wqe_raddr_seg); |
5011 | size += sizeof(struct mlx5_wqe_raddr_seg) / 16; | |
5012 | break; | |
5013 | ||
5014 | default: | |
5015 | break; | |
5016 | } | |
5017 | break; | |
5018 | ||
e126ba97 | 5019 | case IB_QPT_SMI: |
1e0e50b6 MG |
5020 | if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) { |
5021 | mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n"); | |
5022 | err = -EPERM; | |
5023 | *bad_wr = wr; | |
5024 | goto out; | |
5025 | } | |
f6b1ee34 | 5026 | /* fall through */ |
d16e91da | 5027 | case MLX5_IB_QPT_HW_GSI: |
e126ba97 | 5028 | set_datagram_seg(seg, wr); |
f241e749 | 5029 | seg += sizeof(struct mlx5_wqe_datagram_seg); |
e126ba97 | 5030 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; |
34f4c955 GL |
5031 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
5032 | ||
e126ba97 | 5033 | break; |
f0313965 ES |
5034 | case IB_QPT_UD: |
5035 | set_datagram_seg(seg, wr); | |
5036 | seg += sizeof(struct mlx5_wqe_datagram_seg); | |
5037 | size += sizeof(struct mlx5_wqe_datagram_seg) / 16; | |
34f4c955 | 5038 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
f0313965 ES |
5039 | |
5040 | /* handle qp that supports ud offload */ | |
5041 | if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) { | |
5042 | struct mlx5_wqe_eth_pad *pad; | |
e126ba97 | 5043 | |
f0313965 ES |
5044 | pad = seg; |
5045 | memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad)); | |
5046 | seg += sizeof(struct mlx5_wqe_eth_pad); | |
5047 | size += sizeof(struct mlx5_wqe_eth_pad) / 16; | |
34f4c955 GL |
5048 | set_eth_seg(wr, qp, &seg, &size, &cur_edge); |
5049 | handle_post_send_edge(&qp->sq, &seg, size, | |
5050 | &cur_edge); | |
f0313965 ES |
5051 | } |
5052 | break; | |
e126ba97 EC |
5053 | case MLX5_IB_QPT_REG_UMR: |
5054 | if (wr->opcode != MLX5_IB_WR_UMR) { | |
5055 | err = -EINVAL; | |
5056 | mlx5_ib_warn(dev, "bad opcode\n"); | |
5057 | goto out; | |
5058 | } | |
5059 | qp->sq.wr_data[idx] = MLX5_IB_WR_UMR; | |
e622f2f4 | 5060 | ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey); |
c8d75a98 MD |
5061 | err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic))); |
5062 | if (unlikely(err)) | |
5063 | goto out; | |
e126ba97 EC |
5064 | seg += sizeof(struct mlx5_wqe_umr_ctrl_seg); |
5065 | size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16; | |
34f4c955 | 5066 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
e126ba97 EC |
5067 | set_reg_mkey_segment(seg, wr); |
5068 | seg += sizeof(struct mlx5_mkey_seg); | |
5069 | size += sizeof(struct mlx5_mkey_seg) / 16; | |
34f4c955 | 5070 | handle_post_send_edge(&qp->sq, &seg, size, &cur_edge); |
e126ba97 EC |
5071 | break; |
5072 | ||
5073 | default: | |
5074 | break; | |
5075 | } | |
5076 | ||
5077 | if (wr->send_flags & IB_SEND_INLINE && num_sge) { | |
34f4c955 | 5078 | err = set_data_inl_seg(qp, wr, &seg, &size, &cur_edge); |
e126ba97 EC |
5079 | if (unlikely(err)) { |
5080 | mlx5_ib_warn(dev, "\n"); | |
5081 | *bad_wr = wr; | |
5082 | goto out; | |
5083 | } | |
e126ba97 | 5084 | } else { |
e126ba97 | 5085 | for (i = 0; i < num_sge; i++) { |
34f4c955 GL |
5086 | handle_post_send_edge(&qp->sq, &seg, size, |
5087 | &cur_edge); | |
e126ba97 | 5088 | if (likely(wr->sg_list[i].length)) { |
34f4c955 GL |
5089 | set_data_ptr_seg |
5090 | ((struct mlx5_wqe_data_seg *)seg, | |
5091 | wr->sg_list + i); | |
e126ba97 | 5092 | size += sizeof(struct mlx5_wqe_data_seg) / 16; |
34f4c955 | 5093 | seg += sizeof(struct mlx5_wqe_data_seg); |
e126ba97 EC |
5094 | } |
5095 | } | |
5096 | } | |
5097 | ||
6e8484c5 | 5098 | qp->next_fence = next_fence; |
34f4c955 GL |
5099 | finish_wqe(qp, ctrl, seg, size, cur_edge, idx, wr->wr_id, nreq, |
5100 | fence, mlx5_ib_opcode[wr->opcode]); | |
e6631814 | 5101 | skip_psv: |
e126ba97 EC |
5102 | if (0) |
5103 | dump_wqe(qp, idx, size); | |
5104 | } | |
5105 | ||
5106 | out: | |
5107 | if (likely(nreq)) { | |
5108 | qp->sq.head += nreq; | |
5109 | ||
5110 | /* Make sure that descriptors are written before | |
5111 | * updating doorbell record and ringing the doorbell | |
5112 | */ | |
5113 | wmb(); | |
5114 | ||
5115 | qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post); | |
5116 | ||
ada388f7 EC |
5117 | /* Make sure doorbell record is visible to the HCA before |
5118 | * we hit doorbell */ | |
5119 | wmb(); | |
5120 | ||
5fe9dec0 EC |
5121 | /* currently we support only regular doorbells */ |
5122 | mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL); | |
5123 | /* Make sure doorbells don't leak out of SQ spinlock | |
5124 | * and reach the HCA out of order. | |
5125 | */ | |
5126 | mmiowb(); | |
e126ba97 | 5127 | bf->offset ^= bf->buf_size; |
e126ba97 EC |
5128 | } |
5129 | ||
5130 | spin_unlock_irqrestore(&qp->sq.lock, flags); | |
5131 | ||
5132 | return err; | |
5133 | } | |
5134 | ||
d34ac5cd BVA |
5135 | int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, |
5136 | const struct ib_send_wr **bad_wr) | |
d0e84c0a YH |
5137 | { |
5138 | return _mlx5_ib_post_send(ibqp, wr, bad_wr, false); | |
5139 | } | |
5140 | ||
e126ba97 EC |
5141 | static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size) |
5142 | { | |
5143 | sig->signature = calc_sig(sig, size); | |
5144 | } | |
5145 | ||
d34ac5cd BVA |
5146 | static int _mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
5147 | const struct ib_recv_wr **bad_wr, bool drain) | |
e126ba97 EC |
5148 | { |
5149 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
5150 | struct mlx5_wqe_data_seg *scat; | |
5151 | struct mlx5_rwqe_sig *sig; | |
89ea94a7 MG |
5152 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); |
5153 | struct mlx5_core_dev *mdev = dev->mdev; | |
e126ba97 EC |
5154 | unsigned long flags; |
5155 | int err = 0; | |
5156 | int nreq; | |
5157 | int ind; | |
5158 | int i; | |
5159 | ||
6c75520f PP |
5160 | if (unlikely(mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR && |
5161 | !drain)) { | |
5162 | *bad_wr = wr; | |
5163 | return -EIO; | |
5164 | } | |
5165 | ||
d16e91da HE |
5166 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5167 | return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr); | |
5168 | ||
e126ba97 EC |
5169 | spin_lock_irqsave(&qp->rq.lock, flags); |
5170 | ||
5171 | ind = qp->rq.head & (qp->rq.wqe_cnt - 1); | |
5172 | ||
5173 | for (nreq = 0; wr; nreq++, wr = wr->next) { | |
5174 | if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { | |
5175 | err = -ENOMEM; | |
5176 | *bad_wr = wr; | |
5177 | goto out; | |
5178 | } | |
5179 | ||
5180 | if (unlikely(wr->num_sge > qp->rq.max_gs)) { | |
5181 | err = -EINVAL; | |
5182 | *bad_wr = wr; | |
5183 | goto out; | |
5184 | } | |
5185 | ||
34f4c955 | 5186 | scat = mlx5_frag_buf_get_wqe(&qp->rq.fbc, ind); |
e126ba97 EC |
5187 | if (qp->wq_sig) |
5188 | scat++; | |
5189 | ||
5190 | for (i = 0; i < wr->num_sge; i++) | |
5191 | set_data_ptr_seg(scat + i, wr->sg_list + i); | |
5192 | ||
5193 | if (i < qp->rq.max_gs) { | |
5194 | scat[i].byte_count = 0; | |
5195 | scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY); | |
5196 | scat[i].addr = 0; | |
5197 | } | |
5198 | ||
5199 | if (qp->wq_sig) { | |
5200 | sig = (struct mlx5_rwqe_sig *)scat; | |
5201 | set_sig_seg(sig, (qp->rq.max_gs + 1) << 2); | |
5202 | } | |
5203 | ||
5204 | qp->rq.wrid[ind] = wr->wr_id; | |
5205 | ||
5206 | ind = (ind + 1) & (qp->rq.wqe_cnt - 1); | |
5207 | } | |
5208 | ||
5209 | out: | |
5210 | if (likely(nreq)) { | |
5211 | qp->rq.head += nreq; | |
5212 | ||
5213 | /* Make sure that descriptors are written before | |
5214 | * doorbell record. | |
5215 | */ | |
5216 | wmb(); | |
5217 | ||
5218 | *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); | |
5219 | } | |
5220 | ||
5221 | spin_unlock_irqrestore(&qp->rq.lock, flags); | |
5222 | ||
5223 | return err; | |
5224 | } | |
5225 | ||
d34ac5cd BVA |
5226 | int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, |
5227 | const struct ib_recv_wr **bad_wr) | |
d0e84c0a YH |
5228 | { |
5229 | return _mlx5_ib_post_recv(ibqp, wr, bad_wr, false); | |
5230 | } | |
5231 | ||
e126ba97 EC |
5232 | static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state) |
5233 | { | |
5234 | switch (mlx5_state) { | |
5235 | case MLX5_QP_STATE_RST: return IB_QPS_RESET; | |
5236 | case MLX5_QP_STATE_INIT: return IB_QPS_INIT; | |
5237 | case MLX5_QP_STATE_RTR: return IB_QPS_RTR; | |
5238 | case MLX5_QP_STATE_RTS: return IB_QPS_RTS; | |
5239 | case MLX5_QP_STATE_SQ_DRAINING: | |
5240 | case MLX5_QP_STATE_SQD: return IB_QPS_SQD; | |
5241 | case MLX5_QP_STATE_SQER: return IB_QPS_SQE; | |
5242 | case MLX5_QP_STATE_ERR: return IB_QPS_ERR; | |
5243 | default: return -1; | |
5244 | } | |
5245 | } | |
5246 | ||
5247 | static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state) | |
5248 | { | |
5249 | switch (mlx5_mig_state) { | |
5250 | case MLX5_QP_PM_ARMED: return IB_MIG_ARMED; | |
5251 | case MLX5_QP_PM_REARM: return IB_MIG_REARM; | |
5252 | case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED; | |
5253 | default: return -1; | |
5254 | } | |
5255 | } | |
5256 | ||
5257 | static int to_ib_qp_access_flags(int mlx5_flags) | |
5258 | { | |
5259 | int ib_flags = 0; | |
5260 | ||
5261 | if (mlx5_flags & MLX5_QP_BIT_RRE) | |
5262 | ib_flags |= IB_ACCESS_REMOTE_READ; | |
5263 | if (mlx5_flags & MLX5_QP_BIT_RWE) | |
5264 | ib_flags |= IB_ACCESS_REMOTE_WRITE; | |
5265 | if (mlx5_flags & MLX5_QP_BIT_RAE) | |
5266 | ib_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
5267 | ||
5268 | return ib_flags; | |
5269 | } | |
5270 | ||
38349389 | 5271 | static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev, |
d8966fcd | 5272 | struct rdma_ah_attr *ah_attr, |
38349389 | 5273 | struct mlx5_qp_path *path) |
e126ba97 | 5274 | { |
e126ba97 | 5275 | |
d8966fcd | 5276 | memset(ah_attr, 0, sizeof(*ah_attr)); |
e126ba97 | 5277 | |
e7996a9a | 5278 | if (!path->port || path->port > ibdev->num_ports) |
e126ba97 EC |
5279 | return; |
5280 | ||
ae59c3f0 LR |
5281 | ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port); |
5282 | ||
d8966fcd DC |
5283 | rdma_ah_set_port_num(ah_attr, path->port); |
5284 | rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf); | |
5285 | ||
5286 | rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); | |
5287 | rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f); | |
5288 | rdma_ah_set_static_rate(ah_attr, | |
5289 | path->static_rate ? path->static_rate - 5 : 0); | |
5290 | if (path->grh_mlid & (1 << 7)) { | |
5291 | u32 tc_fl = be32_to_cpu(path->tclass_flowlabel); | |
5292 | ||
5293 | rdma_ah_set_grh(ah_attr, NULL, | |
5294 | tc_fl & 0xfffff, | |
5295 | path->mgid_index, | |
5296 | path->hop_limit, | |
5297 | (tc_fl >> 20) & 0xff); | |
5298 | rdma_ah_set_dgid_raw(ah_attr, path->rgid); | |
e126ba97 EC |
5299 | } |
5300 | } | |
5301 | ||
6d2f89df | 5302 | static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev, |
5303 | struct mlx5_ib_sq *sq, | |
5304 | u8 *sq_state) | |
5305 | { | |
6d2f89df | 5306 | int err; |
5307 | ||
28160771 | 5308 | err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state); |
6d2f89df | 5309 | if (err) |
5310 | goto out; | |
6d2f89df | 5311 | sq->state = *sq_state; |
5312 | ||
5313 | out: | |
6d2f89df | 5314 | return err; |
5315 | } | |
5316 | ||
5317 | static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev, | |
5318 | struct mlx5_ib_rq *rq, | |
5319 | u8 *rq_state) | |
5320 | { | |
5321 | void *out; | |
5322 | void *rqc; | |
5323 | int inlen; | |
5324 | int err; | |
5325 | ||
5326 | inlen = MLX5_ST_SZ_BYTES(query_rq_out); | |
1b9a07ee | 5327 | out = kvzalloc(inlen, GFP_KERNEL); |
6d2f89df | 5328 | if (!out) |
5329 | return -ENOMEM; | |
5330 | ||
5331 | err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out); | |
5332 | if (err) | |
5333 | goto out; | |
5334 | ||
5335 | rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context); | |
5336 | *rq_state = MLX5_GET(rqc, rqc, state); | |
5337 | rq->state = *rq_state; | |
5338 | ||
5339 | out: | |
5340 | kvfree(out); | |
5341 | return err; | |
5342 | } | |
5343 | ||
5344 | static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state, | |
5345 | struct mlx5_ib_qp *qp, u8 *qp_state) | |
5346 | { | |
5347 | static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = { | |
5348 | [MLX5_RQC_STATE_RST] = { | |
5349 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
5350 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
5351 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD, | |
5352 | [MLX5_SQ_STATE_NA] = IB_QPS_RESET, | |
5353 | }, | |
5354 | [MLX5_RQC_STATE_RDY] = { | |
5355 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
5356 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
5357 | [MLX5_SQC_STATE_ERR] = IB_QPS_SQE, | |
5358 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE, | |
5359 | }, | |
5360 | [MLX5_RQC_STATE_ERR] = { | |
5361 | [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD, | |
5362 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD, | |
5363 | [MLX5_SQC_STATE_ERR] = IB_QPS_ERR, | |
5364 | [MLX5_SQ_STATE_NA] = IB_QPS_ERR, | |
5365 | }, | |
5366 | [MLX5_RQ_STATE_NA] = { | |
5367 | [MLX5_SQC_STATE_RST] = IB_QPS_RESET, | |
5368 | [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE, | |
5369 | [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE, | |
5370 | [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD, | |
5371 | }, | |
5372 | }; | |
5373 | ||
5374 | *qp_state = sqrq_trans[rq_state][sq_state]; | |
5375 | ||
5376 | if (*qp_state == MLX5_QP_STATE_BAD) { | |
5377 | WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x", | |
5378 | qp->raw_packet_qp.sq.base.mqp.qpn, sq_state, | |
5379 | qp->raw_packet_qp.rq.base.mqp.qpn, rq_state); | |
5380 | return -EINVAL; | |
5381 | } | |
5382 | ||
5383 | if (*qp_state == MLX5_QP_STATE) | |
5384 | *qp_state = qp->state; | |
5385 | ||
5386 | return 0; | |
5387 | } | |
5388 | ||
5389 | static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev, | |
5390 | struct mlx5_ib_qp *qp, | |
5391 | u8 *raw_packet_qp_state) | |
5392 | { | |
5393 | struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp; | |
5394 | struct mlx5_ib_sq *sq = &raw_packet_qp->sq; | |
5395 | struct mlx5_ib_rq *rq = &raw_packet_qp->rq; | |
5396 | int err; | |
5397 | u8 sq_state = MLX5_SQ_STATE_NA; | |
5398 | u8 rq_state = MLX5_RQ_STATE_NA; | |
5399 | ||
5400 | if (qp->sq.wqe_cnt) { | |
5401 | err = query_raw_packet_qp_sq_state(dev, sq, &sq_state); | |
5402 | if (err) | |
5403 | return err; | |
5404 | } | |
5405 | ||
5406 | if (qp->rq.wqe_cnt) { | |
5407 | err = query_raw_packet_qp_rq_state(dev, rq, &rq_state); | |
5408 | if (err) | |
5409 | return err; | |
5410 | } | |
5411 | ||
5412 | return sqrq_state_to_qp_state(sq_state, rq_state, qp, | |
5413 | raw_packet_qp_state); | |
5414 | } | |
5415 | ||
5416 | static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp, | |
5417 | struct ib_qp_attr *qp_attr) | |
e126ba97 | 5418 | { |
09a7d9ec | 5419 | int outlen = MLX5_ST_SZ_BYTES(query_qp_out); |
e126ba97 EC |
5420 | struct mlx5_qp_context *context; |
5421 | int mlx5_state; | |
09a7d9ec | 5422 | u32 *outb; |
e126ba97 EC |
5423 | int err = 0; |
5424 | ||
09a7d9ec | 5425 | outb = kzalloc(outlen, GFP_KERNEL); |
6d2f89df | 5426 | if (!outb) |
5427 | return -ENOMEM; | |
5428 | ||
19098df2 | 5429 | err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb, |
09a7d9ec | 5430 | outlen); |
e126ba97 | 5431 | if (err) |
6d2f89df | 5432 | goto out; |
e126ba97 | 5433 | |
09a7d9ec SM |
5434 | /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */ |
5435 | context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc); | |
5436 | ||
e126ba97 EC |
5437 | mlx5_state = be32_to_cpu(context->flags) >> 28; |
5438 | ||
5439 | qp->state = to_ib_qp_state(mlx5_state); | |
e126ba97 EC |
5440 | qp_attr->path_mtu = context->mtu_msgmax >> 5; |
5441 | qp_attr->path_mig_state = | |
5442 | to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3); | |
5443 | qp_attr->qkey = be32_to_cpu(context->qkey); | |
5444 | qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; | |
5445 | qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; | |
5446 | qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff; | |
5447 | qp_attr->qp_access_flags = | |
5448 | to_ib_qp_access_flags(be32_to_cpu(context->params2)); | |
5449 | ||
5450 | if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { | |
38349389 DC |
5451 | to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); |
5452 | to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path); | |
d3ae2bde NO |
5453 | qp_attr->alt_pkey_index = |
5454 | be16_to_cpu(context->alt_path.pkey_index); | |
d8966fcd DC |
5455 | qp_attr->alt_port_num = |
5456 | rdma_ah_get_port_num(&qp_attr->alt_ah_attr); | |
e126ba97 EC |
5457 | } |
5458 | ||
d3ae2bde | 5459 | qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index); |
e126ba97 EC |
5460 | qp_attr->port_num = context->pri_path.port; |
5461 | ||
5462 | /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ | |
5463 | qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING; | |
5464 | ||
5465 | qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7); | |
5466 | ||
5467 | qp_attr->max_dest_rd_atomic = | |
5468 | 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7); | |
5469 | qp_attr->min_rnr_timer = | |
5470 | (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; | |
5471 | qp_attr->timeout = context->pri_path.ackto_lt >> 3; | |
5472 | qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7; | |
5473 | qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7; | |
5474 | qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3; | |
6d2f89df | 5475 | |
5476 | out: | |
5477 | kfree(outb); | |
5478 | return err; | |
5479 | } | |
5480 | ||
776a3906 MS |
5481 | static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp, |
5482 | struct ib_qp_attr *qp_attr, int qp_attr_mask, | |
5483 | struct ib_qp_init_attr *qp_init_attr) | |
5484 | { | |
5485 | struct mlx5_core_dct *dct = &mqp->dct.mdct; | |
5486 | u32 *out; | |
5487 | u32 access_flags = 0; | |
5488 | int outlen = MLX5_ST_SZ_BYTES(query_dct_out); | |
5489 | void *dctc; | |
5490 | int err; | |
5491 | int supported_mask = IB_QP_STATE | | |
5492 | IB_QP_ACCESS_FLAGS | | |
5493 | IB_QP_PORT | | |
5494 | IB_QP_MIN_RNR_TIMER | | |
5495 | IB_QP_AV | | |
5496 | IB_QP_PATH_MTU | | |
5497 | IB_QP_PKEY_INDEX; | |
5498 | ||
5499 | if (qp_attr_mask & ~supported_mask) | |
5500 | return -EINVAL; | |
5501 | if (mqp->state != IB_QPS_RTR) | |
5502 | return -EINVAL; | |
5503 | ||
5504 | out = kzalloc(outlen, GFP_KERNEL); | |
5505 | if (!out) | |
5506 | return -ENOMEM; | |
5507 | ||
5508 | err = mlx5_core_dct_query(dev->mdev, dct, out, outlen); | |
5509 | if (err) | |
5510 | goto out; | |
5511 | ||
5512 | dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry); | |
5513 | ||
5514 | if (qp_attr_mask & IB_QP_STATE) | |
5515 | qp_attr->qp_state = IB_QPS_RTR; | |
5516 | ||
5517 | if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { | |
5518 | if (MLX5_GET(dctc, dctc, rre)) | |
5519 | access_flags |= IB_ACCESS_REMOTE_READ; | |
5520 | if (MLX5_GET(dctc, dctc, rwe)) | |
5521 | access_flags |= IB_ACCESS_REMOTE_WRITE; | |
5522 | if (MLX5_GET(dctc, dctc, rae)) | |
5523 | access_flags |= IB_ACCESS_REMOTE_ATOMIC; | |
5524 | qp_attr->qp_access_flags = access_flags; | |
5525 | } | |
5526 | ||
5527 | if (qp_attr_mask & IB_QP_PORT) | |
5528 | qp_attr->port_num = MLX5_GET(dctc, dctc, port); | |
5529 | if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) | |
5530 | qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak); | |
5531 | if (qp_attr_mask & IB_QP_AV) { | |
5532 | qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass); | |
5533 | qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label); | |
5534 | qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index); | |
5535 | qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit); | |
5536 | } | |
5537 | if (qp_attr_mask & IB_QP_PATH_MTU) | |
5538 | qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu); | |
5539 | if (qp_attr_mask & IB_QP_PKEY_INDEX) | |
5540 | qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index); | |
5541 | out: | |
5542 | kfree(out); | |
5543 | return err; | |
5544 | } | |
5545 | ||
6d2f89df | 5546 | int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, |
5547 | int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) | |
5548 | { | |
5549 | struct mlx5_ib_dev *dev = to_mdev(ibqp->device); | |
5550 | struct mlx5_ib_qp *qp = to_mqp(ibqp); | |
5551 | int err = 0; | |
5552 | u8 raw_packet_qp_state; | |
5553 | ||
28d61370 YH |
5554 | if (ibqp->rwq_ind_tbl) |
5555 | return -ENOSYS; | |
5556 | ||
d16e91da HE |
5557 | if (unlikely(ibqp->qp_type == IB_QPT_GSI)) |
5558 | return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask, | |
5559 | qp_init_attr); | |
5560 | ||
c2e53b2c YH |
5561 | /* Not all of output fields are applicable, make sure to zero them */ |
5562 | memset(qp_init_attr, 0, sizeof(*qp_init_attr)); | |
5563 | memset(qp_attr, 0, sizeof(*qp_attr)); | |
5564 | ||
776a3906 MS |
5565 | if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT)) |
5566 | return mlx5_ib_dct_query_qp(dev, qp, qp_attr, | |
5567 | qp_attr_mask, qp_init_attr); | |
5568 | ||
6d2f89df | 5569 | mutex_lock(&qp->mutex); |
5570 | ||
c2e53b2c YH |
5571 | if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET || |
5572 | qp->flags & MLX5_IB_QP_UNDERLAY) { | |
6d2f89df | 5573 | err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state); |
5574 | if (err) | |
5575 | goto out; | |
5576 | qp->state = raw_packet_qp_state; | |
5577 | qp_attr->port_num = 1; | |
5578 | } else { | |
5579 | err = query_qp_attr(dev, qp, qp_attr); | |
5580 | if (err) | |
5581 | goto out; | |
5582 | } | |
5583 | ||
5584 | qp_attr->qp_state = qp->state; | |
e126ba97 EC |
5585 | qp_attr->cur_qp_state = qp_attr->qp_state; |
5586 | qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; | |
5587 | qp_attr->cap.max_recv_sge = qp->rq.max_gs; | |
5588 | ||
5589 | if (!ibqp->uobject) { | |
0540d814 | 5590 | qp_attr->cap.max_send_wr = qp->sq.max_post; |
e126ba97 | 5591 | qp_attr->cap.max_send_sge = qp->sq.max_gs; |
0540d814 | 5592 | qp_init_attr->qp_context = ibqp->qp_context; |
e126ba97 EC |
5593 | } else { |
5594 | qp_attr->cap.max_send_wr = 0; | |
5595 | qp_attr->cap.max_send_sge = 0; | |
5596 | } | |
5597 | ||
0540d814 NO |
5598 | qp_init_attr->qp_type = ibqp->qp_type; |
5599 | qp_init_attr->recv_cq = ibqp->recv_cq; | |
5600 | qp_init_attr->send_cq = ibqp->send_cq; | |
5601 | qp_init_attr->srq = ibqp->srq; | |
5602 | qp_attr->cap.max_inline_data = qp->max_inline_data; | |
e126ba97 EC |
5603 | |
5604 | qp_init_attr->cap = qp_attr->cap; | |
5605 | ||
5606 | qp_init_attr->create_flags = 0; | |
5607 | if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK) | |
5608 | qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; | |
5609 | ||
051f2630 LR |
5610 | if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) |
5611 | qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL; | |
5612 | if (qp->flags & MLX5_IB_QP_MANAGED_SEND) | |
5613 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND; | |
5614 | if (qp->flags & MLX5_IB_QP_MANAGED_RECV) | |
5615 | qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV; | |
b11a4f9c HE |
5616 | if (qp->flags & MLX5_IB_QP_SQPN_QP1) |
5617 | qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1(); | |
051f2630 | 5618 | |
e126ba97 EC |
5619 | qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ? |
5620 | IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; | |
5621 | ||
e126ba97 EC |
5622 | out: |
5623 | mutex_unlock(&qp->mutex); | |
5624 | return err; | |
5625 | } | |
5626 | ||
5627 | struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev, | |
5628 | struct ib_ucontext *context, | |
5629 | struct ib_udata *udata) | |
5630 | { | |
5631 | struct mlx5_ib_dev *dev = to_mdev(ibdev); | |
5632 | struct mlx5_ib_xrcd *xrcd; | |
5633 | int err; | |
5634 | ||
938fe83c | 5635 | if (!MLX5_CAP_GEN(dev->mdev, xrc)) |
e126ba97 EC |
5636 | return ERR_PTR(-ENOSYS); |
5637 | ||
5638 | xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL); | |
5639 | if (!xrcd) | |
5640 | return ERR_PTR(-ENOMEM); | |
5641 | ||
5aa3771d | 5642 | err = mlx5_cmd_xrcd_alloc(dev->mdev, &xrcd->xrcdn, 0); |
e126ba97 EC |
5643 | if (err) { |
5644 | kfree(xrcd); | |
5645 | return ERR_PTR(-ENOMEM); | |
5646 | } | |
5647 | ||
5648 | return &xrcd->ibxrcd; | |
5649 | } | |
5650 | ||
5651 | int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd) | |
5652 | { | |
5653 | struct mlx5_ib_dev *dev = to_mdev(xrcd->device); | |
5654 | u32 xrcdn = to_mxrcd(xrcd)->xrcdn; | |
5655 | int err; | |
5656 | ||
5aa3771d | 5657 | err = mlx5_cmd_xrcd_dealloc(dev->mdev, xrcdn, 0); |
b081808a | 5658 | if (err) |
e126ba97 | 5659 | mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn); |
e126ba97 EC |
5660 | |
5661 | kfree(xrcd); | |
e126ba97 EC |
5662 | return 0; |
5663 | } | |
79b20a6c | 5664 | |
350d0e4c YH |
5665 | static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type) |
5666 | { | |
5667 | struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp); | |
5668 | struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device); | |
5669 | struct ib_event event; | |
5670 | ||
5671 | if (rwq->ibwq.event_handler) { | |
5672 | event.device = rwq->ibwq.device; | |
5673 | event.element.wq = &rwq->ibwq; | |
5674 | switch (type) { | |
5675 | case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: | |
5676 | event.event = IB_EVENT_WQ_FATAL; | |
5677 | break; | |
5678 | default: | |
5679 | mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn); | |
5680 | return; | |
5681 | } | |
5682 | ||
5683 | rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context); | |
5684 | } | |
5685 | } | |
5686 | ||
03404e8a MG |
5687 | static int set_delay_drop(struct mlx5_ib_dev *dev) |
5688 | { | |
5689 | int err = 0; | |
5690 | ||
5691 | mutex_lock(&dev->delay_drop.lock); | |
5692 | if (dev->delay_drop.activate) | |
5693 | goto out; | |
5694 | ||
5695 | err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout); | |
5696 | if (err) | |
5697 | goto out; | |
5698 | ||
5699 | dev->delay_drop.activate = true; | |
5700 | out: | |
5701 | mutex_unlock(&dev->delay_drop.lock); | |
fe248c3a MG |
5702 | |
5703 | if (!err) | |
5704 | atomic_inc(&dev->delay_drop.rqs_cnt); | |
03404e8a MG |
5705 | return err; |
5706 | } | |
5707 | ||
79b20a6c YH |
5708 | static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd, |
5709 | struct ib_wq_init_attr *init_attr) | |
5710 | { | |
5711 | struct mlx5_ib_dev *dev; | |
4be6da1e | 5712 | int has_net_offloads; |
79b20a6c YH |
5713 | __be64 *rq_pas0; |
5714 | void *in; | |
5715 | void *rqc; | |
5716 | void *wq; | |
5717 | int inlen; | |
5718 | int err; | |
5719 | ||
5720 | dev = to_mdev(pd->device); | |
5721 | ||
5722 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas; | |
1b9a07ee | 5723 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
5724 | if (!in) |
5725 | return -ENOMEM; | |
5726 | ||
34d57585 | 5727 | MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid); |
79b20a6c YH |
5728 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); |
5729 | MLX5_SET(rqc, rqc, mem_rq_type, | |
5730 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE); | |
5731 | MLX5_SET(rqc, rqc, user_index, rwq->user_index); | |
5732 | MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn); | |
5733 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); | |
5734 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
5735 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
ccc87087 NO |
5736 | MLX5_SET(wq, wq, wq_type, |
5737 | rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ? | |
5738 | MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC); | |
b1383aa6 NO |
5739 | if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { |
5740 | if (!MLX5_CAP_GEN(dev->mdev, end_pad)) { | |
5741 | mlx5_ib_dbg(dev, "Scatter end padding is not supported\n"); | |
5742 | err = -EOPNOTSUPP; | |
5743 | goto out; | |
5744 | } else { | |
5745 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
5746 | } | |
5747 | } | |
79b20a6c | 5748 | MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride); |
ccc87087 NO |
5749 | if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) { |
5750 | MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en); | |
5751 | MLX5_SET(wq, wq, log_wqe_stride_size, | |
5752 | rwq->single_stride_log_num_of_bytes - | |
5753 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES); | |
5754 | MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides - | |
5755 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES); | |
5756 | } | |
79b20a6c YH |
5757 | MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size); |
5758 | MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn); | |
5759 | MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset); | |
5760 | MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size); | |
5761 | MLX5_SET(wq, wq, wq_signature, rwq->wq_sig); | |
5762 | MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma); | |
4be6da1e | 5763 | has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads); |
b1f74a84 | 5764 | if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) { |
4be6da1e | 5765 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { |
b1f74a84 NO |
5766 | mlx5_ib_dbg(dev, "VLAN offloads are not supported\n"); |
5767 | err = -EOPNOTSUPP; | |
5768 | goto out; | |
5769 | } | |
5770 | } else { | |
5771 | MLX5_SET(rqc, rqc, vsd, 1); | |
5772 | } | |
4be6da1e NO |
5773 | if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) { |
5774 | if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { | |
5775 | mlx5_ib_dbg(dev, "Scatter FCS is not supported\n"); | |
5776 | err = -EOPNOTSUPP; | |
5777 | goto out; | |
5778 | } | |
5779 | MLX5_SET(rqc, rqc, scatter_fcs, 1); | |
5780 | } | |
03404e8a MG |
5781 | if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
5782 | if (!(dev->ib_dev.attrs.raw_packet_caps & | |
5783 | IB_RAW_PACKET_CAP_DELAY_DROP)) { | |
5784 | mlx5_ib_dbg(dev, "Delay drop is not supported\n"); | |
5785 | err = -EOPNOTSUPP; | |
5786 | goto out; | |
5787 | } | |
5788 | MLX5_SET(rqc, rqc, delay_drop_en, 1); | |
5789 | } | |
79b20a6c YH |
5790 | rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas); |
5791 | mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0); | |
350d0e4c | 5792 | err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp); |
03404e8a MG |
5793 | if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) { |
5794 | err = set_delay_drop(dev); | |
5795 | if (err) { | |
5796 | mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n", | |
5797 | err); | |
5798 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); | |
5799 | } else { | |
5800 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP; | |
5801 | } | |
5802 | } | |
b1f74a84 | 5803 | out: |
79b20a6c YH |
5804 | kvfree(in); |
5805 | return err; | |
5806 | } | |
5807 | ||
5808 | static int set_user_rq_size(struct mlx5_ib_dev *dev, | |
5809 | struct ib_wq_init_attr *wq_init_attr, | |
5810 | struct mlx5_ib_create_wq *ucmd, | |
5811 | struct mlx5_ib_rwq *rwq) | |
5812 | { | |
5813 | /* Sanity check RQ size before proceeding */ | |
5814 | if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz))) | |
5815 | return -EINVAL; | |
5816 | ||
5817 | if (!ucmd->rq_wqe_count) | |
5818 | return -EINVAL; | |
5819 | ||
5820 | rwq->wqe_count = ucmd->rq_wqe_count; | |
5821 | rwq->wqe_shift = ucmd->rq_wqe_shift; | |
0dfe4522 LR |
5822 | if (check_shl_overflow(rwq->wqe_count, rwq->wqe_shift, &rwq->buf_size)) |
5823 | return -EINVAL; | |
5824 | ||
79b20a6c YH |
5825 | rwq->log_rq_stride = rwq->wqe_shift; |
5826 | rwq->log_rq_size = ilog2(rwq->wqe_count); | |
5827 | return 0; | |
5828 | } | |
5829 | ||
5830 | static int prepare_user_rq(struct ib_pd *pd, | |
5831 | struct ib_wq_init_attr *init_attr, | |
5832 | struct ib_udata *udata, | |
5833 | struct mlx5_ib_rwq *rwq) | |
5834 | { | |
5835 | struct mlx5_ib_dev *dev = to_mdev(pd->device); | |
5836 | struct mlx5_ib_create_wq ucmd = {}; | |
5837 | int err; | |
5838 | size_t required_cmd_sz; | |
5839 | ||
ccc87087 NO |
5840 | required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes) |
5841 | + sizeof(ucmd.single_stride_log_num_of_bytes); | |
79b20a6c YH |
5842 | if (udata->inlen < required_cmd_sz) { |
5843 | mlx5_ib_dbg(dev, "invalid inlen\n"); | |
5844 | return -EINVAL; | |
5845 | } | |
5846 | ||
5847 | if (udata->inlen > sizeof(ucmd) && | |
5848 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
5849 | udata->inlen - sizeof(ucmd))) { | |
5850 | mlx5_ib_dbg(dev, "inlen is not supported\n"); | |
5851 | return -EOPNOTSUPP; | |
5852 | } | |
5853 | ||
5854 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) { | |
5855 | mlx5_ib_dbg(dev, "copy failed\n"); | |
5856 | return -EFAULT; | |
5857 | } | |
5858 | ||
ccc87087 | 5859 | if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) { |
79b20a6c YH |
5860 | mlx5_ib_dbg(dev, "invalid comp mask\n"); |
5861 | return -EOPNOTSUPP; | |
ccc87087 NO |
5862 | } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) { |
5863 | if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) { | |
5864 | mlx5_ib_dbg(dev, "Striding RQ is not supported\n"); | |
5865 | return -EOPNOTSUPP; | |
5866 | } | |
5867 | if ((ucmd.single_stride_log_num_of_bytes < | |
5868 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) || | |
5869 | (ucmd.single_stride_log_num_of_bytes > | |
5870 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) { | |
5871 | mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n", | |
5872 | ucmd.single_stride_log_num_of_bytes, | |
5873 | MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES, | |
5874 | MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES); | |
5875 | return -EINVAL; | |
5876 | } | |
5877 | if ((ucmd.single_wqe_log_num_of_strides > | |
5878 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) || | |
5879 | (ucmd.single_wqe_log_num_of_strides < | |
5880 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) { | |
5881 | mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n", | |
5882 | ucmd.single_wqe_log_num_of_strides, | |
5883 | MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES, | |
5884 | MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES); | |
5885 | return -EINVAL; | |
5886 | } | |
5887 | rwq->single_stride_log_num_of_bytes = | |
5888 | ucmd.single_stride_log_num_of_bytes; | |
5889 | rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides; | |
5890 | rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en; | |
5891 | rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ; | |
79b20a6c YH |
5892 | } |
5893 | ||
5894 | err = set_user_rq_size(dev, init_attr, &ucmd, rwq); | |
5895 | if (err) { | |
5896 | mlx5_ib_dbg(dev, "err %d\n", err); | |
5897 | return err; | |
5898 | } | |
5899 | ||
b0ea0fa5 | 5900 | err = create_user_rq(dev, pd, udata, rwq, &ucmd); |
79b20a6c YH |
5901 | if (err) { |
5902 | mlx5_ib_dbg(dev, "err %d\n", err); | |
645ba597 | 5903 | return err; |
79b20a6c YH |
5904 | } |
5905 | ||
5906 | rwq->user_index = ucmd.user_index; | |
5907 | return 0; | |
5908 | } | |
5909 | ||
5910 | struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, | |
5911 | struct ib_wq_init_attr *init_attr, | |
5912 | struct ib_udata *udata) | |
5913 | { | |
5914 | struct mlx5_ib_dev *dev; | |
5915 | struct mlx5_ib_rwq *rwq; | |
5916 | struct mlx5_ib_create_wq_resp resp = {}; | |
5917 | size_t min_resp_len; | |
5918 | int err; | |
5919 | ||
5920 | if (!udata) | |
5921 | return ERR_PTR(-ENOSYS); | |
5922 | ||
5923 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); | |
5924 | if (udata->outlen && udata->outlen < min_resp_len) | |
5925 | return ERR_PTR(-EINVAL); | |
5926 | ||
5927 | dev = to_mdev(pd->device); | |
5928 | switch (init_attr->wq_type) { | |
5929 | case IB_WQT_RQ: | |
5930 | rwq = kzalloc(sizeof(*rwq), GFP_KERNEL); | |
5931 | if (!rwq) | |
5932 | return ERR_PTR(-ENOMEM); | |
5933 | err = prepare_user_rq(pd, init_attr, udata, rwq); | |
5934 | if (err) | |
5935 | goto err; | |
5936 | err = create_rq(rwq, pd, init_attr); | |
5937 | if (err) | |
5938 | goto err_user_rq; | |
5939 | break; | |
5940 | default: | |
5941 | mlx5_ib_dbg(dev, "unsupported wq type %d\n", | |
5942 | init_attr->wq_type); | |
5943 | return ERR_PTR(-EINVAL); | |
5944 | } | |
5945 | ||
350d0e4c | 5946 | rwq->ibwq.wq_num = rwq->core_qp.qpn; |
79b20a6c YH |
5947 | rwq->ibwq.state = IB_WQS_RESET; |
5948 | if (udata->outlen) { | |
5949 | resp.response_length = offsetof(typeof(resp), response_length) + | |
5950 | sizeof(resp.response_length); | |
5951 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
5952 | if (err) | |
5953 | goto err_copy; | |
5954 | } | |
5955 | ||
350d0e4c YH |
5956 | rwq->core_qp.event = mlx5_ib_wq_event; |
5957 | rwq->ibwq.event_handler = init_attr->event_handler; | |
79b20a6c YH |
5958 | return &rwq->ibwq; |
5959 | ||
5960 | err_copy: | |
350d0e4c | 5961 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
79b20a6c | 5962 | err_user_rq: |
fe248c3a | 5963 | destroy_user_rq(dev, pd, rwq); |
79b20a6c YH |
5964 | err: |
5965 | kfree(rwq); | |
5966 | return ERR_PTR(err); | |
5967 | } | |
5968 | ||
5969 | int mlx5_ib_destroy_wq(struct ib_wq *wq) | |
5970 | { | |
5971 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
5972 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
5973 | ||
350d0e4c | 5974 | mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp); |
fe248c3a | 5975 | destroy_user_rq(dev, wq->pd, rwq); |
79b20a6c YH |
5976 | kfree(rwq); |
5977 | ||
5978 | return 0; | |
5979 | } | |
5980 | ||
c5f90929 YH |
5981 | struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, |
5982 | struct ib_rwq_ind_table_init_attr *init_attr, | |
5983 | struct ib_udata *udata) | |
5984 | { | |
5985 | struct mlx5_ib_dev *dev = to_mdev(device); | |
5986 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl; | |
5987 | int sz = 1 << init_attr->log_ind_tbl_size; | |
5988 | struct mlx5_ib_create_rwq_ind_tbl_resp resp = {}; | |
5989 | size_t min_resp_len; | |
5990 | int inlen; | |
5991 | int err; | |
5992 | int i; | |
5993 | u32 *in; | |
5994 | void *rqtc; | |
5995 | ||
5996 | if (udata->inlen > 0 && | |
5997 | !ib_is_udata_cleared(udata, 0, | |
5998 | udata->inlen)) | |
5999 | return ERR_PTR(-EOPNOTSUPP); | |
6000 | ||
efd7f400 MG |
6001 | if (init_attr->log_ind_tbl_size > |
6002 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) { | |
6003 | mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n", | |
6004 | init_attr->log_ind_tbl_size, | |
6005 | MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)); | |
6006 | return ERR_PTR(-EINVAL); | |
6007 | } | |
6008 | ||
c5f90929 YH |
6009 | min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved); |
6010 | if (udata->outlen && udata->outlen < min_resp_len) | |
6011 | return ERR_PTR(-EINVAL); | |
6012 | ||
6013 | rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL); | |
6014 | if (!rwq_ind_tbl) | |
6015 | return ERR_PTR(-ENOMEM); | |
6016 | ||
6017 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
1b9a07ee | 6018 | in = kvzalloc(inlen, GFP_KERNEL); |
c5f90929 YH |
6019 | if (!in) { |
6020 | err = -ENOMEM; | |
6021 | goto err; | |
6022 | } | |
6023 | ||
6024 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
6025 | ||
6026 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
6027 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
6028 | ||
6029 | for (i = 0; i < sz; i++) | |
6030 | MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num); | |
6031 | ||
5deba86e YH |
6032 | rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid; |
6033 | MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid); | |
6034 | ||
c5f90929 YH |
6035 | err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn); |
6036 | kvfree(in); | |
6037 | ||
6038 | if (err) | |
6039 | goto err; | |
6040 | ||
6041 | rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn; | |
6042 | if (udata->outlen) { | |
6043 | resp.response_length = offsetof(typeof(resp), response_length) + | |
6044 | sizeof(resp.response_length); | |
6045 | err = ib_copy_to_udata(udata, &resp, resp.response_length); | |
6046 | if (err) | |
6047 | goto err_copy; | |
6048 | } | |
6049 | ||
6050 | return &rwq_ind_tbl->ib_rwq_ind_tbl; | |
6051 | ||
6052 | err_copy: | |
5deba86e | 6053 | mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); |
c5f90929 YH |
6054 | err: |
6055 | kfree(rwq_ind_tbl); | |
6056 | return ERR_PTR(err); | |
6057 | } | |
6058 | ||
6059 | int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) | |
6060 | { | |
6061 | struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl); | |
6062 | struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device); | |
6063 | ||
5deba86e | 6064 | mlx5_cmd_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid); |
c5f90929 YH |
6065 | |
6066 | kfree(rwq_ind_tbl); | |
6067 | return 0; | |
6068 | } | |
6069 | ||
79b20a6c YH |
6070 | int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, |
6071 | u32 wq_attr_mask, struct ib_udata *udata) | |
6072 | { | |
6073 | struct mlx5_ib_dev *dev = to_mdev(wq->device); | |
6074 | struct mlx5_ib_rwq *rwq = to_mrwq(wq); | |
6075 | struct mlx5_ib_modify_wq ucmd = {}; | |
6076 | size_t required_cmd_sz; | |
6077 | int curr_wq_state; | |
6078 | int wq_state; | |
6079 | int inlen; | |
6080 | int err; | |
6081 | void *rqc; | |
6082 | void *in; | |
6083 | ||
6084 | required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved); | |
6085 | if (udata->inlen < required_cmd_sz) | |
6086 | return -EINVAL; | |
6087 | ||
6088 | if (udata->inlen > sizeof(ucmd) && | |
6089 | !ib_is_udata_cleared(udata, sizeof(ucmd), | |
6090 | udata->inlen - sizeof(ucmd))) | |
6091 | return -EOPNOTSUPP; | |
6092 | ||
6093 | if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) | |
6094 | return -EFAULT; | |
6095 | ||
6096 | if (ucmd.comp_mask || ucmd.reserved) | |
6097 | return -EOPNOTSUPP; | |
6098 | ||
6099 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 6100 | in = kvzalloc(inlen, GFP_KERNEL); |
79b20a6c YH |
6101 | if (!in) |
6102 | return -ENOMEM; | |
6103 | ||
6104 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
6105 | ||
6106 | curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ? | |
6107 | wq_attr->curr_wq_state : wq->state; | |
6108 | wq_state = (wq_attr_mask & IB_WQ_STATE) ? | |
6109 | wq_attr->wq_state : curr_wq_state; | |
6110 | if (curr_wq_state == IB_WQS_ERR) | |
6111 | curr_wq_state = MLX5_RQC_STATE_ERR; | |
6112 | if (wq_state == IB_WQS_ERR) | |
6113 | wq_state = MLX5_RQC_STATE_ERR; | |
6114 | MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state); | |
34d57585 | 6115 | MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid); |
79b20a6c YH |
6116 | MLX5_SET(rqc, rqc, state, wq_state); |
6117 | ||
b1f74a84 NO |
6118 | if (wq_attr_mask & IB_WQ_FLAGS) { |
6119 | if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) { | |
6120 | if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && | |
6121 | MLX5_CAP_ETH(dev->mdev, vlan_cap))) { | |
6122 | mlx5_ib_dbg(dev, "VLAN offloads are not " | |
6123 | "supported\n"); | |
6124 | err = -EOPNOTSUPP; | |
6125 | goto out; | |
6126 | } | |
6127 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
6128 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
6129 | MLX5_SET(rqc, rqc, vsd, | |
6130 | (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1); | |
6131 | } | |
b1383aa6 NO |
6132 | |
6133 | if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) { | |
6134 | mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n"); | |
6135 | err = -EOPNOTSUPP; | |
6136 | goto out; | |
6137 | } | |
b1f74a84 NO |
6138 | } |
6139 | ||
23a6964e MD |
6140 | if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) { |
6141 | if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) { | |
6142 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
6143 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID); | |
e1f24a79 PP |
6144 | MLX5_SET(rqc, rqc, counter_set_id, |
6145 | dev->port->cnts.set_id); | |
23a6964e | 6146 | } else |
5a738b5d JG |
6147 | dev_info_once( |
6148 | &dev->ib_dev.dev, | |
6149 | "Receive WQ counters are not supported on current FW\n"); | |
23a6964e MD |
6150 | } |
6151 | ||
350d0e4c | 6152 | err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen); |
79b20a6c YH |
6153 | if (!err) |
6154 | rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state; | |
6155 | ||
b1f74a84 NO |
6156 | out: |
6157 | kvfree(in); | |
79b20a6c YH |
6158 | return err; |
6159 | } | |
d0e84c0a YH |
6160 | |
6161 | struct mlx5_ib_drain_cqe { | |
6162 | struct ib_cqe cqe; | |
6163 | struct completion done; | |
6164 | }; | |
6165 | ||
6166 | static void mlx5_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc) | |
6167 | { | |
6168 | struct mlx5_ib_drain_cqe *cqe = container_of(wc->wr_cqe, | |
6169 | struct mlx5_ib_drain_cqe, | |
6170 | cqe); | |
6171 | ||
6172 | complete(&cqe->done); | |
6173 | } | |
6174 | ||
6175 | /* This function returns only once the drained WR was completed */ | |
6176 | static void handle_drain_completion(struct ib_cq *cq, | |
6177 | struct mlx5_ib_drain_cqe *sdrain, | |
6178 | struct mlx5_ib_dev *dev) | |
6179 | { | |
6180 | struct mlx5_core_dev *mdev = dev->mdev; | |
6181 | ||
6182 | if (cq->poll_ctx == IB_POLL_DIRECT) { | |
6183 | while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0) | |
6184 | ib_process_cq_direct(cq, -1); | |
6185 | return; | |
6186 | } | |
6187 | ||
6188 | if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6189 | struct mlx5_ib_cq *mcq = to_mcq(cq); | |
6190 | bool triggered = false; | |
6191 | unsigned long flags; | |
6192 | ||
6193 | spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); | |
6194 | /* Make sure that the CQ handler won't run if wasn't run yet */ | |
6195 | if (!mcq->mcq.reset_notify_added) | |
6196 | mcq->mcq.reset_notify_added = 1; | |
6197 | else | |
6198 | triggered = true; | |
6199 | spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); | |
6200 | ||
6201 | if (triggered) { | |
6202 | /* Wait for any scheduled/running task to be ended */ | |
6203 | switch (cq->poll_ctx) { | |
6204 | case IB_POLL_SOFTIRQ: | |
6205 | irq_poll_disable(&cq->iop); | |
6206 | irq_poll_enable(&cq->iop); | |
6207 | break; | |
6208 | case IB_POLL_WORKQUEUE: | |
6209 | cancel_work_sync(&cq->work); | |
6210 | break; | |
6211 | default: | |
6212 | WARN_ON_ONCE(1); | |
6213 | } | |
6214 | } | |
6215 | ||
6216 | /* Run the CQ handler - this makes sure that the drain WR will | |
6217 | * be processed if wasn't processed yet. | |
6218 | */ | |
6219 | mcq->mcq.comp(&mcq->mcq); | |
6220 | } | |
6221 | ||
6222 | wait_for_completion(&sdrain->done); | |
6223 | } | |
6224 | ||
6225 | void mlx5_ib_drain_sq(struct ib_qp *qp) | |
6226 | { | |
6227 | struct ib_cq *cq = qp->send_cq; | |
6228 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
6229 | struct mlx5_ib_drain_cqe sdrain; | |
d34ac5cd | 6230 | const struct ib_send_wr *bad_swr; |
d0e84c0a YH |
6231 | struct ib_rdma_wr swr = { |
6232 | .wr = { | |
6233 | .next = NULL, | |
6234 | { .wr_cqe = &sdrain.cqe, }, | |
6235 | .opcode = IB_WR_RDMA_WRITE, | |
6236 | }, | |
6237 | }; | |
6238 | int ret; | |
6239 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
6240 | struct mlx5_core_dev *mdev = dev->mdev; | |
6241 | ||
6242 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
6243 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6244 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
6245 | return; | |
6246 | } | |
6247 | ||
6248 | sdrain.cqe.done = mlx5_ib_drain_qp_done; | |
6249 | init_completion(&sdrain.done); | |
6250 | ||
6251 | ret = _mlx5_ib_post_send(qp, &swr.wr, &bad_swr, true); | |
6252 | if (ret) { | |
6253 | WARN_ONCE(ret, "failed to drain send queue: %d\n", ret); | |
6254 | return; | |
6255 | } | |
6256 | ||
6257 | handle_drain_completion(cq, &sdrain, dev); | |
6258 | } | |
6259 | ||
6260 | void mlx5_ib_drain_rq(struct ib_qp *qp) | |
6261 | { | |
6262 | struct ib_cq *cq = qp->recv_cq; | |
6263 | struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR }; | |
6264 | struct mlx5_ib_drain_cqe rdrain; | |
d34ac5cd BVA |
6265 | struct ib_recv_wr rwr = {}; |
6266 | const struct ib_recv_wr *bad_rwr; | |
d0e84c0a YH |
6267 | int ret; |
6268 | struct mlx5_ib_dev *dev = to_mdev(qp->device); | |
6269 | struct mlx5_core_dev *mdev = dev->mdev; | |
6270 | ||
6271 | ret = ib_modify_qp(qp, &attr, IB_QP_STATE); | |
6272 | if (ret && mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
6273 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
6274 | return; | |
6275 | } | |
6276 | ||
6277 | rwr.wr_cqe = &rdrain.cqe; | |
6278 | rdrain.cqe.done = mlx5_ib_drain_qp_done; | |
6279 | init_completion(&rdrain.done); | |
6280 | ||
6281 | ret = _mlx5_ib_post_recv(qp, &rwr, &bad_rwr, true); | |
6282 | if (ret) { | |
6283 | WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret); | |
6284 | return; | |
6285 | } | |
6286 | ||
6287 | handle_drain_completion(cq, &rdrain, dev); | |
6288 | } |