[thirdparty/kernel/stable.git] / drivers / irqchip / irq-meson-gpio.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015 Endless Mobile, Inc.
 * Author: Carlo Caione <carlo@endlessm.com>
 * Copyright (c) 2016 BayLibre, SAS.
 * Author: Jerome Brunet <jbrunet@baylibre.com>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/io.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>

#define NUM_CHANNEL 8
#define MAX_INPUT_MUX 256

#define REG_EDGE_POL	0x00
#define REG_PIN_03_SEL	0x04
#define REG_PIN_47_SEL	0x08
#define REG_FILTER_SEL	0x0c

#define REG_EDGE_POL_MASK(x)	(BIT(x) | BIT(16 + (x)))
#define REG_EDGE_POL_EDGE(x)	BIT(x)
#define REG_EDGE_POL_LOW(x)	BIT(16 + (x))
#define REG_PIN_SEL_SHIFT(x)	(((x) % 4) * 8)
#define REG_FILTER_SEL_SHIFT(x)	((x) * 4)

struct meson_gpio_irq_params {
	unsigned int nr_hwirq;
};

static const struct meson_gpio_irq_params meson8_params = {
	.nr_hwirq = 134,
};

static const struct meson_gpio_irq_params meson8b_params = {
	.nr_hwirq = 119,
};

static const struct meson_gpio_irq_params gxbb_params = {
	.nr_hwirq = 133,
};

static const struct meson_gpio_irq_params gxl_params = {
	.nr_hwirq = 110,
};

static const struct meson_gpio_irq_params axg_params = {
	.nr_hwirq = 100,
};

static const struct of_device_id meson_irq_gpio_matches[] = {
	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
	{ }
};

struct meson_gpio_irq_controller {
	unsigned int nr_hwirq;
	void __iomem *base;
	u32 channel_irqs[NUM_CHANNEL];
	DECLARE_BITMAP(channel_map, NUM_CHANNEL);
	spinlock_t lock;
};

static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
				       unsigned int reg, u32 mask, u32 val)
{
	u32 tmp;

	tmp = readl_relaxed(ctl->base + reg);
	tmp &= ~mask;
	tmp |= val;
	writel_relaxed(tmp, ctl->base + reg);
}

static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
{
	return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
}

static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
			       unsigned long  hwirq,
			       u32 **channel_hwirq)
{
	unsigned int reg, idx;

	spin_lock(&ctl->lock);

	/* Find a free channel */
	idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
	if (idx >= NUM_CHANNEL) {
		spin_unlock(&ctl->lock);
		pr_err("No channel available\n");
		return -ENOSPC;
	}

	/* Mark the channel as used */
	set_bit(idx, ctl->channel_map);

	/*
	 * Setup the mux of the channel to route the signal of the pad
	 * to the appropriate input of the GIC
	 */
	reg = meson_gpio_irq_channel_to_reg(idx);
	meson_gpio_irq_update_bits(ctl, reg,
				   0xff << REG_PIN_SEL_SHIFT(idx),
				   hwirq << REG_PIN_SEL_SHIFT(idx));

	/*
	 * Get the hwirq number assigned to this channel through
	 * a pointer the channel_irq table. The added benifit of this
	 * method is that we can also retrieve the channel index with
	 * it, using the table base.
	 */
	*channel_hwirq = &(ctl->channel_irqs[idx]);

	spin_unlock(&ctl->lock);

	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
		 hwirq, idx, **channel_hwirq);

	return 0;
}

static unsigned int
meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
			       u32 *channel_hwirq)
{
	return channel_hwirq - ctl->channel_irqs;
}

static void
meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
			       u32 *channel_hwirq)
{
	unsigned int idx;

	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
	clear_bit(idx, ctl->channel_map);
}

static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
				     unsigned int type,
				     u32 *channel_hwirq)
{
	u32 val = 0;
	unsigned int idx;

	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);

	/*
	 * The controller has a filter block to operate in either LEVEL or
	 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
	 * EDGE_FALLING support (which the GIC does not support), the filter
	 * block is also able to invert the input signal it gets before
	 * providing it to the GIC.
	 */
	type &= IRQ_TYPE_SENSE_MASK;

	if (type == IRQ_TYPE_EDGE_BOTH)
		return -EINVAL;

	if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
		val |= REG_EDGE_POL_EDGE(idx);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
		val |= REG_EDGE_POL_LOW(idx);

	spin_lock(&ctl->lock);

	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
				   REG_EDGE_POL_MASK(idx), val);

	spin_unlock(&ctl->lock);

	return 0;
}

static unsigned int meson_gpio_irq_type_output(unsigned int type)
{
	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;

	type &= ~IRQ_TYPE_SENSE_MASK;

	/*
	 * The polarity of the signal provided to the GIC should always
	 * be high.
	 */
	if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		type |= IRQ_TYPE_LEVEL_HIGH;
	else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
		type |= IRQ_TYPE_EDGE_RISING;

	return type;
}

static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	struct meson_gpio_irq_controller *ctl = data->domain->host_data;
	u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
	int ret;

	ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
	if (ret)
		return ret;

	return irq_chip_set_type_parent(data,
					meson_gpio_irq_type_output(type));
}

static struct irq_chip meson_gpio_irq_chip = {
	.name			= "meson-gpio-irqchip",
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_type		= meson_gpio_irq_set_type,
	.irq_retrigger		= irq_chip_retrigger_hierarchy,
#ifdef CONFIG_SMP
	.irq_set_affinity	= irq_chip_set_affinity_parent,
#endif
	.flags			= IRQCHIP_SET_TYPE_MASKED,
};

static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
					   struct irq_fwspec *fwspec,
					   unsigned long *hwirq,
					   unsigned int *type)
{
	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
		*hwirq	= fwspec->param[0];
		*type	= fwspec->param[1];
		return 0;
	}

	return -EINVAL;
}

static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
					   unsigned int virq,
					   u32 hwirq,
					   unsigned int type)
{
	struct irq_fwspec fwspec;

	fwspec.fwnode = domain->parent->fwnode;
	fwspec.param_count = 3;
	fwspec.param[0] = 0;	/* SPI */
	fwspec.param[1] = hwirq;
	fwspec.param[2] = meson_gpio_irq_type_output(type);

	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
}

static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
				       unsigned int virq,
				       unsigned int nr_irqs,
				       void *data)
{
	struct irq_fwspec *fwspec = data;
	struct meson_gpio_irq_controller *ctl = domain->host_data;
	unsigned long hwirq;
	u32 *channel_hwirq;
	unsigned int type;
	int ret;

	if (WARN_ON(nr_irqs != 1))
		return -EINVAL;

	ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
	if (ret)
		return ret;

	ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
	if (ret)
		return ret;

	ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
					      *channel_hwirq, type);
	if (ret < 0) {
		pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
		meson_gpio_irq_release_channel(ctl, channel_hwirq);
		return ret;
	}

	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
				      &meson_gpio_irq_chip, channel_hwirq);

	return 0;
}

static void meson_gpio_irq_domain_free(struct irq_domain *domain,
				       unsigned int virq,
				       unsigned int nr_irqs)
{
	struct meson_gpio_irq_controller *ctl = domain->host_data;
	struct irq_data *irq_data;
	u32 *channel_hwirq;

	if (WARN_ON(nr_irqs != 1))
		return;

	irq_domain_free_irqs_parent(domain, virq, 1);

	irq_data = irq_domain_get_irq_data(domain, virq);
	channel_hwirq = irq_data_get_irq_chip_data(irq_data);

	meson_gpio_irq_release_channel(ctl, channel_hwirq);
}

static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
	.alloc		= meson_gpio_irq_domain_alloc,
	.free		= meson_gpio_irq_domain_free,
	.translate	= meson_gpio_irq_domain_translate,
};

static int __init meson_gpio_irq_parse_dt(struct device_node *node,
					  struct meson_gpio_irq_controller *ctl)
{
	const struct of_device_id *match;
	const struct meson_gpio_irq_params *params;
	int ret;

	match = of_match_node(meson_irq_gpio_matches, node);
	if (!match)
		return -ENODEV;

	params = match->data;
	ctl->nr_hwirq = params->nr_hwirq;

	ret = of_property_read_variable_u32_array(node,
						  "amlogic,channel-interrupts",
						  ctl->channel_irqs,
						  NUM_CHANNEL,
						  NUM_CHANNEL);
	if (ret < 0) {
		pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
		return ret;
	}

	return 0;
}

static int __init meson_gpio_irq_of_init(struct device_node *node,
					 struct device_node *parent)
{
	struct irq_domain *domain, *parent_domain;
	struct meson_gpio_irq_controller *ctl;
	int ret;

	if (!parent) {
		pr_err("missing parent interrupt node\n");
		return -ENODEV;
	}

	parent_domain = irq_find_host(parent);
	if (!parent_domain) {
		pr_err("unable to obtain parent domain\n");
		return -ENXIO;
	}

	ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
	if (!ctl)
		return -ENOMEM;

	spin_lock_init(&ctl->lock);

	ctl->base = of_iomap(node, 0);
	if (!ctl->base) {
		ret = -ENOMEM;
		goto free_ctl;
	}

	ret = meson_gpio_irq_parse_dt(node, ctl);
	if (ret)
		goto free_channel_irqs;

	domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
					     of_node_to_fwnode(node),
					     &meson_gpio_irq_domain_ops,
					     ctl);
	if (!domain) {
		pr_err("failed to add domain\n");
		ret = -ENODEV;
		goto free_channel_irqs;
	}

	pr_info("%d to %d gpio interrupt mux initialized\n",
		ctl->nr_hwirq, NUM_CHANNEL);

	return 0;

free_channel_irqs:
	iounmap(ctl->base);
free_ctl:
	kfree(ctl);

	return ret;
}

IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
		meson_gpio_irq_of_init);
Commit	Line	Data
38cf0d46	1	// SPDX-License-Identifier: GPL-2.0-only
215f4cc0 JB	2	/*
	3	* Copyright (c) 2015 Endless Mobile, Inc.
	4	* Author: Carlo Caione <carlo@endlessm.com>
	5	* Copyright (c) 2016 BayLibre, SAS.
	6	* Author: Jerome Brunet <jbrunet@baylibre.com>
215f4cc0 JB	7	*/
	8
	9	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	10
	11	#include <linux/io.h>
	12	#include <linux/module.h>
	13	#include <linux/irq.h>
	14	#include <linux/irqdomain.h>
	15	#include <linux/irqchip.h>
	16	#include <linux/of.h>
	17	#include <linux/of_address.h>
	18
	19	#define NUM_CHANNEL 8
	20	#define MAX_INPUT_MUX 256
	21
	22	#define REG_EDGE_POL 0x00
	23	#define REG_PIN_03_SEL 0x04
	24	#define REG_PIN_47_SEL 0x08
	25	#define REG_FILTER_SEL 0x0c
	26
	27	#define REG_EDGE_POL_MASK(x) (BIT(x) \| BIT(16 + (x)))
	28	#define REG_EDGE_POL_EDGE(x) BIT(x)
	29	#define REG_EDGE_POL_LOW(x) BIT(16 + (x))
	30	#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
	31	#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
	32
	33	struct meson_gpio_irq_params {
	34	unsigned int nr_hwirq;
	35	};
	36
4e4cb1b1 MB	37	static const struct meson_gpio_irq_params meson8_params = {
	38	.nr_hwirq = 134,
	39	};
	40
215f4cc0 JB	41	static const struct meson_gpio_irq_params meson8b_params = {
	42	.nr_hwirq = 119,
	43	};
	44
	45	static const struct meson_gpio_irq_params gxbb_params = {
	46	.nr_hwirq = 133,
	47	};
	48
	49	static const struct meson_gpio_irq_params gxl_params = {
	50	.nr_hwirq = 110,
	51	};
	52
868c4e07 YL	53	static const struct meson_gpio_irq_params axg_params = {
	54	.nr_hwirq = 100,
	55	};
	56
215f4cc0	57	static const struct of_device_id meson_irq_gpio_matches[] = {
4e4cb1b1	58	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
215f4cc0 JB	59	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
	60	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
	61	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
868c4e07	62	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
215f4cc0 JB	63	{ }
	64	};
	65
	66	struct meson_gpio_irq_controller {
	67	unsigned int nr_hwirq;
	68	void __iomem *base;
	69	u32 channel_irqs[NUM_CHANNEL];
	70	DECLARE_BITMAP(channel_map, NUM_CHANNEL);
	71	spinlock_t lock;
	72	};
	73
	74	static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
	75	unsigned int reg, u32 mask, u32 val)
	76	{
	77	u32 tmp;
	78
	79	tmp = readl_relaxed(ctl->base + reg);
	80	tmp &= ~mask;
	81	tmp \|= val;
	82	writel_relaxed(tmp, ctl->base + reg);
	83	}
	84
	85	static unsigned int meson_gpio_irq_channel_to_reg(unsigned int channel)
	86	{
	87	return (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
	88	}
	89
	90	static int
	91	meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
	92	unsigned long hwirq,
	93	u32 **channel_hwirq)
	94	{
	95	unsigned int reg, idx;
	96
	97	spin_lock(&ctl->lock);
	98
	99	/* Find a free channel */
	100	idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
	101	if (idx >= NUM_CHANNEL) {
	102	spin_unlock(&ctl->lock);
	103	pr_err("No channel available\n");
	104	return -ENOSPC;
	105	}
	106
	107	/* Mark the channel as used */
	108	set_bit(idx, ctl->channel_map);
	109
	110	/*
	111	* Setup the mux of the channel to route the signal of the pad
	112	* to the appropriate input of the GIC
	113	*/
	114	reg = meson_gpio_irq_channel_to_reg(idx);
	115	meson_gpio_irq_update_bits(ctl, reg,
	116	0xff << REG_PIN_SEL_SHIFT(idx),
	117	hwirq << REG_PIN_SEL_SHIFT(idx));
	118
	119	/*
	120	* Get the hwirq number assigned to this channel through
	121	* a pointer the channel_irq table. The added benifit of this
	122	* method is that we can also retrieve the channel index with
	123	* it, using the table base.
	124	*/
	125	*channel_hwirq = &(ctl->channel_irqs[idx]);
	126
127	spin_unlock(&ctl->lock);
128
129	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
130	hwirq, idx, **channel_hwirq);
131
132	return 0;
133	}
134
135	static unsigned int
136	meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
137	u32 *channel_hwirq)
138	{
139	return channel_hwirq - ctl->channel_irqs;
140	}
141
142	static void
143	meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
144	u32 *channel_hwirq)
145	{
146	unsigned int idx;
147
148	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
149	clear_bit(idx, ctl->channel_map);
150	}
151
152	static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
153	unsigned int type,
154	u32 *channel_hwirq)
155	{
156	u32 val = 0;
157	unsigned int idx;
158
159	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
160
161	/*
162	* The controller has a filter block to operate in either LEVEL or
163	* EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
164	* EDGE_FALLING support (which the GIC does not support), the filter
165	* block is also able to invert the input signal it gets before
166	* providing it to the GIC.
167	*/
168	type &= IRQ_TYPE_SENSE_MASK;
169
170	if (type == IRQ_TYPE_EDGE_BOTH)
171	return -EINVAL;
172
173	if (type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING))
174	val \|= REG_EDGE_POL_EDGE(idx);
175
176	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_EDGE_FALLING))
177	val \|= REG_EDGE_POL_LOW(idx);
178
179	spin_lock(&ctl->lock);
180
181	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
182	REG_EDGE_POL_MASK(idx), val);
183
184	spin_unlock(&ctl->lock);
185
186	return 0;
187	}
188
189	static unsigned int meson_gpio_irq_type_output(unsigned int type)
190	{
191	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
192
193	type &= ~IRQ_TYPE_SENSE_MASK;
194
195	/*
196	* The polarity of the signal provided to the GIC should always
197	* be high.
198	*/
199	if (sense & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW))
200	type \|= IRQ_TYPE_LEVEL_HIGH;
201	else if (sense & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING))
202	type \|= IRQ_TYPE_EDGE_RISING;
203
204	return type;
205	}
206
207	static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
208	{
209	struct meson_gpio_irq_controller *ctl = data->domain->host_data;
210	u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
211	int ret;
212
213	ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
214	if (ret)
215	return ret;
216
217	return irq_chip_set_type_parent(data,
218	meson_gpio_irq_type_output(type));
219	}
220
221	static struct irq_chip meson_gpio_irq_chip = {
222	.name = "meson-gpio-irqchip",
223	.irq_mask = irq_chip_mask_parent,
224	.irq_unmask = irq_chip_unmask_parent,
225	.irq_eoi = irq_chip_eoi_parent,
226	.irq_set_type = meson_gpio_irq_set_type,
227	.irq_retrigger = irq_chip_retrigger_hierarchy,
228	#ifdef CONFIG_SMP
229	.irq_set_affinity = irq_chip_set_affinity_parent,
230	#endif
231	.flags = IRQCHIP_SET_TYPE_MASKED,
232	};
233
234	static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
235	struct irq_fwspec *fwspec,
236	unsigned long *hwirq,
237	unsigned int *type)
238	{
239	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
240	*hwirq = fwspec->param[0];
241	*type = fwspec->param[1];
242	return 0;
243	}
244
245	return -EINVAL;
246	}
247
248	static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
249	unsigned int virq,
250	u32 hwirq,
251	unsigned int type)
252	{
253	struct irq_fwspec fwspec;
254
255	fwspec.fwnode = domain->parent->fwnode;
256	fwspec.param_count = 3;
257	fwspec.param[0] = 0; /* SPI */
258	fwspec.param[1] = hwirq;
259	fwspec.param[2] = meson_gpio_irq_type_output(type);
260
261	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
262	}
263
264	static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
265	unsigned int virq,
266	unsigned int nr_irqs,
267	void *data)
268	{
269	struct irq_fwspec *fwspec = data;
270	struct meson_gpio_irq_controller *ctl = domain->host_data;
271	unsigned long hwirq;
272	u32 *channel_hwirq;
273	unsigned int type;
274	int ret;
275
276	if (WARN_ON(nr_irqs != 1))
277	return -EINVAL;
278
279	ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
280	if (ret)
281	return ret;
282
283	ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
284	if (ret)
285	return ret;
286
287	ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
288	*channel_hwirq, type);
289	if (ret < 0) {
290	pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
291	meson_gpio_irq_release_channel(ctl, channel_hwirq);
292	return ret;
293	}
294
295	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
296	&meson_gpio_irq_chip, channel_hwirq);
297
298	return 0;
299	}
300
301	static void meson_gpio_irq_domain_free(struct irq_domain *domain,
302	unsigned int virq,
303	unsigned int nr_irqs)
304	{
305	struct meson_gpio_irq_controller *ctl = domain->host_data;
306	struct irq_data *irq_data;
307	u32 *channel_hwirq;
308
309	if (WARN_ON(nr_irqs != 1))
310	return;
311
312	irq_domain_free_irqs_parent(domain, virq, 1);
313
314	irq_data = irq_domain_get_irq_data(domain, virq);
315	channel_hwirq = irq_data_get_irq_chip_data(irq_data);
316
317	meson_gpio_irq_release_channel(ctl, channel_hwirq);
318	}
319
320	static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
321	.alloc = meson_gpio_irq_domain_alloc,
322	.free = meson_gpio_irq_domain_free,
323	.translate = meson_gpio_irq_domain_translate,
324	};
325
326	static int __init meson_gpio_irq_parse_dt(struct device_node *node,
327	struct meson_gpio_irq_controller *ctl)
328	{
329	const struct of_device_id *match;
330	const struct meson_gpio_irq_params *params;
331	int ret;
332
333	match = of_match_node(meson_irq_gpio_matches, node);
334	if (!match)
335	return -ENODEV;
336
337	params = match->data;
338	ctl->nr_hwirq = params->nr_hwirq;
339
340	ret = of_property_read_variable_u32_array(node,
341	"amlogic,channel-interrupts",
342	ctl->channel_irqs,
343	NUM_CHANNEL,
344	NUM_CHANNEL);
345	if (ret < 0) {
346	pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
347	return ret;
348	}
349
350	return 0;
351	}
352
353	static int __init meson_gpio_irq_of_init(struct device_node *node,
354	struct device_node *parent)
355	{
356	struct irq_domain domain, parent_domain;
357	struct meson_gpio_irq_controller *ctl;
358	int ret;
359
360	if (!parent) {
361	pr_err("missing parent interrupt node\n");
362	return -ENODEV;
363	}
364
365	parent_domain = irq_find_host(parent);
366	if (!parent_domain) {
367	pr_err("unable to obtain parent domain\n");
368	return -ENXIO;
369	}
370
371	ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
372	if (!ctl)
373	return -ENOMEM;
374
375	spin_lock_init(&ctl->lock);
376
377	ctl->base = of_iomap(node, 0);
378	if (!ctl->base) {
379	ret = -ENOMEM;
380	goto free_ctl;
381	}
382
383	ret = meson_gpio_irq_parse_dt(node, ctl);
384	if (ret)
385	goto free_channel_irqs;
386
387	domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq,
388	of_node_to_fwnode(node),
389	&meson_gpio_irq_domain_ops,
390	ctl);
391	if (!domain) {
392	pr_err("failed to add domain\n");
393	ret = -ENODEV;
394	goto free_channel_irqs;
395	}
396
397	pr_info("%d to %d gpio interrupt mux initialized\n",
398	ctl->nr_hwirq, NUM_CHANNEL);
399
400	return 0;
401
402	free_channel_irqs:
403	iounmap(ctl->base);
404	free_ctl:
405	kfree(ctl);
406
407	return ret;
408	}
409
410	IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
411	meson_gpio_irq_of_init);