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r8169: disable ASPM again
[thirdparty/kernel/stable.git] / drivers / net / ethernet / realtek / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
c2f6f3ee 16#include <linux/clk.h>
1da177e4
LT		 17#include <linux/delay.h>
18#include <linux/ethtool.h>
f1e911d5 19#include <linux/phy.h>
1da177e4
LT		 20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
098b01ad 23#include <linux/io.h>
1da177e4
LT		 24#include <linux/ip.h>
25#include <linux/tcp.h>
a6b7a407 26#include <linux/interrupt.h>
1da177e4 27#include <linux/dma-mapping.h>
e1759441 28#include <linux/pm_runtime.h>
bca03d5f 29#include <linux/firmware.h>
70c71606 30#include <linux/prefetch.h>
1e4a7e78 31#include <linux/pci-aspm.h>
e974604b 32#include <linux/ipv6.h>
33#include <net/ip6_checksum.h>
1da177e4 34
1da177e4 35#define MODULENAME "r8169"
1da177e4 36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 39#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 41#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
c2218925
HW		 42#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
5a5e4443 44#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
7e18dca1 45#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
b3d7b2f2 46#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
45dd95c4 47#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
5598bfe5 48#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
58152cd4 49#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
beb330a4 50#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
57538c4a 51#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
6e1d0b89
CHL		 52#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
55#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
bca03d5f 56
b57b7e5a 57#define R8169_MSG_DEFAULT \
f0e837d9 58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 59
477206a0
JD		 60#define TX_SLOTS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
62
63/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
64#define TX_FRAGS_READY_FOR(tp,nr_frags) \
65 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
1da177e4 66
1da177e4
LT		 67/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
68 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 69static const int multicast_filter_limit = 32;
1da177e4 70
aee77e4a 71#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
1da177e4
LT		 72#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73
74#define R8169_REGS_SIZE 256
1d0254dd 75#define R8169_RX_BUF_SIZE (SZ_16K - 1)
1da177e4 76#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
9fba0812 77#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
1da177e4
LT		 78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
1da177e4
LT		 82
83/* write/read MMIO register */
1ef7286e
AS		 84#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
85#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
86#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
87#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
88#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
89#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
1da177e4
LT		 90
91enum mac_version {
85bffe6c
FR		 92 RTL_GIGA_MAC_VER_01 = 0,
93 RTL_GIGA_MAC_VER_02,
94 RTL_GIGA_MAC_VER_03,
95 RTL_GIGA_MAC_VER_04,
96 RTL_GIGA_MAC_VER_05,
97 RTL_GIGA_MAC_VER_06,
98 RTL_GIGA_MAC_VER_07,
99 RTL_GIGA_MAC_VER_08,
100 RTL_GIGA_MAC_VER_09,
101 RTL_GIGA_MAC_VER_10,
102 RTL_GIGA_MAC_VER_11,
103 RTL_GIGA_MAC_VER_12,
104 RTL_GIGA_MAC_VER_13,
105 RTL_GIGA_MAC_VER_14,
106 RTL_GIGA_MAC_VER_15,
107 RTL_GIGA_MAC_VER_16,
108 RTL_GIGA_MAC_VER_17,
109 RTL_GIGA_MAC_VER_18,
110 RTL_GIGA_MAC_VER_19,
111 RTL_GIGA_MAC_VER_20,
112 RTL_GIGA_MAC_VER_21,
113 RTL_GIGA_MAC_VER_22,
114 RTL_GIGA_MAC_VER_23,
115 RTL_GIGA_MAC_VER_24,
116 RTL_GIGA_MAC_VER_25,
117 RTL_GIGA_MAC_VER_26,
118 RTL_GIGA_MAC_VER_27,
119 RTL_GIGA_MAC_VER_28,
120 RTL_GIGA_MAC_VER_29,
121 RTL_GIGA_MAC_VER_30,
122 RTL_GIGA_MAC_VER_31,
123 RTL_GIGA_MAC_VER_32,
124 RTL_GIGA_MAC_VER_33,
70090424 125 RTL_GIGA_MAC_VER_34,
c2218925
HW		 126 RTL_GIGA_MAC_VER_35,
127 RTL_GIGA_MAC_VER_36,
7e18dca1 128 RTL_GIGA_MAC_VER_37,
b3d7b2f2 129 RTL_GIGA_MAC_VER_38,
5598bfe5 130 RTL_GIGA_MAC_VER_39,
c558386b
HW		 131 RTL_GIGA_MAC_VER_40,
132 RTL_GIGA_MAC_VER_41,
57538c4a 133 RTL_GIGA_MAC_VER_42,
58152cd4 134 RTL_GIGA_MAC_VER_43,
45dd95c4 135 RTL_GIGA_MAC_VER_44,
6e1d0b89
CHL		 136 RTL_GIGA_MAC_VER_45,
137 RTL_GIGA_MAC_VER_46,
138 RTL_GIGA_MAC_VER_47,
139 RTL_GIGA_MAC_VER_48,
935e2218
CHL		 140 RTL_GIGA_MAC_VER_49,
141 RTL_GIGA_MAC_VER_50,
142 RTL_GIGA_MAC_VER_51,
85bffe6c 143 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 144};
145
d58d46b5
FR		 146#define JUMBO_1K ETH_DATA_LEN
147#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
148#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
149#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
150#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151
3c6bee1d 152static const struct {
1da177e4 153 const char *name;
953a12cc 154 const char *fw_name;
85bffe6c
FR		 155} rtl_chip_infos[] = {
156 /* PCI devices. */
abe8b2f7
HK		 157 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
158 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
159 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
160 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
161 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
162 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
85bffe6c 163 /* PCI-E devices. */
abe8b2f7
HK		 164 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
166 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
167 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
170 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
171 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
172 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
173 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
174 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
175 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
179 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
180 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
181 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
182 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
183 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
184 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
186 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
187 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
188 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
189 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
190 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
191 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
192 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
193 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
194 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
195 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
196 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
197 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
198 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
199 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
200 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
201 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
202 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
203 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
204 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
205 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
206 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
207 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
208 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
953a12cc
FR		 209};
210
bcf0bf90
FR		 211enum cfg_version {
212 RTL_CFG_0 = 0x00,
213 RTL_CFG_1,
214 RTL_CFG_2
215};
216
9baa3c34 217static const struct pci_device_id rtl8169_pci_tbl[] = {
19ad57e2
KHF		 218 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
219 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
bcf0bf90 220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
610c9087 222 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
d81bf551 223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 224 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
9fd0e09a 225 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 226 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
2a35cfa5
FR		 227 { PCI_VENDOR_ID_DLINK, 0x4300,
228 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
bcf0bf90 229 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 230 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 231 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 232 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
233 { PCI_VENDOR_ID_LINKSYS, 0x1032,
234 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 235 { 0x0001, 0x8168,
236 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 237 {0,},
238};
239
240MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
241
27896c83 242static int use_dac = -1;
b57b7e5a
SH		 243static struct {
244 u32 msg_enable;
245} debug = { -1 };
1da177e4 246
07d3f51f
FR		 247enum rtl_registers {
248 MAC0 = 0, /* Ethernet hardware address. */
773d2021 249 MAC4 = 4,
07d3f51f
FR		 250 MAR0 = 8, /* Multicast filter. */
251 CounterAddrLow = 0x10,
252 CounterAddrHigh = 0x14,
253 TxDescStartAddrLow = 0x20,
254 TxDescStartAddrHigh = 0x24,
255 TxHDescStartAddrLow = 0x28,
256 TxHDescStartAddrHigh = 0x2c,
257 FLASH = 0x30,
258 ERSR = 0x36,
259 ChipCmd = 0x37,
260 TxPoll = 0x38,
261 IntrMask = 0x3c,
262 IntrStatus = 0x3e,
4f6b00e5 263
07d3f51f 264 TxConfig = 0x40,
4f6b00e5
HW		 265#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
266#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 267
4f6b00e5
HW		 268 RxConfig = 0x44,
269#define RX128_INT_EN (1 << 15) /* 8111c and later */
270#define RX_MULTI_EN (1 << 14) /* 8111c only */
271#define RXCFG_FIFO_SHIFT 13
272 /* No threshold before first PCI xfer */
273#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
beb330a4 274#define RX_EARLY_OFF (1 << 11)
4f6b00e5
HW		 275#define RXCFG_DMA_SHIFT 8
276 /* Unlimited maximum PCI burst. */
277#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 278
07d3f51f
FR		 279 RxMissed = 0x4c,
280 Cfg9346 = 0x50,
281 Config0 = 0x51,
282 Config1 = 0x52,
283 Config2 = 0x53,
d387b427
FR		 284#define PME_SIGNAL (1 << 5) /* 8168c and later */
285
07d3f51f
FR		 286 Config3 = 0x54,
287 Config4 = 0x55,
288 Config5 = 0x56,
289 MultiIntr = 0x5c,
290 PHYAR = 0x60,
07d3f51f
FR		 291 PHYstatus = 0x6c,
292 RxMaxSize = 0xda,
293 CPlusCmd = 0xe0,
294 IntrMitigate = 0xe2,
50970831
FR		 295
296#define RTL_COALESCE_MASK 0x0f
297#define RTL_COALESCE_SHIFT 4
298#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
299#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
300
07d3f51f
FR		 301 RxDescAddrLow = 0xe4,
302 RxDescAddrHigh = 0xe8,
f0298f81 303 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
304
305#define NoEarlyTx 0x3f /* Max value : no early transmit. */
306
307 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
308
309#define TxPacketMax (8064 >> 7)
3090bd9a 310#define EarlySize 0x27
f0298f81 311
07d3f51f
FR		 312 FuncEvent = 0xf0,
313 FuncEventMask = 0xf4,
314 FuncPresetState = 0xf8,
935e2218
CHL		 315 IBCR0 = 0xf8,
316 IBCR2 = 0xf9,
317 IBIMR0 = 0xfa,
318 IBISR0 = 0xfb,
07d3f51f 319 FuncForceEvent = 0xfc,
1da177e4
LT		 320};
321
f162a5d1
FR		 322enum rtl8168_8101_registers {
323 CSIDR = 0x64,
324 CSIAR = 0x68,
325#define CSIAR_FLAG 0x80000000
326#define CSIAR_WRITE_CMD 0x80000000
ff1d7331
HK		 327#define CSIAR_BYTE_ENABLE 0x0000f000
328#define CSIAR_ADDR_MASK 0x00000fff
065c27c1 329 PMCH = 0x6f,
f162a5d1
FR		 330 EPHYAR = 0x80,
331#define EPHYAR_FLAG 0x80000000
332#define EPHYAR_WRITE_CMD 0x80000000
333#define EPHYAR_REG_MASK 0x1f
334#define EPHYAR_REG_SHIFT 16
335#define EPHYAR_DATA_MASK 0xffff
5a5e4443 336 DLLPR = 0xd0,
4f6b00e5 337#define PFM_EN (1 << 6)
6e1d0b89 338#define TX_10M_PS_EN (1 << 7)
f162a5d1
FR		 339 DBG_REG = 0xd1,
340#define FIX_NAK_1 (1 << 4)
341#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 342 TWSI = 0xd2,
343 MCU = 0xd3,
4f6b00e5 344#define NOW_IS_OOB (1 << 7)
c558386b
HW		 345#define TX_EMPTY (1 << 5)
346#define RX_EMPTY (1 << 4)
347#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
5a5e4443
HW		 348#define EN_NDP (1 << 3)
349#define EN_OOB_RESET (1 << 2)
c558386b 350#define LINK_LIST_RDY (1 << 1)
daf9df6d 351 EFUSEAR = 0xdc,
352#define EFUSEAR_FLAG 0x80000000
353#define EFUSEAR_WRITE_CMD 0x80000000
354#define EFUSEAR_READ_CMD 0x00000000
355#define EFUSEAR_REG_MASK 0x03ff
356#define EFUSEAR_REG_SHIFT 8
357#define EFUSEAR_DATA_MASK 0xff
6e1d0b89
CHL		 358 MISC_1 = 0xf2,
359#define PFM_D3COLD_EN (1 << 6)
f162a5d1
FR		 360};
361
c0e45c1c 362enum rtl8168_registers {
4f6b00e5
HW		 363 LED_FREQ = 0x1a,
364 EEE_LED = 0x1b,
b646d900 365 ERIDR = 0x70,
366 ERIAR = 0x74,
367#define ERIAR_FLAG 0x80000000
368#define ERIAR_WRITE_CMD 0x80000000
369#define ERIAR_READ_CMD 0x00000000
370#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 371#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 372#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
373#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
374#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
935e2218 375#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
4f6b00e5
HW		 376#define ERIAR_MASK_SHIFT 12
377#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
378#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
6e1d0b89 379#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
c558386b 380#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
4f6b00e5 381#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 382 EPHY_RXER_NUM = 0x7c,
383 OCPDR = 0xb0, /* OCP GPHY access */
384#define OCPDR_WRITE_CMD 0x80000000
385#define OCPDR_READ_CMD 0x00000000
386#define OCPDR_REG_MASK 0x7f
387#define OCPDR_GPHY_REG_SHIFT 16
388#define OCPDR_DATA_MASK 0xffff
389 OCPAR = 0xb4,
390#define OCPAR_FLAG 0x80000000
391#define OCPAR_GPHY_WRITE_CMD 0x8000f060
392#define OCPAR_GPHY_READ_CMD 0x0000f060
c558386b 393 GPHY_OCP = 0xb8,
01dc7fec 394 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
395 MISC = 0xf0, /* 8168e only. */
cecb5fd7 396#define TXPLA_RST (1 << 29)
5598bfe5 397#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
4f6b00e5 398#define PWM_EN (1 << 22)
c558386b 399#define RXDV_GATED_EN (1 << 19)
5598bfe5 400#define EARLY_TALLY_EN (1 << 16)
c0e45c1c 401};
402
07d3f51f 403enum rtl_register_content {
1da177e4 404 /* InterruptStatusBits */
07d3f51f
FR		 405 SYSErr = 0x8000,
406 PCSTimeout = 0x4000,
407 SWInt = 0x0100,
408 TxDescUnavail = 0x0080,
409 RxFIFOOver = 0x0040,
410 LinkChg = 0x0020,
411 RxOverflow = 0x0010,
412 TxErr = 0x0008,
413 TxOK = 0x0004,
414 RxErr = 0x0002,
415 RxOK = 0x0001,
1da177e4
LT		 416
417 /* RxStatusDesc */
e03f33af 418 RxBOVF = (1 << 24),
9dccf611
FR		 419 RxFOVF = (1 << 23),
420 RxRWT = (1 << 22),
421 RxRES = (1 << 21),
422 RxRUNT = (1 << 20),
423 RxCRC = (1 << 19),
1da177e4
LT		 424
425 /* ChipCmdBits */
4f6b00e5 426 StopReq = 0x80,
07d3f51f
FR		 427 CmdReset = 0x10,
428 CmdRxEnb = 0x08,
429 CmdTxEnb = 0x04,
430 RxBufEmpty = 0x01,
1da177e4 431
275391a4
FR		 432 /* TXPoll register p.5 */
433 HPQ = 0x80, /* Poll cmd on the high prio queue */
434 NPQ = 0x40, /* Poll cmd on the low prio queue */
435 FSWInt = 0x01, /* Forced software interrupt */
436
1da177e4 437 /* Cfg9346Bits */
07d3f51f
FR		 438 Cfg9346_Lock = 0x00,
439 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 440
441 /* rx_mode_bits */
07d3f51f
FR		 442 AcceptErr = 0x20,
443 AcceptRunt = 0x10,
444 AcceptBroadcast = 0x08,
445 AcceptMulticast = 0x04,
446 AcceptMyPhys = 0x02,
447 AcceptAllPhys = 0x01,
1687b566 448#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 449
1da177e4
LT		 450 /* TxConfigBits */
451 TxInterFrameGapShift = 24,
452 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
453
5d06a99f 454 /* Config1 register p.24 */
f162a5d1
FR		 455 LEDS1 = (1 << 7),
456 LEDS0 = (1 << 6),
f162a5d1
FR		 457 Speed_down = (1 << 4),
458 MEMMAP = (1 << 3),
459 IOMAP = (1 << 2),
460 VPD = (1 << 1),
5d06a99f
FR		 461 PMEnable = (1 << 0), /* Power Management Enable */
462
6dccd16b 463 /* Config2 register p. 25 */
57538c4a 464 ClkReqEn = (1 << 7), /* Clock Request Enable */
2ca6cf06 465 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
6dccd16b
FR		 466 PCI_Clock_66MHz = 0x01,
467 PCI_Clock_33MHz = 0x00,
468
61a4dcc2
FR		 469 /* Config3 register p.25 */
470 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
471 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
d58d46b5 472 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
b51ecea8 473 Rdy_to_L23 = (1 << 1), /* L23 Enable */
f162a5d1 474 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 475
d58d46b5
FR		 476 /* Config4 register */
477 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
478
5d06a99f 479 /* Config5 register p.27 */
61a4dcc2
FR		 480 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
481 MWF = (1 << 5), /* Accept Multicast wakeup frame */
482 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 483 Spi_en = (1 << 3),
61a4dcc2 484 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f 485 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
57538c4a 486 ASPM_en = (1 << 0), /* ASPM enable */
5d06a99f 487
1da177e4 488 /* CPlusCmd p.31 */
f162a5d1
FR		 489 EnableBist = (1 << 15), // 8168 8101
490 Mac_dbgo_oe = (1 << 14), // 8168 8101
491 Normal_mode = (1 << 13), // unused
492 Force_half_dup = (1 << 12), // 8168 8101
493 Force_rxflow_en = (1 << 11), // 8168 8101
494 Force_txflow_en = (1 << 10), // 8168 8101
495 Cxpl_dbg_sel = (1 << 9), // 8168 8101
496 ASF = (1 << 8), // 8168 8101
497 PktCntrDisable = (1 << 7), // 8168 8101
498 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 499 RxVlan = (1 << 6),
500 RxChkSum = (1 << 5),
501 PCIDAC = (1 << 4),
502 PCIMulRW = (1 << 3),
9a3c81fa 503#define INTT_MASK GENMASK(1, 0)
0e485150
FR		 504 INTT_0 = 0x0000, // 8168
505 INTT_1 = 0x0001, // 8168
506 INTT_2 = 0x0002, // 8168
507 INTT_3 = 0x0003, // 8168
1da177e4
LT		 508
509 /* rtl8169_PHYstatus */
07d3f51f
FR		 510 TBI_Enable = 0x80,
511 TxFlowCtrl = 0x40,
512 RxFlowCtrl = 0x20,
513 _1000bpsF = 0x10,
514 _100bps = 0x08,
515 _10bps = 0x04,
516 LinkStatus = 0x02,
517 FullDup = 0x01,
1da177e4 518
1da177e4 519 /* _TBICSRBit */
07d3f51f 520 TBILinkOK = 0x02000000,
d4a3a0fc 521
6e85d5ad
CV		 522 /* ResetCounterCommand */
523 CounterReset = 0x1,
524
d4a3a0fc 525 /* DumpCounterCommand */
07d3f51f 526 CounterDump = 0x8,
6e1d0b89
CHL		 527
528 /* magic enable v2 */
529 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
1da177e4
LT		 530};
531
2b7b4318
FR		 532enum rtl_desc_bit {
533 /* First doubleword. */
1da177e4
LT		 534 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
535 RingEnd = (1 << 30), /* End of descriptor ring */
536 FirstFrag = (1 << 29), /* First segment of a packet */
537 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 538};
539
540/* Generic case. */
541enum rtl_tx_desc_bit {
542 /* First doubleword. */
543 TD_LSO = (1 << 27), /* Large Send Offload */
544#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 545
2b7b4318
FR		 546 /* Second doubleword. */
547 TxVlanTag = (1 << 17), /* Add VLAN tag */
548};
549
550/* 8169, 8168b and 810x except 8102e. */
551enum rtl_tx_desc_bit_0 {
552 /* First doubleword. */
553#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
554 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
555 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
556 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
557};
558
559/* 8102e, 8168c and beyond. */
560enum rtl_tx_desc_bit_1 {
bdfa4ed6 561 /* First doubleword. */
562 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
e974604b 563 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
bdfa4ed6 564#define GTTCPHO_SHIFT 18
e974604b 565#define GTTCPHO_MAX 0x7fU
bdfa4ed6 566
2b7b4318 567 /* Second doubleword. */
e974604b 568#define TCPHO_SHIFT 18
569#define TCPHO_MAX 0x3ffU
2b7b4318 570#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
e974604b 571 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
572 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
2b7b4318
FR		 573 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
574 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
575};
1da177e4 576
2b7b4318 577enum rtl_rx_desc_bit {
1da177e4
LT		 578 /* Rx private */
579 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
9b60047a 580 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
1da177e4
LT		 581
582#define RxProtoUDP (PID1)
583#define RxProtoTCP (PID0)
584#define RxProtoIP (PID1 | PID0)
585#define RxProtoMask RxProtoIP
586
587 IPFail = (1 << 16), /* IP checksum failed */
588 UDPFail = (1 << 15), /* UDP/IP checksum failed */
589 TCPFail = (1 << 14), /* TCP/IP checksum failed */
590 RxVlanTag = (1 << 16), /* VLAN tag available */
591};
592
593#define RsvdMask 0x3fffc000
12d42c50 594#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
1da177e4
LT		 595
596struct TxDesc {
6cccd6e7
REB		 597 __le32 opts1;
598 __le32 opts2;
599 __le64 addr;
1da177e4
LT		 600};
601
602struct RxDesc {
6cccd6e7
REB		 603 __le32 opts1;
604 __le32 opts2;
605 __le64 addr;
1da177e4
LT		 606};
607
608struct ring_info {
609 struct sk_buff *skb;
610 u32 len;
611 u8 __pad[sizeof(void *) - sizeof(u32)];
612};
613
355423d0
IV		 614struct rtl8169_counters {
615 __le64 tx_packets;
616 __le64 rx_packets;
617 __le64 tx_errors;
618 __le32 rx_errors;
619 __le16 rx_missed;
620 __le16 align_errors;
621 __le32 tx_one_collision;
622 __le32 tx_multi_collision;
623 __le64 rx_unicast;
624 __le64 rx_broadcast;
625 __le32 rx_multicast;
626 __le16 tx_aborted;
627 __le16 tx_underun;
628};
629
6e85d5ad
CV		 630struct rtl8169_tc_offsets {
631 bool inited;
632 __le64 tx_errors;
633 __le32 tx_multi_collision;
6e85d5ad
CV		 634 __le16 tx_aborted;
635};
636
da78dbff 637enum rtl_flag {
6ad56901 638 RTL_FLAG_TASK_ENABLED = 0,
da78dbff
FR		 639 RTL_FLAG_TASK_SLOW_PENDING,
640 RTL_FLAG_TASK_RESET_PENDING,
da78dbff
FR		 641 RTL_FLAG_MAX
642};
643
8027aa24
JW		 644struct rtl8169_stats {
645 u64 packets;
646 u64 bytes;
647 struct u64_stats_sync syncp;
648};
649
1da177e4
LT		 650struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 652 struct pci_dev *pci_dev;
c4028958 653 struct net_device *dev;
bea3348e 654 struct napi_struct napi;
b57b7e5a 655 u32 msg_enable;
2b7b4318 656 u16 mac_version;
1da177e4
LT		 657 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
658 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
1da177e4 659 u32 dirty_tx;
8027aa24
JW		 660 struct rtl8169_stats rx_stats;
661 struct rtl8169_stats tx_stats;
1da177e4
LT		 662 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
663 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
664 dma_addr_t TxPhyAddr;
665 dma_addr_t RxPhyAddr;
6f0333b8 666 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 667 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4 668 u16 cp_cmd;
da78dbff
FR		 669
670 u16 event_slow;
50970831 671 const struct rtl_coalesce_info *coalesce_info;
c2f6f3ee 672 struct clk *clk;
c0e45c1c 673
674 struct mdio_ops {
24192210
FR		 675 void (*write)(struct rtl8169_private *, int, int);
676 int (*read)(struct rtl8169_private *, int);
c0e45c1c 677 } mdio_ops;
678
d58d46b5
FR		 679 struct jumbo_ops {
680 void (*enable)(struct rtl8169_private *);
681 void (*disable)(struct rtl8169_private *);
682 } jumbo_ops;
683
61cb532d 684 void (*hw_start)(struct rtl8169_private *tp);
5888d3fc 685 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
4422bcd4
FR		 686
687 struct {
da78dbff
FR		 688 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
689 struct mutex mutex;
4422bcd4
FR		 690 struct work_struct work;
691 } wk;
692
f7ffa9ae 693 unsigned supports_gmii:1;
f1e911d5 694 struct mii_bus *mii_bus;
42020320
CV		 695 dma_addr_t counters_phys_addr;
696 struct rtl8169_counters *counters;
6e85d5ad 697 struct rtl8169_tc_offsets tc_offset;
e1759441 698 u32 saved_wolopts;
f1e02ed1 699
b6ffd97f
FR		 700 struct rtl_fw {
701 const struct firmware *fw;
1c361efb
FR		 702
703#define RTL_VER_SIZE 32
704
705 char version[RTL_VER_SIZE];
706
707 struct rtl_fw_phy_action {
708 __le32 *code;
709 size_t size;
710 } phy_action;
b6ffd97f 711 } *rtl_fw;
497888cf 712#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
c558386b
HW		 713
714 u32 ocp_base;
1da177e4
LT		 715};
716
979b6c13 717MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 718MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 719module_param(use_dac, int, 0);
4300e8c7 720MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 721module_param_named(debug, debug.msg_enable, int, 0);
722MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
6e09bef3 723MODULE_SOFTDEP("pre: realtek");
1da177e4 724MODULE_LICENSE("GPL");
bca03d5f 725MODULE_FIRMWARE(FIRMWARE_8168D_1);
726MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 727MODULE_FIRMWARE(FIRMWARE_8168E_1);
728MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 729MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 730MODULE_FIRMWARE(FIRMWARE_8105E_1);
c2218925
HW		 731MODULE_FIRMWARE(FIRMWARE_8168F_1);
732MODULE_FIRMWARE(FIRMWARE_8168F_2);
7e18dca1 733MODULE_FIRMWARE(FIRMWARE_8402_1);
b3d7b2f2 734MODULE_FIRMWARE(FIRMWARE_8411_1);
45dd95c4 735MODULE_FIRMWARE(FIRMWARE_8411_2);
5598bfe5 736MODULE_FIRMWARE(FIRMWARE_8106E_1);
58152cd4 737MODULE_FIRMWARE(FIRMWARE_8106E_2);
beb330a4 738MODULE_FIRMWARE(FIRMWARE_8168G_2);
57538c4a 739MODULE_FIRMWARE(FIRMWARE_8168G_3);
6e1d0b89
CHL		 740MODULE_FIRMWARE(FIRMWARE_8168H_1);
741MODULE_FIRMWARE(FIRMWARE_8168H_2);
a3bf5c42
FR		 742MODULE_FIRMWARE(FIRMWARE_8107E_1);
743MODULE_FIRMWARE(FIRMWARE_8107E_2);
1da177e4 744
1e1205b7
HK		 745static inline struct device *tp_to_dev(struct rtl8169_private *tp)
746{
747 return &tp->pci_dev->dev;
748}
749
da78dbff
FR		 750static void rtl_lock_work(struct rtl8169_private *tp)
751{
752 mutex_lock(&tp->wk.mutex);
753}
754
755static void rtl_unlock_work(struct rtl8169_private *tp)
756{
757 mutex_unlock(&tp->wk.mutex);
758}
759
cb73200c 760static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
d58d46b5 761{
cb73200c 762 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
7d7903b2 763 PCI_EXP_DEVCTL_READRQ, force);
d58d46b5
FR		 764}
765
ffc46952
FR		 766struct rtl_cond {
767 bool (*check)(struct rtl8169_private *);
768 const char *msg;
769};
770
771static void rtl_udelay(unsigned int d)
772{
773 udelay(d);
774}
775
776static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
777 void (*delay)(unsigned int), unsigned int d, int n,
778 bool high)
779{
780 int i;
781
782 for (i = 0; i < n; i++) {
783 delay(d);
784 if (c->check(tp) == high)
785 return true;
786 }
82e316ef
FR		 787 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
788 c->msg, !high, n, d);
ffc46952
FR		 789 return false;
790}
791
792static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
793 const struct rtl_cond *c,
794 unsigned int d, int n)
795{
796 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
797}
798
799static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
800 const struct rtl_cond *c,
801 unsigned int d, int n)
802{
803 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
804}
805
806static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
807 const struct rtl_cond *c,
808 unsigned int d, int n)
809{
810 return rtl_loop_wait(tp, c, msleep, d, n, true);
811}
812
813static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
814 const struct rtl_cond *c,
815 unsigned int d, int n)
816{
817 return rtl_loop_wait(tp, c, msleep, d, n, false);
818}
819
820#define DECLARE_RTL_COND(name) \
821static bool name ## _check(struct rtl8169_private *); \
822 \
823static const struct rtl_cond name = { \
824 .check = name ## _check, \
825 .msg = #name \
826}; \
827 \
828static bool name ## _check(struct rtl8169_private *tp)
829
c558386b
HW		 830static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
831{
832 if (reg & 0xffff0001) {
833 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
834 return true;
835 }
836 return false;
837}
838
839DECLARE_RTL_COND(rtl_ocp_gphy_cond)
840{
1ef7286e 841 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
c558386b
HW		 842}
843
844static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
845{
c558386b
HW		 846 if (rtl_ocp_reg_failure(tp, reg))
847 return;
848
1ef7286e 849 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 850
851 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
852}
853
854static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
855{
c558386b
HW		 856 if (rtl_ocp_reg_failure(tp, reg))
857 return 0;
858
1ef7286e 859 RTL_W32(tp, GPHY_OCP, reg << 15);
c558386b
HW		 860
861 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1ef7286e 862 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
c558386b
HW		 863}
864
c558386b
HW		 865static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
866{
c558386b
HW		 867 if (rtl_ocp_reg_failure(tp, reg))
868 return;
869
1ef7286e 870 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
c558386b
HW		 871}
872
873static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
874{
c558386b
HW		 875 if (rtl_ocp_reg_failure(tp, reg))
876 return 0;
877
1ef7286e 878 RTL_W32(tp, OCPDR, reg << 15);
c558386b 879
1ef7286e 880 return RTL_R32(tp, OCPDR);
c558386b
HW		 881}
882
883#define OCP_STD_PHY_BASE 0xa400
884
885static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
886{
887 if (reg == 0x1f) {
888 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
889 return;
890 }
891
892 if (tp->ocp_base != OCP_STD_PHY_BASE)
893 reg -= 0x10;
894
895 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
896}
897
898static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
899{
900 if (tp->ocp_base != OCP_STD_PHY_BASE)
901 reg -= 0x10;
902
903 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
904}
905
eee3786f 906static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
907{
908 if (reg == 0x1f) {
909 tp->ocp_base = value << 4;
910 return;
911 }
912
913 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
914}
915
916static int mac_mcu_read(struct rtl8169_private *tp, int reg)
917{
918 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
919}
920
ffc46952
FR		 921DECLARE_RTL_COND(rtl_phyar_cond)
922{
1ef7286e 923 return RTL_R32(tp, PHYAR) & 0x80000000;
ffc46952
FR		 924}
925
24192210 926static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1da177e4 927{
1ef7286e 928 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1da177e4 929
ffc46952 930 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
024a07ba 931 /*
81a95f04
TT		 932 * According to hardware specs a 20us delay is required after write
933 * complete indication, but before sending next command.
024a07ba 934 */
81a95f04 935 udelay(20);
1da177e4
LT		 936}
937
24192210 938static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1da177e4 939{
ffc46952 940 int value;
1da177e4 941
1ef7286e 942 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1da177e4 943
ffc46952 944 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1ef7286e 945 RTL_R32(tp, PHYAR) & 0xffff : ~0;
ffc46952 946
81a95f04
TT		 947 /*
948 * According to hardware specs a 20us delay is required after read
949 * complete indication, but before sending next command.
950 */
951 udelay(20);
952
1da177e4
LT		 953 return value;
954}
955
935e2218
CHL		 956DECLARE_RTL_COND(rtl_ocpar_cond)
957{
1ef7286e 958 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
935e2218
CHL		 959}
960
24192210 961static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
c0e45c1c 962{
1ef7286e
AS		 963 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
964 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
965 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 966
ffc46952 967 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
c0e45c1c 968}
969
24192210 970static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
c0e45c1c 971{
24192210
FR		 972 r8168dp_1_mdio_access(tp, reg,
973 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
c0e45c1c 974}
975
24192210 976static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
c0e45c1c 977{
24192210 978 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
c0e45c1c 979
980 mdelay(1);
1ef7286e
AS		 981 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
982 RTL_W32(tp, EPHY_RXER_NUM, 0);
c0e45c1c 983
ffc46952 984 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1ef7286e 985 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
c0e45c1c 986}
987
e6de30d6 988#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
989
1ef7286e 990static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
e6de30d6 991{
1ef7286e 992 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 993}
994
1ef7286e 995static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
e6de30d6 996{
1ef7286e 997 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
e6de30d6 998}
999
24192210 1000static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
e6de30d6 1001{
1ef7286e 1002 r8168dp_2_mdio_start(tp);
e6de30d6 1003
24192210 1004 r8169_mdio_write(tp, reg, value);
e6de30d6 1005
1ef7286e 1006 r8168dp_2_mdio_stop(tp);
e6de30d6 1007}
1008
24192210 1009static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
e6de30d6 1010{
1011 int value;
1012
1ef7286e 1013 r8168dp_2_mdio_start(tp);
e6de30d6 1014
24192210 1015 value = r8169_mdio_read(tp, reg);
e6de30d6 1016
1ef7286e 1017 r8168dp_2_mdio_stop(tp);
e6de30d6 1018
1019 return value;
1020}
1021
4da19633 1022static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 1023{
24192210 1024 tp->mdio_ops.write(tp, location, val);
dacf8154
FR		 1025}
1026
4da19633 1027static int rtl_readphy(struct rtl8169_private *tp, int location)
1028{
24192210 1029 return tp->mdio_ops.read(tp, location);
4da19633 1030}
1031
1032static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1033{
1034 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1035}
1036
76564428 1037static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 1038{
1039 int val;
1040
4da19633 1041 val = rtl_readphy(tp, reg_addr);
76564428 1042 rtl_writephy(tp, reg_addr, (val & ~m) | p);
daf9df6d 1043}
1044
ffc46952
FR		 1045DECLARE_RTL_COND(rtl_ephyar_cond)
1046{
1ef7286e 1047 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
ffc46952
FR		 1048}
1049
fdf6fc06 1050static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
dacf8154 1051{
1ef7286e 1052 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
dacf8154
FR		 1053 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1054
ffc46952
FR		 1055 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1056
1057 udelay(10);
dacf8154
FR		 1058}
1059
fdf6fc06 1060static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
dacf8154 1061{
1ef7286e 1062 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
dacf8154 1063
ffc46952 1064 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1ef7286e 1065 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
dacf8154
FR		 1066}
1067
935e2218
CHL		 1068DECLARE_RTL_COND(rtl_eriar_cond)
1069{
1ef7286e 1070 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
935e2218
CHL		 1071}
1072
fdf6fc06
FR		 1073static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1074 u32 val, int type)
133ac40a 1075{
133ac40a 1076 BUG_ON((addr & 3) || (mask == 0));
1ef7286e
AS		 1077 RTL_W32(tp, ERIDR, val);
1078 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
133ac40a 1079
ffc46952 1080 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
133ac40a
HW		 1081}
1082
fdf6fc06 1083static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
133ac40a 1084{
1ef7286e 1085 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
133ac40a 1086
ffc46952 1087 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1ef7286e 1088 RTL_R32(tp, ERIDR) : ~0;
133ac40a
HW		 1089}
1090
706123d0 1091static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
fdf6fc06 1092 u32 m, int type)
133ac40a
HW		 1093{
1094 u32 val;
1095
fdf6fc06
FR		 1096 val = rtl_eri_read(tp, addr, type);
1097 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
133ac40a
HW		 1098}
1099
935e2218
CHL		 1100static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1101{
1ef7286e 1102 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218 1103 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1ef7286e 1104 RTL_R32(tp, OCPDR) : ~0;
935e2218
CHL		 1105}
1106
1107static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1108{
1109 return rtl_eri_read(tp, reg, ERIAR_OOB);
1110}
1111
1112static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1113{
1114 switch (tp->mac_version) {
1115 case RTL_GIGA_MAC_VER_27:
1116 case RTL_GIGA_MAC_VER_28:
1117 case RTL_GIGA_MAC_VER_31:
1118 return r8168dp_ocp_read(tp, mask, reg);
1119 case RTL_GIGA_MAC_VER_49:
1120 case RTL_GIGA_MAC_VER_50:
1121 case RTL_GIGA_MAC_VER_51:
1122 return r8168ep_ocp_read(tp, mask, reg);
1123 default:
1124 BUG();
1125 return ~0;
1126 }
1127}
1128
1129static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1130 u32 data)
1131{
1ef7286e
AS		 1132 RTL_W32(tp, OCPDR, data);
1133 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
935e2218
CHL		 1134 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1135}
1136
1137static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1138 u32 data)
1139{
1140 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1141 data, ERIAR_OOB);
1142}
1143
1144static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1145{
1146 switch (tp->mac_version) {
1147 case RTL_GIGA_MAC_VER_27:
1148 case RTL_GIGA_MAC_VER_28:
1149 case RTL_GIGA_MAC_VER_31:
1150 r8168dp_ocp_write(tp, mask, reg, data);
1151 break;
1152 case RTL_GIGA_MAC_VER_49:
1153 case RTL_GIGA_MAC_VER_50:
1154 case RTL_GIGA_MAC_VER_51:
1155 r8168ep_ocp_write(tp, mask, reg, data);
1156 break;
1157 default:
1158 BUG();
1159 break;
1160 }
1161}
1162
2a9b4d96
CHL		 1163static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1164{
1165 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1166
1167 ocp_write(tp, 0x1, 0x30, 0x00000001);
1168}
1169
1170#define OOB_CMD_RESET 0x00
1171#define OOB_CMD_DRIVER_START 0x05
1172#define OOB_CMD_DRIVER_STOP 0x06
1173
1174static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1175{
1176 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1177}
1178
1179DECLARE_RTL_COND(rtl_ocp_read_cond)
1180{
1181 u16 reg;
1182
1183 reg = rtl8168_get_ocp_reg(tp);
1184
1185 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1186}
1187
935e2218 1188DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
2a9b4d96 1189{
935e2218
CHL		 1190 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1191}
1192
1193DECLARE_RTL_COND(rtl_ocp_tx_cond)
1194{
1ef7286e 1195 return RTL_R8(tp, IBISR0) & 0x20;
935e2218 1196}
2a9b4d96 1197
003609da
CHL		 1198static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1199{
1ef7286e 1200 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
086ca23d 1201 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1ef7286e
AS		 1202 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1203 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
003609da
CHL		 1204}
1205
935e2218
CHL		 1206static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1207{
1208 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
2a9b4d96
CHL		 1209 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1210}
1211
935e2218 1212static void rtl8168ep_driver_start(struct rtl8169_private *tp)
2a9b4d96 1213{
935e2218
CHL		 1214 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1215 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1216 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1217}
1218
1219static void rtl8168_driver_start(struct rtl8169_private *tp)
1220{
1221 switch (tp->mac_version) {
1222 case RTL_GIGA_MAC_VER_27:
1223 case RTL_GIGA_MAC_VER_28:
1224 case RTL_GIGA_MAC_VER_31:
1225 rtl8168dp_driver_start(tp);
1226 break;
1227 case RTL_GIGA_MAC_VER_49:
1228 case RTL_GIGA_MAC_VER_50:
1229 case RTL_GIGA_MAC_VER_51:
1230 rtl8168ep_driver_start(tp);
1231 break;
1232 default:
1233 BUG();
1234 break;
1235 }
1236}
2a9b4d96 1237
935e2218
CHL		 1238static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1239{
1240 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
2a9b4d96
CHL		 1241 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1242}
1243
935e2218
CHL		 1244static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1245{
003609da 1246 rtl8168ep_stop_cmac(tp);
935e2218
CHL		 1247 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1248 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1249 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1250}
1251
1252static void rtl8168_driver_stop(struct rtl8169_private *tp)
1253{
1254 switch (tp->mac_version) {
1255 case RTL_GIGA_MAC_VER_27:
1256 case RTL_GIGA_MAC_VER_28:
1257 case RTL_GIGA_MAC_VER_31:
1258 rtl8168dp_driver_stop(tp);
1259 break;
1260 case RTL_GIGA_MAC_VER_49:
1261 case RTL_GIGA_MAC_VER_50:
1262 case RTL_GIGA_MAC_VER_51:
1263 rtl8168ep_driver_stop(tp);
1264 break;
1265 default:
1266 BUG();
1267 break;
1268 }
1269}
1270
9dbe7896 1271static bool r8168dp_check_dash(struct rtl8169_private *tp)
2a9b4d96
CHL		 1272{
1273 u16 reg = rtl8168_get_ocp_reg(tp);
1274
9dbe7896 1275 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
2a9b4d96
CHL		 1276}
1277
9dbe7896 1278static bool r8168ep_check_dash(struct rtl8169_private *tp)
935e2218 1279{
9dbe7896 1280 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
935e2218
CHL		 1281}
1282
9dbe7896 1283static bool r8168_check_dash(struct rtl8169_private *tp)
935e2218
CHL		 1284{
1285 switch (tp->mac_version) {
1286 case RTL_GIGA_MAC_VER_27:
1287 case RTL_GIGA_MAC_VER_28:
1288 case RTL_GIGA_MAC_VER_31:
1289 return r8168dp_check_dash(tp);
1290 case RTL_GIGA_MAC_VER_49:
1291 case RTL_GIGA_MAC_VER_50:
1292 case RTL_GIGA_MAC_VER_51:
1293 return r8168ep_check_dash(tp);
1294 default:
9dbe7896 1295 return false;
935e2218
CHL		 1296 }
1297}
1298
c28aa385 1299struct exgmac_reg {
1300 u16 addr;
1301 u16 mask;
1302 u32 val;
1303};
1304
fdf6fc06 1305static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
c28aa385 1306 const struct exgmac_reg *r, int len)
1307{
1308 while (len-- > 0) {
fdf6fc06 1309 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
c28aa385 1310 r++;
1311 }
1312}
1313
ffc46952
FR		 1314DECLARE_RTL_COND(rtl_efusear_cond)
1315{
1ef7286e 1316 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
ffc46952
FR		 1317}
1318
fdf6fc06 1319static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
daf9df6d 1320{
1ef7286e 1321 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
daf9df6d 1322
ffc46952 1323 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1ef7286e 1324 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
daf9df6d 1325}
1326
9085cdfa
FR		 1327static u16 rtl_get_events(struct rtl8169_private *tp)
1328{
1ef7286e 1329 return RTL_R16(tp, IntrStatus);
9085cdfa
FR		 1330}
1331
1332static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1333{
1ef7286e 1334 RTL_W16(tp, IntrStatus, bits);
9085cdfa
FR		 1335 mmiowb();
1336}
1337
1338static void rtl_irq_disable(struct rtl8169_private *tp)
1339{
1ef7286e 1340 RTL_W16(tp, IntrMask, 0);
9085cdfa
FR		 1341 mmiowb();
1342}
1343
3e990ff5
FR		 1344static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1345{
1ef7286e 1346 RTL_W16(tp, IntrMask, bits);
3e990ff5
FR		 1347}
1348
da78dbff
FR		 1349#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1350#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1351#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1352
1353static void rtl_irq_enable_all(struct rtl8169_private *tp)
1354{
1355 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1356}
1357
811fd301 1358static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1da177e4 1359{
9085cdfa 1360 rtl_irq_disable(tp);
da78dbff 1361 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1ef7286e 1362 RTL_R8(tp, ChipCmd);
1da177e4
LT		 1363}
1364
70090424
HW		 1365static void rtl_link_chg_patch(struct rtl8169_private *tp)
1366{
70090424 1367 struct net_device *dev = tp->dev;
29a12b49 1368 struct phy_device *phydev = dev->phydev;
70090424
HW		 1369
1370 if (!netif_running(dev))
1371 return;
1372
b3d7b2f2
HW		 1373 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1374 tp->mac_version == RTL_GIGA_MAC_VER_38) {
29a12b49 1375 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1376 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1377 ERIAR_EXGMAC);
1378 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1379 ERIAR_EXGMAC);
29a12b49 1380 } else if (phydev->speed == SPEED_100) {
fdf6fc06
FR		 1381 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1382 ERIAR_EXGMAC);
1383 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1384 ERIAR_EXGMAC);
70090424 1385 } else {
fdf6fc06
FR		 1386 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1387 ERIAR_EXGMAC);
1388 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1389 ERIAR_EXGMAC);
70090424
HW		 1390 }
1391 /* Reset packet filter */
706123d0 1392 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
70090424 1393 ERIAR_EXGMAC);
706123d0 1394 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
70090424 1395 ERIAR_EXGMAC);
c2218925
HW		 1396 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1397 tp->mac_version == RTL_GIGA_MAC_VER_36) {
29a12b49 1398 if (phydev->speed == SPEED_1000) {
fdf6fc06
FR		 1399 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1400 ERIAR_EXGMAC);
1401 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1402 ERIAR_EXGMAC);
c2218925 1403 } else {
fdf6fc06
FR		 1404 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1405 ERIAR_EXGMAC);
1406 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1407 ERIAR_EXGMAC);
c2218925 1408 }
7e18dca1 1409 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
29a12b49 1410 if (phydev->speed == SPEED_10) {
fdf6fc06
FR		 1411 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1412 ERIAR_EXGMAC);
1413 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1414 ERIAR_EXGMAC);
7e18dca1 1415 } else {
fdf6fc06
FR		 1416 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1417 ERIAR_EXGMAC);
7e18dca1 1418 }
70090424
HW		 1419 }
1420}
1421
e1759441
RW		 1422#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1423
1424static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1425{
61a4dcc2 1426 u8 options;
e1759441 1427 u32 wolopts = 0;
61a4dcc2 1428
1ef7286e 1429 options = RTL_R8(tp, Config1);
61a4dcc2 1430 if (!(options & PMEnable))
e1759441 1431 return 0;
61a4dcc2 1432
1ef7286e 1433 options = RTL_R8(tp, Config3);
61a4dcc2 1434 if (options & LinkUp)
e1759441 1435 wolopts |= WAKE_PHY;
6e1d0b89 1436 switch (tp->mac_version) {
2a71883c
HK		 1437 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1438 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1439 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1440 wolopts |= WAKE_MAGIC;
1441 break;
1442 default:
1443 if (options & MagicPacket)
1444 wolopts |= WAKE_MAGIC;
1445 break;
1446 }
61a4dcc2 1447
1ef7286e 1448 options = RTL_R8(tp, Config5);
61a4dcc2 1449 if (options & UWF)
e1759441 1450 wolopts |= WAKE_UCAST;
61a4dcc2 1451 if (options & BWF)
e1759441 1452 wolopts |= WAKE_BCAST;
61a4dcc2 1453 if (options & MWF)
e1759441 1454 wolopts |= WAKE_MCAST;
61a4dcc2 1455
e1759441 1456 return wolopts;
61a4dcc2
FR		 1457}
1458
e1759441 1459static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1460{
1461 struct rtl8169_private *tp = netdev_priv(dev);
e1759441 1462
da78dbff 1463 rtl_lock_work(tp);
e1759441 1464 wol->supported = WAKE_ANY;
433f9d0d 1465 wol->wolopts = tp->saved_wolopts;
da78dbff 1466 rtl_unlock_work(tp);
e1759441
RW		 1467}
1468
1469static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1470{
6e1d0b89 1471 unsigned int i, tmp;
350f7596 1472 static const struct {
61a4dcc2
FR		 1473 u32 opt;
1474 u16 reg;
1475 u8 mask;
1476 } cfg[] = {
61a4dcc2 1477 { WAKE_PHY, Config3, LinkUp },
61a4dcc2
FR		 1478 { WAKE_UCAST, Config5, UWF },
1479 { WAKE_BCAST, Config5, BWF },
1480 { WAKE_MCAST, Config5, MWF },
6e1d0b89
CHL		 1481 { WAKE_ANY, Config5, LanWake },
1482 { WAKE_MAGIC, Config3, MagicPacket }
61a4dcc2 1483 };
851e6022 1484 u8 options;
61a4dcc2 1485
1ef7286e 1486 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
61a4dcc2 1487
6e1d0b89 1488 switch (tp->mac_version) {
2a71883c
HK		 1489 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1490 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
6e1d0b89
CHL		 1491 tmp = ARRAY_SIZE(cfg) - 1;
1492 if (wolopts & WAKE_MAGIC)
706123d0 1493 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1494 0x0dc,
1495 ERIAR_MASK_0100,
1496 MagicPacket_v2,
1497 0x0000,
1498 ERIAR_EXGMAC);
1499 else
706123d0 1500 rtl_w0w1_eri(tp,
6e1d0b89
CHL		 1501 0x0dc,
1502 ERIAR_MASK_0100,
1503 0x0000,
1504 MagicPacket_v2,
1505 ERIAR_EXGMAC);
1506 break;
1507 default:
1508 tmp = ARRAY_SIZE(cfg);
1509 break;
1510 }
1511
1512 for (i = 0; i < tmp; i++) {
1ef7286e 1513 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
e1759441 1514 if (wolopts & cfg[i].opt)
61a4dcc2 1515 options |= cfg[i].mask;
1ef7286e 1516 RTL_W8(tp, cfg[i].reg, options);
61a4dcc2
FR		 1517 }
1518
851e6022
FR		 1519 switch (tp->mac_version) {
1520 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1ef7286e 1521 options = RTL_R8(tp, Config1) & ~PMEnable;
851e6022
FR		 1522 if (wolopts)
1523 options |= PMEnable;
1ef7286e 1524 RTL_W8(tp, Config1, options);
851e6022
FR		 1525 break;
1526 default:
1ef7286e 1527 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
d387b427
FR		 1528 if (wolopts)
1529 options |= PME_SIGNAL;
1ef7286e 1530 RTL_W8(tp, Config2, options);
851e6022
FR		 1531 break;
1532 }
1533
1ef7286e 1534 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
648458fe
HK		 1535
1536 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
e1759441
RW		 1537}
1538
1539static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1540{
1541 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1542 struct device *d = tp_to_dev(tp);
5fa80a32 1543
2f533f6b
HK		 1544 if (wol->wolopts & ~WAKE_ANY)
1545 return -EINVAL;
1546
5fa80a32 1547 pm_runtime_get_noresume(d);
e1759441 1548
da78dbff 1549 rtl_lock_work(tp);
61a4dcc2 1550
2f533f6b 1551 tp->saved_wolopts = wol->wolopts;
433f9d0d 1552
5fa80a32 1553 if (pm_runtime_active(d))
433f9d0d 1554 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff
FR		 1555
1556 rtl_unlock_work(tp);
61a4dcc2 1557
5fa80a32
CHL		 1558 pm_runtime_put_noidle(d);
1559
61a4dcc2
FR		 1560 return 0;
1561}
1562
31bd204f
FR		 1563static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1564{
85bffe6c 1565 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1566}
1567
1da177e4
LT		 1568static void rtl8169_get_drvinfo(struct net_device *dev,
1569 struct ethtool_drvinfo *info)
1570{
1571 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1572 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4 1573
68aad78c 1574 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
68aad78c 1575 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1c361efb 1576 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
8ac72d16
RJ		 1577 if (!IS_ERR_OR_NULL(rtl_fw))
1578 strlcpy(info->fw_version, rtl_fw->version,
1579 sizeof(info->fw_version));
1da177e4
LT		 1580}
1581
1582static int rtl8169_get_regs_len(struct net_device *dev)
1583{
1584 return R8169_REGS_SIZE;
1585}
1586
c8f44aff
MM		 1587static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1588 netdev_features_t features)
1da177e4 1589{
d58d46b5
FR		 1590 struct rtl8169_private *tp = netdev_priv(dev);
1591
2b7b4318 1592 if (dev->mtu > TD_MSS_MAX)
350fb32a 1593 features &= ~NETIF_F_ALL_TSO;
1da177e4 1594
d58d46b5 1595 if (dev->mtu > JUMBO_1K &&
6ed0e08f 1596 tp->mac_version > RTL_GIGA_MAC_VER_06)
d58d46b5
FR		 1597 features &= ~NETIF_F_IP_CSUM;
1598
350fb32a 1599 return features;
1da177e4
LT		 1600}
1601
a3984578
HK		 1602static int rtl8169_set_features(struct net_device *dev,
1603 netdev_features_t features)
1da177e4
LT		 1604{
1605 struct rtl8169_private *tp = netdev_priv(dev);
929a031d 1606 u32 rx_config;
1da177e4 1607
a3984578
HK		 1608 rtl_lock_work(tp);
1609
1ef7286e 1610 rx_config = RTL_R32(tp, RxConfig);
929a031d 1611 if (features & NETIF_F_RXALL)
1612 rx_config |= (AcceptErr | AcceptRunt);
1613 else
1614 rx_config &= ~(AcceptErr | AcceptRunt);
1da177e4 1615
1ef7286e 1616 RTL_W32(tp, RxConfig, rx_config);
350fb32a 1617
929a031d 1618 if (features & NETIF_F_RXCSUM)
1619 tp->cp_cmd |= RxChkSum;
1620 else
1621 tp->cp_cmd &= ~RxChkSum;
6bbe021d 1622
929a031d 1623 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1624 tp->cp_cmd |= RxVlan;
1625 else
1626 tp->cp_cmd &= ~RxVlan;
1627
1ef7286e
AS		 1628 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1629 RTL_R16(tp, CPlusCmd);
1da177e4 1630
da78dbff 1631 rtl_unlock_work(tp);
1da177e4
LT		 1632
1633 return 0;
1634}
1635
810f4893 1636static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1da177e4 1637{
df8a39de
JP		 1638 return (skb_vlan_tag_present(skb)) ?
1639 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1da177e4
LT		 1640}
1641
7a8fc77b 1642static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1643{
1644 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1645
7a8fc77b 1646 if (opts2 & RxVlanTag)
86a9bad3 1647 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1da177e4
LT		 1648}
1649
1da177e4
LT		 1650static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1651 void *p)
1652{
5b0384f4 1653 struct rtl8169_private *tp = netdev_priv(dev);
15edae91
PW		 1654 u32 __iomem *data = tp->mmio_addr;
1655 u32 *dw = p;
1656 int i;
1da177e4 1657
da78dbff 1658 rtl_lock_work(tp);
15edae91
PW		 1659 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1660 memcpy_fromio(dw++, data++, 4);
da78dbff 1661 rtl_unlock_work(tp);
1da177e4
LT		 1662}
1663
b57b7e5a
SH		 1664static u32 rtl8169_get_msglevel(struct net_device *dev)
1665{
1666 struct rtl8169_private *tp = netdev_priv(dev);
1667
1668 return tp->msg_enable;
1669}
1670
1671static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1672{
1673 struct rtl8169_private *tp = netdev_priv(dev);
1674
1675 tp->msg_enable = value;
1676}
1677
d4a3a0fc
SH		 1678static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1679 "tx_packets",
1680 "rx_packets",
1681 "tx_errors",
1682 "rx_errors",
1683 "rx_missed",
1684 "align_errors",
1685 "tx_single_collisions",
1686 "tx_multi_collisions",
1687 "unicast",
1688 "broadcast",
1689 "multicast",
1690 "tx_aborted",
1691 "tx_underrun",
1692};
1693
b9f2c044 1694static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1695{
b9f2c044
JG		 1696 switch (sset) {
1697 case ETH_SS_STATS:
1698 return ARRAY_SIZE(rtl8169_gstrings);
1699 default:
1700 return -EOPNOTSUPP;
1701 }
d4a3a0fc
SH		 1702}
1703
42020320 1704DECLARE_RTL_COND(rtl_counters_cond)
6e85d5ad 1705{
1ef7286e 1706 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
6e85d5ad
CV		 1707}
1708
e71c9ce2 1709static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
6e85d5ad 1710{
42020320
CV		 1711 dma_addr_t paddr = tp->counters_phys_addr;
1712 u32 cmd;
6e85d5ad 1713
1ef7286e
AS		 1714 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1715 RTL_R32(tp, CounterAddrHigh);
42020320 1716 cmd = (u64)paddr & DMA_BIT_MASK(32);
1ef7286e
AS		 1717 RTL_W32(tp, CounterAddrLow, cmd);
1718 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
6e85d5ad 1719
a78e9366 1720 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
6e85d5ad
CV		 1721}
1722
e71c9ce2 1723static bool rtl8169_reset_counters(struct rtl8169_private *tp)
6e85d5ad 1724{
6e85d5ad
CV		 1725 /*
1726 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1727 * tally counters.
1728 */
1729 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1730 return true;
1731
e71c9ce2 1732 return rtl8169_do_counters(tp, CounterReset);
ffc46952
FR		 1733}
1734
e71c9ce2 1735static bool rtl8169_update_counters(struct rtl8169_private *tp)
d4a3a0fc 1736{
d976151a
HK		 1737 u8 val = RTL_R8(tp, ChipCmd);
1738
355423d0
IV		 1739 /*
1740 * Some chips are unable to dump tally counters when the receiver
d976151a 1741 * is disabled. If 0xff chip may be in a PCI power-save state.
355423d0 1742 */
d976151a 1743 if (!(val & CmdRxEnb) || val == 0xff)
6e85d5ad 1744 return true;
d4a3a0fc 1745
e71c9ce2 1746 return rtl8169_do_counters(tp, CounterDump);
6e85d5ad
CV		 1747}
1748
e71c9ce2 1749static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
6e85d5ad 1750{
42020320 1751 struct rtl8169_counters *counters = tp->counters;
6e85d5ad
CV		 1752 bool ret = false;
1753
1754 /*
1755 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1756 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1757 * reset by a power cycle, while the counter values collected by the
1758 * driver are reset at every driver unload/load cycle.
1759 *
1760 * To make sure the HW values returned by @get_stats64 match the SW
1761 * values, we collect the initial values at first open(*) and use them
1762 * as offsets to normalize the values returned by @get_stats64.
1763 *
1764 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1765 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1766 * set at open time by rtl_hw_start.
1767 */
1768
1769 if (tp->tc_offset.inited)
1770 return true;
1771
1772 /* If both, reset and update fail, propagate to caller. */
e71c9ce2 1773 if (rtl8169_reset_counters(tp))
6e85d5ad
CV		 1774 ret = true;
1775
e71c9ce2 1776 if (rtl8169_update_counters(tp))
6e85d5ad
CV		 1777 ret = true;
1778
42020320
CV		 1779 tp->tc_offset.tx_errors = counters->tx_errors;
1780 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1781 tp->tc_offset.tx_aborted = counters->tx_aborted;
6e85d5ad
CV		 1782 tp->tc_offset.inited = true;
1783
1784 return ret;
d4a3a0fc
SH		 1785}
1786
355423d0
IV		 1787static void rtl8169_get_ethtool_stats(struct net_device *dev,
1788 struct ethtool_stats *stats, u64 *data)
1789{
1790 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 1791 struct device *d = tp_to_dev(tp);
42020320 1792 struct rtl8169_counters *counters = tp->counters;
355423d0
IV		 1793
1794 ASSERT_RTNL();
1795
e0636236
CHL		 1796 pm_runtime_get_noresume(d);
1797
1798 if (pm_runtime_active(d))
e71c9ce2 1799 rtl8169_update_counters(tp);
e0636236
CHL		 1800
1801 pm_runtime_put_noidle(d);
355423d0 1802
42020320
CV		 1803 data[0] = le64_to_cpu(counters->tx_packets);
1804 data[1] = le64_to_cpu(counters->rx_packets);
1805 data[2] = le64_to_cpu(counters->tx_errors);
1806 data[3] = le32_to_cpu(counters->rx_errors);
1807 data[4] = le16_to_cpu(counters->rx_missed);
1808 data[5] = le16_to_cpu(counters->align_errors);
1809 data[6] = le32_to_cpu(counters->tx_one_collision);
1810 data[7] = le32_to_cpu(counters->tx_multi_collision);
1811 data[8] = le64_to_cpu(counters->rx_unicast);
1812 data[9] = le64_to_cpu(counters->rx_broadcast);
1813 data[10] = le32_to_cpu(counters->rx_multicast);
1814 data[11] = le16_to_cpu(counters->tx_aborted);
1815 data[12] = le16_to_cpu(counters->tx_underun);
355423d0
IV		 1816}
1817
d4a3a0fc
SH		 1818static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1819{
1820 switch(stringset) {
1821 case ETH_SS_STATS:
1822 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1823 break;
1824 }
1825}
1826
50970831
FR		 1827/*
1828 * Interrupt coalescing
1829 *
1830 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1831 * > 8169, 8168 and 810x line of chipsets
1832 *
1833 * 8169, 8168, and 8136(810x) serial chipsets support it.
1834 *
1835 * > 2 - the Tx timer unit at gigabit speed
1836 *
1837 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1838 * (0xe0) bit 1 and bit 0.
1839 *
1840 * For 8169
1841 * bit[1:0] \ speed 1000M 100M 10M
1842 * 0 0 320ns 2.56us 40.96us
1843 * 0 1 2.56us 20.48us 327.7us
1844 * 1 0 5.12us 40.96us 655.4us
1845 * 1 1 10.24us 81.92us 1.31ms
1846 *
1847 * For the other
1848 * bit[1:0] \ speed 1000M 100M 10M
1849 * 0 0 5us 2.56us 40.96us
1850 * 0 1 40us 20.48us 327.7us
1851 * 1 0 80us 40.96us 655.4us
1852 * 1 1 160us 81.92us 1.31ms
1853 */
1854
1855/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1856struct rtl_coalesce_scale {
1857 /* Rx / Tx */
1858 u32 nsecs[2];
1859};
1860
1861/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1862struct rtl_coalesce_info {
1863 u32 speed;
1864 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1865};
1866
1867/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1868#define rxtx_x1822(r, t) { \
1869 {{(r), (t)}}, \
1870 {{(r)*8, (t)*8}}, \
1871 {{(r)*8*2, (t)*8*2}}, \
1872 {{(r)*8*2*2, (t)*8*2*2}}, \
1873}
1874static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1875 /* speed delays: rx00 tx00 */
1876 { SPEED_10, rxtx_x1822(40960, 40960) },
1877 { SPEED_100, rxtx_x1822( 2560, 2560) },
1878 { SPEED_1000, rxtx_x1822( 320, 320) },
1879 { 0 },
1880};
1881
1882static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1883 /* speed delays: rx00 tx00 */
1884 { SPEED_10, rxtx_x1822(40960, 40960) },
1885 { SPEED_100, rxtx_x1822( 2560, 2560) },
1886 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1887 { 0 },
1888};
1889#undef rxtx_x1822
1890
1891/* get rx/tx scale vector corresponding to current speed */
1892static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1893{
1894 struct rtl8169_private *tp = netdev_priv(dev);
1895 struct ethtool_link_ksettings ecmd;
1896 const struct rtl_coalesce_info *ci;
1897 int rc;
1898
45772433 1899 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
50970831
FR		 1900 if (rc < 0)
1901 return ERR_PTR(rc);
1902
1903 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1904 if (ecmd.base.speed == ci->speed) {
1905 return ci;
1906 }
1907 }
1908
1909 return ERR_PTR(-ELNRNG);
1910}
1911
1912static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1913{
1914 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1915 const struct rtl_coalesce_info *ci;
1916 const struct rtl_coalesce_scale *scale;
1917 struct {
1918 u32 *max_frames;
1919 u32 *usecs;
1920 } coal_settings [] = {
1921 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1922 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1923 }, *p = coal_settings;
1924 int i;
1925 u16 w;
1926
1927 memset(ec, 0, sizeof(*ec));
1928
1929 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1930 ci = rtl_coalesce_info(dev);
1931 if (IS_ERR(ci))
1932 return PTR_ERR(ci);
1933
0ae0974e 1934 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
50970831
FR		 1935
1936 /* read IntrMitigate and adjust according to scale */
1ef7286e 1937 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
50970831
FR		 1938 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1939 w >>= RTL_COALESCE_SHIFT;
1940 *p->usecs = w & RTL_COALESCE_MASK;
1941 }
1942
1943 for (i = 0; i < 2; i++) {
1944 p = coal_settings + i;
1945 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1946
1947 /*
1948 * ethtool_coalesce says it is illegal to set both usecs and
1949 * max_frames to 0.
1950 */
1951 if (!*p->usecs && !*p->max_frames)
1952 *p->max_frames = 1;
1953 }
1954
1955 return 0;
1956}
1957
1958/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1959static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1960 struct net_device *dev, u32 nsec, u16 *cp01)
1961{
1962 const struct rtl_coalesce_info *ci;
1963 u16 i;
1964
1965 ci = rtl_coalesce_info(dev);
1966 if (IS_ERR(ci))
1967 return ERR_CAST(ci);
1968
1969 for (i = 0; i < 4; i++) {
1970 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1971 ci->scalev[i].nsecs[1]);
1972 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1973 *cp01 = i;
1974 return &ci->scalev[i];
1975 }
1976 }
1977
1978 return ERR_PTR(-EINVAL);
1979}
1980
1981static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1982{
1983 struct rtl8169_private *tp = netdev_priv(dev);
50970831
FR		 1984 const struct rtl_coalesce_scale *scale;
1985 struct {
1986 u32 frames;
1987 u32 usecs;
1988 } coal_settings [] = {
1989 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1990 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1991 }, *p = coal_settings;
1992 u16 w = 0, cp01;
1993 int i;
1994
1995 scale = rtl_coalesce_choose_scale(dev,
1996 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1997 if (IS_ERR(scale))
1998 return PTR_ERR(scale);
1999
2000 for (i = 0; i < 2; i++, p++) {
2001 u32 units;
2002
2003 /*
2004 * accept max_frames=1 we returned in rtl_get_coalesce.
2005 * accept it not only when usecs=0 because of e.g. the following scenario:
2006 *
2007 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2008 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2009 * - then user does `ethtool -C eth0 rx-usecs 100`
2010 *
2011 * since ethtool sends to kernel whole ethtool_coalesce
2012 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2013 * we'll reject it below in `frames % 4 != 0`.
2014 */
2015 if (p->frames == 1) {
2016 p->frames = 0;
2017 }
2018
2019 units = p->usecs * 1000 / scale->nsecs[i];
2020 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2021 return -EINVAL;
2022
2023 w <<= RTL_COALESCE_SHIFT;
2024 w |= units;
2025 w <<= RTL_COALESCE_SHIFT;
2026 w |= p->frames >> 2;
2027 }
2028
2029 rtl_lock_work(tp);
2030
1ef7286e 2031 RTL_W16(tp, IntrMitigate, swab16(w));
50970831 2032
9a3c81fa 2033 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1ef7286e
AS		 2034 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2035 RTL_R16(tp, CPlusCmd);
50970831
FR		 2036
2037 rtl_unlock_work(tp);
2038
2039 return 0;
2040}
2041
7282d491 2042static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 2043 .get_drvinfo = rtl8169_get_drvinfo,
2044 .get_regs_len = rtl8169_get_regs_len,
2045 .get_link = ethtool_op_get_link,
50970831
FR		 2046 .get_coalesce = rtl_get_coalesce,
2047 .set_coalesce = rtl_set_coalesce,
b57b7e5a
SH		 2048 .get_msglevel = rtl8169_get_msglevel,
2049 .set_msglevel = rtl8169_set_msglevel,
1da177e4 2050 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 2051 .get_wol = rtl8169_get_wol,
2052 .set_wol = rtl8169_set_wol,
d4a3a0fc 2053 .get_strings = rtl8169_get_strings,
b9f2c044 2054 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 2055 .get_ethtool_stats = rtl8169_get_ethtool_stats,
e1593bb1 2056 .get_ts_info = ethtool_op_get_ts_info,
dd84957e 2057 .nway_reset = phy_ethtool_nway_reset,
45772433
HK		 2058 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2059 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1da177e4
LT		 2060};
2061
07d3f51f 2062static void rtl8169_get_mac_version(struct rtl8169_private *tp,
22148df0 2063 u8 default_version)
1da177e4 2064{
0e485150
FR		 2065 /*
2066 * The driver currently handles the 8168Bf and the 8168Be identically
2067 * but they can be identified more specifically through the test below
2068 * if needed:
2069 *
1ef7286e 2070 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 2071 *
2072 * Same thing for the 8101Eb and the 8101Ec:
2073 *
1ef7286e 2074 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 2075 */
3744100e 2076 static const struct rtl_mac_info {
1da177e4 2077 u32 mask;
e3cf0cc0 2078 u32 val;
1da177e4
LT		 2079 int mac_version;
2080 } mac_info[] = {
935e2218
CHL		 2081 /* 8168EP family. */
2082 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2083 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2084 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2085
6e1d0b89
CHL		 2086 /* 8168H family. */
2087 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2088 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2089
c558386b 2090 /* 8168G family. */
45dd95c4 2091 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
57538c4a 2092 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
c558386b
HW		 2093 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2094 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2095
c2218925 2096 /* 8168F family. */
b3d7b2f2 2097 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
c2218925
HW		 2098 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2099 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2100
01dc7fec 2101 /* 8168E family. */
70090424 2102 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 2103 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2104 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2105
5b538df9 2106 /* 8168D family. */
daf9df6d 2107 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 2108 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 2109
e6de30d6 2110 /* 8168DP family. */
2111 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2112 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 2113 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 2114
ef808d50 2115 /* 8168C family. */
ef3386f0 2116 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 2117 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 2118 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 2119 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2120 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 2121 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
ef808d50 2122 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 2123
2124 /* 8168B family. */
2125 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
e3cf0cc0
FR		 2126 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2127 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2128
2129 /* 8101 family. */
5598bfe5 2130 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
7e18dca1 2131 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
5a5e4443
HW		 2132 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2133 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 2134 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2135 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2136 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2137 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 2138 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 2139 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 2140 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 2141 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2142 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 2143 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2144 /* FIXME: where did these entries come from ? -- FR */
2145 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2146 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2147
2148 /* 8110 family. */
2149 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2150 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2151 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2152 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2153 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2154 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2155
f21b75e9
JD		 2156 /* Catch-all */
2157 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 2158 };
2159 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 2160 u32 reg;
2161
1ef7286e 2162 reg = RTL_R32(tp, TxConfig);
e3cf0cc0 2163 while ((reg & p->mask) != p->val)
1da177e4
LT		 2164 p++;
2165 tp->mac_version = p->mac_version;
5d320a20
FR		 2166
2167 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
22148df0
HK		 2168 dev_notice(tp_to_dev(tp),
2169 "unknown MAC, using family default\n");
5d320a20 2170 tp->mac_version = default_version;
58152cd4 2171 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
f7ffa9ae 2172 tp->mac_version = tp->supports_gmii ?
58152cd4 2173 RTL_GIGA_MAC_VER_42 :
2174 RTL_GIGA_MAC_VER_43;
6e1d0b89 2175 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
f7ffa9ae 2176 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2177 RTL_GIGA_MAC_VER_45 :
2178 RTL_GIGA_MAC_VER_47;
2179 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
f7ffa9ae 2180 tp->mac_version = tp->supports_gmii ?
6e1d0b89
CHL		 2181 RTL_GIGA_MAC_VER_46 :
2182 RTL_GIGA_MAC_VER_48;
5d320a20 2183 }
1da177e4
LT		 2184}
2185
2186static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2187{
49d17512 2188 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 2189}
2190
867763c1
FR		 2191struct phy_reg {
2192 u16 reg;
2193 u16 val;
2194};
2195
4da19633 2196static void rtl_writephy_batch(struct rtl8169_private *tp,
2197 const struct phy_reg *regs, int len)
867763c1
FR		 2198{
2199 while (len-- > 0) {
4da19633 2200 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 2201 regs++;
2202 }
2203}
2204
bca03d5f 2205#define PHY_READ 0x00000000
2206#define PHY_DATA_OR 0x10000000
2207#define PHY_DATA_AND 0x20000000
2208#define PHY_BJMPN 0x30000000
eee3786f 2209#define PHY_MDIO_CHG 0x40000000
bca03d5f 2210#define PHY_CLEAR_READCOUNT 0x70000000
2211#define PHY_WRITE 0x80000000
2212#define PHY_READCOUNT_EQ_SKIP 0x90000000
2213#define PHY_COMP_EQ_SKIPN 0xa0000000
2214#define PHY_COMP_NEQ_SKIPN 0xb0000000
2215#define PHY_WRITE_PREVIOUS 0xc0000000
2216#define PHY_SKIPN 0xd0000000
2217#define PHY_DELAY_MS 0xe0000000
bca03d5f 2218
960aee6c
HW		 2219struct fw_info {
2220 u32 magic;
2221 char version[RTL_VER_SIZE];
2222 __le32 fw_start;
2223 __le32 fw_len;
2224 u8 chksum;
2225} __packed;
2226
1c361efb
FR		 2227#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2228
2229static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 2230{
b6ffd97f 2231 const struct firmware *fw = rtl_fw->fw;
960aee6c 2232 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 2233 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2234 char *version = rtl_fw->version;
2235 bool rc = false;
2236
2237 if (fw->size < FW_OPCODE_SIZE)
2238 goto out;
960aee6c
HW		 2239
2240 if (!fw_info->magic) {
2241 size_t i, size, start;
2242 u8 checksum = 0;
2243
2244 if (fw->size < sizeof(*fw_info))
2245 goto out;
2246
2247 for (i = 0; i < fw->size; i++)
2248 checksum += fw->data[i];
2249 if (checksum != 0)
2250 goto out;
2251
2252 start = le32_to_cpu(fw_info->fw_start);
2253 if (start > fw->size)
2254 goto out;
2255
2256 size = le32_to_cpu(fw_info->fw_len);
2257 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2258 goto out;
2259
2260 memcpy(version, fw_info->version, RTL_VER_SIZE);
2261
2262 pa->code = (__le32 *)(fw->data + start);
2263 pa->size = size;
2264 } else {
1c361efb
FR		 2265 if (fw->size % FW_OPCODE_SIZE)
2266 goto out;
2267
2268 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2269
2270 pa->code = (__le32 *)fw->data;
2271 pa->size = fw->size / FW_OPCODE_SIZE;
2272 }
2273 version[RTL_VER_SIZE - 1] = 0;
2274
2275 rc = true;
2276out:
2277 return rc;
2278}
2279
fd112f2e
FR		 2280static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2281 struct rtl_fw_phy_action *pa)
1c361efb 2282{
fd112f2e 2283 bool rc = false;
1c361efb 2284 size_t index;
bca03d5f 2285
1c361efb
FR		 2286 for (index = 0; index < pa->size; index++) {
2287 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 2288 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 2289
42b82dc1 2290 switch(action & 0xf0000000) {
2291 case PHY_READ:
2292 case PHY_DATA_OR:
2293 case PHY_DATA_AND:
eee3786f 2294 case PHY_MDIO_CHG:
42b82dc1 2295 case PHY_CLEAR_READCOUNT:
2296 case PHY_WRITE:
2297 case PHY_WRITE_PREVIOUS:
2298 case PHY_DELAY_MS:
2299 break;
2300
2301 case PHY_BJMPN:
2302 if (regno > index) {
fd112f2e 2303 netif_err(tp, ifup, tp->dev,
cecb5fd7 2304 "Out of range of firmware\n");
fd112f2e 2305 goto out;
42b82dc1 2306 }
2307 break;
2308 case PHY_READCOUNT_EQ_SKIP:
1c361efb 2309 if (index + 2 >= pa->size) {
fd112f2e 2310 netif_err(tp, ifup, tp->dev,
cecb5fd7 2311 "Out of range of firmware\n");
fd112f2e 2312 goto out;
42b82dc1 2313 }
2314 break;
2315 case PHY_COMP_EQ_SKIPN:
2316 case PHY_COMP_NEQ_SKIPN:
2317 case PHY_SKIPN:
1c361efb 2318 if (index + 1 + regno >= pa->size) {
fd112f2e 2319 netif_err(tp, ifup, tp->dev,
cecb5fd7 2320 "Out of range of firmware\n");
fd112f2e 2321 goto out;
42b82dc1 2322 }
bca03d5f 2323 break;
2324
42b82dc1 2325 default:
fd112f2e 2326 netif_err(tp, ifup, tp->dev,
42b82dc1 2327 "Invalid action 0x%08x\n", action);
fd112f2e 2328 goto out;
bca03d5f 2329 }
2330 }
fd112f2e
FR		 2331 rc = true;
2332out:
2333 return rc;
2334}
bca03d5f 2335
fd112f2e
FR		 2336static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2337{
2338 struct net_device *dev = tp->dev;
2339 int rc = -EINVAL;
2340
2341 if (!rtl_fw_format_ok(tp, rtl_fw)) {
5c2d2b14 2342 netif_err(tp, ifup, dev, "invalid firmware\n");
fd112f2e
FR		 2343 goto out;
2344 }
2345
2346 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2347 rc = 0;
2348out:
2349 return rc;
2350}
2351
2352static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2353{
2354 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
eee3786f 2355 struct mdio_ops org, *ops = &tp->mdio_ops;
fd112f2e
FR		 2356 u32 predata, count;
2357 size_t index;
2358
2359 predata = count = 0;
eee3786f 2360 org.write = ops->write;
2361 org.read = ops->read;
42b82dc1 2362
1c361efb
FR		 2363 for (index = 0; index < pa->size; ) {
2364 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2365 u32 data = action & 0x0000ffff;
42b82dc1 2366 u32 regno = (action & 0x0fff0000) >> 16;
2367
2368 if (!action)
2369 break;
bca03d5f 2370
2371 switch(action & 0xf0000000) {
42b82dc1 2372 case PHY_READ:
2373 predata = rtl_readphy(tp, regno);
2374 count++;
2375 index++;
2376 break;
2377 case PHY_DATA_OR:
2378 predata |= data;
2379 index++;
2380 break;
2381 case PHY_DATA_AND:
2382 predata &= data;
2383 index++;
2384 break;
2385 case PHY_BJMPN:
2386 index -= regno;
2387 break;
eee3786f 2388 case PHY_MDIO_CHG:
2389 if (data == 0) {
2390 ops->write = org.write;
2391 ops->read = org.read;
2392 } else if (data == 1) {
2393 ops->write = mac_mcu_write;
2394 ops->read = mac_mcu_read;
2395 }
2396
42b82dc1 2397 index++;
2398 break;
2399 case PHY_CLEAR_READCOUNT:
2400 count = 0;
2401 index++;
2402 break;
bca03d5f 2403 case PHY_WRITE:
42b82dc1 2404 rtl_writephy(tp, regno, data);
2405 index++;
2406 break;
2407 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2408 index += (count == data) ? 2 : 1;
bca03d5f 2409 break;
42b82dc1 2410 case PHY_COMP_EQ_SKIPN:
2411 if (predata == data)
2412 index += regno;
2413 index++;
2414 break;
2415 case PHY_COMP_NEQ_SKIPN:
2416 if (predata != data)
2417 index += regno;
2418 index++;
2419 break;
2420 case PHY_WRITE_PREVIOUS:
2421 rtl_writephy(tp, regno, predata);
2422 index++;
2423 break;
2424 case PHY_SKIPN:
2425 index += regno + 1;
2426 break;
2427 case PHY_DELAY_MS:
2428 mdelay(data);
2429 index++;
2430 break;
2431
bca03d5f 2432 default:
2433 BUG();
2434 }
2435 }
eee3786f 2436
2437 ops->write = org.write;
2438 ops->read = org.read;
bca03d5f 2439}
2440
f1e02ed1 2441static void rtl_release_firmware(struct rtl8169_private *tp)
2442{
b6ffd97f
FR		 2443 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2444 release_firmware(tp->rtl_fw->fw);
2445 kfree(tp->rtl_fw);
2446 }
2447 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2448}
2449
953a12cc 2450static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2451{
b6ffd97f 2452 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2453
2454 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
eef63cc1 2455 if (!IS_ERR_OR_NULL(rtl_fw))
b6ffd97f 2456 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2457}
2458
2459static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2460{
2461 if (rtl_readphy(tp, reg) != val)
2462 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2463 else
2464 rtl_apply_firmware(tp);
f1e02ed1 2465}
2466
4da19633 2467static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2468{
350f7596 2469 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2470 { 0x1f, 0x0001 },
2471 { 0x06, 0x006e },
2472 { 0x08, 0x0708 },
2473 { 0x15, 0x4000 },
2474 { 0x18, 0x65c7 },
1da177e4 2475
0b9b571d 2476 { 0x1f, 0x0001 },
2477 { 0x03, 0x00a1 },
2478 { 0x02, 0x0008 },
2479 { 0x01, 0x0120 },
2480 { 0x00, 0x1000 },
2481 { 0x04, 0x0800 },
2482 { 0x04, 0x0000 },
1da177e4 2483
0b9b571d 2484 { 0x03, 0xff41 },
2485 { 0x02, 0xdf60 },
2486 { 0x01, 0x0140 },
2487 { 0x00, 0x0077 },
2488 { 0x04, 0x7800 },
2489 { 0x04, 0x7000 },
2490
2491 { 0x03, 0x802f },
2492 { 0x02, 0x4f02 },
2493 { 0x01, 0x0409 },
2494 { 0x00, 0xf0f9 },
2495 { 0x04, 0x9800 },
2496 { 0x04, 0x9000 },
2497
2498 { 0x03, 0xdf01 },
2499 { 0x02, 0xdf20 },
2500 { 0x01, 0xff95 },
2501 { 0x00, 0xba00 },
2502 { 0x04, 0xa800 },
2503 { 0x04, 0xa000 },
2504
2505 { 0x03, 0xff41 },
2506 { 0x02, 0xdf20 },
2507 { 0x01, 0x0140 },
2508 { 0x00, 0x00bb },
2509 { 0x04, 0xb800 },
2510 { 0x04, 0xb000 },
2511
2512 { 0x03, 0xdf41 },
2513 { 0x02, 0xdc60 },
2514 { 0x01, 0x6340 },
2515 { 0x00, 0x007d },
2516 { 0x04, 0xd800 },
2517 { 0x04, 0xd000 },
2518
2519 { 0x03, 0xdf01 },
2520 { 0x02, 0xdf20 },
2521 { 0x01, 0x100a },
2522 { 0x00, 0xa0ff },
2523 { 0x04, 0xf800 },
2524 { 0x04, 0xf000 },
2525
2526 { 0x1f, 0x0000 },
2527 { 0x0b, 0x0000 },
2528 { 0x00, 0x9200 }
2529 };
1da177e4 2530
4da19633 2531 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2532}
2533
4da19633 2534static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2535{
350f7596 2536 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2537 { 0x1f, 0x0002 },
2538 { 0x01, 0x90d0 },
2539 { 0x1f, 0x0000 }
2540 };
2541
4da19633 2542 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2543}
2544
4da19633 2545static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2546{
2547 struct pci_dev *pdev = tp->pci_dev;
2e955856 2548
ccbae55e
SS		 2549 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2550 (pdev->subsystem_device != 0xe000))
2e955856 2551 return;
2552
4da19633 2553 rtl_writephy(tp, 0x1f, 0x0001);
2554 rtl_writephy(tp, 0x10, 0xf01b);
2555 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2556}
2557
4da19633 2558static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2559{
350f7596 2560 static const struct phy_reg phy_reg_init[] = {
2e955856 2561 { 0x1f, 0x0001 },
2562 { 0x04, 0x0000 },
2563 { 0x03, 0x00a1 },
2564 { 0x02, 0x0008 },
2565 { 0x01, 0x0120 },
2566 { 0x00, 0x1000 },
2567 { 0x04, 0x0800 },
2568 { 0x04, 0x9000 },
2569 { 0x03, 0x802f },
2570 { 0x02, 0x4f02 },
2571 { 0x01, 0x0409 },
2572 { 0x00, 0xf099 },
2573 { 0x04, 0x9800 },
2574 { 0x04, 0xa000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0xff95 },
2578 { 0x00, 0xba00 },
2579 { 0x04, 0xa800 },
2580 { 0x04, 0xf000 },
2581 { 0x03, 0xdf01 },
2582 { 0x02, 0xdf20 },
2583 { 0x01, 0x101a },
2584 { 0x00, 0xa0ff },
2585 { 0x04, 0xf800 },
2586 { 0x04, 0x0000 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x10, 0xf41b },
2591 { 0x14, 0xfb54 },
2592 { 0x18, 0xf5c7 },
2593 { 0x1f, 0x0000 },
2594
2595 { 0x1f, 0x0001 },
2596 { 0x17, 0x0cc0 },
2597 { 0x1f, 0x0000 }
2598 };
2599
4da19633 2600 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2601
4da19633 2602 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2603}
2604
4da19633 2605static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2606{
350f7596 2607 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2608 { 0x1f, 0x0001 },
2609 { 0x04, 0x0000 },
2610 { 0x03, 0x00a1 },
2611 { 0x02, 0x0008 },
2612 { 0x01, 0x0120 },
2613 { 0x00, 0x1000 },
2614 { 0x04, 0x0800 },
2615 { 0x04, 0x9000 },
2616 { 0x03, 0x802f },
2617 { 0x02, 0x4f02 },
2618 { 0x01, 0x0409 },
2619 { 0x00, 0xf099 },
2620 { 0x04, 0x9800 },
2621 { 0x04, 0xa000 },
2622 { 0x03, 0xdf01 },
2623 { 0x02, 0xdf20 },
2624 { 0x01, 0xff95 },
2625 { 0x00, 0xba00 },
2626 { 0x04, 0xa800 },
2627 { 0x04, 0xf000 },
2628 { 0x03, 0xdf01 },
2629 { 0x02, 0xdf20 },
2630 { 0x01, 0x101a },
2631 { 0x00, 0xa0ff },
2632 { 0x04, 0xf800 },
2633 { 0x04, 0x0000 },
2634 { 0x1f, 0x0000 },
2635
2636 { 0x1f, 0x0001 },
2637 { 0x0b, 0x8480 },
2638 { 0x1f, 0x0000 },
2639
2640 { 0x1f, 0x0001 },
2641 { 0x18, 0x67c7 },
2642 { 0x04, 0x2000 },
2643 { 0x03, 0x002f },
2644 { 0x02, 0x4360 },
2645 { 0x01, 0x0109 },
2646 { 0x00, 0x3022 },
2647 { 0x04, 0x2800 },
2648 { 0x1f, 0x0000 },
2649
2650 { 0x1f, 0x0001 },
2651 { 0x17, 0x0cc0 },
2652 { 0x1f, 0x0000 }
2653 };
2654
4da19633 2655 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2656}
2657
4da19633 2658static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2659{
350f7596 2660 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2661 { 0x10, 0xf41b },
2662 { 0x1f, 0x0000 }
2663 };
2664
4da19633 2665 rtl_writephy(tp, 0x1f, 0x0001);
2666 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2667
4da19633 2668 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2669}
2670
4da19633 2671static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2672{
350f7596 2673 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2674 { 0x1f, 0x0001 },
2675 { 0x10, 0xf41b },
2676 { 0x1f, 0x0000 }
2677 };
2678
4da19633 2679 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2680}
2681
4da19633 2682static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2683{
350f7596 2684 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2685 { 0x1f, 0x0000 },
2686 { 0x1d, 0x0f00 },
2687 { 0x1f, 0x0002 },
2688 { 0x0c, 0x1ec8 },
2689 { 0x1f, 0x0000 }
2690 };
2691
4da19633 2692 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2693}
2694
4da19633 2695static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2696{
350f7596 2697 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2698 { 0x1f, 0x0001 },
2699 { 0x1d, 0x3d98 },
2700 { 0x1f, 0x0000 }
2701 };
2702
4da19633 2703 rtl_writephy(tp, 0x1f, 0x0000);
2704 rtl_patchphy(tp, 0x14, 1 << 5);
2705 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2706
4da19633 2707 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2708}
2709
4da19633 2710static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2711{
350f7596 2712 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2713 { 0x1f, 0x0001 },
2714 { 0x12, 0x2300 },
867763c1
FR		 2715 { 0x1f, 0x0002 },
2716 { 0x00, 0x88d4 },
2717 { 0x01, 0x82b1 },
2718 { 0x03, 0x7002 },
2719 { 0x08, 0x9e30 },
2720 { 0x09, 0x01f0 },
2721 { 0x0a, 0x5500 },
2722 { 0x0c, 0x00c8 },
2723 { 0x1f, 0x0003 },
2724 { 0x12, 0xc096 },
2725 { 0x16, 0x000a },
f50d4275
FR		 2726 { 0x1f, 0x0000 },
2727 { 0x1f, 0x0000 },
2728 { 0x09, 0x2000 },
2729 { 0x09, 0x0000 }
867763c1
FR		 2730 };
2731
4da19633 2732 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2733
4da19633 2734 rtl_patchphy(tp, 0x14, 1 << 5);
2735 rtl_patchphy(tp, 0x0d, 1 << 5);
2736 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2737}
2738
4da19633 2739static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2740{
350f7596 2741 static const struct phy_reg phy_reg_init[] = {
f50d4275 2742 { 0x1f, 0x0001 },
7da97ec9 2743 { 0x12, 0x2300 },
f50d4275
FR		 2744 { 0x03, 0x802f },
2745 { 0x02, 0x4f02 },
2746 { 0x01, 0x0409 },
2747 { 0x00, 0xf099 },
2748 { 0x04, 0x9800 },
2749 { 0x04, 0x9000 },
2750 { 0x1d, 0x3d98 },
7da97ec9
FR		 2751 { 0x1f, 0x0002 },
2752 { 0x0c, 0x7eb8 },
f50d4275
FR		 2753 { 0x06, 0x0761 },
2754 { 0x1f, 0x0003 },
2755 { 0x16, 0x0f0a },
7da97ec9
FR		 2756 { 0x1f, 0x0000 }
2757 };
2758
4da19633 2759 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2760
4da19633 2761 rtl_patchphy(tp, 0x16, 1 << 0);
2762 rtl_patchphy(tp, 0x14, 1 << 5);
2763 rtl_patchphy(tp, 0x0d, 1 << 5);
2764 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2765}
2766
4da19633 2767static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2768{
350f7596 2769 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2770 { 0x1f, 0x0001 },
2771 { 0x12, 0x2300 },
2772 { 0x1d, 0x3d98 },
2773 { 0x1f, 0x0002 },
2774 { 0x0c, 0x7eb8 },
2775 { 0x06, 0x5461 },
2776 { 0x1f, 0x0003 },
2777 { 0x16, 0x0f0a },
2778 { 0x1f, 0x0000 }
2779 };
2780
4da19633 2781 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2782
4da19633 2783 rtl_patchphy(tp, 0x16, 1 << 0);
2784 rtl_patchphy(tp, 0x14, 1 << 5);
2785 rtl_patchphy(tp, 0x0d, 1 << 5);
2786 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2787}
2788
4da19633 2789static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2790{
4da19633 2791 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2792}
2793
bca03d5f 2794static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2795{
350f7596 2796 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2797 /* Channel Estimation */
5b538df9 2798 { 0x1f, 0x0001 },
daf9df6d 2799 { 0x06, 0x4064 },
2800 { 0x07, 0x2863 },
2801 { 0x08, 0x059c },
2802 { 0x09, 0x26b4 },
2803 { 0x0a, 0x6a19 },
2804 { 0x0b, 0xdcc8 },
2805 { 0x10, 0xf06d },
2806 { 0x14, 0x7f68 },
2807 { 0x18, 0x7fd9 },
2808 { 0x1c, 0xf0ff },
2809 { 0x1d, 0x3d9c },
5b538df9 2810 { 0x1f, 0x0003 },
daf9df6d 2811 { 0x12, 0xf49f },
2812 { 0x13, 0x070b },
2813 { 0x1a, 0x05ad },
bca03d5f 2814 { 0x14, 0x94c0 },
2815
2816 /*
2817 * Tx Error Issue
cecb5fd7 2818 * Enhance line driver power
bca03d5f 2819 */
5b538df9 2820 { 0x1f, 0x0002 },
daf9df6d 2821 { 0x06, 0x5561 },
2822 { 0x1f, 0x0005 },
2823 { 0x05, 0x8332 },
bca03d5f 2824 { 0x06, 0x5561 },
2825
2826 /*
2827 * Can not link to 1Gbps with bad cable
2828 * Decrease SNR threshold form 21.07dB to 19.04dB
2829 */
2830 { 0x1f, 0x0001 },
2831 { 0x17, 0x0cc0 },
daf9df6d 2832
5b538df9 2833 { 0x1f, 0x0000 },
bca03d5f 2834 { 0x0d, 0xf880 }
daf9df6d 2835 };
2836
4da19633 2837 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2838
bca03d5f 2839 /*
2840 * Rx Error Issue
2841 * Fine Tune Switching regulator parameter
2842 */
4da19633 2843 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2844 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2845 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2846
fdf6fc06 2847 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2848 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2849 { 0x1f, 0x0002 },
2850 { 0x05, 0x669a },
2851 { 0x1f, 0x0005 },
2852 { 0x05, 0x8330 },
2853 { 0x06, 0x669a },
2854 { 0x1f, 0x0002 }
2855 };
2856 int val;
2857
4da19633 2858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2859
4da19633 2860 val = rtl_readphy(tp, 0x0d);
daf9df6d 2861
2862 if ((val & 0x00ff) != 0x006c) {
350f7596 2863 static const u32 set[] = {
daf9df6d 2864 0x0065, 0x0066, 0x0067, 0x0068,
2865 0x0069, 0x006a, 0x006b, 0x006c
2866 };
2867 int i;
2868
4da19633 2869 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2870
2871 val &= 0xff00;
2872 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2873 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2874 }
2875 } else {
350f7596 2876 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2877 { 0x1f, 0x0002 },
2878 { 0x05, 0x6662 },
2879 { 0x1f, 0x0005 },
2880 { 0x05, 0x8330 },
2881 { 0x06, 0x6662 }
2882 };
2883
4da19633 2884 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2885 }
2886
bca03d5f 2887 /* RSET couple improve */
4da19633 2888 rtl_writephy(tp, 0x1f, 0x0002);
2889 rtl_patchphy(tp, 0x0d, 0x0300);
2890 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2891
bca03d5f 2892 /* Fine tune PLL performance */
4da19633 2893 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2894 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2895 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2896
4da19633 2897 rtl_writephy(tp, 0x1f, 0x0005);
2898 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2899
2900 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2901
4da19633 2902 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2903}
2904
bca03d5f 2905static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2906{
350f7596 2907 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2908 /* Channel Estimation */
daf9df6d 2909 { 0x1f, 0x0001 },
2910 { 0x06, 0x4064 },
2911 { 0x07, 0x2863 },
2912 { 0x08, 0x059c },
2913 { 0x09, 0x26b4 },
2914 { 0x0a, 0x6a19 },
2915 { 0x0b, 0xdcc8 },
2916 { 0x10, 0xf06d },
2917 { 0x14, 0x7f68 },
2918 { 0x18, 0x7fd9 },
2919 { 0x1c, 0xf0ff },
2920 { 0x1d, 0x3d9c },
2921 { 0x1f, 0x0003 },
2922 { 0x12, 0xf49f },
2923 { 0x13, 0x070b },
2924 { 0x1a, 0x05ad },
2925 { 0x14, 0x94c0 },
2926
bca03d5f 2927 /*
2928 * Tx Error Issue
cecb5fd7 2929 * Enhance line driver power
bca03d5f 2930 */
daf9df6d 2931 { 0x1f, 0x0002 },
2932 { 0x06, 0x5561 },
2933 { 0x1f, 0x0005 },
2934 { 0x05, 0x8332 },
bca03d5f 2935 { 0x06, 0x5561 },
2936
2937 /*
2938 * Can not link to 1Gbps with bad cable
2939 * Decrease SNR threshold form 21.07dB to 19.04dB
2940 */
2941 { 0x1f, 0x0001 },
2942 { 0x17, 0x0cc0 },
daf9df6d 2943
2944 { 0x1f, 0x0000 },
bca03d5f 2945 { 0x0d, 0xf880 }
5b538df9
FR		 2946 };
2947
4da19633 2948 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2949
fdf6fc06 2950 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
350f7596 2951 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2952 { 0x1f, 0x0002 },
2953 { 0x05, 0x669a },
5b538df9 2954 { 0x1f, 0x0005 },
daf9df6d 2955 { 0x05, 0x8330 },
2956 { 0x06, 0x669a },
2957
2958 { 0x1f, 0x0002 }
2959 };
2960 int val;
2961
4da19633 2962 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2963
4da19633 2964 val = rtl_readphy(tp, 0x0d);
daf9df6d 2965 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2966 static const u32 set[] = {
daf9df6d 2967 0x0065, 0x0066, 0x0067, 0x0068,
2968 0x0069, 0x006a, 0x006b, 0x006c
2969 };
2970 int i;
2971
4da19633 2972 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2973
2974 val &= 0xff00;
2975 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2976 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2977 }
2978 } else {
350f7596 2979 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2980 { 0x1f, 0x0002 },
2981 { 0x05, 0x2642 },
5b538df9 2982 { 0x1f, 0x0005 },
daf9df6d 2983 { 0x05, 0x8330 },
2984 { 0x06, 0x2642 }
5b538df9
FR		 2985 };
2986
4da19633 2987 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2988 }
2989
bca03d5f 2990 /* Fine tune PLL performance */
4da19633 2991 rtl_writephy(tp, 0x1f, 0x0002);
76564428
CHL		 2992 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2993 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2994
bca03d5f 2995 /* Switching regulator Slew rate */
4da19633 2996 rtl_writephy(tp, 0x1f, 0x0002);
2997 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2998
4da19633 2999 rtl_writephy(tp, 0x1f, 0x0005);
3000 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 3001
3002 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 3003
4da19633 3004 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 3005}
3006
4da19633 3007static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 3008{
350f7596 3009 static const struct phy_reg phy_reg_init[] = {
daf9df6d 3010 { 0x1f, 0x0002 },
3011 { 0x10, 0x0008 },
3012 { 0x0d, 0x006c },
3013
3014 { 0x1f, 0x0000 },
3015 { 0x0d, 0xf880 },
3016
3017 { 0x1f, 0x0001 },
3018 { 0x17, 0x0cc0 },
3019
3020 { 0x1f, 0x0001 },
3021 { 0x0b, 0xa4d8 },
3022 { 0x09, 0x281c },
3023 { 0x07, 0x2883 },
3024 { 0x0a, 0x6b35 },
3025 { 0x1d, 0x3da4 },
3026 { 0x1c, 0xeffd },
3027 { 0x14, 0x7f52 },
3028 { 0x18, 0x7fc6 },
3029 { 0x08, 0x0601 },
3030 { 0x06, 0x4063 },
3031 { 0x10, 0xf074 },
3032 { 0x1f, 0x0003 },
3033 { 0x13, 0x0789 },
3034 { 0x12, 0xf4bd },
3035 { 0x1a, 0x04fd },
3036 { 0x14, 0x84b0 },
3037 { 0x1f, 0x0000 },
3038 { 0x00, 0x9200 },
3039
3040 { 0x1f, 0x0005 },
3041 { 0x01, 0x0340 },
3042 { 0x1f, 0x0001 },
3043 { 0x04, 0x4000 },
3044 { 0x03, 0x1d21 },
3045 { 0x02, 0x0c32 },
3046 { 0x01, 0x0200 },
3047 { 0x00, 0x5554 },
3048 { 0x04, 0x4800 },
3049 { 0x04, 0x4000 },
3050 { 0x04, 0xf000 },
3051 { 0x03, 0xdf01 },
3052 { 0x02, 0xdf20 },
3053 { 0x01, 0x101a },
3054 { 0x00, 0xa0ff },
3055 { 0x04, 0xf800 },
3056 { 0x04, 0xf000 },
3057 { 0x1f, 0x0000 },
3058
3059 { 0x1f, 0x0007 },
3060 { 0x1e, 0x0023 },
3061 { 0x16, 0x0000 },
3062 { 0x1f, 0x0000 }
3063 };
3064
4da19633 3065 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 3066}
3067
e6de30d6 3068static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3069{
3070 static const struct phy_reg phy_reg_init[] = {
3071 { 0x1f, 0x0001 },
3072 { 0x17, 0x0cc0 },
3073
3074 { 0x1f, 0x0007 },
3075 { 0x1e, 0x002d },
3076 { 0x18, 0x0040 },
3077 { 0x1f, 0x0000 }
3078 };
3079
3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3081 rtl_patchphy(tp, 0x0d, 1 << 5);
3082}
3083
70090424 3084static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 3085{
3086 static const struct phy_reg phy_reg_init[] = {
3087 /* Enable Delay cap */
3088 { 0x1f, 0x0005 },
3089 { 0x05, 0x8b80 },
3090 { 0x06, 0xc896 },
3091 { 0x1f, 0x0000 },
3092
3093 /* Channel estimation fine tune */
3094 { 0x1f, 0x0001 },
3095 { 0x0b, 0x6c20 },
3096 { 0x07, 0x2872 },
3097 { 0x1c, 0xefff },
3098 { 0x1f, 0x0003 },
3099 { 0x14, 0x6420 },
3100 { 0x1f, 0x0000 },
3101
3102 /* Update PFM & 10M TX idle timer */
3103 { 0x1f, 0x0007 },
3104 { 0x1e, 0x002f },
3105 { 0x15, 0x1919 },
3106 { 0x1f, 0x0000 },
3107
3108 { 0x1f, 0x0007 },
3109 { 0x1e, 0x00ac },
3110 { 0x18, 0x0006 },
3111 { 0x1f, 0x0000 }
3112 };
3113
15ecd039
FR		 3114 rtl_apply_firmware(tp);
3115
01dc7fec 3116 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3117
3118 /* DCO enable for 10M IDLE Power */
3119 rtl_writephy(tp, 0x1f, 0x0007);
3120 rtl_writephy(tp, 0x1e, 0x0023);
76564428 3121 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
01dc7fec 3122 rtl_writephy(tp, 0x1f, 0x0000);
3123
3124 /* For impedance matching */
3125 rtl_writephy(tp, 0x1f, 0x0002);
76564428 3126 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 3127 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3128
3129 /* PHY auto speed down */
3130 rtl_writephy(tp, 0x1f, 0x0007);
3131 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3132 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
01dc7fec 3133 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3134 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
01dc7fec 3135
3136 rtl_writephy(tp, 0x1f, 0x0005);
3137 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3138 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
01dc7fec 3139 rtl_writephy(tp, 0x1f, 0x0000);
3140
3141 rtl_writephy(tp, 0x1f, 0x0005);
3142 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3143 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
01dc7fec 3144 rtl_writephy(tp, 0x1f, 0x0007);
3145 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3146 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
01dc7fec 3147 rtl_writephy(tp, 0x1f, 0x0006);
3148 rtl_writephy(tp, 0x00, 0x5a00);
3149 rtl_writephy(tp, 0x1f, 0x0000);
3150 rtl_writephy(tp, 0x0d, 0x0007);
3151 rtl_writephy(tp, 0x0e, 0x003c);
3152 rtl_writephy(tp, 0x0d, 0x4007);
3153 rtl_writephy(tp, 0x0e, 0x0000);
3154 rtl_writephy(tp, 0x0d, 0x0000);
3155}
3156
9ecb9aab 3157static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3158{
3159 const u16 w[] = {
3160 addr[0] | (addr[1] << 8),
3161 addr[2] | (addr[3] << 8),
3162 addr[4] | (addr[5] << 8)
3163 };
3164 const struct exgmac_reg e[] = {
3165 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3166 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3167 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3168 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3169 };
3170
3171 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3172}
3173
70090424
HW		 3174static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3175{
3176 static const struct phy_reg phy_reg_init[] = {
3177 /* Enable Delay cap */
3178 { 0x1f, 0x0004 },
3179 { 0x1f, 0x0007 },
3180 { 0x1e, 0x00ac },
3181 { 0x18, 0x0006 },
3182 { 0x1f, 0x0002 },
3183 { 0x1f, 0x0000 },
3184 { 0x1f, 0x0000 },
3185
3186 /* Channel estimation fine tune */
3187 { 0x1f, 0x0003 },
3188 { 0x09, 0xa20f },
3189 { 0x1f, 0x0000 },
3190 { 0x1f, 0x0000 },
3191
3192 /* Green Setting */
3193 { 0x1f, 0x0005 },
3194 { 0x05, 0x8b5b },
3195 { 0x06, 0x9222 },
3196 { 0x05, 0x8b6d },
3197 { 0x06, 0x8000 },
3198 { 0x05, 0x8b76 },
3199 { 0x06, 0x8000 },
3200 { 0x1f, 0x0000 }
3201 };
3202
3203 rtl_apply_firmware(tp);
3204
3205 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3206
3207 /* For 4-corner performance improve */
3208 rtl_writephy(tp, 0x1f, 0x0005);
3209 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3210 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
70090424
HW		 3211 rtl_writephy(tp, 0x1f, 0x0000);
3212
3213 /* PHY auto speed down */
3214 rtl_writephy(tp, 0x1f, 0x0004);
3215 rtl_writephy(tp, 0x1f, 0x0007);
3216 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3217 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
70090424
HW		 3218 rtl_writephy(tp, 0x1f, 0x0002);
3219 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3220 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
70090424
HW		 3221
3222 /* improve 10M EEE waveform */
3223 rtl_writephy(tp, 0x1f, 0x0005);
3224 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3225 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
70090424
HW		 3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* Improve 2-pair detection performance */
3229 rtl_writephy(tp, 0x1f, 0x0005);
3230 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3231 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
70090424
HW		 3232 rtl_writephy(tp, 0x1f, 0x0000);
3233
3234 /* EEE setting */
1814d6a8 3235 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
70090424
HW		 3236 rtl_writephy(tp, 0x1f, 0x0005);
3237 rtl_writephy(tp, 0x05, 0x8b85);
1814d6a8 3238 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
70090424
HW		 3239 rtl_writephy(tp, 0x1f, 0x0004);
3240 rtl_writephy(tp, 0x1f, 0x0007);
3241 rtl_writephy(tp, 0x1e, 0x0020);
1814d6a8 3242 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
70090424
HW		 3243 rtl_writephy(tp, 0x1f, 0x0002);
3244 rtl_writephy(tp, 0x1f, 0x0000);
3245 rtl_writephy(tp, 0x0d, 0x0007);
3246 rtl_writephy(tp, 0x0e, 0x003c);
3247 rtl_writephy(tp, 0x0d, 0x4007);
1814d6a8 3248 rtl_writephy(tp, 0x0e, 0x0006);
70090424
HW		 3249 rtl_writephy(tp, 0x0d, 0x0000);
3250
3251 /* Green feature */
3252 rtl_writephy(tp, 0x1f, 0x0003);
1814d6a8
HK		 3253 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3254 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
70090424 3255 rtl_writephy(tp, 0x1f, 0x0000);
b399a394
HK		 3256 rtl_writephy(tp, 0x1f, 0x0005);
3257 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3258 rtl_writephy(tp, 0x1f, 0x0000);
e0c07557 3259
9ecb9aab 3260 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3261 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
70090424
HW		 3262}
3263
5f886e08
HW		 3264static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3265{
3266 /* For 4-corner performance improve */
3267 rtl_writephy(tp, 0x1f, 0x0005);
3268 rtl_writephy(tp, 0x05, 0x8b80);
76564428 3269 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
5f886e08
HW		 3270 rtl_writephy(tp, 0x1f, 0x0000);
3271
3272 /* PHY auto speed down */
3273 rtl_writephy(tp, 0x1f, 0x0007);
3274 rtl_writephy(tp, 0x1e, 0x002d);
76564428 3275 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
5f886e08 3276 rtl_writephy(tp, 0x1f, 0x0000);
76564428 3277 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
5f886e08
HW		 3278
3279 /* Improve 10M EEE waveform */
3280 rtl_writephy(tp, 0x1f, 0x0005);
3281 rtl_writephy(tp, 0x05, 0x8b86);
76564428 3282 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
5f886e08
HW		 3283 rtl_writephy(tp, 0x1f, 0x0000);
3284}
3285
c2218925
HW		 3286static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3287{
3288 static const struct phy_reg phy_reg_init[] = {
3289 /* Channel estimation fine tune */
3290 { 0x1f, 0x0003 },
3291 { 0x09, 0xa20f },
3292 { 0x1f, 0x0000 },
3293
3294 /* Modify green table for giga & fnet */
3295 { 0x1f, 0x0005 },
3296 { 0x05, 0x8b55 },
3297 { 0x06, 0x0000 },
3298 { 0x05, 0x8b5e },
3299 { 0x06, 0x0000 },
3300 { 0x05, 0x8b67 },
3301 { 0x06, 0x0000 },
3302 { 0x05, 0x8b70 },
3303 { 0x06, 0x0000 },
3304 { 0x1f, 0x0000 },
3305 { 0x1f, 0x0007 },
3306 { 0x1e, 0x0078 },
3307 { 0x17, 0x0000 },
3308 { 0x19, 0x00fb },
3309 { 0x1f, 0x0000 },
3310
3311 /* Modify green table for 10M */
3312 { 0x1f, 0x0005 },
3313 { 0x05, 0x8b79 },
3314 { 0x06, 0xaa00 },
3315 { 0x1f, 0x0000 },
3316
3317 /* Disable hiimpedance detection (RTCT) */
3318 { 0x1f, 0x0003 },
3319 { 0x01, 0x328a },
3320 { 0x1f, 0x0000 }
3321 };
3322
3323 rtl_apply_firmware(tp);
3324
3325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3326
5f886e08 3327 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3328
3329 /* Improve 2-pair detection performance */
3330 rtl_writephy(tp, 0x1f, 0x0005);
3331 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3332 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
c2218925
HW		 3333 rtl_writephy(tp, 0x1f, 0x0000);
3334}
3335
3336static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3337{
3338 rtl_apply_firmware(tp);
3339
5f886e08 3340 rtl8168f_hw_phy_config(tp);
c2218925
HW		 3341}
3342
b3d7b2f2
HW		 3343static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3344{
b3d7b2f2
HW		 3345 static const struct phy_reg phy_reg_init[] = {
3346 /* Channel estimation fine tune */
3347 { 0x1f, 0x0003 },
3348 { 0x09, 0xa20f },
3349 { 0x1f, 0x0000 },
3350
3351 /* Modify green table for giga & fnet */
3352 { 0x1f, 0x0005 },
3353 { 0x05, 0x8b55 },
3354 { 0x06, 0x0000 },
3355 { 0x05, 0x8b5e },
3356 { 0x06, 0x0000 },
3357 { 0x05, 0x8b67 },
3358 { 0x06, 0x0000 },
3359 { 0x05, 0x8b70 },
3360 { 0x06, 0x0000 },
3361 { 0x1f, 0x0000 },
3362 { 0x1f, 0x0007 },
3363 { 0x1e, 0x0078 },
3364 { 0x17, 0x0000 },
3365 { 0x19, 0x00aa },
3366 { 0x1f, 0x0000 },
3367
3368 /* Modify green table for 10M */
3369 { 0x1f, 0x0005 },
3370 { 0x05, 0x8b79 },
3371 { 0x06, 0xaa00 },
3372 { 0x1f, 0x0000 },
3373
3374 /* Disable hiimpedance detection (RTCT) */
3375 { 0x1f, 0x0003 },
3376 { 0x01, 0x328a },
3377 { 0x1f, 0x0000 }
3378 };
3379
3380
3381 rtl_apply_firmware(tp);
3382
3383 rtl8168f_hw_phy_config(tp);
3384
3385 /* Improve 2-pair detection performance */
3386 rtl_writephy(tp, 0x1f, 0x0005);
3387 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3388 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
b3d7b2f2
HW		 3389 rtl_writephy(tp, 0x1f, 0x0000);
3390
3391 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3392
3393 /* Modify green table for giga */
3394 rtl_writephy(tp, 0x1f, 0x0005);
3395 rtl_writephy(tp, 0x05, 0x8b54);
76564428 3396 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3397 rtl_writephy(tp, 0x05, 0x8b5d);
76564428 3398 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
b3d7b2f2 3399 rtl_writephy(tp, 0x05, 0x8a7c);
76564428 3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3401 rtl_writephy(tp, 0x05, 0x8a7f);
76564428 3402 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
b3d7b2f2 3403 rtl_writephy(tp, 0x05, 0x8a82);
76564428 3404 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3405 rtl_writephy(tp, 0x05, 0x8a85);
76564428 3406 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2 3407 rtl_writephy(tp, 0x05, 0x8a88);
76564428 3408 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
b3d7b2f2
HW		 3409 rtl_writephy(tp, 0x1f, 0x0000);
3410
3411 /* uc same-seed solution */
3412 rtl_writephy(tp, 0x1f, 0x0005);
3413 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3414 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
b3d7b2f2
HW		 3415 rtl_writephy(tp, 0x1f, 0x0000);
3416
3417 /* eee setting */
706123d0 3418 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
b3d7b2f2
HW		 3419 rtl_writephy(tp, 0x1f, 0x0005);
3420 rtl_writephy(tp, 0x05, 0x8b85);
76564428 3421 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
b3d7b2f2
HW		 3422 rtl_writephy(tp, 0x1f, 0x0004);
3423 rtl_writephy(tp, 0x1f, 0x0007);
3424 rtl_writephy(tp, 0x1e, 0x0020);
76564428 3425 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
b3d7b2f2
HW		 3426 rtl_writephy(tp, 0x1f, 0x0000);
3427 rtl_writephy(tp, 0x0d, 0x0007);
3428 rtl_writephy(tp, 0x0e, 0x003c);
3429 rtl_writephy(tp, 0x0d, 0x4007);
3430 rtl_writephy(tp, 0x0e, 0x0000);
3431 rtl_writephy(tp, 0x0d, 0x0000);
3432
3433 /* Green feature */
3434 rtl_writephy(tp, 0x1f, 0x0003);
76564428
CHL		 3435 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3436 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
b3d7b2f2
HW		 3437 rtl_writephy(tp, 0x1f, 0x0000);
3438}
3439
c558386b
HW		 3440static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3441{
c558386b
HW		 3442 rtl_apply_firmware(tp);
3443
41f44d13 3444 rtl_writephy(tp, 0x1f, 0x0a46);
3445 if (rtl_readphy(tp, 0x10) & 0x0100) {
3446 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3447 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
41f44d13 3448 } else {
3449 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3450 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
41f44d13 3451 }
c558386b 3452
41f44d13 3453 rtl_writephy(tp, 0x1f, 0x0a46);
3454 if (rtl_readphy(tp, 0x13) & 0x0100) {
3455 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3456 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
41f44d13 3457 } else {
fe7524c0 3458 rtl_writephy(tp, 0x1f, 0x0c41);
76564428 3459 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
41f44d13 3460 }
c558386b 3461
41f44d13 3462 /* Enable PHY auto speed down */
3463 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3464 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
c558386b 3465
fe7524c0 3466 rtl_writephy(tp, 0x1f, 0x0bcc);
76564428 3467 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
fe7524c0 3468 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3469 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
fe7524c0 3470 rtl_writephy(tp, 0x1f, 0x0a43);
3471 rtl_writephy(tp, 0x13, 0x8084);
76564428
CHL		 3472 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3473 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
fe7524c0 3474
41f44d13 3475 /* EEE auto-fallback function */
3476 rtl_writephy(tp, 0x1f, 0x0a4b);
76564428 3477 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
c558386b 3478
41f44d13 3479 /* Enable UC LPF tune function */
3480 rtl_writephy(tp, 0x1f, 0x0a43);
3481 rtl_writephy(tp, 0x13, 0x8012);
76564428 3482 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
41f44d13 3483
3484 rtl_writephy(tp, 0x1f, 0x0c42);
76564428 3485 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
41f44d13 3486
fe7524c0 3487 /* Improve SWR Efficiency */
3488 rtl_writephy(tp, 0x1f, 0x0bcd);
3489 rtl_writephy(tp, 0x14, 0x5065);
3490 rtl_writephy(tp, 0x14, 0xd065);
3491 rtl_writephy(tp, 0x1f, 0x0bc8);
3492 rtl_writephy(tp, 0x11, 0x5655);
3493 rtl_writephy(tp, 0x1f, 0x0bcd);
3494 rtl_writephy(tp, 0x14, 0x1065);
3495 rtl_writephy(tp, 0x14, 0x9065);
3496 rtl_writephy(tp, 0x14, 0x1065);
3497
1bac1072
DC		 3498 /* Check ALDPS bit, disable it if enabled */
3499 rtl_writephy(tp, 0x1f, 0x0a43);
3500 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3501 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
1bac1072 3502
41f44d13 3503 rtl_writephy(tp, 0x1f, 0x0000);
c558386b
HW		 3504}
3505
57538c4a 3506static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3507{
3508 rtl_apply_firmware(tp);
3509}
3510
6e1d0b89
CHL		 3511static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3512{
3513 u16 dout_tapbin;
3514 u32 data;
3515
3516 rtl_apply_firmware(tp);
3517
3518 /* CHN EST parameters adjust - giga master */
3519 rtl_writephy(tp, 0x1f, 0x0a43);
3520 rtl_writephy(tp, 0x13, 0x809b);
76564428 3521 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
6e1d0b89 3522 rtl_writephy(tp, 0x13, 0x80a2);
76564428 3523 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
6e1d0b89 3524 rtl_writephy(tp, 0x13, 0x80a4);
76564428 3525 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
6e1d0b89 3526 rtl_writephy(tp, 0x13, 0x809c);
76564428 3527 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
6e1d0b89
CHL		 3528 rtl_writephy(tp, 0x1f, 0x0000);
3529
3530 /* CHN EST parameters adjust - giga slave */
3531 rtl_writephy(tp, 0x1f, 0x0a43);
3532 rtl_writephy(tp, 0x13, 0x80ad);
76564428 3533 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
6e1d0b89 3534 rtl_writephy(tp, 0x13, 0x80b4);
76564428 3535 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
6e1d0b89 3536 rtl_writephy(tp, 0x13, 0x80ac);
76564428 3537 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
6e1d0b89
CHL		 3538 rtl_writephy(tp, 0x1f, 0x0000);
3539
3540 /* CHN EST parameters adjust - fnet */
3541 rtl_writephy(tp, 0x1f, 0x0a43);
3542 rtl_writephy(tp, 0x13, 0x808e);
76564428 3543 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
6e1d0b89 3544 rtl_writephy(tp, 0x13, 0x8090);
76564428 3545 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
6e1d0b89 3546 rtl_writephy(tp, 0x13, 0x8092);
76564428 3547 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
6e1d0b89
CHL		 3548 rtl_writephy(tp, 0x1f, 0x0000);
3549
3550 /* enable R-tune & PGA-retune function */
3551 dout_tapbin = 0;
3552 rtl_writephy(tp, 0x1f, 0x0a46);
3553 data = rtl_readphy(tp, 0x13);
3554 data &= 3;
3555 data <<= 2;
3556 dout_tapbin |= data;
3557 data = rtl_readphy(tp, 0x12);
3558 data &= 0xc000;
3559 data >>= 14;
3560 dout_tapbin |= data;
3561 dout_tapbin = ~(dout_tapbin^0x08);
3562 dout_tapbin <<= 12;
3563 dout_tapbin &= 0xf000;
3564 rtl_writephy(tp, 0x1f, 0x0a43);
3565 rtl_writephy(tp, 0x13, 0x827a);
76564428 3566 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3567 rtl_writephy(tp, 0x13, 0x827b);
76564428 3568 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3569 rtl_writephy(tp, 0x13, 0x827c);
76564428 3570 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89 3571 rtl_writephy(tp, 0x13, 0x827d);
76564428 3572 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
6e1d0b89
CHL		 3573
3574 rtl_writephy(tp, 0x1f, 0x0a43);
3575 rtl_writephy(tp, 0x13, 0x0811);
76564428 3576 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3577 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3578 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3579 rtl_writephy(tp, 0x1f, 0x0000);
3580
3581 /* enable GPHY 10M */
3582 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3583 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3584 rtl_writephy(tp, 0x1f, 0x0000);
3585
3586 /* SAR ADC performance */
3587 rtl_writephy(tp, 0x1f, 0x0bca);
76564428 3588 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
6e1d0b89
CHL		 3589 rtl_writephy(tp, 0x1f, 0x0000);
3590
3591 rtl_writephy(tp, 0x1f, 0x0a43);
3592 rtl_writephy(tp, 0x13, 0x803f);
76564428 3593 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3594 rtl_writephy(tp, 0x13, 0x8047);
76564428 3595 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3596 rtl_writephy(tp, 0x13, 0x804f);
76564428 3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3598 rtl_writephy(tp, 0x13, 0x8057);
76564428 3599 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3600 rtl_writephy(tp, 0x13, 0x805f);
76564428 3601 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3602 rtl_writephy(tp, 0x13, 0x8067);
76564428 3603 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89 3604 rtl_writephy(tp, 0x13, 0x806f);
76564428 3605 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
6e1d0b89
CHL		 3606 rtl_writephy(tp, 0x1f, 0x0000);
3607
3608 /* disable phy pfm mode */
3609 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3610 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3611 rtl_writephy(tp, 0x1f, 0x0000);
3612
3613 /* Check ALDPS bit, disable it if enabled */
3614 rtl_writephy(tp, 0x1f, 0x0a43);
3615 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3616 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3617
3618 rtl_writephy(tp, 0x1f, 0x0000);
3619}
3620
3621static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3622{
3623 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3624 u16 rlen;
3625 u32 data;
3626
3627 rtl_apply_firmware(tp);
3628
3629 /* CHIN EST parameter update */
3630 rtl_writephy(tp, 0x1f, 0x0a43);
3631 rtl_writephy(tp, 0x13, 0x808a);
76564428 3632 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
6e1d0b89
CHL		 3633 rtl_writephy(tp, 0x1f, 0x0000);
3634
3635 /* enable R-tune & PGA-retune function */
3636 rtl_writephy(tp, 0x1f, 0x0a43);
3637 rtl_writephy(tp, 0x13, 0x0811);
76564428 3638 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
6e1d0b89 3639 rtl_writephy(tp, 0x1f, 0x0a42);
76564428 3640 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
6e1d0b89
CHL		 3641 rtl_writephy(tp, 0x1f, 0x0000);
3642
3643 /* enable GPHY 10M */
3644 rtl_writephy(tp, 0x1f, 0x0a44);
76564428 3645 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
6e1d0b89
CHL		 3646 rtl_writephy(tp, 0x1f, 0x0000);
3647
3648 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3649 data = r8168_mac_ocp_read(tp, 0xdd02);
3650 ioffset_p3 = ((data & 0x80)>>7);
3651 ioffset_p3 <<= 3;
3652
3653 data = r8168_mac_ocp_read(tp, 0xdd00);
3654 ioffset_p3 |= ((data & (0xe000))>>13);
3655 ioffset_p2 = ((data & (0x1e00))>>9);
3656 ioffset_p1 = ((data & (0x01e0))>>5);
3657 ioffset_p0 = ((data & 0x0010)>>4);
3658 ioffset_p0 <<= 3;
3659 ioffset_p0 |= (data & (0x07));
3660 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3661
05b9687b 3662 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
e2e2788e 3663 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
6e1d0b89
CHL		 3664 rtl_writephy(tp, 0x1f, 0x0bcf);
3665 rtl_writephy(tp, 0x16, data);
3666 rtl_writephy(tp, 0x1f, 0x0000);
3667 }
3668
3669 /* Modify rlen (TX LPF corner frequency) level */
3670 rtl_writephy(tp, 0x1f, 0x0bcd);
3671 data = rtl_readphy(tp, 0x16);
3672 data &= 0x000f;
3673 rlen = 0;
3674 if (data > 3)
3675 rlen = data - 3;
3676 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3677 rtl_writephy(tp, 0x17, data);
3678 rtl_writephy(tp, 0x1f, 0x0bcd);
3679 rtl_writephy(tp, 0x1f, 0x0000);
3680
3681 /* disable phy pfm mode */
3682 rtl_writephy(tp, 0x1f, 0x0a44);
c832c35f 3683 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
6e1d0b89
CHL		 3684 rtl_writephy(tp, 0x1f, 0x0000);
3685
3686 /* Check ALDPS bit, disable it if enabled */
3687 rtl_writephy(tp, 0x1f, 0x0a43);
3688 if (rtl_readphy(tp, 0x10) & 0x0004)
76564428 3689 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
6e1d0b89
CHL		 3690
3691 rtl_writephy(tp, 0x1f, 0x0000);
3692}
3693
935e2218
CHL		 3694static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3695{
3696 /* Enable PHY auto speed down */
3697 rtl_writephy(tp, 0x1f, 0x0a44);
3698 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3699 rtl_writephy(tp, 0x1f, 0x0000);
3700
3701 /* patch 10M & ALDPS */
3702 rtl_writephy(tp, 0x1f, 0x0bcc);
3703 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3704 rtl_writephy(tp, 0x1f, 0x0a44);
3705 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3706 rtl_writephy(tp, 0x1f, 0x0a43);
3707 rtl_writephy(tp, 0x13, 0x8084);
3708 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3709 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3710 rtl_writephy(tp, 0x1f, 0x0000);
3711
3712 /* Enable EEE auto-fallback function */
3713 rtl_writephy(tp, 0x1f, 0x0a4b);
3714 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3715 rtl_writephy(tp, 0x1f, 0x0000);
3716
3717 /* Enable UC LPF tune function */
3718 rtl_writephy(tp, 0x1f, 0x0a43);
3719 rtl_writephy(tp, 0x13, 0x8012);
3720 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3721 rtl_writephy(tp, 0x1f, 0x0000);
3722
3723 /* set rg_sel_sdm_rate */
3724 rtl_writephy(tp, 0x1f, 0x0c42);
3725 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3726 rtl_writephy(tp, 0x1f, 0x0000);
3727
3728 /* Check ALDPS bit, disable it if enabled */
3729 rtl_writephy(tp, 0x1f, 0x0a43);
3730 if (rtl_readphy(tp, 0x10) & 0x0004)
3731 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3732
3733 rtl_writephy(tp, 0x1f, 0x0000);
3734}
3735
3736static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3737{
3738 /* patch 10M & ALDPS */
3739 rtl_writephy(tp, 0x1f, 0x0bcc);
3740 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3741 rtl_writephy(tp, 0x1f, 0x0a44);
3742 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3743 rtl_writephy(tp, 0x1f, 0x0a43);
3744 rtl_writephy(tp, 0x13, 0x8084);
3745 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3746 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3748
3749 /* Enable UC LPF tune function */
3750 rtl_writephy(tp, 0x1f, 0x0a43);
3751 rtl_writephy(tp, 0x13, 0x8012);
3752 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3753 rtl_writephy(tp, 0x1f, 0x0000);
3754
3755 /* Set rg_sel_sdm_rate */
3756 rtl_writephy(tp, 0x1f, 0x0c42);
3757 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3758 rtl_writephy(tp, 0x1f, 0x0000);
3759
3760 /* Channel estimation parameters */
3761 rtl_writephy(tp, 0x1f, 0x0a43);
3762 rtl_writephy(tp, 0x13, 0x80f3);
3763 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3764 rtl_writephy(tp, 0x13, 0x80f0);
3765 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3766 rtl_writephy(tp, 0x13, 0x80ef);
3767 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3768 rtl_writephy(tp, 0x13, 0x80f6);
3769 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3770 rtl_writephy(tp, 0x13, 0x80ec);
3771 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3772 rtl_writephy(tp, 0x13, 0x80ed);
3773 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3774 rtl_writephy(tp, 0x13, 0x80f2);
3775 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3776 rtl_writephy(tp, 0x13, 0x80f4);
3777 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3778 rtl_writephy(tp, 0x1f, 0x0a43);
3779 rtl_writephy(tp, 0x13, 0x8110);
3780 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3781 rtl_writephy(tp, 0x13, 0x810f);
3782 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3783 rtl_writephy(tp, 0x13, 0x8111);
3784 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3785 rtl_writephy(tp, 0x13, 0x8113);
3786 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3787 rtl_writephy(tp, 0x13, 0x8115);
3788 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3789 rtl_writephy(tp, 0x13, 0x810e);
3790 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3791 rtl_writephy(tp, 0x13, 0x810c);
3792 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3793 rtl_writephy(tp, 0x13, 0x810b);
3794 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3795 rtl_writephy(tp, 0x1f, 0x0a43);
3796 rtl_writephy(tp, 0x13, 0x80d1);
3797 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3798 rtl_writephy(tp, 0x13, 0x80cd);
3799 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3800 rtl_writephy(tp, 0x13, 0x80d3);
3801 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3802 rtl_writephy(tp, 0x13, 0x80d5);
3803 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3804 rtl_writephy(tp, 0x13, 0x80d7);
3805 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3806
3807 /* Force PWM-mode */
3808 rtl_writephy(tp, 0x1f, 0x0bcd);
3809 rtl_writephy(tp, 0x14, 0x5065);
3810 rtl_writephy(tp, 0x14, 0xd065);
3811 rtl_writephy(tp, 0x1f, 0x0bc8);
3812 rtl_writephy(tp, 0x12, 0x00ed);
3813 rtl_writephy(tp, 0x1f, 0x0bcd);
3814 rtl_writephy(tp, 0x14, 0x1065);
3815 rtl_writephy(tp, 0x14, 0x9065);
3816 rtl_writephy(tp, 0x14, 0x1065);
3817 rtl_writephy(tp, 0x1f, 0x0000);
3818
3819 /* Check ALDPS bit, disable it if enabled */
3820 rtl_writephy(tp, 0x1f, 0x0a43);
3821 if (rtl_readphy(tp, 0x10) & 0x0004)
3822 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3823
3824 rtl_writephy(tp, 0x1f, 0x0000);
3825}
3826
4da19633 3827static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 3828{
350f7596 3829 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 3830 { 0x1f, 0x0003 },
3831 { 0x08, 0x441d },
3832 { 0x01, 0x9100 },
3833 { 0x1f, 0x0000 }
3834 };
3835
4da19633 3836 rtl_writephy(tp, 0x1f, 0x0000);
3837 rtl_patchphy(tp, 0x11, 1 << 12);
3838 rtl_patchphy(tp, 0x19, 1 << 13);
3839 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 3840
4da19633 3841 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 3842}
3843
5a5e4443
HW		 3844static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3845{
3846 static const struct phy_reg phy_reg_init[] = {
3847 { 0x1f, 0x0005 },
3848 { 0x1a, 0x0000 },
3849 { 0x1f, 0x0000 },
3850
3851 { 0x1f, 0x0004 },
3852 { 0x1c, 0x0000 },
3853 { 0x1f, 0x0000 },
3854
3855 { 0x1f, 0x0001 },
3856 { 0x15, 0x7701 },
3857 { 0x1f, 0x0000 }
3858 };
3859
3860 /* Disable ALDPS before ram code */
eef63cc1
FR		 3861 rtl_writephy(tp, 0x1f, 0x0000);
3862 rtl_writephy(tp, 0x18, 0x0310);
3863 msleep(100);
5a5e4443 3864
953a12cc 3865 rtl_apply_firmware(tp);
5a5e4443
HW		 3866
3867 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3868}
3869
7e18dca1
HW		 3870static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3871{
7e18dca1 3872 /* Disable ALDPS before setting firmware */
eef63cc1
FR		 3873 rtl_writephy(tp, 0x1f, 0x0000);
3874 rtl_writephy(tp, 0x18, 0x0310);
3875 msleep(20);
7e18dca1
HW		 3876
3877 rtl_apply_firmware(tp);
3878
3879 /* EEE setting */
fdf6fc06 3880 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
7e18dca1
HW		 3881 rtl_writephy(tp, 0x1f, 0x0004);
3882 rtl_writephy(tp, 0x10, 0x401f);
3883 rtl_writephy(tp, 0x19, 0x7030);
3884 rtl_writephy(tp, 0x1f, 0x0000);
3885}
3886
5598bfe5
HW		 3887static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3888{
5598bfe5
HW		 3889 static const struct phy_reg phy_reg_init[] = {
3890 { 0x1f, 0x0004 },
3891 { 0x10, 0xc07f },
3892 { 0x19, 0x7030 },
3893 { 0x1f, 0x0000 }
3894 };
3895
3896 /* Disable ALDPS before ram code */
eef63cc1
FR		 3897 rtl_writephy(tp, 0x1f, 0x0000);
3898 rtl_writephy(tp, 0x18, 0x0310);
3899 msleep(100);
5598bfe5
HW		 3900
3901 rtl_apply_firmware(tp);
3902
fdf6fc06 3903 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3904 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3905
fdf6fc06 3906 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5598bfe5
HW		 3907}
3908
5615d9f1
FR		 3909static void rtl_hw_phy_config(struct net_device *dev)
3910{
3911 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 3912
3913 rtl8169_print_mac_version(tp);
3914
3915 switch (tp->mac_version) {
3916 case RTL_GIGA_MAC_VER_01:
3917 break;
3918 case RTL_GIGA_MAC_VER_02:
3919 case RTL_GIGA_MAC_VER_03:
4da19633 3920 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 3921 break;
3922 case RTL_GIGA_MAC_VER_04:
4da19633 3923 rtl8169sb_hw_phy_config(tp);
5615d9f1 3924 break;
2e955856 3925 case RTL_GIGA_MAC_VER_05:
4da19633 3926 rtl8169scd_hw_phy_config(tp);
2e955856 3927 break;
8c7006aa 3928 case RTL_GIGA_MAC_VER_06:
4da19633 3929 rtl8169sce_hw_phy_config(tp);
8c7006aa 3930 break;
2857ffb7
FR		 3931 case RTL_GIGA_MAC_VER_07:
3932 case RTL_GIGA_MAC_VER_08:
3933 case RTL_GIGA_MAC_VER_09:
4da19633 3934 rtl8102e_hw_phy_config(tp);
2857ffb7 3935 break;
236b8082 3936 case RTL_GIGA_MAC_VER_11:
4da19633 3937 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 3938 break;
3939 case RTL_GIGA_MAC_VER_12:
4da19633 3940 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 3941 break;
3942 case RTL_GIGA_MAC_VER_17:
4da19633 3943 rtl8168bef_hw_phy_config(tp);
236b8082 3944 break;
867763c1 3945 case RTL_GIGA_MAC_VER_18:
4da19633 3946 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 3947 break;
3948 case RTL_GIGA_MAC_VER_19:
4da19633 3949 rtl8168c_1_hw_phy_config(tp);
867763c1 3950 break;
7da97ec9 3951 case RTL_GIGA_MAC_VER_20:
4da19633 3952 rtl8168c_2_hw_phy_config(tp);
7da97ec9 3953 break;
197ff761 3954 case RTL_GIGA_MAC_VER_21:
4da19633 3955 rtl8168c_3_hw_phy_config(tp);
197ff761 3956 break;
6fb07058 3957 case RTL_GIGA_MAC_VER_22:
4da19633 3958 rtl8168c_4_hw_phy_config(tp);
6fb07058 3959 break;
ef3386f0 3960 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 3961 case RTL_GIGA_MAC_VER_24:
4da19633 3962 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 3963 break;
5b538df9 3964 case RTL_GIGA_MAC_VER_25:
bca03d5f 3965 rtl8168d_1_hw_phy_config(tp);
daf9df6d 3966 break;
3967 case RTL_GIGA_MAC_VER_26:
bca03d5f 3968 rtl8168d_2_hw_phy_config(tp);
daf9df6d 3969 break;
3970 case RTL_GIGA_MAC_VER_27:
4da19633 3971 rtl8168d_3_hw_phy_config(tp);
5b538df9 3972 break;
e6de30d6 3973 case RTL_GIGA_MAC_VER_28:
3974 rtl8168d_4_hw_phy_config(tp);
3975 break;
5a5e4443
HW		 3976 case RTL_GIGA_MAC_VER_29:
3977 case RTL_GIGA_MAC_VER_30:
3978 rtl8105e_hw_phy_config(tp);
3979 break;
cecb5fd7
FR		 3980 case RTL_GIGA_MAC_VER_31:
3981 /* None. */
3982 break;
01dc7fec 3983 case RTL_GIGA_MAC_VER_32:
01dc7fec 3984 case RTL_GIGA_MAC_VER_33:
70090424
HW		 3985 rtl8168e_1_hw_phy_config(tp);
3986 break;
3987 case RTL_GIGA_MAC_VER_34:
3988 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3989 break;
c2218925
HW		 3990 case RTL_GIGA_MAC_VER_35:
3991 rtl8168f_1_hw_phy_config(tp);
3992 break;
3993 case RTL_GIGA_MAC_VER_36:
3994 rtl8168f_2_hw_phy_config(tp);
3995 break;
ef3386f0 3996
7e18dca1
HW		 3997 case RTL_GIGA_MAC_VER_37:
3998 rtl8402_hw_phy_config(tp);
3999 break;
4000
b3d7b2f2
HW		 4001 case RTL_GIGA_MAC_VER_38:
4002 rtl8411_hw_phy_config(tp);
4003 break;
4004
5598bfe5
HW		 4005 case RTL_GIGA_MAC_VER_39:
4006 rtl8106e_hw_phy_config(tp);
4007 break;
4008
c558386b
HW		 4009 case RTL_GIGA_MAC_VER_40:
4010 rtl8168g_1_hw_phy_config(tp);
4011 break;
57538c4a 4012 case RTL_GIGA_MAC_VER_42:
58152cd4 4013 case RTL_GIGA_MAC_VER_43:
45dd95c4 4014 case RTL_GIGA_MAC_VER_44:
57538c4a 4015 rtl8168g_2_hw_phy_config(tp);
4016 break;
6e1d0b89
CHL		 4017 case RTL_GIGA_MAC_VER_45:
4018 case RTL_GIGA_MAC_VER_47:
4019 rtl8168h_1_hw_phy_config(tp);
4020 break;
4021 case RTL_GIGA_MAC_VER_46:
4022 case RTL_GIGA_MAC_VER_48:
4023 rtl8168h_2_hw_phy_config(tp);
4024 break;
c558386b 4025
935e2218
CHL		 4026 case RTL_GIGA_MAC_VER_49:
4027 rtl8168ep_1_hw_phy_config(tp);
4028 break;
4029 case RTL_GIGA_MAC_VER_50:
4030 case RTL_GIGA_MAC_VER_51:
4031 rtl8168ep_2_hw_phy_config(tp);
4032 break;
4033
c558386b 4034 case RTL_GIGA_MAC_VER_41:
5615d9f1
FR		 4035 default:
4036 break;
4037 }
4038}
4039
da78dbff
FR		 4040static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4041{
da78dbff
FR		 4042 if (!test_and_set_bit(flag, tp->wk.flags))
4043 schedule_work(&tp->wk.work);
da78dbff
FR		 4044}
4045
2544bfc0
FR		 4046static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4047{
2544bfc0 4048 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
e397286b 4049 (RTL_R8(tp, PHYstatus) & TBI_Enable);
2544bfc0
FR		 4050}
4051
4ff96fa6
FR		 4052static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4053{
5615d9f1 4054 rtl_hw_phy_config(dev);
4ff96fa6 4055
77332894 4056 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
49d17512
HK		 4057 netif_dbg(tp, drv, dev,
4058 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4059 RTL_W8(tp, 0x82, 0x01);
77332894 4060 }
4ff96fa6 4061
6dccd16b
FR		 4062 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4063
4064 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4065 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 4066
bcf0bf90 4067 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
49d17512
HK		 4068 netif_dbg(tp, drv, dev,
4069 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1ef7286e 4070 RTL_W8(tp, 0x82, 0x01);
49d17512
HK		 4071 netif_dbg(tp, drv, dev,
4072 "Set PHY Reg 0x0bh = 0x00h\n");
4da19633 4073 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 4074 }
4075
5b7ad4b7
HK		 4076 /* We may have called phy_speed_down before */
4077 phy_speed_up(dev->phydev);
4078
f75222bc 4079 genphy_soft_reset(dev->phydev);
10bc6a60 4080
9003b369 4081 /* It was reported that several chips end up with 10MBit/Half on a
10bc6a60 4082 * 1GBit link after resuming from S3. For whatever reason the PHY on
9003b369 4083 * these chips doesn't properly start a renegotiation when soft-reset.
10bc6a60
HK		 4084 * Explicitly requesting a renegotiation fixes this.
4085 */
9003b369 4086 if (dev->phydev->autoneg == AUTONEG_ENABLE)
10bc6a60 4087 phy_restart_aneg(dev->phydev);
4ff96fa6
FR		 4088}
4089
773d2021
FR		 4090static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4091{
da78dbff 4092 rtl_lock_work(tp);
773d2021 4093
1ef7286e 4094 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
908ba2bf 4095
1ef7286e
AS		 4096 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4097 RTL_R32(tp, MAC4);
908ba2bf 4098
1ef7286e
AS		 4099 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4100 RTL_R32(tp, MAC0);
908ba2bf 4101
9ecb9aab 4102 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4103 rtl_rar_exgmac_set(tp, addr);
c28aa385 4104
1ef7286e 4105 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
773d2021 4106
da78dbff 4107 rtl_unlock_work(tp);
773d2021
FR		 4108}
4109
4110static int rtl_set_mac_address(struct net_device *dev, void *p)
4111{
4112 struct rtl8169_private *tp = netdev_priv(dev);
1e1205b7 4113 struct device *d = tp_to_dev(tp);
1f7aa2bc 4114 int ret;
773d2021 4115
1f7aa2bc
HK		 4116 ret = eth_mac_addr(dev, p);
4117 if (ret)
4118 return ret;
773d2021 4119
f51d4a10
CHL		 4120 pm_runtime_get_noresume(d);
4121
4122 if (pm_runtime_active(d))
4123 rtl_rar_set(tp, dev->dev_addr);
4124
4125 pm_runtime_put_noidle(d);
773d2021
FR		 4126
4127 return 0;
4128}
4129
e397286b 4130static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8b4ab28d 4131{
69b3c59f
HK		 4132 if (!netif_running(dev))
4133 return -ENODEV;
e397286b 4134
69b3c59f 4135 return phy_mii_ioctl(dev->phydev, ifr, cmd);
8b4ab28d
FR		 4136}
4137
baf63293 4138static void rtl_init_mdio_ops(struct rtl8169_private *tp)
c0e45c1c 4139{
4140 struct mdio_ops *ops = &tp->mdio_ops;
4141
4142 switch (tp->mac_version) {
4143 case RTL_GIGA_MAC_VER_27:
4144 ops->write = r8168dp_1_mdio_write;
4145 ops->read = r8168dp_1_mdio_read;
4146 break;
e6de30d6 4147 case RTL_GIGA_MAC_VER_28:
4804b3b3 4148 case RTL_GIGA_MAC_VER_31:
e6de30d6 4149 ops->write = r8168dp_2_mdio_write;
4150 ops->read = r8168dp_2_mdio_read;
4151 break;
2a71883c 4152 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
c558386b
HW		 4153 ops->write = r8168g_mdio_write;
4154 ops->read = r8168g_mdio_read;
4155 break;
c0e45c1c 4156 default:
4157 ops->write = r8169_mdio_write;
4158 ops->read = r8169_mdio_read;
4159 break;
4160 }
4161}
4162
649b3b8c 4163static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4164{
649b3b8c 4165 switch (tp->mac_version) {
b00e69de
CB		 4166 case RTL_GIGA_MAC_VER_25:
4167 case RTL_GIGA_MAC_VER_26:
649b3b8c 4168 case RTL_GIGA_MAC_VER_29:
4169 case RTL_GIGA_MAC_VER_30:
4170 case RTL_GIGA_MAC_VER_32:
4171 case RTL_GIGA_MAC_VER_33:
4172 case RTL_GIGA_MAC_VER_34:
2a71883c 4173 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4174 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
649b3b8c 4175 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4176 break;
4177 default:
4178 break;
4179 }
4180}
4181
4182static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4183{
4778b9f0
HK		 4184 struct phy_device *phydev;
4185
4186 if (!__rtl8169_get_wol(tp))
649b3b8c 4187 return false;
4188
4778b9f0
HK		 4189 /* phydev may not be attached to netdevice */
4190 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4191
4192 phy_speed_down(phydev, false);
649b3b8c 4193 rtl_wol_suspend_quirk(tp);
4194
4195 return true;
4196}
4197
065c27c1 4198static void r8168_pll_power_down(struct rtl8169_private *tp)
4199{
9dbe7896 4200 if (r8168_check_dash(tp))
065c27c1 4201 return;
4202
01dc7fec 4203 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4204 tp->mac_version == RTL_GIGA_MAC_VER_33)
fdf6fc06 4205 rtl_ephy_write(tp, 0x19, 0xff64);
01dc7fec 4206
649b3b8c 4207 if (rtl_wol_pll_power_down(tp))
065c27c1 4208 return;
065c27c1 4209
065c27c1 4210 switch (tp->mac_version) {
2a71883c 4211 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4212 case RTL_GIGA_MAC_VER_37:
4213 case RTL_GIGA_MAC_VER_39:
4214 case RTL_GIGA_MAC_VER_43:
42fde737 4215 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4216 case RTL_GIGA_MAC_VER_45:
4217 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4218 case RTL_GIGA_MAC_VER_47:
4219 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4220 case RTL_GIGA_MAC_VER_50:
4221 case RTL_GIGA_MAC_VER_51:
1ef7286e 4222 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
065c27c1 4223 break;
beb330a4 4224 case RTL_GIGA_MAC_VER_40:
4225 case RTL_GIGA_MAC_VER_41:
935e2218 4226 case RTL_GIGA_MAC_VER_49:
706123d0 4227 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
beb330a4 4228 0xfc000000, ERIAR_EXGMAC);
1ef7286e 4229 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
beb330a4 4230 break;
065c27c1 4231 }
4232}
4233
4234static void r8168_pll_power_up(struct rtl8169_private *tp)
4235{
065c27c1 4236 switch (tp->mac_version) {
2a71883c 4237 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
73570bf1
HK		 4238 case RTL_GIGA_MAC_VER_37:
4239 case RTL_GIGA_MAC_VER_39:
4240 case RTL_GIGA_MAC_VER_43:
1ef7286e 4241 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
065c27c1 4242 break;
42fde737 4243 case RTL_GIGA_MAC_VER_44:
6e1d0b89
CHL		 4244 case RTL_GIGA_MAC_VER_45:
4245 case RTL_GIGA_MAC_VER_46:
73570bf1
HK		 4246 case RTL_GIGA_MAC_VER_47:
4247 case RTL_GIGA_MAC_VER_48:
935e2218
CHL		 4248 case RTL_GIGA_MAC_VER_50:
4249 case RTL_GIGA_MAC_VER_51:
1ef7286e 4250 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
6e1d0b89 4251 break;
beb330a4 4252 case RTL_GIGA_MAC_VER_40:
4253 case RTL_GIGA_MAC_VER_41:
935e2218 4254 case RTL_GIGA_MAC_VER_49:
1ef7286e 4255 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
706123d0 4256 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
beb330a4 4257 0x00000000, ERIAR_EXGMAC);
4258 break;
065c27c1 4259 }
4260
242cd9b5
HK		 4261 phy_resume(tp->dev->phydev);
4262 /* give MAC/PHY some time to resume */
4263 msleep(20);
065c27c1 4264}
4265
065c27c1 4266static void rtl_pll_power_down(struct rtl8169_private *tp)
4267{
4f447d29
HK		 4268 switch (tp->mac_version) {
4269 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4270 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4271 break;
4272 default:
4273 r8168_pll_power_down(tp);
4274 }
065c27c1 4275}
4276
4277static void rtl_pll_power_up(struct rtl8169_private *tp)
4278{
065c27c1 4279 switch (tp->mac_version) {
4f447d29
HK		 4280 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4281 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
065c27c1 4282 break;
065c27c1 4283 default:
4f447d29 4284 r8168_pll_power_up(tp);
065c27c1 4285 }
4286}
4287
e542a226
HW		 4288static void rtl_init_rxcfg(struct rtl8169_private *tp)
4289{
e542a226 4290 switch (tp->mac_version) {
2a71883c
HK		 4291 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4292 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
1ef7286e 4293 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
e542a226 4294 break;
2a71883c 4295 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
511cfd58
MS		 4296 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4297 case RTL_GIGA_MAC_VER_38:
1ef7286e 4298 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
e542a226 4299 break;
2a71883c 4300 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4301 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
beb330a4 4302 break;
e542a226 4303 default:
1ef7286e 4304 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
e542a226
HW		 4305 break;
4306 }
4307}
4308
92fc43b4
HW		 4309static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4310{
9fba0812 4311 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
92fc43b4
HW		 4312}
4313
d58d46b5
FR		 4314static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4315{
eda40b8c
HK		 4316 if (tp->jumbo_ops.enable) {
4317 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4318 tp->jumbo_ops.enable(tp);
4319 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4320 }
d58d46b5
FR		 4321}
4322
4323static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4324{
eda40b8c
HK		 4325 if (tp->jumbo_ops.disable) {
4326 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4327 tp->jumbo_ops.disable(tp);
4328 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4329 }
d58d46b5
FR		 4330}
4331
4332static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4333{
1ef7286e
AS		 4334 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4335 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
cb73200c 4336 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4337}
4338
4339static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4340{
1ef7286e
AS		 4341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
8d98aa39 4343 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4344}
4345
4346static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4347{
1ef7286e 4348 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
d58d46b5
FR		 4349}
4350
4351static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4352{
1ef7286e 4353 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
d58d46b5
FR		 4354}
4355
4356static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4357{
1ef7286e
AS		 4358 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4359 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4360 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
cb73200c 4361 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
d58d46b5
FR		 4362}
4363
4364static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4365{
1ef7286e
AS		 4366 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4367 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4368 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
8d98aa39 4369 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
d58d46b5
FR		 4370}
4371
4372static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4373{
cb73200c 4374 rtl_tx_performance_tweak(tp,
f65d539c 4375 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4376}
4377
4378static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4379{
cb73200c 4380 rtl_tx_performance_tweak(tp,
8d98aa39 4381 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
d58d46b5
FR		 4382}
4383
4384static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4385{
d58d46b5
FR		 4386 r8168b_0_hw_jumbo_enable(tp);
4387
1ef7286e 4388 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
d58d46b5
FR		 4389}
4390
4391static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4392{
d58d46b5
FR		 4393 r8168b_0_hw_jumbo_disable(tp);
4394
1ef7286e 4395 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
d58d46b5
FR		 4396}
4397
baf63293 4398static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
d58d46b5
FR		 4399{
4400 struct jumbo_ops *ops = &tp->jumbo_ops;
4401
4402 switch (tp->mac_version) {
4403 case RTL_GIGA_MAC_VER_11:
4404 ops->disable = r8168b_0_hw_jumbo_disable;
4405 ops->enable = r8168b_0_hw_jumbo_enable;
4406 break;
4407 case RTL_GIGA_MAC_VER_12:
4408 case RTL_GIGA_MAC_VER_17:
4409 ops->disable = r8168b_1_hw_jumbo_disable;
4410 ops->enable = r8168b_1_hw_jumbo_enable;
4411 break;
4412 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4413 case RTL_GIGA_MAC_VER_19:
4414 case RTL_GIGA_MAC_VER_20:
4415 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4416 case RTL_GIGA_MAC_VER_22:
4417 case RTL_GIGA_MAC_VER_23:
4418 case RTL_GIGA_MAC_VER_24:
4419 case RTL_GIGA_MAC_VER_25:
4420 case RTL_GIGA_MAC_VER_26:
4421 ops->disable = r8168c_hw_jumbo_disable;
4422 ops->enable = r8168c_hw_jumbo_enable;
4423 break;
4424 case RTL_GIGA_MAC_VER_27:
4425 case RTL_GIGA_MAC_VER_28:
4426 ops->disable = r8168dp_hw_jumbo_disable;
4427 ops->enable = r8168dp_hw_jumbo_enable;
4428 break;
4429 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4430 case RTL_GIGA_MAC_VER_32:
4431 case RTL_GIGA_MAC_VER_33:
4432 case RTL_GIGA_MAC_VER_34:
4433 ops->disable = r8168e_hw_jumbo_disable;
4434 ops->enable = r8168e_hw_jumbo_enable;
4435 break;
4436
4437 /*
4438 * No action needed for jumbo frames with 8169.
4439 * No jumbo for 810x at all.
4440 */
2a71883c 4441 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
d58d46b5
FR		 4442 default:
4443 ops->disable = NULL;
4444 ops->enable = NULL;
4445 break;
4446 }
4447}
4448
ffc46952
FR		 4449DECLARE_RTL_COND(rtl_chipcmd_cond)
4450{
1ef7286e 4451 return RTL_R8(tp, ChipCmd) & CmdReset;
ffc46952
FR		 4452}
4453
6f43adc8
FR		 4454static void rtl_hw_reset(struct rtl8169_private *tp)
4455{
1ef7286e 4456 RTL_W8(tp, ChipCmd, CmdReset);
6f43adc8 4457
ffc46952 4458 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
6f43adc8
FR		 4459}
4460
b6ffd97f 4461static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 4462{
b6ffd97f
FR		 4463 struct rtl_fw *rtl_fw;
4464 const char *name;
4465 int rc = -ENOMEM;
953a12cc 4466
b6ffd97f
FR		 4467 name = rtl_lookup_firmware_name(tp);
4468 if (!name)
4469 goto out_no_firmware;
953a12cc 4470
b6ffd97f
FR		 4471 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4472 if (!rtl_fw)
4473 goto err_warn;
31bd204f 4474
1e1205b7 4475 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
b6ffd97f
FR		 4476 if (rc < 0)
4477 goto err_free;
4478
fd112f2e
FR		 4479 rc = rtl_check_firmware(tp, rtl_fw);
4480 if (rc < 0)
4481 goto err_release_firmware;
4482
b6ffd97f
FR		 4483 tp->rtl_fw = rtl_fw;
4484out:
4485 return;
4486
fd112f2e
FR		 4487err_release_firmware:
4488 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 4489err_free:
4490 kfree(rtl_fw);
4491err_warn:
4492 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4493 name, rc);
4494out_no_firmware:
4495 tp->rtl_fw = NULL;
4496 goto out;
4497}
4498
4499static void rtl_request_firmware(struct rtl8169_private *tp)
4500{
4501 if (IS_ERR(tp->rtl_fw))
4502 rtl_request_uncached_firmware(tp);
953a12cc
FR		 4503}
4504
92fc43b4
HW		 4505static void rtl_rx_close(struct rtl8169_private *tp)
4506{
1ef7286e 4507 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 4508}
4509
ffc46952
FR		 4510DECLARE_RTL_COND(rtl_npq_cond)
4511{
1ef7286e 4512 return RTL_R8(tp, TxPoll) & NPQ;
ffc46952
FR		 4513}
4514
4515DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4516{
1ef7286e 4517 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
ffc46952
FR		 4518}
4519
e6de30d6 4520static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4
LT		 4521{
4522 /* Disable interrupts */
811fd301 4523 rtl8169_irq_mask_and_ack(tp);
1da177e4 4524
92fc43b4
HW		 4525 rtl_rx_close(tp);
4526
b2d43e6e
HK		 4527 switch (tp->mac_version) {
4528 case RTL_GIGA_MAC_VER_27:
4529 case RTL_GIGA_MAC_VER_28:
4530 case RTL_GIGA_MAC_VER_31:
ffc46952 4531 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
b2d43e6e
HK		 4532 break;
4533 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4534 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1ef7286e 4535 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
ffc46952 4536 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
b2d43e6e
HK		 4537 break;
4538 default:
1ef7286e 4539 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
92fc43b4 4540 udelay(100);
b2d43e6e 4541 break;
e6de30d6 4542 }
4543
92fc43b4 4544 rtl_hw_reset(tp);
1da177e4
LT		 4545}
4546
05212ba8 4547static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
9cb427b6 4548{
ad5f97fa
HK		 4549 u32 val = TX_DMA_BURST << TxDMAShift |
4550 InterFrameGap << TxInterFrameGapShift;
4551
4552 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4553 tp->mac_version != RTL_GIGA_MAC_VER_39)
4554 val |= TXCFG_AUTO_FIFO;
4555
4556 RTL_W32(tp, TxConfig, val);
9cb427b6
FR		 4557}
4558
4fd48c4a 4559static void rtl_set_rx_max_size(struct rtl8169_private *tp)
1da177e4 4560{
4fd48c4a
HK		 4561 /* Low hurts. Let's disable the filtering. */
4562 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
07ce4064
FR		 4563}
4564
1ef7286e 4565static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
7f796d83
FR		 4566{
4567 /*
4568 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4569 * register to be written before TxDescAddrLow to work.
4570 * Switching from MMIO to I/O access fixes the issue as well.
4571 */
1ef7286e
AS		 4572 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4573 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4574 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4575 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4576}
4577
1ef7286e 4578static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
6dccd16b 4579{
3744100e 4580 static const struct rtl_cfg2_info {
6dccd16b
FR		 4581 u32 mac_version;
4582 u32 clk;
4583 u32 val;
4584 } cfg2_info [] = {
4585 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4586 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4587 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4588 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4589 };
4590 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4591 unsigned int i;
4592 u32 clk;
4593
1ef7286e 4594 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
cadf1855 4595 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b 4596 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1ef7286e 4597 RTL_W32(tp, 0x7c, p->val);
6dccd16b
FR		 4598 break;
4599 }
4600 }
4601}
4602
e6b763ea
FR		 4603static void rtl_set_rx_mode(struct net_device *dev)
4604{
4605 struct rtl8169_private *tp = netdev_priv(dev);
e6b763ea
FR		 4606 u32 mc_filter[2]; /* Multicast hash filter */
4607 int rx_mode;
4608 u32 tmp = 0;
4609
4610 if (dev->flags & IFF_PROMISC) {
4611 /* Unconditionally log net taps. */
4612 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4613 rx_mode =
4614 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4615 AcceptAllPhys;
4616 mc_filter[1] = mc_filter[0] = 0xffffffff;
4617 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4618 (dev->flags & IFF_ALLMULTI)) {
4619 /* Too many to filter perfectly -- accept all multicasts. */
4620 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4621 mc_filter[1] = mc_filter[0] = 0xffffffff;
4622 } else {
4623 struct netdev_hw_addr *ha;
4624
4625 rx_mode = AcceptBroadcast | AcceptMyPhys;
4626 mc_filter[1] = mc_filter[0] = 0;
4627 netdev_for_each_mc_addr(ha, dev) {
4628 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4629 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4630 rx_mode |= AcceptMulticast;
4631 }
4632 }
4633
4634 if (dev->features & NETIF_F_RXALL)
4635 rx_mode |= (AcceptErr | AcceptRunt);
4636
1ef7286e 4637 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
e6b763ea
FR		 4638
4639 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4640 u32 data = mc_filter[0];
4641
4642 mc_filter[0] = swab32(mc_filter[1]);
4643 mc_filter[1] = swab32(data);
4644 }
4645
0481776b
NW		 4646 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4647 mc_filter[1] = mc_filter[0] = 0xffffffff;
4648
1ef7286e
AS		 4649 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4650 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
e6b763ea 4651
1ef7286e 4652 RTL_W32(tp, RxConfig, tmp);
e6b763ea
FR		 4653}
4654
52f8560e
HK		 4655static void rtl_hw_start(struct rtl8169_private *tp)
4656{
4657 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4658
4659 tp->hw_start(tp);
4660
4661 rtl_set_rx_max_size(tp);
4662 rtl_set_rx_tx_desc_registers(tp);
52f8560e
HK		 4663 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4664
4665 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4666 RTL_R8(tp, IntrMask);
4667 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
05212ba8 4668 rtl_init_rxcfg(tp);
f74dd480 4669 rtl_set_tx_config_registers(tp);
05212ba8 4670
52f8560e
HK		 4671 rtl_set_rx_mode(tp->dev);
4672 /* no early-rx interrupts */
4673 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4674 rtl_irq_enable_all(tp);
4675}
4676
61cb532d 4677static void rtl_hw_start_8169(struct rtl8169_private *tp)
07ce4064 4678{
0ae0974e 4679 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
61cb532d 4680 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
9cb427b6 4681
1ef7286e 4682 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
1da177e4 4683
0ae0974e 4684 tp->cp_cmd |= PCIMulRW;
1da177e4 4685
cecb5fd7
FR		 4686 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4687 tp->mac_version == RTL_GIGA_MAC_VER_03) {
49d17512
HK		 4688 netif_dbg(tp, drv, tp->dev,
4689 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
bcf0bf90 4690 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4691 }
4692
1ef7286e 4693 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
bcf0bf90 4694
1ef7286e 4695 rtl8169_set_magic_reg(tp, tp->mac_version);
6dccd16b 4696
1da177e4
LT		 4697 /*
4698 * Undocumented corner. Supposedly:
4699 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4700 */
1ef7286e 4701 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4 4702
1ef7286e 4703 RTL_W32(tp, RxMissed, 0);
07ce4064 4704}
1da177e4 4705
ffc46952
FR		 4706DECLARE_RTL_COND(rtl_csiar_cond)
4707{
1ef7286e 4708 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
ffc46952
FR		 4709}
4710
ff1d7331 4711static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
beb1fe18 4712{
ff1d7331 4713 u32 func = PCI_FUNC(tp->pci_dev->devfn);
beb1fe18 4714
1ef7286e
AS		 4715 RTL_W32(tp, CSIDR, value);
4716 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
ff1d7331 4717 CSIAR_BYTE_ENABLE | func << 16);
7e18dca1 4718
ffc46952 4719 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
7e18dca1
HW		 4720}
4721
ff1d7331 4722static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
7e18dca1 4723{
ff1d7331
HK		 4724 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4725
4726 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4727 CSIAR_BYTE_ENABLE);
7e18dca1 4728
ffc46952 4729 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
1ef7286e 4730 RTL_R32(tp, CSIDR) : ~0;
7e18dca1
HW		 4731}
4732
ff1d7331 4733static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
45dd95c4 4734{
ff1d7331
HK		 4735 struct pci_dev *pdev = tp->pci_dev;
4736 u32 csi;
45dd95c4 4737
ff1d7331
HK		 4738 /* According to Realtek the value at config space address 0x070f
4739 * controls the L0s/L1 entrance latency. We try standard ECAM access
4740 * first and if it fails fall back to CSI.
4741 */
4742 if (pdev->cfg_size > 0x070f &&
4743 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4744 return;
4745
4746 netdev_notice_once(tp->dev,
4747 "No native access to PCI extended config space, falling back to CSI\n");
4748 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4749 rtl_csi_write(tp, 0x070c, csi | val << 24);
45dd95c4 4750}
4751
f37658da 4752static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
beb1fe18 4753{
ff1d7331 4754 rtl_csi_access_enable(tp, 0x27);
dacf8154
FR		 4755}
4756
4757struct ephy_info {
4758 unsigned int offset;
4759 u16 mask;
4760 u16 bits;
4761};
4762
fdf6fc06
FR		 4763static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4764 int len)
dacf8154
FR		 4765{
4766 u16 w;
4767
4768 while (len-- > 0) {
fdf6fc06
FR		 4769 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4770 rtl_ephy_write(tp, e->offset, w);
dacf8154
FR		 4771 e++;
4772 }
4773}
4774
73c86ee3 4775static void rtl_disable_clock_request(struct rtl8169_private *tp)
b726e493 4776{
73c86ee3 4777 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4778 PCI_EXP_LNKCTL_CLKREQ_EN);
b726e493
FR		 4779}
4780
73c86ee3 4781static void rtl_enable_clock_request(struct rtl8169_private *tp)
e6de30d6 4782{
73c86ee3 4783 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
7d7903b2 4784 PCI_EXP_LNKCTL_CLKREQ_EN);
e6de30d6 4785}
4786
b51ecea8 4787static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4788{
b51ecea8 4789 u8 data;
4790
1ef7286e 4791 data = RTL_R8(tp, Config3);
b51ecea8 4792
4793 if (enable)
4794 data |= Rdy_to_L23;
4795 else
4796 data &= ~Rdy_to_L23;
4797
1ef7286e 4798 RTL_W8(tp, Config3, data);
b51ecea8 4799}
4800
a99790bf
KHF		 4801static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4802{
4803 if (enable) {
a99790bf 4804 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
94235460 4805 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
a99790bf
KHF		 4806 } else {
4807 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4808 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4809 }
94235460
KHF		 4810
4811 udelay(10);
a99790bf
KHF		 4812}
4813
beb1fe18 4814static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
219a1e9d 4815{
1ef7286e 4816 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4817
12d42c50 4818 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4819 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
b726e493 4820
faf1e785 4821 if (tp->dev->mtu <= ETH_DATA_LEN) {
8d98aa39 4822 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
faf1e785 4823 PCI_EXP_DEVCTL_NOSNOOP_EN);
4824 }
219a1e9d
FR		 4825}
4826
beb1fe18 4827static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
219a1e9d 4828{
beb1fe18 4829 rtl_hw_start_8168bb(tp);
b726e493 4830
1ef7286e 4831 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
b726e493 4832
1ef7286e 4833 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
219a1e9d
FR		 4834}
4835
beb1fe18 4836static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
219a1e9d 4837{
1ef7286e 4838 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
b726e493 4839
1ef7286e 4840 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
b726e493 4841
faf1e785 4842 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4843 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
b726e493 4844
73c86ee3 4845 rtl_disable_clock_request(tp);
b726e493 4846
12d42c50 4847 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4848 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
219a1e9d
FR		 4849}
4850
beb1fe18 4851static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
219a1e9d 4852{
350f7596 4853 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4854 { 0x01, 0, 0x0001 },
4855 { 0x02, 0x0800, 0x1000 },
4856 { 0x03, 0, 0x0042 },
4857 { 0x06, 0x0080, 0x0000 },
4858 { 0x07, 0, 0x2000 }
4859 };
4860
f37658da 4861 rtl_set_def_aspm_entry_latency(tp);
b726e493 4862
fdf6fc06 4863 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
b726e493 4864
beb1fe18 4865 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4866}
4867
beb1fe18 4868static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
ef3386f0 4869{
f37658da 4870 rtl_set_def_aspm_entry_latency(tp);
ef3386f0 4871
1ef7286e 4872 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
ef3386f0 4873
faf1e785 4874 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4875 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
ef3386f0 4876
12d42c50 4877 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4878 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
ef3386f0
FR		 4879}
4880
beb1fe18 4881static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
7f3e3d3a 4882{
f37658da 4883 rtl_set_def_aspm_entry_latency(tp);
7f3e3d3a 4884
1ef7286e 4885 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
7f3e3d3a
FR		 4886
4887 /* Magic. */
1ef7286e 4888 RTL_W8(tp, DBG_REG, 0x20);
7f3e3d3a 4889
1ef7286e 4890 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
7f3e3d3a 4891
faf1e785 4892 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4893 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7f3e3d3a 4894
12d42c50 4895 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4896 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
7f3e3d3a
FR		 4897}
4898
beb1fe18 4899static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
219a1e9d 4900{
350f7596 4901 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4902 { 0x02, 0x0800, 0x1000 },
4903 { 0x03, 0, 0x0002 },
4904 { 0x06, 0x0080, 0x0000 }
4905 };
4906
f37658da 4907 rtl_set_def_aspm_entry_latency(tp);
b726e493 4908
1ef7286e 4909 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
b726e493 4910
fdf6fc06 4911 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
b726e493 4912
beb1fe18 4913 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4914}
4915
beb1fe18 4916static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
219a1e9d 4917{
350f7596 4918 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4919 { 0x01, 0, 0x0001 },
4920 { 0x03, 0x0400, 0x0220 }
4921 };
4922
f37658da 4923 rtl_set_def_aspm_entry_latency(tp);
b726e493 4924
fdf6fc06 4925 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
b726e493 4926
beb1fe18 4927 __rtl_hw_start_8168cp(tp);
219a1e9d
FR		 4928}
4929
beb1fe18 4930static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
197ff761 4931{
beb1fe18 4932 rtl_hw_start_8168c_2(tp);
197ff761
FR		 4933}
4934
beb1fe18 4935static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
6fb07058 4936{
f37658da 4937 rtl_set_def_aspm_entry_latency(tp);
6fb07058 4938
beb1fe18 4939 __rtl_hw_start_8168cp(tp);
6fb07058
FR		 4940}
4941
beb1fe18 4942static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5b538df9 4943{
f37658da 4944 rtl_set_def_aspm_entry_latency(tp);
5b538df9 4945
73c86ee3 4946 rtl_disable_clock_request(tp);
5b538df9 4947
1ef7286e 4948 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5b538df9 4949
faf1e785 4950 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4951 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5b538df9 4952
12d42c50 4953 tp->cp_cmd &= CPCMD_QUIRK_MASK;
0ae0974e 4954 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5b538df9
FR		 4955}
4956
beb1fe18 4957static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4804b3b3 4958{
f37658da 4959 rtl_set_def_aspm_entry_latency(tp);
4804b3b3 4960
faf1e785 4961 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 4962 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4804b3b3 4963
1ef7286e 4964 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4804b3b3 4965
73c86ee3 4966 rtl_disable_clock_request(tp);
4804b3b3 4967}
4968
beb1fe18 4969static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
e6de30d6 4970{
4971 static const struct ephy_info e_info_8168d_4[] = {
1016a4a1
CHL		 4972 { 0x0b, 0x0000, 0x0048 },
4973 { 0x19, 0x0020, 0x0050 },
4974 { 0x0c, 0x0100, 0x0020 }
e6de30d6 4975 };
e6de30d6 4976
f37658da 4977 rtl_set_def_aspm_entry_latency(tp);
e6de30d6 4978
8d98aa39 4979 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
e6de30d6 4980
1ef7286e 4981 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
e6de30d6 4982
1016a4a1 4983 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
e6de30d6 4984
73c86ee3 4985 rtl_enable_clock_request(tp);
e6de30d6 4986}
4987
beb1fe18 4988static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
01dc7fec 4989{
70090424 4990 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4991 { 0x00, 0x0200, 0x0100 },
4992 { 0x00, 0x0000, 0x0004 },
4993 { 0x06, 0x0002, 0x0001 },
4994 { 0x06, 0x0000, 0x0030 },
4995 { 0x07, 0x0000, 0x2000 },
4996 { 0x00, 0x0000, 0x0020 },
4997 { 0x03, 0x5800, 0x2000 },
4998 { 0x03, 0x0000, 0x0001 },
4999 { 0x01, 0x0800, 0x1000 },
5000 { 0x07, 0x0000, 0x4000 },
5001 { 0x1e, 0x0000, 0x2000 },
5002 { 0x19, 0xffff, 0xfe6c },
5003 { 0x0a, 0x0000, 0x0040 }
5004 };
5005
f37658da 5006 rtl_set_def_aspm_entry_latency(tp);
01dc7fec 5007
fdf6fc06 5008 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 5009
faf1e785 5010 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5011 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
01dc7fec 5012
1ef7286e 5013 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
01dc7fec 5014
73c86ee3 5015 rtl_disable_clock_request(tp);
01dc7fec 5016
5017 /* Reset tx FIFO pointer */
1ef7286e
AS		 5018 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5019 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
01dc7fec 5020
1ef7286e 5021 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
01dc7fec 5022}
5023
beb1fe18 5024static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
70090424
HW		 5025{
5026 static const struct ephy_info e_info_8168e_2[] = {
5027 { 0x09, 0x0000, 0x0080 },
5028 { 0x19, 0x0000, 0x0224 }
5029 };
5030
f37658da 5031 rtl_set_def_aspm_entry_latency(tp);
70090424 5032
fdf6fc06 5033 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
70090424 5034
faf1e785 5035 if (tp->dev->mtu <= ETH_DATA_LEN)
8d98aa39 5036 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
70090424 5037
fdf6fc06
FR		 5038 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5039 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5040 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5041 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5042 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5043 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
706123d0
CHL		 5044 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5045 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
70090424 5046
1ef7286e 5047 RTL_W8(tp, MaxTxPacketSize, EarlySize);
70090424 5048
73c86ee3 5049 rtl_disable_clock_request(tp);
4521e1a9 5050
1ef7286e 5051 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
70090424
HW		 5052
5053 /* Adjust EEE LED frequency */
1ef7286e 5054 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
70090424 5055
1ef7286e
AS		 5056 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5057 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5058 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
aa1e7d2c
HK		 5059
5060 rtl_hw_aspm_clkreq_enable(tp, true);
70090424
HW		 5061}
5062
5f886e08 5063static void rtl_hw_start_8168f(struct rtl8169_private *tp)
c2218925 5064{
f37658da 5065 rtl_set_def_aspm_entry_latency(tp);
c2218925 5066
8d98aa39 5067 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c2218925 5068
fdf6fc06
FR		 5069 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5070 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5071 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
706123d0
CHL		 5073 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5074 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5075 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5076 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5077 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
c2218925 5079
1ef7286e 5080 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c2218925 5081
73c86ee3 5082 rtl_disable_clock_request(tp);
4521e1a9 5083
1ef7286e
AS		 5084 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5085 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5086 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5087 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
c2218925
HW		 5088}
5089
5f886e08
HW		 5090static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5091{
5f886e08
HW		 5092 static const struct ephy_info e_info_8168f_1[] = {
5093 { 0x06, 0x00c0, 0x0020 },
5094 { 0x08, 0x0001, 0x0002 },
5095 { 0x09, 0x0000, 0x0080 },
5096 { 0x19, 0x0000, 0x0224 }
5097 };
5098
5099 rtl_hw_start_8168f(tp);
5100
fdf6fc06 5101 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5f886e08 5102
706123d0 5103 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5f886e08
HW		 5104
5105 /* Adjust EEE LED frequency */
1ef7286e 5106 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5f886e08
HW		 5107}
5108
b3d7b2f2
HW		 5109static void rtl_hw_start_8411(struct rtl8169_private *tp)
5110{
b3d7b2f2
HW		 5111 static const struct ephy_info e_info_8168f_1[] = {
5112 { 0x06, 0x00c0, 0x0020 },
5113 { 0x0f, 0xffff, 0x5200 },
5114 { 0x1e, 0x0000, 0x4000 },
5115 { 0x19, 0x0000, 0x0224 }
5116 };
5117
5118 rtl_hw_start_8168f(tp);
b51ecea8 5119 rtl_pcie_state_l2l3_enable(tp, false);
b3d7b2f2 5120
fdf6fc06 5121 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
b3d7b2f2 5122
706123d0 5123 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
b3d7b2f2
HW		 5124}
5125
5fbea337 5126static void rtl_hw_start_8168g(struct rtl8169_private *tp)
c558386b 5127{
c558386b
HW		 5128 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5129 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5130 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5131 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5132
f37658da 5133 rtl_set_def_aspm_entry_latency(tp);
c558386b 5134
8d98aa39 5135 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
c558386b 5136
706123d0
CHL		 5137 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5138 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
beb330a4 5139 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
c558386b 5140
1ef7286e
AS		 5141 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5142 RTL_W8(tp, MaxTxPacketSize, EarlySize);
c558386b
HW		 5143
5144 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5145 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5146
5147 /* Adjust EEE LED frequency */
1ef7286e 5148 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
c558386b 5149
706123d0
CHL		 5150 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5151 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
b51ecea8 5152
5153 rtl_pcie_state_l2l3_enable(tp, false);
c558386b
HW		 5154}
5155
5fbea337
CHL		 5156static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5157{
5fbea337
CHL		 5158 static const struct ephy_info e_info_8168g_1[] = {
5159 { 0x00, 0x0000, 0x0008 },
5160 { 0x0c, 0x37d0, 0x0820 },
5161 { 0x1e, 0x0000, 0x0001 },
5162 { 0x19, 0x8000, 0x0000 }
5163 };
5164
5165 rtl_hw_start_8168g(tp);
5166
5167 /* disable aspm and clock request before access ephy */
a99790bf 5168 rtl_hw_aspm_clkreq_enable(tp, false);
5fbea337 5169 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
a99790bf 5170 rtl_hw_aspm_clkreq_enable(tp, true);
5fbea337
CHL		 5171}
5172
57538c4a 5173static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5174{
57538c4a 5175 static const struct ephy_info e_info_8168g_2[] = {
5176 { 0x00, 0x0000, 0x0008 },
5177 { 0x0c, 0x3df0, 0x0200 },
5178 { 0x19, 0xffff, 0xfc00 },
5179 { 0x1e, 0xffff, 0x20eb }
5180 };
5181
5fbea337 5182 rtl_hw_start_8168g(tp);
57538c4a 5183
5184 /* disable aspm and clock request before access ephy */
1ef7286e
AS		 5185 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5186 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
57538c4a 5187 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5188}
5189
45dd95c4 5190static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5191{
45dd95c4 5192 static const struct ephy_info e_info_8411_2[] = {
5193 { 0x00, 0x0000, 0x0008 },
5194 { 0x0c, 0x3df0, 0x0200 },
5195 { 0x0f, 0xffff, 0x5200 },
5196 { 0x19, 0x0020, 0x0000 },
5197 { 0x1e, 0x0000, 0x2000 }
5198 };
5199
5fbea337 5200 rtl_hw_start_8168g(tp);
45dd95c4 5201
5202 /* disable aspm and clock request before access ephy */
a99790bf 5203 rtl_hw_aspm_clkreq_enable(tp, false);
45dd95c4 5204 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
a99790bf 5205 rtl_hw_aspm_clkreq_enable(tp, true);
45dd95c4 5206}
5207
6e1d0b89
CHL		 5208static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5209{
72521ea0 5210 int rg_saw_cnt;
6e1d0b89
CHL		 5211 u32 data;
5212 static const struct ephy_info e_info_8168h_1[] = {
5213 { 0x1e, 0x0800, 0x0001 },
5214 { 0x1d, 0x0000, 0x0800 },
5215 { 0x05, 0xffff, 0x2089 },
5216 { 0x06, 0xffff, 0x5881 },
5217 { 0x04, 0xffff, 0x154a },
5218 { 0x01, 0xffff, 0x068b }
5219 };
5220
5221 /* disable aspm and clock request before access ephy */
a99790bf 5222 rtl_hw_aspm_clkreq_enable(tp, false);
6e1d0b89
CHL		 5223 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5224
6e1d0b89
CHL		 5225 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5226 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5227 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5228 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5229
f37658da 5230 rtl_set_def_aspm_entry_latency(tp);
6e1d0b89 5231
8d98aa39 5232 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
6e1d0b89 5233
706123d0
CHL		 5234 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5235 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6e1d0b89 5236
706123d0 5237 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6e1d0b89 5238
706123d0 5239 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6e1d0b89
CHL		 5240
5241 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5242
1ef7286e
AS		 5243 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5244 RTL_W8(tp, MaxTxPacketSize, EarlySize);
6e1d0b89
CHL		 5245
5246 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5247 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5248
5249 /* Adjust EEE LED frequency */
1ef7286e 5250 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
6e1d0b89 5251
1ef7286e
AS		 5252 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5253 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
6e1d0b89 5254
1ef7286e 5255 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
6e1d0b89 5256
706123d0 5257 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6e1d0b89
CHL		 5258
5259 rtl_pcie_state_l2l3_enable(tp, false);
5260
5261 rtl_writephy(tp, 0x1f, 0x0c42);
58493333 5262 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
6e1d0b89
CHL		 5263 rtl_writephy(tp, 0x1f, 0x0000);
5264 if (rg_saw_cnt > 0) {
5265 u16 sw_cnt_1ms_ini;
5266
5267 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5268 sw_cnt_1ms_ini &= 0x0fff;
5269 data = r8168_mac_ocp_read(tp, 0xd412);
a2cb7ec0 5270 data &= ~0x0fff;
6e1d0b89
CHL		 5271 data |= sw_cnt_1ms_ini;
5272 r8168_mac_ocp_write(tp, 0xd412, data);
5273 }
5274
5275 data = r8168_mac_ocp_read(tp, 0xe056);
a2cb7ec0
CHL		 5276 data &= ~0xf0;
5277 data |= 0x70;
6e1d0b89
CHL		 5278 r8168_mac_ocp_write(tp, 0xe056, data);
5279
5280 data = r8168_mac_ocp_read(tp, 0xe052);
a2cb7ec0
CHL		 5281 data &= ~0x6000;
5282 data |= 0x8008;
6e1d0b89
CHL		 5283 r8168_mac_ocp_write(tp, 0xe052, data);
5284
5285 data = r8168_mac_ocp_read(tp, 0xe0d6);
a2cb7ec0 5286 data &= ~0x01ff;
6e1d0b89
CHL		 5287 data |= 0x017f;
5288 r8168_mac_ocp_write(tp, 0xe0d6, data);
5289
5290 data = r8168_mac_ocp_read(tp, 0xd420);
a2cb7ec0 5291 data &= ~0x0fff;
6e1d0b89
CHL		 5292 data |= 0x047f;
5293 r8168_mac_ocp_write(tp, 0xd420, data);
5294
5295 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5296 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5297 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5298 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
a99790bf
KHF		 5299
5300 rtl_hw_aspm_clkreq_enable(tp, true);
6e1d0b89
CHL		 5301}
5302
935e2218
CHL		 5303static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5304{
003609da
CHL		 5305 rtl8168ep_stop_cmac(tp);
5306
935e2218
CHL		 5307 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5308 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5309 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5310 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5311
f37658da 5312 rtl_set_def_aspm_entry_latency(tp);
935e2218 5313
8d98aa39 5314 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
935e2218
CHL		 5315
5316 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5317 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5318
5319 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5320
5321 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5322
1ef7286e
AS		 5323 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5324 RTL_W8(tp, MaxTxPacketSize, EarlySize);
935e2218
CHL		 5325
5326 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5327 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5328
5329 /* Adjust EEE LED frequency */
1ef7286e 5330 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
935e2218
CHL		 5331
5332 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5333
1ef7286e 5334 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
935e2218
CHL		 5335
5336 rtl_pcie_state_l2l3_enable(tp, false);
5337}
5338
5339static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5340{
935e2218
CHL		 5341 static const struct ephy_info e_info_8168ep_1[] = {
5342 { 0x00, 0xffff, 0x10ab },
5343 { 0x06, 0xffff, 0xf030 },
5344 { 0x08, 0xffff, 0x2006 },
5345 { 0x0d, 0xffff, 0x1666 },
5346 { 0x0c, 0x3ff0, 0x0000 }
5347 };
5348
5349 /* disable aspm and clock request before access ephy */
a99790bf 5350 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5351 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5352
5353 rtl_hw_start_8168ep(tp);
a99790bf
KHF		 5354
5355 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5356}
5357
5358static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5359{
935e2218
CHL		 5360 static const struct ephy_info e_info_8168ep_2[] = {
5361 { 0x00, 0xffff, 0x10a3 },
5362 { 0x19, 0xffff, 0xfc00 },
5363 { 0x1e, 0xffff, 0x20ea }
5364 };
5365
5366 /* disable aspm and clock request before access ephy */
a99790bf 5367 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5368 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5369
5370 rtl_hw_start_8168ep(tp);
5371
1ef7286e
AS		 5372 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5373 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
a99790bf
KHF		 5374
5375 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5376}
5377
5378static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5379{
935e2218
CHL		 5380 u32 data;
5381 static const struct ephy_info e_info_8168ep_3[] = {
5382 { 0x00, 0xffff, 0x10a3 },
5383 { 0x19, 0xffff, 0x7c00 },
5384 { 0x1e, 0xffff, 0x20eb },
5385 { 0x0d, 0xffff, 0x1666 }
5386 };
5387
5388 /* disable aspm and clock request before access ephy */
a99790bf 5389 rtl_hw_aspm_clkreq_enable(tp, false);
935e2218
CHL		 5390 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5391
5392 rtl_hw_start_8168ep(tp);
5393
1ef7286e
AS		 5394 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5395 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
935e2218
CHL		 5396
5397 data = r8168_mac_ocp_read(tp, 0xd3e2);
5398 data &= 0xf000;
5399 data |= 0x0271;
5400 r8168_mac_ocp_write(tp, 0xd3e2, data);
5401
5402 data = r8168_mac_ocp_read(tp, 0xd3e4);
5403 data &= 0xff00;
5404 r8168_mac_ocp_write(tp, 0xd3e4, data);
5405
5406 data = r8168_mac_ocp_read(tp, 0xe860);
5407 data |= 0x0080;
5408 r8168_mac_ocp_write(tp, 0xe860, data);
a99790bf
KHF		 5409
5410 rtl_hw_aspm_clkreq_enable(tp, true);
935e2218
CHL		 5411}
5412
61cb532d 5413static void rtl_hw_start_8168(struct rtl8169_private *tp)
07ce4064 5414{
1ef7286e 5415 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
2dd99530 5416
0ae0974e
HK		 5417 tp->cp_cmd &= ~INTT_MASK;
5418 tp->cp_cmd |= PktCntrDisable | INTT_1;
1ef7286e 5419 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2dd99530 5420
1ef7286e 5421 RTL_W16(tp, IntrMitigate, 0x5151);
2dd99530 5422
0e485150 5423 /* Work around for RxFIFO overflow. */
811fd301 5424 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
da78dbff
FR		 5425 tp->event_slow |= RxFIFOOver | PCSTimeout;
5426 tp->event_slow &= ~RxOverflow;
0e485150
FR		 5427 }
5428
219a1e9d
FR		 5429 switch (tp->mac_version) {
5430 case RTL_GIGA_MAC_VER_11:
beb1fe18 5431 rtl_hw_start_8168bb(tp);
4804b3b3 5432 break;
219a1e9d
FR		 5433
5434 case RTL_GIGA_MAC_VER_12:
5435 case RTL_GIGA_MAC_VER_17:
beb1fe18 5436 rtl_hw_start_8168bef(tp);
4804b3b3 5437 break;
219a1e9d
FR		 5438
5439 case RTL_GIGA_MAC_VER_18:
beb1fe18 5440 rtl_hw_start_8168cp_1(tp);
4804b3b3 5441 break;
219a1e9d
FR		 5442
5443 case RTL_GIGA_MAC_VER_19:
beb1fe18 5444 rtl_hw_start_8168c_1(tp);
4804b3b3 5445 break;
219a1e9d
FR		 5446
5447 case RTL_GIGA_MAC_VER_20:
beb1fe18 5448 rtl_hw_start_8168c_2(tp);
4804b3b3 5449 break;
219a1e9d 5450
197ff761 5451 case RTL_GIGA_MAC_VER_21:
beb1fe18 5452 rtl_hw_start_8168c_3(tp);
4804b3b3 5453 break;
197ff761 5454
6fb07058 5455 case RTL_GIGA_MAC_VER_22:
beb1fe18 5456 rtl_hw_start_8168c_4(tp);
4804b3b3 5457 break;
6fb07058 5458
ef3386f0 5459 case RTL_GIGA_MAC_VER_23:
beb1fe18 5460 rtl_hw_start_8168cp_2(tp);
4804b3b3 5461 break;
ef3386f0 5462
7f3e3d3a 5463 case RTL_GIGA_MAC_VER_24:
beb1fe18 5464 rtl_hw_start_8168cp_3(tp);
4804b3b3 5465 break;
7f3e3d3a 5466
5b538df9 5467 case RTL_GIGA_MAC_VER_25:
daf9df6d 5468 case RTL_GIGA_MAC_VER_26:
5469 case RTL_GIGA_MAC_VER_27:
beb1fe18 5470 rtl_hw_start_8168d(tp);
4804b3b3 5471 break;
5b538df9 5472
e6de30d6 5473 case RTL_GIGA_MAC_VER_28:
beb1fe18 5474 rtl_hw_start_8168d_4(tp);
4804b3b3 5475 break;
cecb5fd7 5476
4804b3b3 5477 case RTL_GIGA_MAC_VER_31:
beb1fe18 5478 rtl_hw_start_8168dp(tp);
4804b3b3 5479 break;
5480
01dc7fec 5481 case RTL_GIGA_MAC_VER_32:
5482 case RTL_GIGA_MAC_VER_33:
beb1fe18 5483 rtl_hw_start_8168e_1(tp);
70090424
HW		 5484 break;
5485 case RTL_GIGA_MAC_VER_34:
beb1fe18 5486 rtl_hw_start_8168e_2(tp);
01dc7fec 5487 break;
e6de30d6 5488
c2218925
HW		 5489 case RTL_GIGA_MAC_VER_35:
5490 case RTL_GIGA_MAC_VER_36:
beb1fe18 5491 rtl_hw_start_8168f_1(tp);
c2218925
HW		 5492 break;
5493
b3d7b2f2
HW		 5494 case RTL_GIGA_MAC_VER_38:
5495 rtl_hw_start_8411(tp);
5496 break;
5497
c558386b
HW		 5498 case RTL_GIGA_MAC_VER_40:
5499 case RTL_GIGA_MAC_VER_41:
5500 rtl_hw_start_8168g_1(tp);
5501 break;
57538c4a 5502 case RTL_GIGA_MAC_VER_42:
5503 rtl_hw_start_8168g_2(tp);
5504 break;
c558386b 5505
45dd95c4 5506 case RTL_GIGA_MAC_VER_44:
5507 rtl_hw_start_8411_2(tp);
5508 break;
5509
6e1d0b89
CHL		 5510 case RTL_GIGA_MAC_VER_45:
5511 case RTL_GIGA_MAC_VER_46:
5512 rtl_hw_start_8168h_1(tp);
5513 break;
5514
935e2218
CHL		 5515 case RTL_GIGA_MAC_VER_49:
5516 rtl_hw_start_8168ep_1(tp);
5517 break;
5518
5519 case RTL_GIGA_MAC_VER_50:
5520 rtl_hw_start_8168ep_2(tp);
5521 break;
5522
5523 case RTL_GIGA_MAC_VER_51:
5524 rtl_hw_start_8168ep_3(tp);
5525 break;
5526
219a1e9d 5527 default:
49d17512
HK		 5528 netif_err(tp, drv, tp->dev,
5529 "unknown chipset (mac_version = %d)\n",
5530 tp->mac_version);
4804b3b3 5531 break;
219a1e9d 5532 }
07ce4064 5533}
1da177e4 5534
beb1fe18 5535static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
2857ffb7 5536{
350f7596 5537 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 5538 { 0x01, 0, 0x6e65 },
5539 { 0x02, 0, 0x091f },
5540 { 0x03, 0, 0xc2f9 },
5541 { 0x06, 0, 0xafb5 },
5542 { 0x07, 0, 0x0e00 },
5543 { 0x19, 0, 0xec80 },
5544 { 0x01, 0, 0x2e65 },
5545 { 0x01, 0, 0x6e65 }
5546 };
5547 u8 cfg1;
5548
f37658da 5549 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5550
1ef7286e 5551 RTL_W8(tp, DBG_REG, FIX_NAK_1);
2857ffb7 5552
8d98aa39 5553 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5554
1ef7286e 5555 RTL_W8(tp, Config1,
2857ffb7 5556 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
1ef7286e 5557 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7 5558
1ef7286e 5559 cfg1 = RTL_R8(tp, Config1);
2857ffb7 5560 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
1ef7286e 5561 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
2857ffb7 5562
fdf6fc06 5563 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2857ffb7
FR		 5564}
5565
beb1fe18 5566static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
2857ffb7 5567{
f37658da 5568 rtl_set_def_aspm_entry_latency(tp);
2857ffb7 5569
8d98aa39 5570 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
2857ffb7 5571
1ef7286e
AS		 5572 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5573 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857ffb7
FR		 5574}
5575
beb1fe18 5576static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
2857ffb7 5577{
beb1fe18 5578 rtl_hw_start_8102e_2(tp);
2857ffb7 5579
fdf6fc06 5580 rtl_ephy_write(tp, 0x03, 0xc2f9);
2857ffb7
FR		 5581}
5582
beb1fe18 5583static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5a5e4443
HW		 5584{
5585 static const struct ephy_info e_info_8105e_1[] = {
5586 { 0x07, 0, 0x4000 },
5587 { 0x19, 0, 0x0200 },
5588 { 0x19, 0, 0x0020 },
5589 { 0x1e, 0, 0x2000 },
5590 { 0x03, 0, 0x0001 },
5591 { 0x19, 0, 0x0100 },
5592 { 0x19, 0, 0x0004 },
5593 { 0x0a, 0, 0x0020 }
5594 };
5595
cecb5fd7 5596 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5597 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5a5e4443 5598
cecb5fd7 5599 /* Disable Early Tally Counter */
1ef7286e 5600 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5a5e4443 5601
1ef7286e
AS		 5602 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5603 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5a5e4443 5604
fdf6fc06 5605 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
b51ecea8 5606
5607 rtl_pcie_state_l2l3_enable(tp, false);
5a5e4443
HW		 5608}
5609
beb1fe18 5610static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5a5e4443 5611{
beb1fe18 5612 rtl_hw_start_8105e_1(tp);
fdf6fc06 5613 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5a5e4443
HW		 5614}
5615
7e18dca1
HW		 5616static void rtl_hw_start_8402(struct rtl8169_private *tp)
5617{
7e18dca1
HW		 5618 static const struct ephy_info e_info_8402[] = {
5619 { 0x19, 0xffff, 0xff64 },
5620 { 0x1e, 0, 0x4000 }
5621 };
5622
f37658da 5623 rtl_set_def_aspm_entry_latency(tp);
7e18dca1
HW		 5624
5625 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5626 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
7e18dca1 5627
1ef7286e 5628 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7e18dca1 5629
fdf6fc06 5630 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
7e18dca1 5631
8d98aa39 5632 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
7e18dca1 5633
fdf6fc06
FR		 5634 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5635 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
706123d0
CHL		 5636 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5637 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
fdf6fc06
FR		 5638 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5639 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
706123d0 5640 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
b51ecea8 5641
5642 rtl_pcie_state_l2l3_enable(tp, false);
7e18dca1
HW		 5643}
5644
5598bfe5
HW		 5645static void rtl_hw_start_8106(struct rtl8169_private *tp)
5646{
0866cd15
KHF		 5647 rtl_hw_aspm_clkreq_enable(tp, false);
5648
5598bfe5 5649 /* Force LAN exit from ASPM if Rx/Tx are not idle */
1ef7286e 5650 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5598bfe5 5651
1ef7286e
AS		 5652 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5653 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5654 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
b51ecea8 5655
5656 rtl_pcie_state_l2l3_enable(tp, false);
0866cd15 5657 rtl_hw_aspm_clkreq_enable(tp, true);
5598bfe5
HW		 5658}
5659
61cb532d 5660static void rtl_hw_start_8101(struct rtl8169_private *tp)
07ce4064 5661{
da78dbff
FR		 5662 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5663 tp->event_slow &= ~RxFIFOOver;
811fd301 5664
cecb5fd7 5665 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
7d7903b2 5666 tp->mac_version == RTL_GIGA_MAC_VER_16)
61cb532d 5667 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
8200bc72 5668 PCI_EXP_DEVCTL_NOSNOOP_EN);
cdf1a608 5669
1ef7286e 5670 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
1a964649 5671
12d42c50 5672 tp->cp_cmd &= CPCMD_QUIRK_MASK;
1ef7286e 5673 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1a964649 5674
2857ffb7
FR		 5675 switch (tp->mac_version) {
5676 case RTL_GIGA_MAC_VER_07:
beb1fe18 5677 rtl_hw_start_8102e_1(tp);
2857ffb7
FR		 5678 break;
5679
5680 case RTL_GIGA_MAC_VER_08:
beb1fe18 5681 rtl_hw_start_8102e_3(tp);
2857ffb7
FR		 5682 break;
5683
5684 case RTL_GIGA_MAC_VER_09:
beb1fe18 5685 rtl_hw_start_8102e_2(tp);
2857ffb7 5686 break;
5a5e4443
HW		 5687
5688 case RTL_GIGA_MAC_VER_29:
beb1fe18 5689 rtl_hw_start_8105e_1(tp);
5a5e4443
HW		 5690 break;
5691 case RTL_GIGA_MAC_VER_30:
beb1fe18 5692 rtl_hw_start_8105e_2(tp);
5a5e4443 5693 break;
7e18dca1
HW		 5694
5695 case RTL_GIGA_MAC_VER_37:
5696 rtl_hw_start_8402(tp);
5697 break;
5598bfe5
HW		 5698
5699 case RTL_GIGA_MAC_VER_39:
5700 rtl_hw_start_8106(tp);
5701 break;
58152cd4 5702 case RTL_GIGA_MAC_VER_43:
5703 rtl_hw_start_8168g_2(tp);
5704 break;
6e1d0b89
CHL		 5705 case RTL_GIGA_MAC_VER_47:
5706 case RTL_GIGA_MAC_VER_48:
5707 rtl_hw_start_8168h_1(tp);
5708 break;
cdf1a608
FR		 5709 }
5710
1ef7286e 5711 RTL_W16(tp, IntrMitigate, 0x0000);
1da177e4
LT		 5712}
5713
5714static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5715{
d58d46b5
FR		 5716 struct rtl8169_private *tp = netdev_priv(dev);
5717
d58d46b5
FR		 5718 if (new_mtu > ETH_DATA_LEN)
5719 rtl_hw_jumbo_enable(tp);
5720 else
5721 rtl_hw_jumbo_disable(tp);
5722
1da177e4 5723 dev->mtu = new_mtu;
350fb32a
MM		 5724 netdev_update_features(dev);
5725
323bb685 5726 return 0;
1da177e4
LT		 5727}
5728
5729static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5730{
95e0918d 5731 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 5732 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5733}
5734
6f0333b8
ED		 5735static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5736 void **data_buff, struct RxDesc *desc)
1da177e4 5737{
1d0254dd
HK		 5738 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5739 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
48addcc9 5740
6f0333b8
ED		 5741 kfree(*data_buff);
5742 *data_buff = NULL;
1da177e4
LT		 5743 rtl8169_make_unusable_by_asic(desc);
5744}
5745
1d0254dd 5746static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
1da177e4
LT		 5747{
5748 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5749
a0750138
AD		 5750 /* Force memory writes to complete before releasing descriptor */
5751 dma_wmb();
5752
1d0254dd 5753 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
1da177e4
LT		 5754}
5755
6f0333b8
ED		 5756static inline void *rtl8169_align(void *data)
5757{
5758 return (void *)ALIGN((long)data, 16);
5759}
5760
0ecbe1ca
SG		 5761static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5762 struct RxDesc *desc)
1da177e4 5763{
6f0333b8 5764 void *data;
1da177e4 5765 dma_addr_t mapping;
1e1205b7 5766 struct device *d = tp_to_dev(tp);
d3b404c2 5767 int node = dev_to_node(d);
1da177e4 5768
1d0254dd 5769 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
6f0333b8
ED		 5770 if (!data)
5771 return NULL;
e9f63f30 5772
6f0333b8
ED		 5773 if (rtl8169_align(data) != data) {
5774 kfree(data);
1d0254dd 5775 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
6f0333b8
ED		 5776 if (!data)
5777 return NULL;
5778 }
3eafe507 5779
1d0254dd 5780 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
231aee63 5781 DMA_FROM_DEVICE);
d827d86b
SG		 5782 if (unlikely(dma_mapping_error(d, mapping))) {
5783 if (net_ratelimit())
5784 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 5785 goto err_out;
d827d86b 5786 }
1da177e4 5787
d731af78
HK		 5788 desc->addr = cpu_to_le64(mapping);
5789 rtl8169_mark_to_asic(desc);
6f0333b8 5790 return data;
3eafe507
SG		 5791
5792err_out:
5793 kfree(data);
5794 return NULL;
1da177e4
LT		 5795}
5796
5797static void rtl8169_rx_clear(struct rtl8169_private *tp)
5798{
07d3f51f 5799 unsigned int i;
1da177e4
LT		 5800
5801 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 5802 if (tp->Rx_databuff[i]) {
5803 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 5804 tp->RxDescArray + i);
5805 }
5806 }
5807}
5808
0ecbe1ca 5809static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 5810{
0ecbe1ca
SG		 5811 desc->opts1 |= cpu_to_le32(RingEnd);
5812}
5b0384f4 5813
0ecbe1ca
SG		 5814static int rtl8169_rx_fill(struct rtl8169_private *tp)
5815{
5816 unsigned int i;
1da177e4 5817
0ecbe1ca
SG		 5818 for (i = 0; i < NUM_RX_DESC; i++) {
5819 void *data;
4ae47c2d 5820
0ecbe1ca 5821 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 5822 if (!data) {
5823 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 5824 goto err_out;
6f0333b8
ED		 5825 }
5826 tp->Rx_databuff[i] = data;
1da177e4 5827 }
1da177e4 5828
0ecbe1ca
SG		 5829 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5830 return 0;
5831
5832err_out:
5833 rtl8169_rx_clear(tp);
5834 return -ENOMEM;
1da177e4
LT		 5835}
5836
b1127e64 5837static int rtl8169_init_ring(struct rtl8169_private *tp)
1da177e4 5838{
1da177e4
LT		 5839 rtl8169_init_ring_indexes(tp);
5840
b1127e64
HK		 5841 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5842 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
1da177e4 5843
0ecbe1ca 5844 return rtl8169_rx_fill(tp);
1da177e4
LT		 5845}
5846
48addcc9 5847static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 5848 struct TxDesc *desc)
5849{
5850 unsigned int len = tx_skb->len;
5851
48addcc9
SG		 5852 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5853
1da177e4
LT		 5854 desc->opts1 = 0x00;
5855 desc->opts2 = 0x00;
5856 desc->addr = 0x00;
5857 tx_skb->len = 0;
5858}
5859
3eafe507
SG		 5860static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5861 unsigned int n)
1da177e4
LT		 5862{
5863 unsigned int i;
5864
3eafe507
SG		 5865 for (i = 0; i < n; i++) {
5866 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 5867 struct ring_info *tx_skb = tp->tx_skb + entry;
5868 unsigned int len = tx_skb->len;
5869
5870 if (len) {
5871 struct sk_buff *skb = tx_skb->skb;
5872
1e1205b7 5873 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
1da177e4
LT		 5874 tp->TxDescArray + entry);
5875 if (skb) {
7a4b813c 5876 dev_consume_skb_any(skb);
1da177e4
LT		 5877 tx_skb->skb = NULL;
5878 }
1da177e4
LT		 5879 }
5880 }
3eafe507
SG		 5881}
5882
5883static void rtl8169_tx_clear(struct rtl8169_private *tp)
5884{
5885 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 5886 tp->cur_tx = tp->dirty_tx = 0;
5887}
5888
4422bcd4 5889static void rtl_reset_work(struct rtl8169_private *tp)
1da177e4 5890{
c4028958 5891 struct net_device *dev = tp->dev;
56de414c 5892 int i;
1da177e4 5893
da78dbff
FR		 5894 napi_disable(&tp->napi);
5895 netif_stop_queue(dev);
5896 synchronize_sched();
1da177e4 5897
c7c2c39b 5898 rtl8169_hw_reset(tp);
5899
56de414c 5900 for (i = 0; i < NUM_RX_DESC; i++)
1d0254dd 5901 rtl8169_mark_to_asic(tp->RxDescArray + i);
56de414c 5902
1da177e4 5903 rtl8169_tx_clear(tp);
c7c2c39b 5904 rtl8169_init_ring_indexes(tp);
1da177e4 5905
da78dbff 5906 napi_enable(&tp->napi);
61cb532d 5907 rtl_hw_start(tp);
56de414c 5908 netif_wake_queue(dev);
1da177e4
LT		 5909}
5910
5911static void rtl8169_tx_timeout(struct net_device *dev)
5912{
da78dbff
FR		 5913 struct rtl8169_private *tp = netdev_priv(dev);
5914
5915 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 5916}
5917
5918static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5919 u32 *opts)
1da177e4
LT		 5920{
5921 struct skb_shared_info *info = skb_shinfo(skb);
5922 unsigned int cur_frag, entry;
6e1d0b89 5923 struct TxDesc *uninitialized_var(txd);
1e1205b7 5924 struct device *d = tp_to_dev(tp);
1da177e4
LT		 5925
5926 entry = tp->cur_tx;
5927 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
9e903e08 5928 const skb_frag_t *frag = info->frags + cur_frag;
1da177e4
LT		 5929 dma_addr_t mapping;
5930 u32 status, len;
5931 void *addr;
5932
5933 entry = (entry + 1) % NUM_TX_DESC;
5934
5935 txd = tp->TxDescArray + entry;
9e903e08 5936 len = skb_frag_size(frag);
929f6189 5937 addr = skb_frag_address(frag);
48addcc9 5938 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5939 if (unlikely(dma_mapping_error(d, mapping))) {
5940 if (net_ratelimit())
5941 netif_err(tp, drv, tp->dev,
5942 "Failed to map TX fragments DMA!\n");
3eafe507 5943 goto err_out;
d827d86b 5944 }
1da177e4 5945
cecb5fd7 5946 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5947 status = opts[0] | len |
5948 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5949
5950 txd->opts1 = cpu_to_le32(status);
2b7b4318 5951 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5952 txd->addr = cpu_to_le64(mapping);
5953
5954 tp->tx_skb[entry].len = len;
5955 }
5956
5957 if (cur_frag) {
5958 tp->tx_skb[entry].skb = skb;
5959 txd->opts1 |= cpu_to_le32(LastFrag);
5960 }
5961
5962 return cur_frag;
3eafe507
SG		 5963
5964err_out:
5965 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5966 return -EIO;
1da177e4
LT		 5967}
5968
b423e9ae 5969static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5970{
5971 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5972}
5973
e974604b 5974static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5975 struct net_device *dev);
5976/* r8169_csum_workaround()
5977 * The hw limites the value the transport offset. When the offset is out of the
5978 * range, calculate the checksum by sw.
5979 */
5980static void r8169_csum_workaround(struct rtl8169_private *tp,
5981 struct sk_buff *skb)
5982{
5983 if (skb_shinfo(skb)->gso_size) {
5984 netdev_features_t features = tp->dev->features;
5985 struct sk_buff *segs, *nskb;
5986
5987 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5988 segs = skb_gso_segment(skb, features);
5989 if (IS_ERR(segs) || !segs)
5990 goto drop;
5991
5992 do {
5993 nskb = segs;
5994 segs = segs->next;
5995 nskb->next = NULL;
5996 rtl8169_start_xmit(nskb, tp->dev);
5997 } while (segs);
5998
eb781397 5999 dev_consume_skb_any(skb);
e974604b 6000 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6001 if (skb_checksum_help(skb) < 0)
6002 goto drop;
6003
6004 rtl8169_start_xmit(skb, tp->dev);
6005 } else {
6006 struct net_device_stats *stats;
6007
6008drop:
6009 stats = &tp->dev->stats;
6010 stats->tx_dropped++;
eb781397 6011 dev_kfree_skb_any(skb);
e974604b 6012 }
6013}
6014
6015/* msdn_giant_send_check()
6016 * According to the document of microsoft, the TCP Pseudo Header excludes the
6017 * packet length for IPv6 TCP large packets.
6018 */
6019static int msdn_giant_send_check(struct sk_buff *skb)
6020{
6021 const struct ipv6hdr *ipv6h;
6022 struct tcphdr *th;
6023 int ret;
6024
6025 ret = skb_cow_head(skb, 0);
6026 if (ret)
6027 return ret;
6028
6029 ipv6h = ipv6_hdr(skb);
6030 th = tcp_hdr(skb);
6031
6032 th->check = 0;
6033 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6034
6035 return ret;
6036}
6037
5888d3fc 6038static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6039 struct sk_buff *skb, u32 *opts)
1da177e4 6040{
350fb32a
MM		 6041 u32 mss = skb_shinfo(skb)->gso_size;
6042
2b7b4318
FR		 6043 if (mss) {
6044 opts[0] |= TD_LSO;
5888d3fc 6045 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6046 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6047 const struct iphdr *ip = ip_hdr(skb);
6048
6049 if (ip->protocol == IPPROTO_TCP)
6050 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6051 else if (ip->protocol == IPPROTO_UDP)
6052 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6053 else
6054 WARN_ON_ONCE(1);
6055 }
6056
6057 return true;
6058}
6059
6060static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6061 struct sk_buff *skb, u32 *opts)
6062{
bdfa4ed6 6063 u32 transport_offset = (u32)skb_transport_offset(skb);
5888d3fc 6064 u32 mss = skb_shinfo(skb)->gso_size;
6065
6066 if (mss) {
e974604b 6067 if (transport_offset > GTTCPHO_MAX) {
6068 netif_warn(tp, tx_err, tp->dev,
6069 "Invalid transport offset 0x%x for TSO\n",
6070 transport_offset);
6071 return false;
6072 }
6073
4ff36466 6074 switch (vlan_get_protocol(skb)) {
e974604b 6075 case htons(ETH_P_IP):
6076 opts[0] |= TD1_GTSENV4;
6077 break;
6078
6079 case htons(ETH_P_IPV6):
6080 if (msdn_giant_send_check(skb))
6081 return false;
6082
6083 opts[0] |= TD1_GTSENV6;
6084 break;
6085
6086 default:
6087 WARN_ON_ONCE(1);
6088 break;
6089 }
6090
bdfa4ed6 6091 opts[0] |= transport_offset << GTTCPHO_SHIFT;
5888d3fc 6092 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
2b7b4318 6093 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
e974604b 6094 u8 ip_protocol;
1da177e4 6095
b423e9ae 6096 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6097 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
b423e9ae 6098
e974604b 6099 if (transport_offset > TCPHO_MAX) {
6100 netif_warn(tp, tx_err, tp->dev,
6101 "Invalid transport offset 0x%x\n",
6102 transport_offset);
6103 return false;
6104 }
6105
4ff36466 6106 switch (vlan_get_protocol(skb)) {
e974604b 6107 case htons(ETH_P_IP):
6108 opts[1] |= TD1_IPv4_CS;
6109 ip_protocol = ip_hdr(skb)->protocol;
6110 break;
6111
6112 case htons(ETH_P_IPV6):
6113 opts[1] |= TD1_IPv6_CS;
6114 ip_protocol = ipv6_hdr(skb)->nexthdr;
6115 break;
6116
6117 default:
6118 ip_protocol = IPPROTO_RAW;
6119 break;
6120 }
6121
6122 if (ip_protocol == IPPROTO_TCP)
6123 opts[1] |= TD1_TCP_CS;
6124 else if (ip_protocol == IPPROTO_UDP)
6125 opts[1] |= TD1_UDP_CS;
2b7b4318
FR		 6126 else
6127 WARN_ON_ONCE(1);
e974604b 6128
6129 opts[1] |= transport_offset << TCPHO_SHIFT;
b423e9ae 6130 } else {
6131 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
207c5f44 6132 return !eth_skb_pad(skb);
1da177e4 6133 }
5888d3fc 6134
b423e9ae 6135 return true;
1da177e4
LT		 6136}
6137
61357325
SH		 6138static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6139 struct net_device *dev)
1da177e4
LT		 6140{
6141 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 6142 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4 6143 struct TxDesc *txd = tp->TxDescArray + entry;
1e1205b7 6144 struct device *d = tp_to_dev(tp);
1da177e4
LT		 6145 dma_addr_t mapping;
6146 u32 status, len;
2b7b4318 6147 u32 opts[2];
3eafe507 6148 int frags;
5b0384f4 6149
477206a0 6150 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
bf82c189 6151 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 6152 goto err_stop_0;
1da177e4
LT		 6153 }
6154
6155 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 6156 goto err_stop_0;
6157
b423e9ae 6158 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6159 opts[0] = DescOwn;
6160
e974604b 6161 if (!tp->tso_csum(tp, skb, opts)) {
6162 r8169_csum_workaround(tp, skb);
6163 return NETDEV_TX_OK;
6164 }
b423e9ae 6165
3eafe507 6166 len = skb_headlen(skb);
48addcc9 6167 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 6168 if (unlikely(dma_mapping_error(d, mapping))) {
6169 if (net_ratelimit())
6170 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 6171 goto err_dma_0;
d827d86b 6172 }
3eafe507
SG		 6173
6174 tp->tx_skb[entry].len = len;
6175 txd->addr = cpu_to_le64(mapping);
1da177e4 6176
2b7b4318 6177 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 6178 if (frags < 0)
6179 goto err_dma_1;
6180 else if (frags)
2b7b4318 6181 opts[0] |= FirstFrag;
3eafe507 6182 else {
2b7b4318 6183 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 6184 tp->tx_skb[entry].skb = skb;
6185 }
6186
2b7b4318
FR		 6187 txd->opts2 = cpu_to_le32(opts[1]);
6188
5047fb5d
RC		 6189 skb_tx_timestamp(skb);
6190
a0750138
AD		 6191 /* Force memory writes to complete before releasing descriptor */
6192 dma_wmb();
1da177e4 6193
cecb5fd7 6194 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 6195 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 6196 txd->opts1 = cpu_to_le32(status);
6197
a0750138 6198 /* Force all memory writes to complete before notifying device */
4c020a96 6199 wmb();
1da177e4 6200
a0750138
AD		 6201 tp->cur_tx += frags + 1;
6202
1ef7286e 6203 RTL_W8(tp, TxPoll, NPQ);
1da177e4 6204
87cda7cb 6205 mmiowb();
da78dbff 6206
87cda7cb 6207 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
ae1f23fb
FR		 6208 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6209 * not miss a ring update when it notices a stopped queue.
6210 */
6211 smp_wmb();
1da177e4 6212 netif_stop_queue(dev);
ae1f23fb
FR		 6213 /* Sync with rtl_tx:
6214 * - publish queue status and cur_tx ring index (write barrier)
6215 * - refresh dirty_tx ring index (read barrier).
6216 * May the current thread have a pessimistic view of the ring
6217 * status and forget to wake up queue, a racing rtl_tx thread
6218 * can't.
6219 */
1e874e04 6220 smp_mb();
477206a0 6221 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
1da177e4
LT		 6222 netif_wake_queue(dev);
6223 }
6224
61357325 6225 return NETDEV_TX_OK;
1da177e4 6226
3eafe507 6227err_dma_1:
48addcc9 6228 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507 6229err_dma_0:
989c9ba1 6230 dev_kfree_skb_any(skb);
3eafe507
SG		 6231 dev->stats.tx_dropped++;
6232 return NETDEV_TX_OK;
6233
6234err_stop_0:
1da177e4 6235 netif_stop_queue(dev);
cebf8cc7 6236 dev->stats.tx_dropped++;
61357325 6237 return NETDEV_TX_BUSY;
1da177e4
LT		 6238}
6239
6240static void rtl8169_pcierr_interrupt(struct net_device *dev)
6241{
6242 struct rtl8169_private *tp = netdev_priv(dev);
6243 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 6244 u16 pci_status, pci_cmd;
6245
6246 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6247 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6248
bf82c189
JP		 6249 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6250 pci_cmd, pci_status);
1da177e4
LT		 6251
6252 /*
6253 * The recovery sequence below admits a very elaborated explanation:
6254 * - it seems to work;
d03902b8
FR		 6255 * - I did not see what else could be done;
6256 * - it makes iop3xx happy.
1da177e4
LT		 6257 *
6258 * Feel free to adjust to your needs.
6259 */
a27993f3 6260 if (pdev->broken_parity_status)
d03902b8
FR		 6261 pci_cmd &= ~PCI_COMMAND_PARITY;
6262 else
6263 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6264
6265 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 6266
6267 pci_write_config_word(pdev, PCI_STATUS,
6268 pci_status & (PCI_STATUS_DETECTED_PARITY |
6269 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6270 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6271
6272 /* The infamous DAC f*ckup only happens at boot time */
9fba0812 6273 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
bf82c189 6274 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4 6275 tp->cp_cmd &= ~PCIDAC;
1ef7286e 6276 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1da177e4 6277 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 6278 }
6279
e6de30d6 6280 rtl8169_hw_reset(tp);
d03902b8 6281
98ddf986 6282 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
1da177e4
LT		 6283}
6284
da78dbff 6285static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
1da177e4
LT		 6286{
6287 unsigned int dirty_tx, tx_left;
6288
1da177e4
LT		 6289 dirty_tx = tp->dirty_tx;
6290 smp_rmb();
6291 tx_left = tp->cur_tx - dirty_tx;
6292
6293 while (tx_left > 0) {
6294 unsigned int entry = dirty_tx % NUM_TX_DESC;
6295 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 6296 u32 status;
6297
1da177e4
LT		 6298 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6299 if (status & DescOwn)
6300 break;
6301
a0750138
AD		 6302 /* This barrier is needed to keep us from reading
6303 * any other fields out of the Tx descriptor until
6304 * we know the status of DescOwn
6305 */
6306 dma_rmb();
6307
1e1205b7 6308 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
48addcc9 6309 tp->TxDescArray + entry);
1da177e4 6310 if (status & LastFrag) {
87cda7cb
DM		 6311 u64_stats_update_begin(&tp->tx_stats.syncp);
6312 tp->tx_stats.packets++;
6313 tp->tx_stats.bytes += tx_skb->skb->len;
6314 u64_stats_update_end(&tp->tx_stats.syncp);
7a4b813c 6315 dev_consume_skb_any(tx_skb->skb);
1da177e4
LT		 6316 tx_skb->skb = NULL;
6317 }
6318 dirty_tx++;
6319 tx_left--;
6320 }
6321
6322 if (tp->dirty_tx != dirty_tx) {
6323 tp->dirty_tx = dirty_tx;
ae1f23fb
FR		 6324 /* Sync with rtl8169_start_xmit:
6325 * - publish dirty_tx ring index (write barrier)
6326 * - refresh cur_tx ring index and queue status (read barrier)
6327 * May the current thread miss the stopped queue condition,
6328 * a racing xmit thread can only have a right view of the
6329 * ring status.
6330 */
1e874e04 6331 smp_mb();
1da177e4 6332 if (netif_queue_stopped(dev) &&
477206a0 6333 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
1da177e4
LT		 6334 netif_wake_queue(dev);
6335 }
d78ae2dc
FR		 6336 /*
6337 * 8168 hack: TxPoll requests are lost when the Tx packets are
6338 * too close. Let's kick an extra TxPoll request when a burst
6339 * of start_xmit activity is detected (if it is not detected,
6340 * it is slow enough). -- FR
6341 */
1ef7286e
AS		 6342 if (tp->cur_tx != dirty_tx)
6343 RTL_W8(tp, TxPoll, NPQ);
1da177e4
LT		 6344 }
6345}
6346
126fa4b9
FR		 6347static inline int rtl8169_fragmented_frame(u32 status)
6348{
6349 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6350}
6351
adea1ac7 6352static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 6353{
1da177e4
LT		 6354 u32 status = opts1 & RxProtoMask;
6355
6356 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 6357 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 6358 skb->ip_summed = CHECKSUM_UNNECESSARY;
6359 else
bc8acf2c 6360 skb_checksum_none_assert(skb);
1da177e4
LT		 6361}
6362
6f0333b8
ED		 6363static struct sk_buff *rtl8169_try_rx_copy(void *data,
6364 struct rtl8169_private *tp,
6365 int pkt_size,
6366 dma_addr_t addr)
1da177e4 6367{
b449655f 6368 struct sk_buff *skb;
1e1205b7 6369 struct device *d = tp_to_dev(tp);
b449655f 6370
6f0333b8 6371 data = rtl8169_align(data);
48addcc9 6372 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8 6373 prefetch(data);
e2338f86 6374 skb = napi_alloc_skb(&tp->napi, pkt_size);
6f0333b8 6375 if (skb)
8a67aa86 6376 skb_copy_to_linear_data(skb, data, pkt_size);
48addcc9
SG		 6377 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6378
6f0333b8 6379 return skb;
1da177e4
LT		 6380}
6381
da78dbff 6382static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
1da177e4
LT		 6383{
6384 unsigned int cur_rx, rx_left;
6f0333b8 6385 unsigned int count;
1da177e4 6386
1da177e4 6387 cur_rx = tp->cur_rx;
1da177e4 6388
9fba0812 6389 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
1da177e4 6390 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 6391 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 6392 u32 status;
6393
6202806e 6394 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 6395 if (status & DescOwn)
6396 break;
a0750138
AD		 6397
6398 /* This barrier is needed to keep us from reading
6399 * any other fields out of the Rx descriptor until
6400 * we know the status of DescOwn
6401 */
6402 dma_rmb();
6403
4dcb7d33 6404 if (unlikely(status & RxRES)) {
bf82c189
JP		 6405 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6406 status);
cebf8cc7 6407 dev->stats.rx_errors++;
1da177e4 6408 if (status & (RxRWT | RxRUNT))
cebf8cc7 6409 dev->stats.rx_length_errors++;
1da177e4 6410 if (status & RxCRC)
cebf8cc7 6411 dev->stats.rx_crc_errors++;
6202806e
HK		 6412 /* RxFOVF is a reserved bit on later chip versions */
6413 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6414 status & RxFOVF) {
da78dbff 6415 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
cebf8cc7 6416 dev->stats.rx_fifo_errors++;
6202806e
HK		 6417 } else if (status & (RxRUNT | RxCRC) &&
6418 !(status & RxRWT) &&
6419 dev->features & NETIF_F_RXALL) {
6bbe021d 6420 goto process_pkt;
6202806e 6421 }
1da177e4 6422 } else {
6f0333b8 6423 struct sk_buff *skb;
6bbe021d
BG		 6424 dma_addr_t addr;
6425 int pkt_size;
6426
6427process_pkt:
6428 addr = le64_to_cpu(desc->addr);
79d0c1d2
BG		 6429 if (likely(!(dev->features & NETIF_F_RXFCS)))
6430 pkt_size = (status & 0x00003fff) - 4;
6431 else
6432 pkt_size = status & 0x00003fff;
1da177e4 6433
126fa4b9
FR		 6434 /*
6435 * The driver does not support incoming fragmented
6436 * frames. They are seen as a symptom of over-mtu
6437 * sized frames.
6438 */
6439 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 6440 dev->stats.rx_dropped++;
6441 dev->stats.rx_length_errors++;
ce11ff5e 6442 goto release_descriptor;
126fa4b9
FR		 6443 }
6444
6f0333b8
ED		 6445 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6446 tp, pkt_size, addr);
6f0333b8
ED		 6447 if (!skb) {
6448 dev->stats.rx_dropped++;
ce11ff5e 6449 goto release_descriptor;
1da177e4
LT		 6450 }
6451
adea1ac7 6452 rtl8169_rx_csum(skb, status);
1da177e4
LT		 6453 skb_put(skb, pkt_size);
6454 skb->protocol = eth_type_trans(skb, dev);
6455
7a8fc77b
FR		 6456 rtl8169_rx_vlan_tag(desc, skb);
6457
39174291 6458 if (skb->pkt_type == PACKET_MULTICAST)
6459 dev->stats.multicast++;
6460
56de414c 6461 napi_gro_receive(&tp->napi, skb);
1da177e4 6462
8027aa24
JW		 6463 u64_stats_update_begin(&tp->rx_stats.syncp);
6464 tp->rx_stats.packets++;
6465 tp->rx_stats.bytes += pkt_size;
6466 u64_stats_update_end(&tp->rx_stats.syncp);
1da177e4 6467 }
ce11ff5e 6468release_descriptor:
6469 desc->opts2 = 0;
1d0254dd 6470 rtl8169_mark_to_asic(desc);
1da177e4
LT		 6471 }
6472
6473 count = cur_rx - tp->cur_rx;
6474 tp->cur_rx = cur_rx;
6475
1da177e4
LT		 6476 return count;
6477}
6478
07d3f51f 6479static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 6480{
ebcd5daa 6481 struct rtl8169_private *tp = dev_instance;
05bbe558 6482 u16 status = rtl_get_events(tp);
1da177e4 6483
05bbe558
HK		 6484 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6485 return IRQ_NONE;
1da177e4 6486
05bbe558
HK		 6487 rtl_irq_disable(tp);
6488 napi_schedule_irqoff(&tp->napi);
6489
6490 return IRQ_HANDLED;
da78dbff 6491}
1da177e4 6492
da78dbff
FR		 6493/*
6494 * Workqueue context.
6495 */
6496static void rtl_slow_event_work(struct rtl8169_private *tp)
6497{
6498 struct net_device *dev = tp->dev;
6499 u16 status;
6500
6501 status = rtl_get_events(tp) & tp->event_slow;
6502 rtl_ack_events(tp, status);
1da177e4 6503
da78dbff
FR		 6504 if (unlikely(status & RxFIFOOver)) {
6505 switch (tp->mac_version) {
6506 /* Work around for rx fifo overflow */
6507 case RTL_GIGA_MAC_VER_11:
6508 netif_stop_queue(dev);
934714d0
FR		 6509 /* XXX - Hack alert. See rtl_task(). */
6510 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
da78dbff 6511 default:
f11a377b
DD		 6512 break;
6513 }
da78dbff 6514 }
1da177e4 6515
da78dbff
FR		 6516 if (unlikely(status & SYSErr))
6517 rtl8169_pcierr_interrupt(dev);
0e485150 6518
da78dbff 6519 if (status & LinkChg)
f1e911d5 6520 phy_mac_interrupt(dev->phydev);
1da177e4 6521
7dbb4918 6522 rtl_irq_enable_all(tp);
1da177e4
LT		 6523}
6524
4422bcd4
FR		 6525static void rtl_task(struct work_struct *work)
6526{
da78dbff
FR		 6527 static const struct {
6528 int bitnr;
6529 void (*action)(struct rtl8169_private *);
6530 } rtl_work[] = {
934714d0 6531 /* XXX - keep rtl_slow_event_work() as first element. */
da78dbff
FR		 6532 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6533 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
da78dbff 6534 };
4422bcd4
FR		 6535 struct rtl8169_private *tp =
6536 container_of(work, struct rtl8169_private, wk.work);
da78dbff
FR		 6537 struct net_device *dev = tp->dev;
6538 int i;
6539
6540 rtl_lock_work(tp);
6541
6c4a70c5
FR		 6542 if (!netif_running(dev) ||
6543 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
da78dbff
FR		 6544 goto out_unlock;
6545
6546 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6547 bool pending;
6548
da78dbff 6549 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
da78dbff
FR		 6550 if (pending)
6551 rtl_work[i].action(tp);
6552 }
4422bcd4 6553
da78dbff
FR		 6554out_unlock:
6555 rtl_unlock_work(tp);
4422bcd4
FR		 6556}
6557
bea3348e 6558static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 6559{
bea3348e
SH		 6560 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6561 struct net_device *dev = tp->dev;
da78dbff 6562 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6b839b6c 6563 int work_done;
da78dbff
FR		 6564 u16 status;
6565
6566 status = rtl_get_events(tp);
6567 rtl_ack_events(tp, status & ~tp->event_slow);
6568
6b839b6c 6569 work_done = rtl_rx(dev, tp, (u32) budget);
da78dbff 6570
6b839b6c 6571 rtl_tx(dev, tp);
1da177e4 6572
da78dbff
FR		 6573 if (status & tp->event_slow) {
6574 enable_mask &= ~tp->event_slow;
6575
6576 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6577 }
1da177e4 6578
bea3348e 6579 if (work_done < budget) {
6ad20165 6580 napi_complete_done(napi, work_done);
f11a377b 6581
da78dbff
FR		 6582 rtl_irq_enable(tp, enable_mask);
6583 mmiowb();
1da177e4
LT		 6584 }
6585
bea3348e 6586 return work_done;
1da177e4 6587}
1da177e4 6588
1ef7286e 6589static void rtl8169_rx_missed(struct net_device *dev)
523a6094
FR		 6590{
6591 struct rtl8169_private *tp = netdev_priv(dev);
6592
6593 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6594 return;
6595
1ef7286e
AS		 6596 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6597 RTL_W32(tp, RxMissed, 0);
523a6094
FR		 6598}
6599
f1e911d5
HK		 6600static void r8169_phylink_handler(struct net_device *ndev)
6601{
6602 struct rtl8169_private *tp = netdev_priv(ndev);
6603
6604 if (netif_carrier_ok(ndev)) {
6605 rtl_link_chg_patch(tp);
6606 pm_request_resume(&tp->pci_dev->dev);
6607 } else {
6608 pm_runtime_idle(&tp->pci_dev->dev);
6609 }
6610
6611 if (net_ratelimit())
6612 phy_print_status(ndev->phydev);
6613}
6614
6615static int r8169_phy_connect(struct rtl8169_private *tp)
6616{
6617 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6618 phy_interface_t phy_mode;
6619 int ret;
6620
f7ffa9ae 6621 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
f1e911d5
HK		 6622 PHY_INTERFACE_MODE_MII;
6623
6624 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6625 phy_mode);
6626 if (ret)
6627 return ret;
6628
f7ffa9ae 6629 if (!tp->supports_gmii)
f1e911d5
HK		 6630 phy_set_max_speed(phydev, SPEED_100);
6631
6632 /* Ensure to advertise everything, incl. pause */
6633 phydev->advertising = phydev->supported;
6634
6635 phy_attached_info(phydev);
6636
6637 return 0;
6638}
6639
1da177e4
LT		 6640static void rtl8169_down(struct net_device *dev)
6641{
6642 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 6643
f1e911d5
HK		 6644 phy_stop(dev->phydev);
6645
93dd79e8 6646 napi_disable(&tp->napi);
da78dbff 6647 netif_stop_queue(dev);
1da177e4 6648
92fc43b4 6649 rtl8169_hw_reset(tp);
323bb685
SG		 6650 /*
6651 * At this point device interrupts can not be enabled in any function,
209e5ac8
FR		 6652 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6653 * and napi is disabled (rtl8169_poll).
323bb685 6654 */
1ef7286e 6655 rtl8169_rx_missed(dev);
1da177e4 6656
1da177e4 6657 /* Give a racing hard_start_xmit a few cycles to complete. */
da78dbff 6658 synchronize_sched();
1da177e4 6659
1da177e4
LT		 6660 rtl8169_tx_clear(tp);
6661
6662 rtl8169_rx_clear(tp);
065c27c1 6663
6664 rtl_pll_power_down(tp);
1da177e4
LT		 6665}
6666
6667static int rtl8169_close(struct net_device *dev)
6668{
6669 struct rtl8169_private *tp = netdev_priv(dev);
6670 struct pci_dev *pdev = tp->pci_dev;
6671
e1759441
RW		 6672 pm_runtime_get_sync(&pdev->dev);
6673
cecb5fd7 6674 /* Update counters before going down */
e71c9ce2 6675 rtl8169_update_counters(tp);
355423d0 6676
da78dbff 6677 rtl_lock_work(tp);
6ad56901
KHF		 6678 /* Clear all task flags */
6679 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
da78dbff 6680
1da177e4 6681 rtl8169_down(dev);
da78dbff 6682 rtl_unlock_work(tp);
1da177e4 6683
4ea72445
L		 6684 cancel_work_sync(&tp->wk.work);
6685
f1e911d5
HK		 6686 phy_disconnect(dev->phydev);
6687
ebcd5daa 6688 pci_free_irq(pdev, 0, tp);
1da177e4 6689
82553bb6
SG		 6690 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6691 tp->RxPhyAddr);
6692 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6693 tp->TxPhyAddr);
1da177e4
LT		 6694 tp->TxDescArray = NULL;
6695 tp->RxDescArray = NULL;
6696
e1759441
RW		 6697 pm_runtime_put_sync(&pdev->dev);
6698
1da177e4
LT		 6699 return 0;
6700}
6701
dc1c00ce
FR		 6702#ifdef CONFIG_NET_POLL_CONTROLLER
6703static void rtl8169_netpoll(struct net_device *dev)
6704{
6705 struct rtl8169_private *tp = netdev_priv(dev);
6706
6d8b8349 6707 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
dc1c00ce
FR		 6708}
6709#endif
6710
df43ac78
FR		 6711static int rtl_open(struct net_device *dev)
6712{
6713 struct rtl8169_private *tp = netdev_priv(dev);
df43ac78
FR		 6714 struct pci_dev *pdev = tp->pci_dev;
6715 int retval = -ENOMEM;
6716
6717 pm_runtime_get_sync(&pdev->dev);
6718
6719 /*
e75d6606 6720 * Rx and Tx descriptors needs 256 bytes alignment.
df43ac78
FR		 6721 * dma_alloc_coherent provides more.
6722 */
6723 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6724 &tp->TxPhyAddr, GFP_KERNEL);
6725 if (!tp->TxDescArray)
6726 goto err_pm_runtime_put;
6727
6728 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6729 &tp->RxPhyAddr, GFP_KERNEL);
6730 if (!tp->RxDescArray)
6731 goto err_free_tx_0;
6732
b1127e64 6733 retval = rtl8169_init_ring(tp);
df43ac78
FR		 6734 if (retval < 0)
6735 goto err_free_rx_1;
6736
6737 INIT_WORK(&tp->wk.work, rtl_task);
6738
6739 smp_mb();
6740
6741 rtl_request_firmware(tp);
6742
ebcd5daa 6743 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6c6aa15f 6744 dev->name);
df43ac78
FR		 6745 if (retval < 0)
6746 goto err_release_fw_2;
6747
f1e911d5
HK		 6748 retval = r8169_phy_connect(tp);
6749 if (retval)
6750 goto err_free_irq;
6751
df43ac78
FR		 6752 rtl_lock_work(tp);
6753
6754 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6755
6756 napi_enable(&tp->napi);
6757
6758 rtl8169_init_phy(dev, tp);
6759
df43ac78
FR		 6760 rtl_pll_power_up(tp);
6761
61cb532d 6762 rtl_hw_start(tp);
df43ac78 6763
e71c9ce2 6764 if (!rtl8169_init_counter_offsets(tp))
6e85d5ad
CV		 6765 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6766
f1e911d5 6767 phy_start(dev->phydev);
df43ac78
FR		 6768 netif_start_queue(dev);
6769
6770 rtl_unlock_work(tp);
6771
a92a0849 6772 pm_runtime_put_sync(&pdev->dev);
df43ac78
FR		 6773out:
6774 return retval;
6775
f1e911d5
HK		 6776err_free_irq:
6777 pci_free_irq(pdev, 0, tp);
df43ac78
FR		 6778err_release_fw_2:
6779 rtl_release_firmware(tp);
6780 rtl8169_rx_clear(tp);
6781err_free_rx_1:
6782 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6783 tp->RxPhyAddr);
6784 tp->RxDescArray = NULL;
6785err_free_tx_0:
6786 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6787 tp->TxPhyAddr);
6788 tp->TxDescArray = NULL;
6789err_pm_runtime_put:
6790 pm_runtime_put_noidle(&pdev->dev);
6791 goto out;
6792}
6793
bc1f4470 6794static void
8027aa24 6795rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
1da177e4
LT		 6796{
6797 struct rtl8169_private *tp = netdev_priv(dev);
f09cf4b7 6798 struct pci_dev *pdev = tp->pci_dev;
42020320 6799 struct rtl8169_counters *counters = tp->counters;
8027aa24 6800 unsigned int start;
1da177e4 6801
f09cf4b7
CHL		 6802 pm_runtime_get_noresume(&pdev->dev);
6803
6804 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
1ef7286e 6805 rtl8169_rx_missed(dev);
5b0384f4 6806
8027aa24 6807 do {
57a7744e 6808 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
8027aa24
JW		 6809 stats->rx_packets = tp->rx_stats.packets;
6810 stats->rx_bytes = tp->rx_stats.bytes;
57a7744e 6811 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
8027aa24 6812
8027aa24 6813 do {
57a7744e 6814 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
8027aa24
JW		 6815 stats->tx_packets = tp->tx_stats.packets;
6816 stats->tx_bytes = tp->tx_stats.bytes;
57a7744e 6817 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
8027aa24
JW		 6818
6819 stats->rx_dropped = dev->stats.rx_dropped;
6820 stats->tx_dropped = dev->stats.tx_dropped;
6821 stats->rx_length_errors = dev->stats.rx_length_errors;
6822 stats->rx_errors = dev->stats.rx_errors;
6823 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6824 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6825 stats->rx_missed_errors = dev->stats.rx_missed_errors;
d7d2d89d 6826 stats->multicast = dev->stats.multicast;
8027aa24 6827
6e85d5ad
CV		 6828 /*
6829 * Fetch additonal counter values missing in stats collected by driver
6830 * from tally counters.
6831 */
f09cf4b7 6832 if (pm_runtime_active(&pdev->dev))
e71c9ce2 6833 rtl8169_update_counters(tp);
6e85d5ad
CV		 6834
6835 /*
6836 * Subtract values fetched during initalization.
6837 * See rtl8169_init_counter_offsets for a description why we do that.
6838 */
42020320 6839 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6e85d5ad 6840 le64_to_cpu(tp->tc_offset.tx_errors);
42020320 6841 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6e85d5ad 6842 le32_to_cpu(tp->tc_offset.tx_multi_collision);
42020320 6843 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6e85d5ad
CV		 6844 le16_to_cpu(tp->tc_offset.tx_aborted);
6845
f09cf4b7 6846 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 6847}
6848
861ab440 6849static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 6850{
065c27c1 6851 struct rtl8169_private *tp = netdev_priv(dev);
6852
5d06a99f 6853 if (!netif_running(dev))
861ab440 6854 return;
5d06a99f 6855
f1e911d5 6856 phy_stop(dev->phydev);
5d06a99f
FR		 6857 netif_device_detach(dev);
6858 netif_stop_queue(dev);
da78dbff
FR		 6859
6860 rtl_lock_work(tp);
6861 napi_disable(&tp->napi);
6ad56901
KHF		 6862 /* Clear all task flags */
6863 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6864
da78dbff
FR		 6865 rtl_unlock_work(tp);
6866
6867 rtl_pll_power_down(tp);
861ab440
RW		 6868}
6869
6870#ifdef CONFIG_PM
6871
6872static int rtl8169_suspend(struct device *device)
6873{
6874 struct pci_dev *pdev = to_pci_dev(device);
6875 struct net_device *dev = pci_get_drvdata(pdev);
ac8bd9e1 6876 struct rtl8169_private *tp = netdev_priv(dev);
5d06a99f 6877
861ab440 6878 rtl8169_net_suspend(dev);
ac8bd9e1 6879 clk_disable_unprepare(tp->clk);
1371fa6d 6880
5d06a99f
FR		 6881 return 0;
6882}
6883
e1759441
RW		 6884static void __rtl8169_resume(struct net_device *dev)
6885{
065c27c1 6886 struct rtl8169_private *tp = netdev_priv(dev);
6887
e1759441 6888 netif_device_attach(dev);
065c27c1 6889
6890 rtl_pll_power_up(tp);
92bad850 6891 rtl8169_init_phy(dev, tp);
065c27c1 6892
f1e911d5
HK		 6893 phy_start(tp->dev->phydev);
6894
cff4c162
AS		 6895 rtl_lock_work(tp);
6896 napi_enable(&tp->napi);
6c4a70c5 6897 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
cff4c162 6898 rtl_unlock_work(tp);
da78dbff 6899
98ddf986 6900 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
e1759441
RW		 6901}
6902
861ab440 6903static int rtl8169_resume(struct device *device)
5d06a99f 6904{
861ab440 6905 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 6906 struct net_device *dev = pci_get_drvdata(pdev);
ac8bd9e1
HG		 6907 struct rtl8169_private *tp = netdev_priv(dev);
6908
6909 clk_prepare_enable(tp->clk);
5d06a99f 6910
e1759441
RW		 6911 if (netif_running(dev))
6912 __rtl8169_resume(dev);
5d06a99f 6913
e1759441
RW		 6914 return 0;
6915}
6916
6917static int rtl8169_runtime_suspend(struct device *device)
6918{
6919 struct pci_dev *pdev = to_pci_dev(device);
6920 struct net_device *dev = pci_get_drvdata(pdev);
6921 struct rtl8169_private *tp = netdev_priv(dev);
6922
07df5bd8 6923 if (!tp->TxDescArray)
e1759441
RW		 6924 return 0;
6925
da78dbff 6926 rtl_lock_work(tp);
e1759441 6927 __rtl8169_set_wol(tp, WAKE_ANY);
da78dbff 6928 rtl_unlock_work(tp);
e1759441
RW		 6929
6930 rtl8169_net_suspend(dev);
6931
f09cf4b7 6932 /* Update counters before going runtime suspend */
1ef7286e 6933 rtl8169_rx_missed(dev);
e71c9ce2 6934 rtl8169_update_counters(tp);
f09cf4b7 6935
e1759441
RW		 6936 return 0;
6937}
6938
6939static int rtl8169_runtime_resume(struct device *device)
6940{
6941 struct pci_dev *pdev = to_pci_dev(device);
6942 struct net_device *dev = pci_get_drvdata(pdev);
6943 struct rtl8169_private *tp = netdev_priv(dev);
f51d4a10 6944 rtl_rar_set(tp, dev->dev_addr);
e1759441
RW		 6945
6946 if (!tp->TxDescArray)
6947 return 0;
6948
da78dbff 6949 rtl_lock_work(tp);
e1759441 6950 __rtl8169_set_wol(tp, tp->saved_wolopts);
da78dbff 6951 rtl_unlock_work(tp);
e1759441
RW		 6952
6953 __rtl8169_resume(dev);
5d06a99f 6954
5d06a99f
FR		 6955 return 0;
6956}
6957
e1759441
RW		 6958static int rtl8169_runtime_idle(struct device *device)
6959{
6960 struct pci_dev *pdev = to_pci_dev(device);
6961 struct net_device *dev = pci_get_drvdata(pdev);
e1759441 6962
a92a0849
HK		 6963 if (!netif_running(dev) || !netif_carrier_ok(dev))
6964 pm_schedule_suspend(device, 10000);
6965
6966 return -EBUSY;
e1759441
RW		 6967}
6968
47145210 6969static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 6970 .suspend = rtl8169_suspend,
6971 .resume = rtl8169_resume,
6972 .freeze = rtl8169_suspend,
6973 .thaw = rtl8169_resume,
6974 .poweroff = rtl8169_suspend,
6975 .restore = rtl8169_resume,
6976 .runtime_suspend = rtl8169_runtime_suspend,
6977 .runtime_resume = rtl8169_runtime_resume,
6978 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 6979};
6980
6981#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6982
6983#else /* !CONFIG_PM */
6984
6985#define RTL8169_PM_OPS NULL
6986
6987#endif /* !CONFIG_PM */
6988
649b3b8c 6989static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6990{
649b3b8c 6991 /* WoL fails with 8168b when the receiver is disabled. */
6992 switch (tp->mac_version) {
6993 case RTL_GIGA_MAC_VER_11:
6994 case RTL_GIGA_MAC_VER_12:
6995 case RTL_GIGA_MAC_VER_17:
6996 pci_clear_master(tp->pci_dev);
6997
1ef7286e 6998 RTL_W8(tp, ChipCmd, CmdRxEnb);
649b3b8c 6999 /* PCI commit */
1ef7286e 7000 RTL_R8(tp, ChipCmd);
649b3b8c 7001 break;
7002 default:
7003 break;
7004 }
7005}
7006
1765f95d
FR		 7007static void rtl_shutdown(struct pci_dev *pdev)
7008{
861ab440 7009 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 7010 struct rtl8169_private *tp = netdev_priv(dev);
861ab440
RW		 7011
7012 rtl8169_net_suspend(dev);
1765f95d 7013
cecb5fd7 7014 /* Restore original MAC address */
cc098dc7
IV		 7015 rtl_rar_set(tp, dev->perm_addr);
7016
92fc43b4 7017 rtl8169_hw_reset(tp);
4bb3f522 7018
861ab440 7019 if (system_state == SYSTEM_POWER_OFF) {
433f9d0d 7020 if (tp->saved_wolopts) {
649b3b8c 7021 rtl_wol_suspend_quirk(tp);
7022 rtl_wol_shutdown_quirk(tp);
ca52efd5 7023 }
7024
861ab440
RW		 7025 pci_wake_from_d3(pdev, true);
7026 pci_set_power_state(pdev, PCI_D3hot);
7027 }
7028}
5d06a99f 7029
baf63293 7030static void rtl_remove_one(struct pci_dev *pdev)
e27566ed
FR		 7031{
7032 struct net_device *dev = pci_get_drvdata(pdev);
7033 struct rtl8169_private *tp = netdev_priv(dev);
7034
9dbe7896 7035 if (r8168_check_dash(tp))
e27566ed 7036 rtl8168_driver_stop(tp);
e27566ed 7037
ad1be8d3
DN		 7038 netif_napi_del(&tp->napi);
7039
e27566ed 7040 unregister_netdev(dev);
f1e911d5 7041 mdiobus_unregister(tp->mii_bus);
e27566ed
FR		 7042
7043 rtl_release_firmware(tp);
7044
7045 if (pci_dev_run_wake(pdev))
7046 pm_runtime_get_noresume(&pdev->dev);
7047
7048 /* restore original MAC address */
7049 rtl_rar_set(tp, dev->perm_addr);
e27566ed
FR		 7050}
7051
fa9c385e 7052static const struct net_device_ops rtl_netdev_ops = {
df43ac78 7053 .ndo_open = rtl_open,
fa9c385e
FR		 7054 .ndo_stop = rtl8169_close,
7055 .ndo_get_stats64 = rtl8169_get_stats64,
7056 .ndo_start_xmit = rtl8169_start_xmit,
7057 .ndo_tx_timeout = rtl8169_tx_timeout,
7058 .ndo_validate_addr = eth_validate_addr,
7059 .ndo_change_mtu = rtl8169_change_mtu,
7060 .ndo_fix_features = rtl8169_fix_features,
7061 .ndo_set_features = rtl8169_set_features,
7062 .ndo_set_mac_address = rtl_set_mac_address,
7063 .ndo_do_ioctl = rtl8169_ioctl,
7064 .ndo_set_rx_mode = rtl_set_rx_mode,
7065#ifdef CONFIG_NET_POLL_CONTROLLER
7066 .ndo_poll_controller = rtl8169_netpoll,
7067#endif
7068
7069};
7070
31fa8b18 7071static const struct rtl_cfg_info {
61cb532d 7072 void (*hw_start)(struct rtl8169_private *tp);
31fa8b18 7073 u16 event_slow;
14967f94 7074 unsigned int has_gmii:1;
50970831 7075 const struct rtl_coalesce_info *coalesce_info;
31fa8b18
FR		 7076 u8 default_ver;
7077} rtl_cfg_infos [] = {
7078 [RTL_CFG_0] = {
7079 .hw_start = rtl_hw_start_8169,
31fa8b18 7080 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
14967f94 7081 .has_gmii = 1,
50970831 7082 .coalesce_info = rtl_coalesce_info_8169,
31fa8b18
FR		 7083 .default_ver = RTL_GIGA_MAC_VER_01,
7084 },
7085 [RTL_CFG_1] = {
7086 .hw_start = rtl_hw_start_8168,
31fa8b18 7087 .event_slow = SYSErr | LinkChg | RxOverflow,
14967f94 7088 .has_gmii = 1,
50970831 7089 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7090 .default_ver = RTL_GIGA_MAC_VER_11,
7091 },
7092 [RTL_CFG_2] = {
7093 .hw_start = rtl_hw_start_8101,
31fa8b18
FR		 7094 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7095 PCSTimeout,
50970831 7096 .coalesce_info = rtl_coalesce_info_8168_8136,
31fa8b18
FR		 7097 .default_ver = RTL_GIGA_MAC_VER_13,
7098 }
7099};
7100
6c6aa15f 7101static int rtl_alloc_irq(struct rtl8169_private *tp)
31fa8b18 7102{
6c6aa15f 7103 unsigned int flags;
31fa8b18 7104
d49c88d7 7105 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1ef7286e
AS		 7106 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7107 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7108 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
6c6aa15f 7109 flags = PCI_IRQ_LEGACY;
d49c88d7 7110 } else {
6c6aa15f 7111 flags = PCI_IRQ_ALL_TYPES;
31fa8b18 7112 }
6c6aa15f
HK		 7113
7114 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
31fa8b18
FR		 7115}
7116
c558386b
HW		 7117DECLARE_RTL_COND(rtl_link_list_ready_cond)
7118{
1ef7286e 7119 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
c558386b
HW		 7120}
7121
7122DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7123{
1ef7286e 7124 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
c558386b
HW		 7125}
7126
f1e911d5
HK		 7127static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7128{
7129 struct rtl8169_private *tp = mii_bus->priv;
7130
7131 if (phyaddr > 0)
7132 return -ENODEV;
7133
7134 return rtl_readphy(tp, phyreg);
7135}
7136
7137static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7138 int phyreg, u16 val)
7139{
7140 struct rtl8169_private *tp = mii_bus->priv;
7141
7142 if (phyaddr > 0)
7143 return -ENODEV;
7144
7145 rtl_writephy(tp, phyreg, val);
7146
7147 return 0;
7148}
7149
7150static int r8169_mdio_register(struct rtl8169_private *tp)
7151{
7152 struct pci_dev *pdev = tp->pci_dev;
7153 struct phy_device *phydev;
7154 struct mii_bus *new_bus;
7155 int ret;
7156
7157 new_bus = devm_mdiobus_alloc(&pdev->dev);
7158 if (!new_bus)
7159 return -ENOMEM;
7160
7161 new_bus->name = "r8169";
7162 new_bus->priv = tp;
7163 new_bus->parent = &pdev->dev;
7164 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7165 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7166 PCI_DEVID(pdev->bus->number, pdev->devfn));
7167
7168 new_bus->read = r8169_mdio_read_reg;
7169 new_bus->write = r8169_mdio_write_reg;
7170
7171 ret = mdiobus_register(new_bus);
7172 if (ret)
7173 return ret;
7174
7175 phydev = mdiobus_get_phy(new_bus, 0);
7176 if (!phydev) {
7177 mdiobus_unregister(new_bus);
7178 return -ENODEV;
7179 }
7180
242cd9b5
HK		 7181 /* PHY will be woken up in rtl_open() */
7182 phy_suspend(phydev);
7183
f1e911d5
HK		 7184 tp->mii_bus = new_bus;
7185
7186 return 0;
7187}
7188
baf63293 7189static void rtl_hw_init_8168g(struct rtl8169_private *tp)
c558386b 7190{
c558386b
HW		 7191 u32 data;
7192
7193 tp->ocp_base = OCP_STD_PHY_BASE;
7194
1ef7286e 7195 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
c558386b
HW		 7196
7197 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7198 return;
7199
7200 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7201 return;
7202
1ef7286e 7203 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
c558386b 7204 msleep(1);
1ef7286e 7205 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
c558386b 7206
5f8bcce9 7207 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7208 data &= ~(1 << 14);
7209 r8168_mac_ocp_write(tp, 0xe8de, data);
7210
7211 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7212 return;
7213
5f8bcce9 7214 data = r8168_mac_ocp_read(tp, 0xe8de);
c558386b
HW		 7215 data |= (1 << 15);
7216 r8168_mac_ocp_write(tp, 0xe8de, data);
7217
7218 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7219 return;
7220}
7221
003609da
CHL		 7222static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7223{
7224 rtl8168ep_stop_cmac(tp);
7225 rtl_hw_init_8168g(tp);
7226}
7227
baf63293 7228static void rtl_hw_initialize(struct rtl8169_private *tp)
c558386b
HW		 7229{
7230 switch (tp->mac_version) {
2a71883c 7231 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
003609da
CHL		 7232 rtl_hw_init_8168g(tp);
7233 break;
2a71883c 7234 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
003609da 7235 rtl_hw_init_8168ep(tp);
c558386b 7236 break;
c558386b
HW		 7237 default:
7238 break;
7239 }
7240}
7241
eb88f5f7
HK		 7242/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7243static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7244{
7245 switch (tp->mac_version) {
7246 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7247 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7248 return false;
7249 default:
7250 return true;
7251 }
7252}
7253
abe8b2f7
HK		 7254static int rtl_jumbo_max(struct rtl8169_private *tp)
7255{
7256 /* Non-GBit versions don't support jumbo frames */
7257 if (!tp->supports_gmii)
7258 return JUMBO_1K;
7259
7260 switch (tp->mac_version) {
7261 /* RTL8169 */
7262 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7263 return JUMBO_7K;
7264 /* RTL8168b */
7265 case RTL_GIGA_MAC_VER_11:
7266 case RTL_GIGA_MAC_VER_12:
7267 case RTL_GIGA_MAC_VER_17:
7268 return JUMBO_4K;
7269 /* RTL8168c */
7270 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7271 return JUMBO_6K;
7272 default:
7273 return JUMBO_9K;
7274 }
7275}
7276
c2f6f3ee
HG		 7277static void rtl_disable_clk(void *data)
7278{
7279 clk_disable_unprepare(data);
7280}
7281
929a031d 7282static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3b6cf25d
FR		 7283{
7284 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3b6cf25d 7285 struct rtl8169_private *tp;
3b6cf25d 7286 struct net_device *dev;
c8d48d9c 7287 int chipset, region, i;
abe8b2f7 7288 int jumbo_max, rc;
3b6cf25d 7289
4c45d24a
HK		 7290 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7291 if (!dev)
7292 return -ENOMEM;
3b6cf25d
FR		 7293
7294 SET_NETDEV_DEV(dev, &pdev->dev);
fa9c385e 7295 dev->netdev_ops = &rtl_netdev_ops;
3b6cf25d
FR		 7296 tp = netdev_priv(dev);
7297 tp->dev = dev;
7298 tp->pci_dev = pdev;
7299 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
f7ffa9ae 7300 tp->supports_gmii = cfg->has_gmii;
3b6cf25d 7301
c2f6f3ee
HG		 7302 /* Get the *optional* external "ether_clk" used on some boards */
7303 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7304 if (IS_ERR(tp->clk)) {
7305 rc = PTR_ERR(tp->clk);
7306 if (rc == -ENOENT) {
7307 /* clk-core allows NULL (for suspend / resume) */
7308 tp->clk = NULL;
7309 } else if (rc == -EPROBE_DEFER) {
7310 return rc;
7311 } else {
7312 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7313 return rc;
7314 }
7315 } else {
7316 rc = clk_prepare_enable(tp->clk);
7317 if (rc) {
7318 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7319 return rc;
7320 }
7321
7322 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7323 tp->clk);
7324 if (rc)
7325 return rc;
7326 }
7327
1e4a7e78
HK		 7328 /* Disable ASPM completely as that cause random device stop working
7329 * problems as well as full system hangs for some PCIe devices users.
7330 */
7331 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7332
3b6cf25d 7333 /* enable device (incl. PCI PM wakeup and hotplug setup) */
4c45d24a 7334 rc = pcim_enable_device(pdev);
3b6cf25d 7335 if (rc < 0) {
22148df0 7336 dev_err(&pdev->dev, "enable failure\n");
4c45d24a 7337 return rc;
3b6cf25d
FR		 7338 }
7339
4c45d24a 7340 if (pcim_set_mwi(pdev) < 0)
22148df0 7341 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
3b6cf25d 7342
c8d48d9c
HK		 7343 /* use first MMIO region */
7344 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7345 if (region < 0) {
22148df0 7346 dev_err(&pdev->dev, "no MMIO resource found\n");
4c45d24a 7347 return -ENODEV;
3b6cf25d
FR		 7348 }
7349
7350 /* check for weird/broken PCI region reporting */
7351 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
22148df0 7352 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
4c45d24a 7353 return -ENODEV;
3b6cf25d
FR		 7354 }
7355
93a00d4d 7356 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
3b6cf25d 7357 if (rc < 0) {
22148df0 7358 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
4c45d24a 7359 return rc;
3b6cf25d
FR		 7360 }
7361
93a00d4d 7362 tp->mmio_addr = pcim_iomap_table(pdev)[region];
3b6cf25d
FR		 7363
7364 if (!pci_is_pcie(pdev))
22148df0 7365 dev_info(&pdev->dev, "not PCI Express\n");
3b6cf25d
FR		 7366
7367 /* Identify chip attached to board */
22148df0 7368 rtl8169_get_mac_version(tp, cfg->default_ver);
3b6cf25d 7369
e397286b
HK		 7370 if (rtl_tbi_enabled(tp)) {
7371 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7372 return -ENODEV;
7373 }
7374
0ae0974e 7375 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
27896c83
AB		 7376
7377 if ((sizeof(dma_addr_t) > 4) &&
7378 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7379 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
f0076436
AB		 7380 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7381 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
27896c83
AB		 7382
7383 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7384 if (!pci_is_pcie(pdev))
7385 tp->cp_cmd |= PCIDAC;
7386 dev->features |= NETIF_F_HIGHDMA;
7387 } else {
7388 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7389 if (rc < 0) {
22148df0 7390 dev_err(&pdev->dev, "DMA configuration failed\n");
4c45d24a 7391 return rc;
27896c83
AB		 7392 }
7393 }
7394
3b6cf25d
FR		 7395 rtl_init_rxcfg(tp);
7396
7397 rtl_irq_disable(tp);
7398
c558386b
HW		 7399 rtl_hw_initialize(tp);
7400
3b6cf25d
FR		 7401 rtl_hw_reset(tp);
7402
7403 rtl_ack_events(tp, 0xffff);
7404
7405 pci_set_master(pdev);
7406
3b6cf25d 7407 rtl_init_mdio_ops(tp);
3b6cf25d
FR		 7408 rtl_init_jumbo_ops(tp);
7409
7410 rtl8169_print_mac_version(tp);
7411
7412 chipset = tp->mac_version;
3b6cf25d 7413
6c6aa15f
HK		 7414 rc = rtl_alloc_irq(tp);
7415 if (rc < 0) {
22148df0 7416 dev_err(&pdev->dev, "Can't allocate interrupt\n");
6c6aa15f
HK		 7417 return rc;
7418 }
3b6cf25d 7419
18041b52 7420 tp->saved_wolopts = __rtl8169_get_wol(tp);
7edf6d31 7421
3b6cf25d 7422 mutex_init(&tp->wk.mutex);
340fea3d
KM		 7423 u64_stats_init(&tp->rx_stats.syncp);
7424 u64_stats_init(&tp->tx_stats.syncp);
3b6cf25d
FR		 7425
7426 /* Get MAC address */
b2d43e6e 7427 switch (tp->mac_version) {
353af85e 7428 u8 mac_addr[ETH_ALEN] __aligned(4);
b2d43e6e
HK		 7429 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7430 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
05b9687b 7431 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
353af85e 7432 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
6e1d0b89 7433
353af85e
HK		 7434 if (is_valid_ether_addr(mac_addr))
7435 rtl_rar_set(tp, mac_addr);
b2d43e6e
HK		 7436 break;
7437 default:
7438 break;
6e1d0b89 7439 }
3b6cf25d 7440 for (i = 0; i < ETH_ALEN; i++)
1ef7286e 7441 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
3b6cf25d 7442
7ad24ea4 7443 dev->ethtool_ops = &rtl8169_ethtool_ops;
3b6cf25d 7444 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3b6cf25d 7445
37621493 7446 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
3b6cf25d
FR		 7447
7448 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7449 * properly for all devices */
7450 dev->features |= NETIF_F_RXCSUM |
f646968f 7451 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7452
7453 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
f646968f
PM		 7454 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7455 NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d
FR		 7456 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7457 NETIF_F_HIGHDMA;
2d0ec544 7458 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
3b6cf25d 7459
929a031d 7460 tp->cp_cmd |= RxChkSum | RxVlan;
7461
7462 /*
7463 * Pretend we are using VLANs; This bypasses a nasty bug where
7464 * Interrupts stop flowing on high load on 8110SCd controllers.
7465 */
3b6cf25d 7466 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
929a031d 7467 /* Disallow toggling */
f646968f 7468 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3b6cf25d 7469
eb88f5f7 7470 if (rtl_chip_supports_csum_v2(tp)) {
5888d3fc 7471 tp->tso_csum = rtl8169_tso_csum_v2;
e974604b 7472 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
eb88f5f7
HK		 7473 } else {
7474 tp->tso_csum = rtl8169_tso_csum_v1;
a4328ddb 7475 }
5888d3fc 7476
3b6cf25d
FR		 7477 dev->hw_features |= NETIF_F_RXALL;
7478 dev->hw_features |= NETIF_F_RXFCS;
7479
c7315a95
JW		 7480 /* MTU range: 60 - hw-specific max */
7481 dev->min_mtu = ETH_ZLEN;
abe8b2f7
HK		 7482 jumbo_max = rtl_jumbo_max(tp);
7483 dev->max_mtu = jumbo_max;
c7315a95 7484
3b6cf25d
FR		 7485 tp->hw_start = cfg->hw_start;
7486 tp->event_slow = cfg->event_slow;
50970831 7487 tp->coalesce_info = cfg->coalesce_info;
3b6cf25d 7488
3b6cf25d
FR		 7489 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7490
4c45d24a
HK		 7491 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7492 &tp->counters_phys_addr,
7493 GFP_KERNEL);
4cf964af
HK		 7494 if (!tp->counters)
7495 return -ENOMEM;
42020320 7496
19c9ea36
HK		 7497 pci_set_drvdata(pdev, dev);
7498
f1e911d5
HK		 7499 rc = r8169_mdio_register(tp);
7500 if (rc)
4cf964af 7501 return rc;
3b6cf25d 7502
07df5bd8
HK		 7503 /* chip gets powered up in rtl_open() */
7504 rtl_pll_power_down(tp);
7505
f1e911d5
HK		 7506 rc = register_netdev(dev);
7507 if (rc)
7508 goto err_mdio_unregister;
7509
2d6c5a61
HK		 7510 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7511 rtl_chip_infos[chipset].name, dev->dev_addr,
90b989c5 7512 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
29274991 7513 pci_irq_vector(pdev, 0));
abe8b2f7
HK		 7514
7515 if (jumbo_max > JUMBO_1K)
7516 netif_info(tp, probe, dev,
7517 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7518 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7519 "ok" : "ko");
3b6cf25d 7520
9dbe7896 7521 if (r8168_check_dash(tp))
3b6cf25d 7522 rtl8168_driver_start(tp);
3b6cf25d 7523
a92a0849
HK		 7524 if (pci_dev_run_wake(pdev))
7525 pm_runtime_put_sync(&pdev->dev);
7526
4c45d24a 7527 return 0;
f1e911d5
HK		 7528
7529err_mdio_unregister:
7530 mdiobus_unregister(tp->mii_bus);
7531 return rc;
3b6cf25d
FR		 7532}
7533
1da177e4
LT		 7534static struct pci_driver rtl8169_pci_driver = {
7535 .name = MODULENAME,
7536 .id_table = rtl8169_pci_tbl,
3b6cf25d 7537 .probe = rtl_init_one,
baf63293 7538 .remove = rtl_remove_one,
1765f95d 7539 .shutdown = rtl_shutdown,
861ab440 7540 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 7541};
7542
3eeb7da9 7543module_pci_driver(rtl8169_pci_driver);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git