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1 | /* This program is free software; you can redistribute it and/or modify |
2 | * it under the terms of the GNU General Public License as published by | |
3 | * the Free Software Foundation; version 2 of the License | |
4 | * | |
5 | * This program is distributed in the hope that it will be useful, | |
6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
8 | * GNU General Public License for more details. | |
9 | * | |
10 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> | |
11 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> | |
12 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> | |
13 | */ | |
14 | ||
15 | #ifndef MTK_ETH_H | |
16 | #define MTK_ETH_H | |
17 | ||
18 | #include <linux/mii.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/netdevice.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/phy.h> | |
23 | #include <linux/ethtool.h> | |
24 | #include <linux/version.h> | |
25 | #include <linux/atomic.h> | |
26 | ||
27 | /* these registers have different offsets depending on the SoC. we use a lookup | |
28 | * table for these | |
29 | */ | |
30 | enum mtk_reg { | |
31 | MTK_REG_PDMA_GLO_CFG = 0, | |
32 | MTK_REG_PDMA_RST_CFG, | |
33 | MTK_REG_DLY_INT_CFG, | |
34 | MTK_REG_TX_BASE_PTR0, | |
35 | MTK_REG_TX_MAX_CNT0, | |
36 | MTK_REG_TX_CTX_IDX0, | |
37 | MTK_REG_TX_DTX_IDX0, | |
38 | MTK_REG_RX_BASE_PTR0, | |
39 | MTK_REG_RX_MAX_CNT0, | |
40 | MTK_REG_RX_CALC_IDX0, | |
41 | MTK_REG_RX_DRX_IDX0, | |
42 | MTK_REG_MTK_INT_ENABLE, | |
43 | MTK_REG_MTK_INT_STATUS, | |
44 | MTK_REG_MTK_DMA_VID_BASE, | |
45 | MTK_REG_MTK_COUNTER_BASE, | |
46 | MTK_REG_MTK_RST_GL, | |
47 | MTK_REG_MTK_INT_STATUS2, | |
48 | MTK_REG_COUNT | |
49 | }; | |
50 | ||
51 | /* delayed interrupt bits */ | |
52 | #define MTK_DELAY_EN_INT 0x80 | |
53 | #define MTK_DELAY_MAX_INT 0x04 | |
54 | #define MTK_DELAY_MAX_TOUT 0x04 | |
55 | #define MTK_DELAY_TIME 20 | |
56 | #define MTK_DELAY_CHAN (((MTK_DELAY_EN_INT | MTK_DELAY_MAX_INT) << 8) \ | |
57 | | MTK_DELAY_MAX_TOUT) | |
58 | #define MTK_DELAY_INIT ((MTK_DELAY_CHAN << 16) | MTK_DELAY_CHAN) | |
59 | #define MTK_PSE_FQFC_CFG_INIT 0x80504000 | |
60 | #define MTK_PSE_FQFC_CFG_256Q 0xff908000 | |
61 | ||
62 | /* interrupt bits */ | |
63 | #define MTK_CNT_PPE_AF BIT(31) | |
64 | #define MTK_CNT_GDM_AF BIT(29) | |
65 | #define MTK_PSE_P2_FC BIT(26) | |
66 | #define MTK_PSE_BUF_DROP BIT(24) | |
67 | #define MTK_GDM_OTHER_DROP BIT(23) | |
68 | #define MTK_PSE_P1_FC BIT(22) | |
69 | #define MTK_PSE_P0_FC BIT(21) | |
70 | #define MTK_PSE_FQ_EMPTY BIT(20) | |
71 | #define MTK_GE1_STA_CHG BIT(18) | |
72 | #define MTK_TX_COHERENT BIT(17) | |
73 | #define MTK_RX_COHERENT BIT(16) | |
74 | #define MTK_TX_DONE_INT3 BIT(11) | |
75 | #define MTK_TX_DONE_INT2 BIT(10) | |
76 | #define MTK_TX_DONE_INT1 BIT(9) | |
77 | #define MTK_TX_DONE_INT0 BIT(8) | |
78 | #define MTK_RX_DONE_INT0 BIT(2) | |
79 | #define MTK_TX_DLY_INT BIT(1) | |
80 | #define MTK_RX_DLY_INT BIT(0) | |
81 | ||
82 | #define MTK_RX_DONE_INT MTK_RX_DONE_INT0 | |
83 | #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ | |
84 | MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) | |
85 | ||
86 | #define RT5350_RX_DLY_INT BIT(30) | |
87 | #define RT5350_TX_DLY_INT BIT(28) | |
88 | #define RT5350_RX_DONE_INT1 BIT(17) | |
89 | #define RT5350_RX_DONE_INT0 BIT(16) | |
90 | #define RT5350_TX_DONE_INT3 BIT(3) | |
91 | #define RT5350_TX_DONE_INT2 BIT(2) | |
92 | #define RT5350_TX_DONE_INT1 BIT(1) | |
93 | #define RT5350_TX_DONE_INT0 BIT(0) | |
94 | ||
95 | #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1) | |
96 | #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \ | |
97 | RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3) | |
98 | ||
99 | /* registers */ | |
100 | #define MTK_GDMA_OFFSET 0x0020 | |
101 | #define MTK_PSE_OFFSET 0x0040 | |
102 | #define MTK_GDMA2_OFFSET 0x0060 | |
103 | #define MTK_CDMA_OFFSET 0x0080 | |
104 | #define MTK_DMA_VID0 0x00a8 | |
105 | #define MTK_PDMA_OFFSET 0x0100 | |
106 | #define MTK_PPE_OFFSET 0x0200 | |
107 | #define MTK_CMTABLE_OFFSET 0x0400 | |
108 | #define MTK_POLICYTABLE_OFFSET 0x1000 | |
109 | ||
110 | #define MT7621_GDMA_OFFSET 0x0500 | |
111 | #define MT7620_GDMA_OFFSET 0x0600 | |
112 | ||
113 | #define RT5350_PDMA_OFFSET 0x0800 | |
114 | #define RT5350_SDM_OFFSET 0x0c00 | |
115 | ||
116 | #define MTK_MDIO_ACCESS 0x00 | |
117 | #define MTK_MDIO_CFG 0x04 | |
118 | #define MTK_GLO_CFG 0x08 | |
119 | #define MTK_RST_GL 0x0C | |
120 | #define MTK_INT_STATUS 0x10 | |
121 | #define MTK_INT_ENABLE 0x14 | |
122 | #define MTK_MDIO_CFG2 0x18 | |
123 | #define MTK_FOC_TS_T 0x1C | |
124 | ||
125 | #define MTK_GDMA1_FWD_CFG (MTK_GDMA_OFFSET + 0x00) | |
126 | #define MTK_GDMA1_SCH_CFG (MTK_GDMA_OFFSET + 0x04) | |
127 | #define MTK_GDMA1_SHPR_CFG (MTK_GDMA_OFFSET + 0x08) | |
128 | #define MTK_GDMA1_MAC_ADRL (MTK_GDMA_OFFSET + 0x0C) | |
129 | #define MTK_GDMA1_MAC_ADRH (MTK_GDMA_OFFSET + 0x10) | |
130 | ||
131 | #define MTK_GDMA2_FWD_CFG (MTK_GDMA2_OFFSET + 0x00) | |
132 | #define MTK_GDMA2_SCH_CFG (MTK_GDMA2_OFFSET + 0x04) | |
133 | #define MTK_GDMA2_SHPR_CFG (MTK_GDMA2_OFFSET + 0x08) | |
134 | #define MTK_GDMA2_MAC_ADRL (MTK_GDMA2_OFFSET + 0x0C) | |
135 | #define MTK_GDMA2_MAC_ADRH (MTK_GDMA2_OFFSET + 0x10) | |
136 | ||
137 | #define MTK_PSE_FQ_CFG (MTK_PSE_OFFSET + 0x00) | |
138 | #define MTK_CDMA_FC_CFG (MTK_PSE_OFFSET + 0x04) | |
139 | #define MTK_GDMA1_FC_CFG (MTK_PSE_OFFSET + 0x08) | |
140 | #define MTK_GDMA2_FC_CFG (MTK_PSE_OFFSET + 0x0C) | |
141 | ||
142 | #define MTK_CDMA_CSG_CFG (MTK_CDMA_OFFSET + 0x00) | |
143 | #define MTK_CDMA_SCH_CFG (MTK_CDMA_OFFSET + 0x04) | |
144 | ||
145 | #define MT7621_GDMA_FWD_CFG(x) (MT7621_GDMA_OFFSET + (x * 0x1000)) | |
146 | ||
147 | /* FIXME this might be different for different SOCs */ | |
148 | #define MT7620_GDMA1_FWD_CFG (MT7621_GDMA_OFFSET + 0x00) | |
149 | ||
150 | #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00) | |
151 | #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04) | |
152 | #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08) | |
153 | #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C) | |
154 | #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10) | |
155 | #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14) | |
156 | #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18) | |
157 | #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C) | |
158 | #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20) | |
159 | #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24) | |
160 | #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28) | |
161 | #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C) | |
162 | #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30) | |
163 | #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34) | |
164 | #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38) | |
165 | #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C) | |
166 | #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100) | |
167 | #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104) | |
168 | #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108) | |
169 | #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C) | |
170 | #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110) | |
171 | #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114) | |
172 | #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118) | |
173 | #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C) | |
174 | #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204) | |
175 | #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208) | |
176 | #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c) | |
177 | #define RT5350_MTK_INT_STATUS (RT5350_PDMA_OFFSET + 0x220) | |
178 | #define RT5350_MTK_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228) | |
179 | #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280) | |
180 | ||
181 | #define MTK_PDMA_GLO_CFG (MTK_PDMA_OFFSET + 0x00) | |
182 | #define MTK_PDMA_RST_CFG (MTK_PDMA_OFFSET + 0x04) | |
183 | #define MTK_PDMA_SCH_CFG (MTK_PDMA_OFFSET + 0x08) | |
184 | #define MTK_DLY_INT_CFG (MTK_PDMA_OFFSET + 0x0C) | |
185 | #define MTK_TX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x10) | |
186 | #define MTK_TX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x14) | |
187 | #define MTK_TX_CTX_IDX0 (MTK_PDMA_OFFSET + 0x18) | |
188 | #define MTK_TX_DTX_IDX0 (MTK_PDMA_OFFSET + 0x1C) | |
189 | #define MTK_TX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x20) | |
190 | #define MTK_TX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x24) | |
191 | #define MTK_TX_CTX_IDX1 (MTK_PDMA_OFFSET + 0x28) | |
192 | #define MTK_TX_DTX_IDX1 (MTK_PDMA_OFFSET + 0x2C) | |
193 | #define MTK_RX_BASE_PTR0 (MTK_PDMA_OFFSET + 0x30) | |
194 | #define MTK_RX_MAX_CNT0 (MTK_PDMA_OFFSET + 0x34) | |
195 | #define MTK_RX_CALC_IDX0 (MTK_PDMA_OFFSET + 0x38) | |
196 | #define MTK_RX_DRX_IDX0 (MTK_PDMA_OFFSET + 0x3C) | |
197 | #define MTK_TX_BASE_PTR2 (MTK_PDMA_OFFSET + 0x40) | |
198 | #define MTK_TX_MAX_CNT2 (MTK_PDMA_OFFSET + 0x44) | |
199 | #define MTK_TX_CTX_IDX2 (MTK_PDMA_OFFSET + 0x48) | |
200 | #define MTK_TX_DTX_IDX2 (MTK_PDMA_OFFSET + 0x4C) | |
201 | #define MTK_TX_BASE_PTR3 (MTK_PDMA_OFFSET + 0x50) | |
202 | #define MTK_TX_MAX_CNT3 (MTK_PDMA_OFFSET + 0x54) | |
203 | #define MTK_TX_CTX_IDX3 (MTK_PDMA_OFFSET + 0x58) | |
204 | #define MTK_TX_DTX_IDX3 (MTK_PDMA_OFFSET + 0x5C) | |
205 | #define MTK_RX_BASE_PTR1 (MTK_PDMA_OFFSET + 0x60) | |
206 | #define MTK_RX_MAX_CNT1 (MTK_PDMA_OFFSET + 0x64) | |
207 | #define MTK_RX_CALC_IDX1 (MTK_PDMA_OFFSET + 0x68) | |
208 | #define MTK_RX_DRX_IDX1 (MTK_PDMA_OFFSET + 0x6C) | |
209 | ||
210 | /* Switch DMA configuration */ | |
211 | #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) | |
212 | #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) | |
213 | #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) | |
214 | #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) | |
215 | #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) | |
216 | #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) | |
217 | #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) | |
218 | #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) | |
219 | #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) | |
220 | #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) | |
221 | ||
222 | #define RT5350_SDM_ICS_EN BIT(16) | |
223 | #define RT5350_SDM_TCS_EN BIT(17) | |
224 | #define RT5350_SDM_UCS_EN BIT(18) | |
225 | ||
226 | /* QDMA registers */ | |
227 | #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) | |
228 | #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) | |
229 | #define MTK_QRX_BASE_PTR0 0x1900 | |
230 | #define MTK_QRX_MAX_CNT0 0x1904 | |
231 | #define MTK_QRX_CRX_IDX0 0x1908 | |
232 | #define MTK_QRX_DRX_IDX0 0x190C | |
233 | #define MTK_QDMA_GLO_CFG 0x1A04 | |
234 | #define MTK_QDMA_RST_IDX 0x1A08 | |
235 | #define MTK_QDMA_DELAY_INT 0x1A0C | |
236 | #define MTK_QDMA_FC_THRES 0x1A10 | |
237 | #define MTK_QMTK_INT_STATUS 0x1A18 | |
238 | #define MTK_QMTK_INT_ENABLE 0x1A1C | |
239 | #define MTK_QDMA_HRED2 0x1A44 | |
240 | ||
241 | #define MTK_QTX_CTX_PTR 0x1B00 | |
242 | #define MTK_QTX_DTX_PTR 0x1B04 | |
243 | ||
244 | #define MTK_QTX_CRX_PTR 0x1B10 | |
245 | #define MTK_QTX_DRX_PTR 0x1B14 | |
246 | ||
247 | #define MTK_QDMA_FQ_HEAD 0x1B20 | |
248 | #define MTK_QDMA_FQ_TAIL 0x1B24 | |
249 | #define MTK_QDMA_FQ_CNT 0x1B28 | |
250 | #define MTK_QDMA_FQ_BLEN 0x1B2C | |
251 | ||
252 | #define QDMA_PAGE_SIZE 2048 | |
253 | #define QDMA_TX_OWNER_CPU BIT(31) | |
254 | #define QDMA_TX_SWC BIT(14) | |
255 | #define TX_QDMA_SDL(_x) (((_x) & 0x3fff) << 16) | |
256 | #define QDMA_RES_THRES 4 | |
257 | ||
258 | /* MDIO_CFG register bits */ | |
259 | #define MTK_MDIO_CFG_AUTO_POLL_EN BIT(29) | |
260 | #define MTK_MDIO_CFG_GP1_BP_EN BIT(16) | |
261 | #define MTK_MDIO_CFG_GP1_FRC_EN BIT(15) | |
262 | #define MTK_MDIO_CFG_GP1_SPEED_10 (0 << 13) | |
263 | #define MTK_MDIO_CFG_GP1_SPEED_100 (1 << 13) | |
264 | #define MTK_MDIO_CFG_GP1_SPEED_1000 (2 << 13) | |
265 | #define MTK_MDIO_CFG_GP1_DUPLEX BIT(12) | |
266 | #define MTK_MDIO_CFG_GP1_FC_TX BIT(11) | |
267 | #define MTK_MDIO_CFG_GP1_FC_RX BIT(10) | |
268 | #define MTK_MDIO_CFG_GP1_LNK_DWN BIT(9) | |
269 | #define MTK_MDIO_CFG_GP1_AN_FAIL BIT(8) | |
270 | #define MTK_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6) | |
271 | #define MTK_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6) | |
272 | #define MTK_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6) | |
273 | #define MTK_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6) | |
274 | #define MTK_MDIO_CFG_TURBO_MII_FREQ BIT(5) | |
275 | #define MTK_MDIO_CFG_TURBO_MII_MODE BIT(4) | |
276 | #define MTK_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2) | |
277 | #define MTK_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2) | |
278 | #define MTK_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2) | |
279 | #define MTK_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2) | |
280 | #define MTK_MDIO_CFG_TX_CLK_SKEW_0 0 | |
281 | #define MTK_MDIO_CFG_TX_CLK_SKEW_200 1 | |
282 | #define MTK_MDIO_CFG_TX_CLK_SKEW_400 2 | |
283 | #define MTK_MDIO_CFG_TX_CLK_SKEW_INV 3 | |
284 | ||
285 | /* uni-cast port */ | |
286 | #define MTK_GDM1_JMB_LEN_MASK 0xf | |
287 | #define MTK_GDM1_JMB_LEN_SHIFT 28 | |
288 | #define MTK_GDM1_ICS_EN BIT(22) | |
289 | #define MTK_GDM1_TCS_EN BIT(21) | |
290 | #define MTK_GDM1_UCS_EN BIT(20) | |
291 | #define MTK_GDM1_JMB_EN BIT(19) | |
292 | #define MTK_GDM1_STRPCRC BIT(16) | |
293 | #define MTK_GDM1_UFRC_P_CPU (0 << 12) | |
294 | #define MTK_GDM1_UFRC_P_GDMA1 (1 << 12) | |
295 | #define MTK_GDM1_UFRC_P_PPE (6 << 12) | |
296 | ||
297 | /* checksums */ | |
298 | #define MTK_ICS_GEN_EN BIT(2) | |
299 | #define MTK_UCS_GEN_EN BIT(1) | |
300 | #define MTK_TCS_GEN_EN BIT(0) | |
301 | ||
302 | /* dma mode */ | |
303 | #define MTK_PDMA BIT(0) | |
304 | #define MTK_QDMA BIT(1) | |
305 | #define MTK_PDMA_RX_QDMA_TX (MTK_PDMA | MTK_QDMA) | |
306 | ||
307 | /* dma ring */ | |
308 | #define MTK_PST_DRX_IDX0 BIT(16) | |
309 | #define MTK_PST_DTX_IDX3 BIT(3) | |
310 | #define MTK_PST_DTX_IDX2 BIT(2) | |
311 | #define MTK_PST_DTX_IDX1 BIT(1) | |
312 | #define MTK_PST_DTX_IDX0 BIT(0) | |
313 | ||
314 | #define MTK_RX_2B_OFFSET BIT(31) | |
315 | #define MTK_TX_WB_DDONE BIT(6) | |
316 | #define MTK_RX_DMA_BUSY BIT(3) | |
317 | #define MTK_TX_DMA_BUSY BIT(1) | |
318 | #define MTK_RX_DMA_EN BIT(2) | |
319 | #define MTK_TX_DMA_EN BIT(0) | |
320 | ||
321 | #define MTK_PDMA_SIZE_4DWORDS (0 << 4) | |
322 | #define MTK_PDMA_SIZE_8DWORDS (1 << 4) | |
323 | #define MTK_PDMA_SIZE_16DWORDS (2 << 4) | |
324 | ||
325 | #define MTK_US_CYC_CNT_MASK 0xff | |
326 | #define MTK_US_CYC_CNT_SHIFT 0x8 | |
327 | #define MTK_US_CYC_CNT_DIVISOR 1000000 | |
328 | ||
329 | /* PDMA descriptor rxd2 */ | |
330 | #define RX_DMA_DONE BIT(31) | |
331 | #define RX_DMA_LSO BIT(30) | |
332 | #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) | |
333 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) | |
334 | #define RX_DMA_TAG BIT(15) | |
335 | ||
336 | /* PDMA descriptor rxd3 */ | |
337 | #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff) | |
338 | #define RX_DMA_VID(_x) ((_x) & 0xfff) | |
339 | ||
340 | /* PDMA descriptor rxd4 */ | |
341 | #define RX_DMA_L4VALID BIT(30) | |
342 | #define RX_DMA_FPORT_SHIFT 19 | |
343 | #define RX_DMA_FPORT_MASK 0x7 | |
344 | ||
345 | struct mtk_rx_dma { | |
346 | unsigned int rxd1; | |
347 | unsigned int rxd2; | |
348 | unsigned int rxd3; | |
349 | unsigned int rxd4; | |
350 | } __packed __aligned(4); | |
351 | ||
352 | /* PDMA tx descriptor bits */ | |
353 | #define TX_DMA_BUF_LEN 0x3fff | |
354 | #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16) | |
355 | #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16) | |
356 | #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) | |
357 | #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN) | |
358 | #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) | |
359 | #define TX_DMA_LS1 BIT(14) | |
360 | #define TX_DMA_LS0 BIT(30) | |
361 | #define TX_DMA_DONE BIT(31) | |
362 | #define TX_DMA_FPORT_SHIFT 25 | |
363 | #define TX_DMA_FPORT_MASK 0x7 | |
364 | #define TX_DMA_INS_VLAN_MT7621 BIT(16) | |
365 | #define TX_DMA_INS_VLAN BIT(7) | |
366 | #define TX_DMA_INS_PPPOE BIT(12) | |
367 | #define TX_DMA_TAG BIT(15) | |
368 | #define TX_DMA_TAG_MASK BIT(15) | |
369 | #define TX_DMA_QN(_x) ((_x) << 16) | |
370 | #define TX_DMA_PN(_x) ((_x) << 24) | |
371 | #define TX_DMA_QN_MASK TX_DMA_QN(0x7) | |
372 | #define TX_DMA_PN_MASK TX_DMA_PN(0x7) | |
373 | #define TX_DMA_UDF BIT(20) | |
374 | #define TX_DMA_CHKSUM (0x7 << 29) | |
375 | #define TX_DMA_TSO BIT(28) | |
376 | #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1)) | |
377 | ||
378 | /* frame engine counters */ | |
379 | #define MTK_PPE_AC_BCNT0 (MTK_CMTABLE_OFFSET + 0x00) | |
380 | #define MTK_GDMA1_TX_GBCNT (MTK_CMTABLE_OFFSET + 0x300) | |
381 | #define MTK_GDMA2_TX_GBCNT (MTK_GDMA1_TX_GBCNT + 0x40) | |
382 | ||
383 | /* phy device flags */ | |
384 | #define MTK_PHY_FLAG_PORT BIT(0) | |
385 | #define MTK_PHY_FLAG_ATTACH BIT(1) | |
386 | ||
387 | struct mtk_tx_dma { | |
388 | unsigned int txd1; | |
389 | unsigned int txd2; | |
390 | unsigned int txd3; | |
391 | unsigned int txd4; | |
392 | } __packed __aligned(4); | |
393 | ||
394 | struct mtk_eth; | |
395 | struct mtk_mac; | |
396 | ||
397 | /* manage the attached phys */ | |
398 | struct mtk_phy { | |
399 | spinlock_t lock; | |
400 | ||
401 | struct phy_device *phy[8]; | |
402 | struct device_node *phy_node[8]; | |
403 | const __be32 *phy_fixed[8]; | |
404 | int duplex[8]; | |
405 | int speed[8]; | |
406 | int tx_fc[8]; | |
407 | int rx_fc[8]; | |
408 | int (*connect)(struct mtk_mac *mac); | |
409 | void (*disconnect)(struct mtk_mac *mac); | |
410 | void (*start)(struct mtk_mac *mac); | |
411 | void (*stop)(struct mtk_mac *mac); | |
412 | }; | |
413 | ||
414 | /* struct mtk_soc_data - the structure that holds the SoC specific data | |
415 | * @reg_table: Some of the legacy registers changed their location | |
416 | * over time. Their offsets are stored in this table | |
417 | * | |
418 | * @init_data: Some features depend on the silicon revision. This | |
419 | * callback allows runtime modification of the content of | |
420 | * this struct | |
421 | * @reset_fe: This callback is used to trigger the reset of the frame | |
422 | * engine | |
423 | * @set_mac: This callback is used to set the unicast mac address | |
424 | * filter | |
425 | * @fwd_config: This callback is used to setup the forward config | |
426 | * register of the MAC | |
427 | * @switch_init: This callback is used to bring up the switch core | |
428 | * @port_init: Some SoCs have ports that can be router to a switch port | |
429 | * or an external PHY. This callback is used to setup these | |
430 | * ports. | |
431 | * @has_carrier: This callback allows driver to check if there is a cable | |
432 | * attached. | |
433 | * @mdio_init: This callbck is used to setup the MDIO bus if one is | |
434 | * present | |
435 | * @mdio_cleanup: This callback is used to cleanup the MDIO state. | |
436 | * @mdio_write: This callback is used to write data to the MDIO bus. | |
437 | * @mdio_read: This callback is used to write data to the MDIO bus. | |
438 | * @mdio_adjust_link: This callback is used to apply the PHY settings. | |
439 | * @piac_offset: the PIAC register has a different different base offset | |
440 | * @hw_features: feature set depends on the SoC type | |
441 | * @dma_ring_size: allow GBit SoCs to set bigger rings than FE SoCs | |
442 | * @napi_weight: allow GBit SoCs to set bigger napi weight than FE SoCs | |
443 | * @dma_type: SoCs is PDMA, QDMA or a mix of the 2 | |
444 | * @pdma_glo_cfg: the default DMA configuration | |
445 | * @rx_int: the TX interrupt bits used by the SoC | |
446 | * @tx_int: the TX interrupt bits used by the SoC | |
447 | * @status_int: the Status interrupt bits used by the SoC | |
448 | * @checksum_bit: the bits used to turn on HW checksumming | |
449 | * @txd4: default value of the TXD4 descriptor | |
450 | * @mac_count: the number of MACs that the SoC has | |
451 | * @new_stats: there is a old and new way to read hardware stats | |
452 | * registers | |
453 | * @jumbo_frame: does the SoC support jumbo frames ? | |
454 | * @rx_2b_offset: tell the rx dma to offset the data by 2 bytes | |
455 | * @rx_sg_dma: scatter gather support | |
456 | * @padding_64b enable 64 bit padding | |
457 | * @padding_bug: rt2880 has a padding bug | |
458 | * @has_switch: does the SoC have a built-in switch | |
459 | * | |
460 | * Although all of the supported SoCs share the same basic functionality, there | |
461 | * are several SoC specific functions and features that we need to support. This | |
462 | * struct holds the SoC specific data so that the common core can figure out | |
463 | * how to setup and use these differences. | |
464 | */ | |
465 | struct mtk_soc_data { | |
466 | const u16 *reg_table; | |
467 | ||
468 | void (*init_data)(struct mtk_soc_data *data, struct net_device *netdev); | |
469 | void (*reset_fe)(struct mtk_eth *eth); | |
470 | void (*set_mac)(struct mtk_mac *mac, unsigned char *macaddr); | |
471 | int (*fwd_config)(struct mtk_eth *eth); | |
472 | int (*switch_init)(struct mtk_eth *eth); | |
473 | void (*port_init)(struct mtk_eth *eth, struct mtk_mac *mac, | |
474 | struct device_node *port); | |
475 | int (*has_carrier)(struct mtk_eth *eth); | |
476 | int (*mdio_init)(struct mtk_eth *eth); | |
477 | void (*mdio_cleanup)(struct mtk_eth *eth); | |
478 | int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, | |
479 | u16 val); | |
480 | int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg); | |
481 | void (*mdio_adjust_link)(struct mtk_eth *eth, int port); | |
482 | u32 piac_offset; | |
483 | netdev_features_t hw_features; | |
484 | u32 dma_ring_size; | |
485 | u32 napi_weight; | |
486 | u32 dma_type; | |
487 | u32 pdma_glo_cfg; | |
488 | u32 rx_int; | |
489 | u32 tx_int; | |
490 | u32 status_int; | |
491 | u32 checksum_bit; | |
492 | u32 txd4; | |
493 | u32 mac_count; | |
494 | ||
495 | u32 new_stats:1; | |
496 | u32 jumbo_frame:1; | |
497 | u32 rx_2b_offset:1; | |
498 | u32 rx_sg_dma:1; | |
499 | u32 padding_64b:1; | |
500 | u32 padding_bug:1; | |
501 | u32 has_switch:1; | |
502 | }; | |
503 | ||
e3cbf478 | 504 | #define MTK_STAT_OFFSET 0x40 |
e3cbf478 JC |
505 | |
506 | /* struct mtk_hw_stats - the structure that holds the traffic statistics. | |
507 | * @stats_lock: make sure that stats operations are atomic | |
508 | * @reg_offset: the status register offset of the SoC | |
509 | * @syncp: the refcount | |
510 | * | |
511 | * All of the supported SoCs have hardware counters for traffic statstics. | |
512 | * Whenever the status IRQ triggers we can read the latest stats from these | |
513 | * counters and store them in this struct. | |
514 | */ | |
515 | struct mtk_hw_stats { | |
516 | spinlock_t stats_lock; | |
517 | u32 reg_offset; | |
518 | struct u64_stats_sync syncp; | |
519 | ||
d84c7b30 KH |
520 | u64 tx_bytes; |
521 | u64 tx_packets; | |
522 | u64 tx_skip; | |
523 | u64 tx_collisions; | |
524 | u64 rx_bytes; | |
525 | u64 rx_packets; | |
526 | u64 rx_overflow; | |
527 | u64 rx_fcs_errors; | |
528 | u64 rx_short_errors; | |
529 | u64 rx_long_errors; | |
530 | u64 rx_checksum_errors; | |
531 | u64 rx_flow_control_packets; | |
e3cbf478 JC |
532 | }; |
533 | ||
534 | /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how | |
535 | * memory was allocated so that it can be freed properly | |
536 | */ | |
537 | enum mtk_tx_flags { | |
538 | MTK_TX_FLAGS_SINGLE0 = 0x01, | |
539 | MTK_TX_FLAGS_PAGE0 = 0x02, | |
540 | MTK_TX_FLAGS_PAGE1 = 0x04, | |
541 | }; | |
542 | ||
543 | /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at | |
544 | * by the TX descriptor s | |
545 | * @skb: The SKB pointer of the packet being sent | |
546 | * @dma_addr0: The base addr of the first segment | |
547 | * @dma_len0: The length of the first segment | |
548 | * @dma_addr1: The base addr of the second segment | |
549 | * @dma_len1: The length of the second segment | |
550 | */ | |
551 | struct mtk_tx_buf { | |
552 | struct sk_buff *skb; | |
553 | u32 flags; | |
554 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); | |
555 | DEFINE_DMA_UNMAP_LEN(dma_len0); | |
556 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); | |
557 | DEFINE_DMA_UNMAP_LEN(dma_len1); | |
558 | }; | |
559 | ||
560 | /* struct mtk_tx_ring - This struct holds info describing a TX ring | |
561 | * @tx_dma: The descriptor ring | |
562 | * @tx_buf: The memory pointed at by the ring | |
563 | * @tx_phys: The physical addr of tx_buf | |
564 | * @tx_next_free: Pointer to the next free descriptor | |
565 | * @tx_last_free: Pointer to the last free descriptor | |
566 | * @tx_thresh: The threshold of minimum amount of free descriptors | |
567 | * @tx_map: Callback to map a new packet into the ring | |
568 | * @tx_poll: Callback for the housekeeping function | |
569 | * @tx_clean: Callback for the cleanup function | |
570 | * @tx_ring_size: How many descriptors are in the ring | |
571 | * @tx_free_idx: The index of th next free descriptor | |
572 | * @tx_next_idx: QDMA uses a linked list. This element points to the next | |
573 | * free descriptor in the list | |
574 | * @tx_free_count: QDMA uses a linked list. Track how many free descriptors | |
575 | * are present | |
576 | */ | |
577 | struct mtk_tx_ring { | |
578 | struct mtk_tx_dma *tx_dma; | |
579 | struct mtk_tx_buf *tx_buf; | |
580 | dma_addr_t tx_phys; | |
581 | struct mtk_tx_dma *tx_next_free; | |
582 | struct mtk_tx_dma *tx_last_free; | |
583 | u16 tx_thresh; | |
584 | int (*tx_map)(struct sk_buff *skb, struct net_device *dev, int tx_num, | |
585 | struct mtk_tx_ring *ring, bool gso); | |
586 | int (*tx_poll)(struct mtk_eth *eth, int budget, bool *tx_again); | |
587 | void (*tx_clean)(struct mtk_eth *eth); | |
588 | ||
589 | /* PDMA only */ | |
590 | u16 tx_ring_size; | |
591 | u16 tx_free_idx; | |
592 | ||
593 | /* QDMA only */ | |
594 | u16 tx_next_idx; | |
595 | atomic_t tx_free_count; | |
596 | }; | |
597 | ||
598 | /* struct mtk_rx_ring - This struct holds info describing a RX ring | |
599 | * @rx_dma: The descriptor ring | |
600 | * @rx_data: The memory pointed at by the ring | |
601 | * @trx_phys: The physical addr of rx_buf | |
602 | * @rx_ring_size: How many descriptors are in the ring | |
603 | * @rx_buf_size: The size of each packet buffer | |
604 | * @rx_calc_idx: The current head of ring | |
605 | */ | |
606 | struct mtk_rx_ring { | |
607 | struct mtk_rx_dma *rx_dma; | |
608 | u8 **rx_data; | |
609 | dma_addr_t rx_phys; | |
610 | u16 rx_ring_size; | |
611 | u16 frag_size; | |
612 | u16 rx_buf_size; | |
613 | u16 rx_calc_idx; | |
614 | }; | |
615 | ||
616 | /* currently no SoC has more than 2 macs */ | |
617 | #define MTK_MAX_DEVS 2 | |
618 | ||
619 | /* struct mtk_eth - This is the main datasructure for holding the state | |
620 | * of the driver | |
621 | * @dev: The device pointer | |
622 | * @base: The mapped register i/o base | |
623 | * @page_lock: Make sure that register operations are atomic | |
624 | * @soc: pointer to our SoC specific data | |
625 | * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a | |
626 | * dummy for NAPI to work | |
627 | * @netdev: The netdev instances | |
628 | * @mac: Each netdev is linked to a physical MAC | |
629 | * @switch_np: The phandle for the switch | |
630 | * @irq: The IRQ that we are using | |
631 | * @msg_enable: Ethtool msg level | |
632 | * @ysclk: The sysclk rate - neeed for calibration | |
633 | * @ethsys: The register map pointing at the range used to setup | |
634 | * MII modes | |
635 | * @dma_refcnt: track how many netdevs are using the DMA engine | |
636 | * @tx_ring: Pointer to the memore holding info about the TX ring | |
637 | * @rx_ring: Pointer to the memore holding info about the RX ring | |
638 | * @rx_napi: The NAPI struct | |
639 | * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring | |
640 | * @scratch_head: The scratch memory that scratch_ring points to. | |
641 | * @phy: Info about the attached PHYs | |
642 | * @mii_bus: If there is a bus we need to create an instance for it | |
643 | * @link: Track if the ports have a physical link | |
644 | * @sw_priv: Pointer to the switches private data | |
645 | * @vlan_map: RX VID tracking | |
646 | */ | |
647 | ||
648 | struct mtk_eth { | |
649 | struct device *dev; | |
650 | void __iomem *base; | |
651 | spinlock_t page_lock; | |
652 | struct mtk_soc_data *soc; | |
653 | struct net_device dummy_dev; | |
654 | struct net_device *netdev[MTK_MAX_DEVS]; | |
655 | struct mtk_mac *mac[MTK_MAX_DEVS]; | |
656 | struct device_node *switch_np; | |
657 | int irq; | |
658 | u32 msg_enable; | |
659 | unsigned long sysclk; | |
660 | struct regmap *ethsys; | |
661 | atomic_t dma_refcnt; | |
662 | struct mtk_tx_ring tx_ring; | |
663 | struct mtk_rx_ring rx_ring[2]; | |
664 | struct napi_struct rx_napi; | |
665 | struct mtk_tx_dma *scratch_ring; | |
666 | void *scratch_head; | |
667 | struct mtk_phy *phy; | |
668 | struct mii_bus *mii_bus; | |
669 | int link[8]; | |
670 | void *sw_priv; | |
671 | unsigned long vlan_map; | |
672 | }; | |
673 | ||
674 | /* struct mtk_mac - the structure that holds the info about the MACs of the | |
675 | * SoC | |
676 | * @id: The number of the MAC | |
677 | * @of_node: Our devicetree node | |
678 | * @hw: Backpointer to our main datastruture | |
679 | * @hw_stats: Packet statistics counter | |
680 | * @phy_dev: The attached PHY if available | |
681 | * @phy_flags: The PHYs flags | |
682 | * @pending_work: The workqueue used to reset the dma ring | |
683 | */ | |
684 | struct mtk_mac { | |
685 | int id; | |
686 | struct device_node *of_node; | |
687 | struct mtk_eth *hw; | |
688 | struct mtk_hw_stats *hw_stats; | |
689 | struct phy_device *phy_dev; | |
690 | u32 phy_flags; | |
691 | struct work_struct pending_work; | |
692 | }; | |
693 | ||
694 | /* the struct describing the SoC. these are declared in the soc_xyz.c files */ | |
695 | extern const struct of_device_id of_mtk_match[]; | |
696 | ||
697 | /* read the hardware status register */ | |
698 | void mtk_stats_update_mac(struct mtk_mac *mac); | |
699 | ||
700 | /* default checksum setup handler */ | |
701 | void mtk_reset(struct mtk_eth *eth, u32 reset_bits); | |
702 | ||
703 | /* register i/o wrappers */ | |
fadd6fda KH |
704 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned int reg); |
705 | u32 mtk_r32(struct mtk_eth *eth, unsigned int reg); | |
e3cbf478 JC |
706 | |
707 | /* default clock calibration handler */ | |
708 | int mtk_set_clock_cycle(struct mtk_eth *eth); | |
709 | ||
710 | /* default checksum setup handler */ | |
711 | void mtk_csum_config(struct mtk_eth *eth); | |
712 | ||
713 | /* default forward config handler */ | |
714 | void mtk_fwd_config(struct mtk_eth *eth); | |
715 | ||
716 | #endif /* MTK_ETH_H */ |