[thirdparty/kernel/stable.git] / drivers / staging / mt7621-spi / spi-mt7621.c

/*
 * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
 *
 * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
 *
 * Some parts are based on spi-orion.c:
 *   Author: Shadi Ammouri <shadi@marvell.com>
 *   Copyright (C) 2007-2008 Marvell Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/swab.h>

#include <ralink_regs.h>

#define SPI_BPW_MASK(bits) BIT((bits) - 1)

#define DRIVER_NAME			"spi-mt7621"
/* in usec */
#define RALINK_SPI_WAIT_MAX_LOOP	2000

/* SPISTAT register bit field */
#define SPISTAT_BUSY			BIT(0)

#define MT7621_SPI_TRANS	0x00
#define SPITRANS_BUSY		BIT(16)

#define MT7621_SPI_OPCODE	0x04
#define MT7621_SPI_DATA0	0x08
#define MT7621_SPI_DATA4	0x18
#define SPI_CTL_TX_RX_CNT_MASK	0xff
#define SPI_CTL_START		BIT(8)

#define MT7621_SPI_POLAR	0x38
#define MT7621_SPI_MASTER	0x28
#define MT7621_SPI_MOREBUF	0x2c
#define MT7621_SPI_SPACE	0x3c

#define MT7621_CPHA		BIT(5)
#define MT7621_CPOL		BIT(4)
#define MT7621_LSB_FIRST	BIT(3)

#define RT2880_SPI_MODE_BITS	(SPI_CPOL | SPI_CPHA |		\
				 SPI_LSB_FIRST | SPI_CS_HIGH)

struct mt7621_spi;

struct mt7621_spi {
	struct spi_master	*master;
	void __iomem		*base;
	unsigned int		sys_freq;
	unsigned int		speed;
	struct clk		*clk;
	int			pending_write;

	struct mt7621_spi_ops	*ops;
};

static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
{
	return spi_master_get_devdata(spi->master);
}

static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
{
	return ioread32(rs->base + reg);
}

static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
{
	iowrite32(val, rs->base + reg);
}

static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
{
	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);

	master |= 7 << 29;
	master |= 1 << 2;
	if (duplex)
		master |= 1 << 10;
	else
		master &= ~(1 << 10);

	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
	rs->pending_write = 0;
}

static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	int cs = spi->chip_select;
	u32 polar = 0;

	mt7621_spi_reset(rs, cs);
	if (enable)
		polar = BIT(cs);
	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
}

static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	u32 rate;
	u32 reg;

	dev_dbg(&spi->dev, "speed:%u\n", speed);

	rate = DIV_ROUND_UP(rs->sys_freq, speed);
	dev_dbg(&spi->dev, "rate-1:%u\n", rate);

	if (rate > 4097)
		return -EINVAL;

	if (rate < 2)
		rate = 2;

	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	reg &= ~(0xfff << 16);
	reg |= (rate - 2) << 16;
	rs->speed = speed;

	reg &= ~MT7621_LSB_FIRST;
	if (spi->mode & SPI_LSB_FIRST)
		reg |= MT7621_LSB_FIRST;

	reg &= ~(MT7621_CPHA | MT7621_CPOL);
	switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
	case SPI_MODE_0:
		break;
	case SPI_MODE_1:
		reg |= MT7621_CPHA;
		break;
	case SPI_MODE_2:
		reg |= MT7621_CPOL;
		break;
	case SPI_MODE_3:
		reg |= MT7621_CPOL | MT7621_CPHA;
		break;
	}
	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);

	return 0;
}

static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
{
	int i;

	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
		u32 status;

		status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		if ((status & SPITRANS_BUSY) == 0)
			return 0;
		cpu_relax();
		udelay(1);
	}

	return -ETIMEDOUT;
}

static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
					int rx_len, u8 *buf)
{
	/* Combine with any pending write, and perform one or
	 * more half-duplex transactions reading 'len' bytes.
	 * Data to be written is already in MT7621_SPI_DATA*
	 */
	int tx_len = rs->pending_write;

	rs->pending_write = 0;

	while (rx_len || tx_len) {
		int i;
		u32 val = (min(tx_len, 4) * 8) << 24;
		int rx = min(rx_len, 32);

		if (tx_len > 4)
			val |= (tx_len - 4) * 8;
		val |= (rx * 8) << 12;
		mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);

		tx_len = 0;

		val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
		val |= SPI_CTL_START;
		mt7621_spi_write(rs, MT7621_SPI_TRANS, val);

		mt7621_spi_wait_till_ready(rs);

		for (i = 0; i < rx; i++) {
			if ((i % 4) == 0)
				val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
			*buf++ = val & 0xff;
			val >>= 8;
		}
		rx_len -= i;
	}
}

static inline void mt7621_spi_flush(struct mt7621_spi *rs)
{
	mt7621_spi_read_half_duplex(rs, 0, NULL);
}

static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
					 int tx_len, const u8 *buf)
{
	int val = 0;
	int len = rs->pending_write;

	if (len & 3) {
		val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
		if (len < 4) {
			val <<= (4 - len) * 8;
			val = swab32(val);
		}
	}

	while (tx_len > 0) {
		if (len >= 36) {
			rs->pending_write = len;
			mt7621_spi_flush(rs);
			len = 0;
		}

		val |= *buf++ << (8 * (len & 3));
		len++;
		if ((len & 3) == 0) {
			if (len == 4)
				/* The byte-order of the opcode is weird! */
				val = swab32(val);
			mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
			val = 0;
		}
		tx_len -= 1;
	}
	if (len & 3) {
		if (len < 4) {
			val = swab32(val);
			val >>= (4 - len) * 8;
		}
		mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
	}
	rs->pending_write = len;
}

static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
					   struct spi_message *m)
{
	struct mt7621_spi *rs = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	unsigned int speed = spi->max_speed_hz;
	struct spi_transfer *t = NULL;
	int status = 0;

	mt7621_spi_wait_till_ready(rs);

	list_for_each_entry(t, &m->transfers, transfer_list)
		if (t->speed_hz < speed)
			speed = t->speed_hz;

	if (mt7621_spi_prepare(spi, speed)) {
		status = -EIO;
		goto msg_done;
	}

	mt7621_spi_set_cs(spi, 1);
	m->actual_length = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->rx_buf)
			mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
		else if (t->tx_buf)
			mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
		m->actual_length += t->len;
	}
	mt7621_spi_flush(rs);

	mt7621_spi_set_cs(spi, 0);
msg_done:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
					   struct spi_message *m)
{
	struct mt7621_spi *rs = spi_master_get_devdata(master);
	struct spi_device *spi = m->spi;
	unsigned int speed = spi->max_speed_hz;
	struct spi_transfer *t = NULL;
	int status = 0;
	int i, len = 0;
	int rx_len = 0;
	u32 data[9] = { 0 };
	u32 val = 0;

	mt7621_spi_wait_till_ready(rs);

	list_for_each_entry(t, &m->transfers, transfer_list) {
		const u8 *buf = t->tx_buf;

		if (t->rx_buf)
			rx_len += t->len;

		if (!buf)
			continue;

		if (WARN_ON(len + t->len > 16)) {
			status = -EIO;
			goto msg_done;
		}

		for (i = 0; i < t->len; i++, len++)
			data[len / 4] |= buf[i] << (8 * (len & 3));
		if (speed > t->speed_hz)
			speed = t->speed_hz;
	}

	if (WARN_ON(rx_len > 16)) {
		status = -EIO;
		goto msg_done;
	}

	if (mt7621_spi_prepare(spi, speed)) {
		status = -EIO;
		goto msg_done;
	}

	for (i = 0; i < len; i += 4)
		mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);

	val |= len * 8;
	val |= (rx_len * 8) << 12;
	mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);

	mt7621_spi_set_cs(spi, 1);

	val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
	val |= SPI_CTL_START;
	mt7621_spi_write(rs, MT7621_SPI_TRANS, val);

	mt7621_spi_wait_till_ready(rs);

	mt7621_spi_set_cs(spi, 0);

	for (i = 0; i < rx_len; i += 4)
		data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);

	m->actual_length = rx_len;

	len = 0;
	list_for_each_entry(t, &m->transfers, transfer_list) {
		u8 *buf = t->rx_buf;

		if (!buf)
			continue;

		for (i = 0; i < t->len; i++, len++)
			buf[i] = data[len / 4] >> (8 * (len & 3));
	}

msg_done:
	m->status = status;
	spi_finalize_current_message(master);

	return 0;
}

static int mt7621_spi_transfer_one_message(struct spi_master *master,
					   struct spi_message *m)
{
	struct spi_device *spi = m->spi;
	int cs = spi->chip_select;

	if (cs)
		return mt7621_spi_transfer_full_duplex(master, m);
	return mt7621_spi_transfer_half_duplex(master, m);
}

static int mt7621_spi_setup(struct spi_device *spi)
{
	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);

	if ((spi->max_speed_hz == 0) ||
		(spi->max_speed_hz > (rs->sys_freq / 2)))
		spi->max_speed_hz = (rs->sys_freq / 2);

	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
			spi->max_speed_hz);
		return -EINVAL;
	}

	return 0;
}

static const struct of_device_id mt7621_spi_match[] = {
	{ .compatible = "ralink,mt7621-spi" },
	{},
};
MODULE_DEVICE_TABLE(of, mt7621_spi_match);

static int mt7621_spi_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct spi_master *master;
	struct mt7621_spi *rs;
	void __iomem *base;
	struct resource *r;
	int status = 0;
	struct clk *clk;
	struct mt7621_spi_ops *ops;
	int ret;

	match = of_match_device(mt7621_spi_match, &pdev->dev);
	if (!match)
		return -EINVAL;
	ops = (struct mt7621_spi_ops *)match->data;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
			status);
		return PTR_ERR(clk);
	}

	status = clk_prepare_enable(clk);
	if (status)
		return status;

	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
	if (master == NULL) {
		dev_info(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	master->mode_bits = RT2880_SPI_MODE_BITS;

	master->setup = mt7621_spi_setup;
	master->transfer_one_message = mt7621_spi_transfer_one_message;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->dev.of_node = pdev->dev.of_node;
	master->num_chipselect = 2;

	dev_set_drvdata(&pdev->dev, master);

	rs = spi_master_get_devdata(master);
	rs->base = base;
	rs->clk = clk;
	rs->master = master;
	rs->sys_freq = clk_get_rate(rs->clk);
	rs->ops = ops;
	rs->pending_write = 0;
	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);

	ret = device_reset(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "SPI reset failed!\n");
		return ret;
	}

	mt7621_spi_reset(rs, 0);

	return spi_register_master(master);
}

static int mt7621_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master;
	struct mt7621_spi *rs;

	master = dev_get_drvdata(&pdev->dev);
	rs = spi_master_get_devdata(master);

	clk_disable(rs->clk);
	spi_unregister_master(master);

	return 0;
}

MODULE_ALIAS("platform:" DRIVER_NAME);

static struct platform_driver mt7621_spi_driver = {
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = mt7621_spi_match,
	},
	.probe = mt7621_spi_probe,
	.remove = mt7621_spi_remove,
};

module_platform_driver(mt7621_spi_driver);

MODULE_DESCRIPTION("MT7621 SPI driver");
MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ab7f2a4 JC	1	/*
	2	* spi-mt7621.c -- MediaTek MT7621 SPI controller driver
	3	*
	4	* Copyright (C) 2011 Sergiy <piratfm@gmail.com>
	5	* Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
	6	* Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
	7	*
	8	* Some parts are based on spi-orion.c:
	9	* Author: Shadi Ammouri <shadi@marvell.com>
	10	* Copyright (C) 2007-2008 Marvell Ltd.
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/module.h>
	19	#include <linux/clk.h>
	20	#include <linux/err.h>
	21	#include <linux/delay.h>
	22	#include <linux/io.h>
	23	#include <linux/reset.h>
	24	#include <linux/spi/spi.h>
	25	#include <linux/of_device.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/swab.h>
	28
	29	#include <ralink_regs.h>
	30
	31	#define SPI_BPW_MASK(bits) BIT((bits) - 1)
	32
	33	#define DRIVER_NAME "spi-mt7621"
	34	/* in usec */
	35	#define RALINK_SPI_WAIT_MAX_LOOP 2000
	36
	37	/* SPISTAT register bit field */
	38	#define SPISTAT_BUSY BIT(0)
	39
	40	#define MT7621_SPI_TRANS 0x00
	41	#define SPITRANS_BUSY BIT(16)
	42
	43	#define MT7621_SPI_OPCODE 0x04
	44	#define MT7621_SPI_DATA0 0x08
	45	#define MT7621_SPI_DATA4 0x18
	46	#define SPI_CTL_TX_RX_CNT_MASK 0xff
	47	#define SPI_CTL_START BIT(8)
	48
	49	#define MT7621_SPI_POLAR 0x38
	50	#define MT7621_SPI_MASTER 0x28
	51	#define MT7621_SPI_MOREBUF 0x2c
	52	#define MT7621_SPI_SPACE 0x3c
	53
	54	#define MT7621_CPHA BIT(5)
	55	#define MT7621_CPOL BIT(4)
	56	#define MT7621_LSB_FIRST BIT(3)
	57
b8a95278 SN	58	#define RT2880_SPI_MODE_BITS (SPI_CPOL \| SPI_CPHA \| \
b8a95278 SN	59	SPI_LSB_FIRST \| SPI_CS_HIGH)
1ab7f2a4 JC	60
	61	struct mt7621_spi;
	62
	63	struct mt7621_spi {
	64	struct spi_master *master;
	65	void __iomem *base;
	66	unsigned int sys_freq;
	67	unsigned int speed;
	68	struct clk *clk;
bf732c6b	69	int pending_write;
1ab7f2a4 JC	70
	71	struct mt7621_spi_ops *ops;
	72	};
	73
	74	static inline struct mt7621_spi spidev_to_mt7621_spi(struct spi_device spi)
	75	{
	76	return spi_master_get_devdata(spi->master);
	77	}
	78
	79	static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
	80	{
	81	return ioread32(rs->base + reg);
	82	}
	83
	84	static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
	85	{
	86	iowrite32(val, rs->base + reg);
	87	}
	88
	89	static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
	90	{
	91	u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	92
	93	master \|= 7 << 29;
	94	master \|= 1 << 2;
	95	if (duplex)
	96	master \|= 1 << 10;
	97	else
	98	master &= ~(1 << 10);
	99
	100	mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
bf732c6b	101	rs->pending_write = 0;
1ab7f2a4 JC	102	}
	103
	104	static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
	105	{
	106	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	107	int cs = spi->chip_select;
	108	u32 polar = 0;
	109
6781e751	110	mt7621_spi_reset(rs, cs);
1ab7f2a4 JC	111	if (enable)
	112	polar = BIT(cs);
	113	mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
	114	}
	115
	116	static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
	117	{
	118	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	119	u32 rate;
	120	u32 reg;
	121
	122	dev_dbg(&spi->dev, "speed:%u\n", speed);
	123
	124	rate = DIV_ROUND_UP(rs->sys_freq, speed);
	125	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
	126
	127	if (rate > 4097)
	128	return -EINVAL;
	129
	130	if (rate < 2)
	131	rate = 2;
	132
	133	reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
	134	reg &= ~(0xfff << 16);
	135	reg \|= (rate - 2) << 16;
	136	rs->speed = speed;
	137
	138	reg &= ~MT7621_LSB_FIRST;
	139	if (spi->mode & SPI_LSB_FIRST)
	140	reg \|= MT7621_LSB_FIRST;
	141
	142	reg &= ~(MT7621_CPHA \| MT7621_CPOL);
6e89217c	143	switch (spi->mode & (SPI_CPOL \| SPI_CPHA)) {
d42fd96a SN	144	case SPI_MODE_0:
	145	break;
	146	case SPI_MODE_1:
	147	reg \|= MT7621_CPHA;
	148	break;
	149	case SPI_MODE_2:
	150	reg \|= MT7621_CPOL;
	151	break;
	152	case SPI_MODE_3:
	153	reg \|= MT7621_CPOL \| MT7621_CPHA;
	154	break;
1ab7f2a4 JC	155	}
	156	mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
	157
	158	return 0;
	159	}
	160
a83834c1	161	static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
1ab7f2a4	162	{
1ab7f2a4 JC	163	int i;
	164
	165	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
	166	u32 status;
	167
	168	status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
9c562d84	169	if ((status & SPITRANS_BUSY) == 0)
1ab7f2a4	170	return 0;
1ab7f2a4 JC	171	cpu_relax();
	172	udelay(1);
	173	}
	174
	175	return -ETIMEDOUT;
	176	}
	177
bf732c6b N	178	static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
bf732c6b N	179	int rx_len, u8 *buf)
1ab7f2a4	180	{
bf732c6b N	181	/* Combine with any pending write, and perform one or
	182	* more half-duplex transactions reading 'len' bytes.
	183	* Data to be written is already in MT7621_SPI_DATA*
	184	*/
	185	int tx_len = rs->pending_write;
1ab7f2a4	186
bf732c6b	187	rs->pending_write = 0;
1ab7f2a4	188
bf732c6b N	189	while (rx_len \|\| tx_len) {
	190	int i;
	191	u32 val = (min(tx_len, 4) * 8) << 24;
	192	int rx = min(rx_len, 32);
1ab7f2a4	193
bf732c6b N	194	if (tx_len > 4)
	195	val \|= (tx_len - 4) * 8;
	196	val \|= (rx * 8) << 12;
	197	mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
1ab7f2a4	198
bf732c6b	199	tx_len = 0;
1ab7f2a4	200
bf732c6b N	201	val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
	202	val \|= SPI_CTL_START;
	203	mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
1ab7f2a4	204
bf732c6b	205	mt7621_spi_wait_till_ready(rs);
1ab7f2a4	206
bf732c6b N	207	for (i = 0; i < rx; i++) {
	208	if ((i % 4) == 0)
	209	val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
	210	*buf++ = val & 0xff;
	211	val >>= 8;
	212	}
	213	rx_len -= i;
1ab7f2a4	214	}
bf732c6b	215	}
1ab7f2a4	216
bf732c6b N	217	static inline void mt7621_spi_flush(struct mt7621_spi *rs)
	218	{
	219	mt7621_spi_read_half_duplex(rs, 0, NULL);
	220	}
1ab7f2a4	221
bf732c6b N	222	static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
	223	int tx_len, const u8 *buf)
	224	{
	225	int val = 0;
	226	int len = rs->pending_write;
	227
	228	if (len & 3) {
	229	val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
	230	if (len < 4) {
	231	val <<= (4 - len) * 8;
	232	val = swab32(val);
	233	}
1ab7f2a4	234	}
1ab7f2a4	235
bf732c6b N	236	while (tx_len > 0) {
	237	if (len >= 36) {
	238	rs->pending_write = len;
	239	mt7621_spi_flush(rs);
	240	len = 0;
	241	}
1ab7f2a4	242
bf732c6b N	243	val \|= buf++ << (8 (len & 3));
	244	len++;
	245	if ((len & 3) == 0) {
	246	if (len == 4)
	247	/* The byte-order of the opcode is weird! */
	248	val = swab32(val);
	249	mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
	250	val = 0;
	251	}
	252	tx_len -= 1;
	253	}
	254	if (len & 3) {
	255	if (len < 4) {
	256	val = swab32(val);
	257	val >>= (4 - len) * 8;
	258	}
	259	mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
	260	}
	261	rs->pending_write = len;
	262	}
1ab7f2a4	263
bf732c6b N	264	static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
	265	struct spi_message *m)
	266	{
	267	struct mt7621_spi *rs = spi_master_get_devdata(master);
	268	struct spi_device *spi = m->spi;
	269	unsigned int speed = spi->max_speed_hz;
	270	struct spi_transfer *t = NULL;
	271	int status = 0;
1ab7f2a4	272
a83834c1	273	mt7621_spi_wait_till_ready(rs);
1ab7f2a4	274
bf732c6b N	275	list_for_each_entry(t, &m->transfers, transfer_list)
	276	if (t->speed_hz < speed)
	277	speed = t->speed_hz;
1ab7f2a4	278
bf732c6b N	279	if (mt7621_spi_prepare(spi, speed)) {
	280	status = -EIO;
	281	goto msg_done;
	282	}
1ab7f2a4	283
bf732c6b N	284	mt7621_spi_set_cs(spi, 1);
bf732c6b N	285	m->actual_length = 0;
1ab7f2a4	286	list_for_each_entry(t, &m->transfers, transfer_list) {
bf732c6b N	287	if (t->rx_buf)
	288	mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
	289	else if (t->tx_buf)
	290	mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
	291	m->actual_length += t->len;
1ab7f2a4	292	}
bf732c6b	293	mt7621_spi_flush(rs);
1ab7f2a4	294
bf732c6b	295	mt7621_spi_set_cs(spi, 0);
1ab7f2a4 JC	296	msg_done:
	297	m->status = status;
	298	spi_finalize_current_message(master);
	299
	300	return 0;
	301	}
	302
	303	static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
	304	struct spi_message *m)
	305	{
	306	struct mt7621_spi *rs = spi_master_get_devdata(master);
	307	struct spi_device *spi = m->spi;
	308	unsigned int speed = spi->max_speed_hz;
	309	struct spi_transfer *t = NULL;
	310	int status = 0;
	311	int i, len = 0;
	312	int rx_len = 0;
	313	u32 data[9] = { 0 };
	314	u32 val = 0;
	315
a83834c1	316	mt7621_spi_wait_till_ready(rs);
1ab7f2a4 JC	317
	318	list_for_each_entry(t, &m->transfers, transfer_list) {
	319	const u8 *buf = t->tx_buf;
	320
	321	if (t->rx_buf)
	322	rx_len += t->len;
	323
	324	if (!buf)
	325	continue;
	326
	327	if (WARN_ON(len + t->len > 16)) {
	328	status = -EIO;
	329	goto msg_done;
	330	}
	331
	332	for (i = 0; i < t->len; i++, len++)
	333	data[len / 4] \|= buf[i] << (8 * (len & 3));
	334	if (speed > t->speed_hz)
	335	speed = t->speed_hz;
	336	}
	337
	338	if (WARN_ON(rx_len > 16)) {
	339	status = -EIO;
	340	goto msg_done;
	341	}
	342
	343	if (mt7621_spi_prepare(spi, speed)) {
	344	status = -EIO;
	345	goto msg_done;
	346	}
	347
	348	for (i = 0; i < len; i += 4)
	349	mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
	350
	351	val \|= len * 8;
	352	val \|= (rx_len * 8) << 12;
	353	mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
	354
	355	mt7621_spi_set_cs(spi, 1);
	356
	357	val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
	358	val \|= SPI_CTL_START;
	359	mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
	360
a83834c1	361	mt7621_spi_wait_till_ready(rs);
1ab7f2a4 JC	362
	363	mt7621_spi_set_cs(spi, 0);
	364
	365	for (i = 0; i < rx_len; i += 4)
	366	data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
	367
	368	m->actual_length = rx_len;
	369
	370	len = 0;
	371	list_for_each_entry(t, &m->transfers, transfer_list) {
	372	u8 *buf = t->rx_buf;
	373
	374	if (!buf)
	375	continue;
	376
	377	for (i = 0; i < t->len; i++, len++)
	378	buf[i] = data[len / 4] >> (8 * (len & 3));
	379	}
	380
	381	msg_done:
	382	m->status = status;
	383	spi_finalize_current_message(master);
	384
	385	return 0;
	386	}
	387
	388	static int mt7621_spi_transfer_one_message(struct spi_master *master,
	389	struct spi_message *m)
	390	{
	391	struct spi_device *spi = m->spi;
	392	int cs = spi->chip_select;
	393
	394	if (cs)
	395	return mt7621_spi_transfer_full_duplex(master, m);
	396	return mt7621_spi_transfer_half_duplex(master, m);
	397	}
	398
	399	static int mt7621_spi_setup(struct spi_device *spi)
	400	{
	401	struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
	402
	403	if ((spi->max_speed_hz == 0) \|\|
	404	(spi->max_speed_hz > (rs->sys_freq / 2)))
	405	spi->max_speed_hz = (rs->sys_freq / 2);
	406
	407	if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
	408	dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
	409	spi->max_speed_hz);
	410	return -EINVAL;
	411	}
	412
	413	return 0;
	414	}
	415
	416	static const struct of_device_id mt7621_spi_match[] = {
	417	{ .compatible = "ralink,mt7621-spi" },
	418	{},
	419	};
	420	MODULE_DEVICE_TABLE(of, mt7621_spi_match);
	421
1ab7f2a4 JC	422	static int mt7621_spi_probe(struct platform_device *pdev)
	423	{
	424	const struct of_device_id *match;
	425	struct spi_master *master;
	426	struct mt7621_spi *rs;
1ab7f2a4 JC	427	void __iomem *base;
	428	struct resource *r;
	429	int status = 0;
	430	struct clk *clk;
	431	struct mt7621_spi_ops *ops;
080e00c8	432	int ret;
1ab7f2a4 JC	433
	434	match = of_match_device(mt7621_spi_match, &pdev->dev);
	435	if (!match)
	436	return -EINVAL;
	437	ops = (struct mt7621_spi_ops *)match->data;
	438
	439	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	440	base = devm_ioremap_resource(&pdev->dev, r);
	441	if (IS_ERR(base))
	442	return PTR_ERR(base);
	443
	444	clk = devm_clk_get(&pdev->dev, NULL);
	445	if (IS_ERR(clk)) {
	446	dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
	447	status);
	448	return PTR_ERR(clk);
	449	}
	450
	451	status = clk_prepare_enable(clk);
	452	if (status)
	453	return status;
	454
	455	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
	456	if (master == NULL) {
	457	dev_info(&pdev->dev, "master allocation failed\n");
	458	return -ENOMEM;
	459	}
	460
	461	master->mode_bits = RT2880_SPI_MODE_BITS;
	462
	463	master->setup = mt7621_spi_setup;
	464	master->transfer_one_message = mt7621_spi_transfer_one_message;
	465	master->bits_per_word_mask = SPI_BPW_MASK(8);
	466	master->dev.of_node = pdev->dev.of_node;
	467	master->num_chipselect = 2;
1ab7f2a4 JC	468
	469	dev_set_drvdata(&pdev->dev, master);
	470
	471	rs = spi_master_get_devdata(master);
	472	rs->base = base;
	473	rs->clk = clk;
	474	rs->master = master;
	475	rs->sys_freq = clk_get_rate(rs->clk);
	476	rs->ops = ops;
bf732c6b	477	rs->pending_write = 0;
1ab7f2a4	478	dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
1ab7f2a4	479
080e00c8 SR	480	ret = device_reset(&pdev->dev);
	481	if (ret) {
	482	dev_err(&pdev->dev, "SPI reset failed!\n");
	483	return ret;
	484	}
1ab7f2a4 JC	485
	486	mt7621_spi_reset(rs, 0);
	487
	488	return spi_register_master(master);
	489	}
	490
	491	static int mt7621_spi_remove(struct platform_device *pdev)
	492	{
	493	struct spi_master *master;
	494	struct mt7621_spi *rs;
	495
	496	master = dev_get_drvdata(&pdev->dev);
	497	rs = spi_master_get_devdata(master);
	498
	499	clk_disable(rs->clk);
	500	spi_unregister_master(master);
	501
	502	return 0;
	503	}
	504
	505	MODULE_ALIAS("platform:" DRIVER_NAME);
	506
	507	static struct platform_driver mt7621_spi_driver = {
	508	.driver = {
	509	.name = DRIVER_NAME,
1ab7f2a4 JC	510	.of_match_table = mt7621_spi_match,
	511	},
	512	.probe = mt7621_spi_probe,
	513	.remove = mt7621_spi_remove,
	514	};
	515
	516	module_platform_driver(mt7621_spi_driver);
	517
	518	MODULE_DESCRIPTION("MT7621 SPI driver");
	519	MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
	520	MODULE_LICENSE("GPL");