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Merge tag 'clang-format-for-linus-v5.1-rc5' of git://github.com/ojeda/linux
[thirdparty/kernel/stable.git] / drivers / tty / serial / sh-sci.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
f43dc23d 5 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 6 * Copyright (C) 2015 Glider bvba
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4 17 */
0b3d4ef6
PM		 18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
1da177e4
LT		 21
22#undef DEBUG
23
8fb9631c
LP		 24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
1da177e4 32#include <linux/errno.h>
8fb9631c 33#include <linux/init.h>
1da177e4 34#include <linux/interrupt.h>
1da177e4 35#include <linux/ioport.h>
b96408b4 36#include <linux/ktime.h>
8fb9631c
LP		 37#include <linux/major.h>
38#include <linux/module.h>
1da177e4 39#include <linux/mm.h>
20bdcab8 40#include <linux/of.h>
6e605a01 41#include <linux/of_device.h>
8fb9631c 42#include <linux/platform_device.h>
5e50d2d6 43#include <linux/pm_runtime.h>
73a19e4c 44#include <linux/scatterlist.h>
8fb9631c
LP		 45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
5a0e3ad6 48#include <linux/slab.h>
8fb9631c
LP		 49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
f907c9ea 59#include "serial_mctrl_gpio.h"
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
628c534a
CB		 68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
89b5c1ab
LP		 70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73};
74
75#define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
f4998e55
GU		 81enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
6af27bf2 83 SCI_SCK, /* Optional External Clock */
1270f865
GU		 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 86 SCI_NUM_CLKS
87};
88
69eee8e9
GU		 89/* Bit x set means sampling rate x + 1 is supported */
90#define SCI_SR(x) BIT((x) - 1)
91#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
92a05748
GU		 93#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
69eee8e9
GU		 97#define min_sr(_port) ffs((_port)->sampling_rate_mask)
98#define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100/* Iterate over all supported sampling rates, from high to low */
101#define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
e095ee6b
LP		 105struct plat_sci_reg {
106 u8 offset, size;
107};
108
109struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
e095ee6b
LP		 117};
118
e108b2ca
PM		 119struct sci_port {
120 struct uart_port port;
121
ce6738b6 122 /* Platform configuration */
e095ee6b 123 const struct sci_port_params *params;
daf5a895 124 const struct plat_sci_port *cfg;
69eee8e9 125 unsigned int sampling_rate_mask;
e4d6f911 126 resource_size_t reg_size;
f907c9ea 127 struct mctrl_gpios *gpios;
e108b2ca 128
f4998e55
GU		 129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 132
1fcc91a6 133 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 134 char *irqstr[SCIx_NR_IRQS];
135
73a19e4c
GL		 136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
f43dc23d 138
73a19e4c 139#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235
GU		 140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
73a19e4c
GL		 142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
79904420
GU		 145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
73a19e4c 147 struct scatterlist sg_rx[2];
7b39d901 148 void *rx_buf[2];
73a19e4c 149 size_t buf_len_rx;
73a19e4c 150 struct work_struct work_tx;
b96408b4
UH		 151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
73a19e4c 153#endif
03940376 154 unsigned int rx_frame;
18e8cf15 155 int rx_trigger;
03940376
UH		 156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
fa2abb03 158 u16 hscif_tot;
33f50ffc 159
97ed9790 160 bool has_rtscts;
33f50ffc 161 bool autorts;
e108b2ca
PM		 162};
163
e108b2ca 164#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 165
e108b2ca 166static struct sci_port sci_ports[SCI_NPORTS];
7678f4c2 167static unsigned long sci_ports_in_use;
e108b2ca 168static struct uart_driver sci_uart_driver;
1da177e4 169
e7c98dc7
MT		 170static inline struct sci_port *
171to_sci_port(struct uart_port *uart)
172{
173 return container_of(uart, struct sci_port, port);
174}
175
e095ee6b 176static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
b2f20ed9
LP		 190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 196 },
197
198 /*
a752ba18 199 * Common definitions for legacy IrDA ports.
61a6976b
PM		 200 */
201 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
b2f20ed9
LP		 212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
b2f20ed9
LP		 236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
b2f20ed9
LP		 261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 267 },
268
3af1f8a4
PE		 269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
b2f20ed9
LP		 286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 292 },
293
10c63443
GU		 294 /*
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
61a6976b
PM		 321 /*
322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
b2f20ed9
LP		 335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 347 .regs = {
348 [SCSMR] = { 0x00, 16 },
a1c2fd7e
GU		 349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
e095ee6b 358 },
b2f20ed9
LP		 359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
b2f20ed9
LP		 386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
e095ee6b 414 },
b2f20ed9
LP		 415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
b2f20ed9
LP		 439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
b2f20ed9
LP		 466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
18e8cf15 489 .fifosize = 64,
b2f20ed9
LP		 490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 495 },
496};
497
e095ee6b 498#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 499
61a6976b
PM		 500/*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
506static unsigned int sci_serial_in(struct uart_port *p, int offset)
507{
d3184e68 508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518}
519
520static void sci_serial_out(struct uart_port *p, int offset, int value)
521{
d3184e68 522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530}
531
23241d43
PM		 532static void sci_port_enable(struct sci_port *sci_port)
533{
f4998e55
GU		 534 unsigned int i;
535
23241d43
PM		 536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
f4998e55
GU		 541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 546}
547
548static void sci_port_disable(struct sci_port *sci_port)
549{
f4998e55
GU		 550 unsigned int i;
551
23241d43
PM		 552 if (!sci_port->port.dev)
553 return;
554
f4998e55
GU		 555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 557
558 pm_runtime_put_sync(sci_port->port.dev);
559}
560
e1910fcd
GU		 561static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562{
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571}
572
573static void sci_start_tx(struct uart_port *port)
574{
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578#ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594#endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601}
602
603static void sci_stop_tx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616}
617
618static void sci_start_rx(struct uart_port *port)
619{
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628}
629
630static void sci_stop_rx(struct uart_port *port)
631{
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642}
643
a1b5b43f
GU		 644static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645{
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
b2f20ed9 649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658}
659
0b0cced1
YS		 660#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 662
663#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 664static int sci_poll_get_char(struct uart_port *port)
1da177e4 665{
1da177e4
LT		 666 unsigned short status;
667 int c;
668
e108b2ca 669 do {
b12bb29f 670 status = serial_port_in(port, SCxSR);
1da177e4 671 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 673 continue;
674 }
3f255eb3
JW		 675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
07d2a1a1 680
b12bb29f 681 c = serial_port_in(port, SCxRDR);
07d2a1a1 682
e7c98dc7 683 /* Dummy read */
b12bb29f 684 serial_port_in(port, SCxSR);
a1b5b43f 685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 686
687 return c;
688}
1f6fd5c9 689#endif
1da177e4 690
07d2a1a1 691static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 692{
1da177e4
LT		 693 unsigned short status;
694
1da177e4 695 do {
b12bb29f 696 status = serial_port_in(port, SCxSR);
1da177e4
LT		 697 } while (!(status & SCxSR_TDxE(port)));
698
b12bb29f 699 serial_port_out(port, SCxTDR, c);
a1b5b43f 700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 701}
0b0cced1
YS		 702#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 704
61a6976b 705static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 706{
61a6976b 707 struct sci_port *s = to_sci_port(port);
1da177e4 708
61a6976b
PM		 709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
1da177e4 715 }
41504c39 716
e9d7a45a 717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 718 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 723 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
e9d7a45a
GU		 735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
cfa6eb23 738 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 741 u16 status = serial_port_in(port, SCSPTR);
742
cfa6eb23
GU		 743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
faf02f8f 752 }
d5701647 753}
e108b2ca 754
72b294cf 755static int sci_txfill(struct uart_port *port)
e108b2ca 756{
b2f20ed9
LP		 757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 759 const struct plat_sci_reg *reg;
e108b2ca 760
72b294cf
PM		 761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
b2f20ed9 763 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 764
72b294cf
PM		 765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
b12bb29f 767 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 768
b12bb29f 769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 770}
771
73a19e4c
GL		 772static int sci_txroom(struct uart_port *port)
773{
72b294cf 774 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 775}
776
777static int sci_rxfill(struct uart_port *port)
e108b2ca 778{
b2f20ed9
LP		 779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 781 const struct plat_sci_reg *reg;
72b294cf
PM		 782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
b2f20ed9 785 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
b2f20ed9 789 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 790
b12bb29f 791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 792}
793
1da177e4
LT		 794/* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
798static void sci_transmit_chars(struct uart_port *port)
799{
ebd2c8f6 800 struct circ_buf *xmit = &port->state->xmit;
1da177e4 801 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 802 unsigned short status;
803 unsigned short ctrl;
e108b2ca 804 int count;
1da177e4 805
b12bb29f 806 status = serial_port_in(port, SCxSR);
1da177e4 807 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 808 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 809 if (uart_circ_empty(xmit))
8e698614 810 ctrl &= ~SCSCR_TIE;
e7c98dc7 811 else
8e698614 812 ctrl |= SCSCR_TIE;
b12bb29f 813 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 814 return;
815 }
816
72b294cf 817 count = sci_txroom(port);
1da177e4
LT		 818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
b12bb29f 832 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 833
834 port->icount.tx++;
835 } while (--count > 0);
836
a1b5b43f 837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
93bcefd4 841 if (uart_circ_empty(xmit))
b129a8cc 842 sci_stop_tx(port);
1da177e4 843
1da177e4
LT		 844}
845
846/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 847#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 848
94c8b6db 849static void sci_receive_chars(struct uart_port *port)
1da177e4 850{
227434f8 851 struct tty_port *tport = &port->state->port;
1da177e4
LT		 852 int i, count, copied = 0;
853 unsigned short status;
33f0f88f 854 unsigned char flag;
1da177e4 855
b12bb29f 856 status = serial_port_in(port, SCxSR);
1da177e4
LT		 857 if (!(status & SCxSR_RDxF(port)))
858 return;
859
860 while (1) {
1da177e4 861 /* Don't copy more bytes than there is room for in the buffer */
227434f8 862 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 863
864 /* If for any reason we can't copy more data, we're done! */
865 if (count == 0)
866 break;
867
868 if (port->type == PORT_SCI) {
b12bb29f 869 char c = serial_port_in(port, SCxRDR);
d5cb1319 870 if (uart_handle_sysrq_char(port, c))
1da177e4 871 count = 0;
e7c98dc7 872 else
92a19f9c 873 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 874 } else {
e7c98dc7 875 for (i = 0; i < count; i++) {
b12bb29f 876 char c = serial_port_in(port, SCxRDR);
d97fbbed 877
b12bb29f 878 status = serial_port_in(port, SCxSR);
7d12e780 879 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 880 count--; i--;
881 continue;
882 }
883
884 /* Store data and status */
73a19e4c 885 if (status & SCxSR_FER(port)) {
33f0f88f 886 flag = TTY_FRAME;
d97fbbed 887 port->icount.frame++;
762c69e3 888 dev_notice(port->dev, "frame error\n");
73a19e4c 889 } else if (status & SCxSR_PER(port)) {
33f0f88f 890 flag = TTY_PARITY;
d97fbbed 891 port->icount.parity++;
762c69e3 892 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 893 } else
894 flag = TTY_NORMAL;
762c69e3 895
92a19f9c 896 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 897 }
898 }
899
b12bb29f 900 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 901 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 902
1da177e4
LT		 903 copied += count;
904 port->icount.rx += count;
905 }
906
907 if (copied) {
908 /* Tell the rest of the system the news. New characters! */
2e124b4a 909 tty_flip_buffer_push(tport);
1da177e4 910 } else {
7842055b
UH		 911 /* TTY buffers full; read from RX reg to prevent lockup */
912 serial_port_in(port, SCxRDR);
b12bb29f 913 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 915 }
916}
917
94c8b6db 918static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 919{
920 int copied = 0;
b12bb29f 921 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 922 struct tty_port *tport = &port->state->port;
debf9507 923 struct sci_port *s = to_sci_port(port);
1da177e4 924
3ae988d9 925 /* Handle overruns */
b2f20ed9 926 if (status & s->params->overrun_mask) {
3ae988d9 927 port->icount.overrun++;
d97fbbed 928
3ae988d9
LP		 929 /* overrun error */
930 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
931 copied++;
762c69e3 932
9b971cd2 933 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 934 }
935
e108b2ca 936 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 937 /* frame error */
938 port->icount.frame++;
d97fbbed 939
d5cb1319
LP		 940 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
941 copied++;
762c69e3 942
d5cb1319 943 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 944 }
945
e108b2ca 946 if (status & SCxSR_PER(port)) {
1da177e4 947 /* parity error */
d97fbbed
PM		 948 port->icount.parity++;
949
92a19f9c 950 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 951 copied++;
762c69e3 952
9b971cd2 953 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 954 }
955
33f0f88f 956 if (copied)
2e124b4a 957 tty_flip_buffer_push(tport);
1da177e4
LT		 958
959 return copied;
960}
961
94c8b6db 962static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 963{
92a19f9c 964 struct tty_port *tport = &port->state->port;
debf9507 965 struct sci_port *s = to_sci_port(port);
d3184e68 966 const struct plat_sci_reg *reg;
2e0842a1 967 int copied = 0;
75c249fd 968 u16 status;
d830fa45 969
b2f20ed9 970 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 971 if (!reg->size)
d830fa45
PM		 972 return 0;
973
b2f20ed9
LP		 974 status = serial_port_in(port, s->params->overrun_reg);
975 if (status & s->params->overrun_mask) {
976 status &= ~s->params->overrun_mask;
977 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 978
d97fbbed
PM		 979 port->icount.overrun++;
980
92a19f9c 981 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 982 tty_flip_buffer_push(tport);
d830fa45 983
51b31f1c 984 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 985 copied++;
986 }
987
988 return copied;
989}
990
94c8b6db 991static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 992{
993 int copied = 0;
b12bb29f 994 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 995 struct tty_port *tport = &port->state->port;
1da177e4 996
0b3d4ef6
PM		 997 if (uart_handle_break(port))
998 return 0;
999
d5cb1319 1000 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 1001 port->icount.brk++;
1002
1da177e4 1003 /* Notify of BREAK */
92a19f9c 1004 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1005 copied++;
762c69e3
PM		 1006
1007 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1008 }
1009
33f0f88f 1010 if (copied)
2e124b4a 1011 tty_flip_buffer_push(tport);
e108b2ca 1012
d830fa45
PM		 1013 copied += sci_handle_fifo_overrun(port);
1014
1da177e4
LT		 1015 return copied;
1016}
1017
a380ed46
UH		 1018static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1019{
1020 unsigned int bits;
1021
1022 if (rx_trig < 1)
1023 rx_trig = 1;
1024 if (rx_trig >= port->fifosize)
1025 rx_trig = port->fifosize;
1026
1027 /* HSCIF can be set to an arbitrary level. */
1028 if (sci_getreg(port, HSRTRGR)->size) {
1029 serial_port_out(port, HSRTRGR, rx_trig);
1030 return rx_trig;
1031 }
1032
1033 switch (port->type) {
1034 case PORT_SCIF:
1035 if (rx_trig < 4) {
1036 bits = 0;
1037 rx_trig = 1;
1038 } else if (rx_trig < 8) {
1039 bits = SCFCR_RTRG0;
1040 rx_trig = 4;
1041 } else if (rx_trig < 14) {
1042 bits = SCFCR_RTRG1;
1043 rx_trig = 8;
1044 } else {
1045 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1046 rx_trig = 14;
1047 }
1048 break;
1049 case PORT_SCIFA:
1050 case PORT_SCIFB:
1051 if (rx_trig < 16) {
1052 bits = 0;
1053 rx_trig = 1;
1054 } else if (rx_trig < 32) {
1055 bits = SCFCR_RTRG0;
1056 rx_trig = 16;
1057 } else if (rx_trig < 48) {
1058 bits = SCFCR_RTRG1;
1059 rx_trig = 32;
1060 } else {
1061 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1062 rx_trig = 48;
1063 }
1064 break;
1065 default:
1066 WARN(1, "unknown FIFO configuration");
1067 return 1;
1068 }
1069
1070 serial_port_out(port, SCFCR,
1071 (serial_port_in(port, SCFCR) &
1072 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1073
1074 return rx_trig;
1075}
1076
03940376
UH		 1077static int scif_rtrg_enabled(struct uart_port *port)
1078{
1079 if (sci_getreg(port, HSRTRGR)->size)
1080 return serial_port_in(port, HSRTRGR) != 0;
1081 else
1082 return (serial_port_in(port, SCFCR) &
1083 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1084}
1085
e99e88a9 1086static void rx_fifo_timer_fn(struct timer_list *t)
03940376 1087{
e99e88a9 1088 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
03940376
UH		 1089 struct uart_port *port = &s->port;
1090
1091 dev_dbg(port->dev, "Rx timed out\n");
1092 scif_set_rtrg(port, 1);
1093}
1094
5d23188a
UH		 1095static ssize_t rx_trigger_show(struct device *dev,
1096 struct device_attribute *attr,
1097 char *buf)
1098{
1099 struct uart_port *port = dev_get_drvdata(dev);
1100 struct sci_port *sci = to_sci_port(port);
1101
1102 return sprintf(buf, "%d\n", sci->rx_trigger);
1103}
1104
1105static ssize_t rx_trigger_store(struct device *dev,
1106 struct device_attribute *attr,
1107 const char *buf,
1108 size_t count)
1109{
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1112 int ret;
5d23188a
UH		 1113 long r;
1114
4ab3c51e
DC		 1115 ret = kstrtol(buf, 0, &r);
1116 if (ret)
1117 return ret;
90afa525 1118
5d23188a 1119 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1120 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1121 scif_set_rtrg(port, 1);
1122
5d23188a
UH		 1123 return count;
1124}
1125
1126static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1127
1128static ssize_t rx_fifo_timeout_show(struct device *dev,
1129 struct device_attribute *attr,
1130 char *buf)
1131{
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
fa2abb03 1134 int v;
5d23188a 1135
fa2abb03
UH		 1136 if (port->type == PORT_HSCIF)
1137 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1138 else
1139 v = sci->rx_fifo_timeout;
1140
1141 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1142}
1143
1144static ssize_t rx_fifo_timeout_store(struct device *dev,
1145 struct device_attribute *attr,
1146 const char *buf,
1147 size_t count)
1148{
1149 struct uart_port *port = dev_get_drvdata(dev);
1150 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1151 int ret;
5d23188a
UH		 1152 long r;
1153
4ab3c51e
DC		 1154 ret = kstrtol(buf, 0, &r);
1155 if (ret)
1156 return ret;
fa2abb03
UH		 1157
1158 if (port->type == PORT_HSCIF) {
1159 if (r < 0 || r > 3)
1160 return -EINVAL;
1161 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1162 } else {
1163 sci->rx_fifo_timeout = r;
1164 scif_set_rtrg(port, 1);
1165 if (r > 0)
e99e88a9 1166 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
fa2abb03
UH		 1167 }
1168
5d23188a
UH		 1169 return count;
1170}
1171
b6b996b6 1172static DEVICE_ATTR_RW(rx_fifo_timeout);
5d23188a
UH		 1173
1174
73a19e4c 1175#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1176static void sci_dma_tx_complete(void *arg)
1177{
1178 struct sci_port *s = arg;
1179 struct uart_port *port = &s->port;
1180 struct circ_buf *xmit = &port->state->xmit;
1181 unsigned long flags;
73a19e4c 1182
e1910fcd 1183 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1184
e1910fcd 1185 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1186
e1910fcd
GU		 1187 xmit->tail += s->tx_dma_len;
1188 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1189
e1910fcd 1190 port->icount.tx += s->tx_dma_len;
1da177e4 1191
e1910fcd
GU		 1192 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1193 uart_write_wakeup(port);
1da177e4 1194
e1910fcd
GU		 1195 if (!uart_circ_empty(xmit)) {
1196 s->cookie_tx = 0;
1197 schedule_work(&s->work_tx);
1198 } else {
1199 s->cookie_tx = -EINVAL;
1200 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1201 u16 ctrl = serial_port_in(port, SCSCR);
1202 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1203 }
1204 }
1da177e4 1205
fd78a76a 1206 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1207}
1208
e1910fcd
GU		 1209/* Locking: called with port lock held */
1210static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1211{
e1910fcd
GU		 1212 struct uart_port *port = &s->port;
1213 struct tty_port *tport = &port->state->port;
1214 int copied;
1da177e4 1215
e1910fcd 1216 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1217 if (copied < count)
e1910fcd 1218 port->icount.buf_overrun++;
1da177e4 1219
e1910fcd 1220 port->icount.rx += copied;
1da177e4 1221
e1910fcd 1222 return copied;
1da177e4
LT		 1223}
1224
e1910fcd 1225static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1226{
e1910fcd 1227 unsigned int i;
1da177e4 1228
e1910fcd
GU		 1229 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1230 if (s->active_rx == s->cookie_rx[i])
1231 return i;
1da177e4 1232
e1910fcd 1233 return -1;
1da177e4
LT		 1234}
1235
11b3770d
GU		 1236static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1237{
1238 unsigned int i;
1239
1240 s->chan_rx = NULL;
1241 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1242 s->cookie_rx[i] = -EINVAL;
1243 s->active_rx = 0;
1244}
1245
8fcf7a65 1246static void sci_dma_rx_release(struct sci_port *s)
f43dc23d 1247{
2c4ee235 1248 struct dma_chan *chan = s->chan_rx_saved;
e1910fcd 1249
11b3770d
GU		 1250 s->chan_rx_saved = NULL;
1251 sci_dma_rx_chan_invalidate(s);
6eefc68d 1252 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1253 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1254 sg_dma_address(&s->sg_rx[0]));
1255 dma_release_channel(chan);
f43dc23d
PM		 1256}
1257
b96408b4
UH		 1258static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1259{
1260 long sec = usec / 1000000;
1261 long nsec = (usec % 1000000) * 1000;
1262 ktime_t t = ktime_set(sec, nsec);
1263
1264 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1265}
1266
38766e4b
GU		 1267static void sci_dma_rx_reenable_irq(struct sci_port *s)
1268{
1269 struct uart_port *port = &s->port;
1270 u16 scr;
1271
1272 /* Direct new serial port interrupts back to CPU */
1273 scr = serial_port_in(port, SCSCR);
1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~SCSCR_RDRQE;
1276 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1277 }
1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1279}
1280
e1910fcd 1281static void sci_dma_rx_complete(void *arg)
1da177e4 1282{
e1910fcd 1283 struct sci_port *s = arg;
1d3db608 1284 struct dma_chan *chan = s->chan_rx;
e1910fcd 1285 struct uart_port *port = &s->port;
67f462b0 1286 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1287 unsigned long flags;
1288 int active, count = 0;
1da177e4 1289
e1910fcd
GU		 1290 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1291 s->active_rx);
cb772fe7 1292
e1910fcd 1293 spin_lock_irqsave(&port->lock, flags);
1da177e4 1294
e1910fcd
GU		 1295 active = sci_dma_rx_find_active(s);
1296 if (active >= 0)
1297 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1298
b96408b4 1299 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
f43dc23d 1300
e1910fcd
GU		 1301 if (count)
1302 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1303
67f462b0
GU		 1304 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1305 DMA_DEV_TO_MEM,
1306 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1307 if (!desc)
1308 goto fail;
1309
1310 desc->callback = sci_dma_rx_complete;
1311 desc->callback_param = s;
1312 s->cookie_rx[active] = dmaengine_submit(desc);
1313 if (dma_submit_error(s->cookie_rx[active]))
1314 goto fail;
1315
1316 s->active_rx = s->cookie_rx[!active];
1317
1d3db608
MHF		 1318 dma_async_issue_pending(chan);
1319
6fc5a520 1320 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1321 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1322 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1323 return;
1324
1325fail:
1326 spin_unlock_irqrestore(&port->lock, flags);
1327 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
2c4ee235
GU		 1328 /* Switch to PIO */
1329 spin_lock_irqsave(&port->lock, flags);
26f07399
GU		 1330 dmaengine_terminate_async(chan);
1331 sci_dma_rx_chan_invalidate(s);
1332 sci_dma_rx_reenable_irq(s);
2c4ee235 1333 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1334}
1335
8fcf7a65 1336static void sci_dma_tx_release(struct sci_port *s)
1da177e4 1337{
2c4ee235 1338 struct dma_chan *chan = s->chan_tx_saved;
1da177e4 1339
f6611317 1340 cancel_work_sync(&s->work_tx);
2c4ee235 1341 s->chan_tx_saved = s->chan_tx = NULL;
e1910fcd 1342 s->cookie_tx = -EINVAL;
6eefc68d 1343 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1344 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1345 DMA_TO_DEVICE);
1346 dma_release_channel(chan);
e1910fcd 1347}
d535a230 1348
8fcf7a65 1349static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
e1910fcd
GU		 1350{
1351 struct dma_chan *chan = s->chan_rx;
2c4ee235
GU		 1352 struct uart_port *port = &s->port;
1353 unsigned long flags;
e1910fcd 1354 int i;
073e84c9 1355
e1910fcd
GU		 1356 for (i = 0; i < 2; i++) {
1357 struct scatterlist *sg = &s->sg_rx[i];
1358 struct dma_async_tx_descriptor *desc;
1da177e4 1359
e1910fcd
GU		 1360 desc = dmaengine_prep_slave_sg(chan,
1361 sg, 1, DMA_DEV_TO_MEM,
1362 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1363 if (!desc)
1364 goto fail;
501b825d 1365
e1910fcd
GU		 1366 desc->callback = sci_dma_rx_complete;
1367 desc->callback_param = s;
1368 s->cookie_rx[i] = dmaengine_submit(desc);
1369 if (dma_submit_error(s->cookie_rx[i]))
1370 goto fail;
9174fc8f 1371
e1910fcd 1372 }
9174fc8f 1373
e1910fcd 1374 s->active_rx = s->cookie_rx[0];
9174fc8f 1375
e1910fcd 1376 dma_async_issue_pending(chan);
71ab1c03 1377 return 0;
9174fc8f 1378
e1910fcd 1379fail:
dd1f2250
GU		 1380 /* Switch to PIO */
1381 if (!port_lock_held)
1382 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1383 if (i)
6eefc68d 1384 dmaengine_terminate_async(chan);
11b3770d 1385 sci_dma_rx_chan_invalidate(s);
2c4ee235 1386 sci_start_rx(port);
dd1f2250
GU		 1387 if (!port_lock_held)
1388 spin_unlock_irqrestore(&port->lock, flags);
71ab1c03 1389 return -EAGAIN;
e1910fcd 1390}
9174fc8f 1391
8fcf7a65 1392static void sci_dma_tx_work_fn(struct work_struct *work)
1da177e4 1393{
e1910fcd
GU		 1394 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1395 struct dma_async_tx_descriptor *desc;
1396 struct dma_chan *chan = s->chan_tx;
1397 struct uart_port *port = &s->port;
1398 struct circ_buf *xmit = &port->state->xmit;
2c4ee235 1399 unsigned long flags;
e1910fcd 1400 dma_addr_t buf;
1da177e4 1401
9174fc8f 1402 /*
e1910fcd
GU		 1403 * DMA is idle now.
1404 * Port xmit buffer is already mapped, and it is one page... Just adjust
1405 * offsets and lengths. Since it is a circular buffer, we have to
1406 * transmit till the end, and then the rest. Take the port lock to get a
1407 * consistent xmit buffer state.
9174fc8f 1408 */
e1910fcd
GU		 1409 spin_lock_irq(&port->lock);
1410 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1411 s->tx_dma_len = min_t(unsigned int,
1412 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1413 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1414 spin_unlock_irq(&port->lock);
0e8963de 1415
e1910fcd
GU		 1416 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1417 DMA_MEM_TO_DEV,
1418 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1419 if (!desc) {
1420 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
2c4ee235 1421 goto switch_to_pio;
e1910fcd 1422 }
0e8963de 1423
e1910fcd
GU		 1424 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1425 DMA_TO_DEVICE);
1da177e4 1426
e1910fcd
GU		 1427 spin_lock_irq(&port->lock);
1428 desc->callback = sci_dma_tx_complete;
1429 desc->callback_param = s;
1430 spin_unlock_irq(&port->lock);
1431 s->cookie_tx = dmaengine_submit(desc);
1432 if (dma_submit_error(s->cookie_tx)) {
1433 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
2c4ee235 1434 goto switch_to_pio;
1da177e4 1435 }
1da177e4 1436
e1910fcd
GU		 1437 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1438 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1439
e1910fcd 1440 dma_async_issue_pending(chan);
2c4ee235
GU		 1441 return;
1442
1443switch_to_pio:
1444 spin_lock_irqsave(&port->lock, flags);
1445 s->chan_tx = NULL;
1446 sci_start_tx(port);
1447 spin_unlock_irqrestore(&port->lock, flags);
1448 return;
1da177e4
LT		 1449}
1450
8fcf7a65 1451static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1da177e4 1452{
b96408b4 1453 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
e7327c09 1454 struct dma_chan *chan = s->chan_rx;
e1910fcd 1455 struct uart_port *port = &s->port;
67f462b0
GU		 1456 struct dma_tx_state state;
1457 enum dma_status status;
1458 unsigned long flags;
1459 unsigned int read;
1460 int active, count;
67f462b0 1461
67f462b0 1462 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1463
6fc5a520
TA		 1464 spin_lock_irqsave(&port->lock, flags);
1465
67f462b0
GU		 1466 active = sci_dma_rx_find_active(s);
1467 if (active < 0) {
1468 spin_unlock_irqrestore(&port->lock, flags);
b96408b4 1469 return HRTIMER_NORESTART;
67f462b0
GU		 1470 }
1471
1472 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1473 if (status == DMA_COMPLETE) {
6fc5a520 1474 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1475 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1476 s->active_rx, active);
3b963042
MHF		 1477
1478 /* Let packet complete handler take care of the packet */
b96408b4 1479 return HRTIMER_NORESTART;
3b963042 1480 }
67f462b0 1481
e7327c09
MHF		 1482 dmaengine_pause(chan);
1483
1484 /*
1485 * sometimes DMA transfer doesn't stop even if it is stopped and
1486 * data keeps on coming until transaction is complete so check
1487 * for DMA_COMPLETE again
1488 * Let packet complete handler take care of the packet
1489 */
1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1491 if (status == DMA_COMPLETE) {
1492 spin_unlock_irqrestore(&port->lock, flags);
1493 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
b96408b4 1494 return HRTIMER_NORESTART;
e7327c09
MHF		 1495 }
1496
67f462b0 1497 /* Handle incomplete DMA receive */
6eefc68d 1498 dmaengine_terminate_async(s->chan_rx);
67f462b0 1499 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1500
1501 if (read) {
1502 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1503 if (count)
1504 tty_flip_buffer_push(&port->state->port);
1505 }
1506
756981be 1507 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
8fcf7a65 1508 sci_dma_rx_submit(s, true);
371cfed3 1509
38766e4b 1510 sci_dma_rx_reenable_irq(s);
371cfed3
MHF		 1511
1512 spin_unlock_irqrestore(&port->lock, flags);
b96408b4
UH		 1513
1514 return HRTIMER_NORESTART;
1da177e4
LT		 1515}
1516
ff441129 1517static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1518 enum dma_transfer_direction dir)
ff441129 1519{
ff441129
GU		 1520 struct dma_chan *chan;
1521 struct dma_slave_config cfg;
1522 int ret;
1523
219fb0c1
LP		 1524 chan = dma_request_slave_channel(port->dev,
1525 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1526 if (!chan) {
c58a3ae5 1527 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1528 return NULL;
1529 }
1530
1531 memset(&cfg, 0, sizeof(cfg));
1532 cfg.direction = dir;
1533 if (dir == DMA_MEM_TO_DEV) {
1534 cfg.dst_addr = port->mapbase +
1535 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1536 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1537 } else {
1538 cfg.src_addr = port->mapbase +
1539 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1540 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1541 }
1542
1543 ret = dmaengine_slave_config(chan, &cfg);
1544 if (ret) {
1545 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1546 dma_release_channel(chan);
1547 return NULL;
1548 }
1549
1550 return chan;
1551}
1552
e1910fcd 1553static void sci_request_dma(struct uart_port *port)
73a19e4c 1554{
e1910fcd 1555 struct sci_port *s = to_sci_port(port);
e1910fcd 1556 struct dma_chan *chan;
73a19e4c 1557
e1910fcd 1558 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1559
219fb0c1 1560 if (!port->dev->of_node)
e1910fcd 1561 return;
73a19e4c 1562
e1910fcd 1563 s->cookie_tx = -EINVAL;
7464779f
AL		 1564
1565 /*
1566 * Don't request a dma channel if no channel was specified
1567 * in the device tree.
1568 */
1569 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1570 return;
1571
219fb0c1 1572 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1573 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1574 if (chan) {
e1910fcd
GU		 1575 /* UART circular tx buffer is an aligned page. */
1576 s->tx_dma_addr = dma_map_single(chan->device->dev,
1577 port->state->xmit.buf,
1578 UART_XMIT_SIZE,
1579 DMA_TO_DEVICE);
1580 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1581 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1582 dma_release_channel(chan);
e1910fcd
GU		 1583 } else {
1584 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1585 __func__, UART_XMIT_SIZE,
1586 port->state->xmit.buf, &s->tx_dma_addr);
2c4ee235 1587
8fcf7a65 1588 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
2c4ee235 1589 s->chan_tx_saved = s->chan_tx = chan;
49d4bcad 1590 }
3089f381
GL		 1591 }
1592
219fb0c1 1593 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1594 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1595 if (chan) {
1596 unsigned int i;
1597 dma_addr_t dma;
1598 void *buf;
73a19e4c 1599
e1910fcd
GU		 1600 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1601 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1602 &dma, GFP_KERNEL);
1603 if (!buf) {
1604 dev_warn(port->dev,
1605 "Failed to allocate Rx dma buffer, using PIO\n");
1606 dma_release_channel(chan);
e1910fcd
GU		 1607 return;
1608 }
73a19e4c 1609
e1910fcd
GU		 1610 for (i = 0; i < 2; i++) {
1611 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1612
e1910fcd
GU		 1613 sg_init_table(sg, 1);
1614 s->rx_buf[i] = buf;
1615 sg_dma_address(sg) = dma;
d09959e7 1616 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1617
e1910fcd
GU		 1618 buf += s->buf_len_rx;
1619 dma += s->buf_len_rx;
1620 }
1621
b96408b4 1622 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
8fcf7a65 1623 s->rx_timer.function = sci_dma_rx_timer_fn;
e1910fcd 1624
202dc3cc
GU		 1625 s->chan_rx_saved = s->chan_rx = chan;
1626
756981be 1627 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
8fcf7a65 1628 sci_dma_rx_submit(s, false);
e1910fcd 1629 }
0533502d
GU		 1630}
1631
e1910fcd 1632static void sci_free_dma(struct uart_port *port)
73a19e4c 1633{
e1910fcd 1634 struct sci_port *s = to_sci_port(port);
73a19e4c 1635
2c4ee235 1636 if (s->chan_tx_saved)
8fcf7a65 1637 sci_dma_tx_release(s);
2c4ee235 1638 if (s->chan_rx_saved)
8fcf7a65 1639 sci_dma_rx_release(s);
e1910fcd 1640}
1cf4a7ef
GU		 1641
1642static void sci_flush_buffer(struct uart_port *port)
1643{
1644 /*
1645 * In uart_flush_buffer(), the xmit circular buffer has just been
1646 * cleared, so we have to reset tx_dma_len accordingly.
1647 */
1648 to_sci_port(port)->tx_dma_len = 0;
1649}
1650#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1651static inline void sci_request_dma(struct uart_port *port)
1652{
1653}
73a19e4c 1654
e1910fcd
GU		 1655static inline void sci_free_dma(struct uart_port *port)
1656{
1657}
1cf4a7ef
GU		 1658
1659#define sci_flush_buffer NULL
1660#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1661
e1910fcd
GU		 1662static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1663{
e1910fcd
GU		 1664 struct uart_port *port = ptr;
1665 struct sci_port *s = to_sci_port(port);
73a19e4c 1666
03940376 1667#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1668 if (s->chan_rx) {
1669 u16 scr = serial_port_in(port, SCSCR);
1670 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1671
e1910fcd
GU		 1672 /* Disable future Rx interrupts */
1673 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1674 disable_irq_nosync(irq);
1675 scr |= SCSCR_RDRQE;
1676 } else {
8fcf7a65 1677 if (sci_dma_rx_submit(s, false) < 0)
71ab1c03
GU		 1678 goto handle_pio;
1679
e1910fcd
GU		 1680 scr &= ~SCSCR_RIE;
1681 }
1682 serial_port_out(port, SCSCR, scr);
1683 /* Clear current interrupt */
1684 serial_port_out(port, SCxSR,
1685 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
b96408b4 1686 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
e1910fcd 1687 jiffies, s->rx_timeout);
b96408b4 1688 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
73a19e4c 1689
e1910fcd
GU		 1690 return IRQ_HANDLED;
1691 }
71ab1c03
GU		 1692
1693handle_pio:
e1910fcd 1694#endif
73a19e4c 1695
03940376
UH		 1696 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1697 if (!scif_rtrg_enabled(port))
1698 scif_set_rtrg(port, s->rx_trigger);
1699
1700 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
b96408b4 1701 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
03940376
UH		 1702 }
1703
e1910fcd
GU		 1704 /* I think sci_receive_chars has to be called irrespective
1705 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1706 * to be disabled?
1707 */
ed8c8e1e 1708 sci_receive_chars(port);
e1910fcd
GU		 1709
1710 return IRQ_HANDLED;
73a19e4c
GL		 1711}
1712
e1910fcd 1713static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1714{
e1910fcd 1715 struct uart_port *port = ptr;
04928b79 1716 unsigned long flags;
73a19e4c 1717
04928b79 1718 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1719 sci_transmit_chars(port);
04928b79 1720 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1721
1722 return IRQ_HANDLED;
73a19e4c
GL		 1723}
1724
628c534a
CB		 1725static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1726{
1727 struct uart_port *port = ptr;
1728
1729 /* Handle BREAKs */
1730 sci_handle_breaks(port);
1731 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1732
1733 return IRQ_HANDLED;
1734}
8b0bbd95 1735
e1910fcd 1736static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1737{
e1910fcd
GU		 1738 struct uart_port *port = ptr;
1739 struct sci_port *s = to_sci_port(port);
73a19e4c 1740
628c534a 1741 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
8b0bbd95
CB		 1742 /* Break and Error interrupts are muxed */
1743 unsigned short ssr_status = serial_port_in(port, SCxSR);
1744
1745 /* Break Interrupt */
1746 if (ssr_status & SCxSR_BRK(port))
1747 sci_br_interrupt(irq, ptr);
1748
1749 /* Break only? */
1750 if (!(ssr_status & SCxSR_ERRORS(port)))
1751 return IRQ_HANDLED;
1752 }
1753
e1910fcd
GU		 1754 /* Handle errors */
1755 if (port->type == PORT_SCI) {
1756 if (sci_handle_errors(port)) {
1757 /* discard character in rx buffer */
1758 serial_port_in(port, SCxSR);
1759 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1760 }
1761 } else {
1762 sci_handle_fifo_overrun(port);
1763 if (!s->chan_rx)
ed8c8e1e 1764 sci_receive_chars(port);
e1910fcd
GU		 1765 }
1766
1767 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1768
1769 /* Kick the transmission */
1770 if (!s->chan_tx)
1771 sci_tx_interrupt(irq, ptr);
1772
1773 return IRQ_HANDLED;
73a19e4c
GL		 1774}
1775
e1910fcd
GU		 1776static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1777{
1778 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1779 struct uart_port *port = ptr;
1780 struct sci_port *s = to_sci_port(port);
1781 irqreturn_t ret = IRQ_NONE;
73a19e4c 1782
e1910fcd
GU		 1783 ssr_status = serial_port_in(port, SCxSR);
1784 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1785 if (s->params->overrun_reg == SCxSR)
e1910fcd 1786 orer_status = ssr_status;
b2f20ed9
LP		 1787 else if (sci_getreg(port, s->params->overrun_reg)->size)
1788 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1789
e1910fcd 1790 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1791
e1910fcd
GU		 1792 /* Tx Interrupt */
1793 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1794 !s->chan_tx)
1795 ret = sci_tx_interrupt(irq, ptr);
658daa95 1796
e1910fcd
GU		 1797 /*
1798 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1799 * DR flags
1800 */
1801 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1802 (scr_status & SCSCR_RIE))
1803 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1804
e1910fcd
GU		 1805 /* Error Interrupt */
1806 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1807 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1808
e1910fcd
GU		 1809 /* Break Interrupt */
1810 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1811 ret = sci_br_interrupt(irq, ptr);
1812
1813 /* Overrun Interrupt */
b2f20ed9 1814 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1815 sci_handle_fifo_overrun(port);
1816 ret = IRQ_HANDLED;
73a19e4c 1817 }
73a19e4c 1818
e1910fcd
GU		 1819 return ret;
1820}
73a19e4c 1821
e1910fcd
GU		 1822static const struct sci_irq_desc {
1823 const char *desc;
1824 irq_handler_t handler;
1825} sci_irq_desc[] = {
1826 /*
1827 * Split out handlers, the default case.
1828 */
1829 [SCIx_ERI_IRQ] = {
1830 .desc = "rx err",
1831 .handler = sci_er_interrupt,
1832 },
3089f381 1833
e1910fcd
GU		 1834 [SCIx_RXI_IRQ] = {
1835 .desc = "rx full",
1836 .handler = sci_rx_interrupt,
1837 },
47aceb92 1838
e1910fcd
GU		 1839 [SCIx_TXI_IRQ] = {
1840 .desc = "tx empty",
1841 .handler = sci_tx_interrupt,
1842 },
73a19e4c 1843
e1910fcd
GU		 1844 [SCIx_BRI_IRQ] = {
1845 .desc = "break",
1846 .handler = sci_br_interrupt,
1847 },
73a19e4c 1848
628c534a
CB		 1849 [SCIx_DRI_IRQ] = {
1850 .desc = "rx ready",
1851 .handler = sci_rx_interrupt,
1852 },
1853
1854 [SCIx_TEI_IRQ] = {
1855 .desc = "tx end",
1856 .handler = sci_tx_interrupt,
1857 },
1858
73a19e4c 1859 /*
e1910fcd 1860 * Special muxed handler.
73a19e4c 1861 */
e1910fcd
GU		 1862 [SCIx_MUX_IRQ] = {
1863 .desc = "mux",
1864 .handler = sci_mpxed_interrupt,
1865 },
1866};
73a19e4c 1867
e1910fcd
GU		 1868static int sci_request_irq(struct sci_port *port)
1869{
1870 struct uart_port *up = &port->port;
628c534a 1871 int i, j, w, ret = 0;
73a19e4c 1872
e1910fcd
GU		 1873 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1874 const struct sci_irq_desc *desc;
1875 int irq;
73a19e4c 1876
628c534a
CB		 1877 /* Check if already registered (muxed) */
1878 for (w = 0; w < i; w++)
1879 if (port->irqs[w] == port->irqs[i])
1880 w = i + 1;
1881 if (w > i)
1882 continue;
1883
e1910fcd
GU		 1884 if (SCIx_IRQ_IS_MUXED(port)) {
1885 i = SCIx_MUX_IRQ;
1886 irq = up->irq;
1887 } else {
1888 irq = port->irqs[i];
1889
1890 /*
1891 * Certain port types won't support all of the
1892 * available interrupt sources.
1893 */
1894 if (unlikely(irq < 0))
1895 continue;
1896 }
1897
1898 desc = sci_irq_desc + i;
628c534a
CB		 1899 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1900 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1901 if (!port->irqstr[j]) {
1902 ret = -ENOMEM;
e1910fcd 1903 goto out_nomem;
623ac1d4 1904 }
e1910fcd
GU		 1905
1906 ret = request_irq(irq, desc->handler, up->irqflags,
1907 port->irqstr[j], port);
1908 if (unlikely(ret)) {
1909 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1910 goto out_noirq;
1911 }
73a19e4c
GL		 1912 }
1913
e1910fcd 1914 return 0;
1da177e4 1915
e1910fcd
GU		 1916out_noirq:
1917 while (--i >= 0)
1918 free_irq(port->irqs[i], port);
f43dc23d 1919
e1910fcd
GU		 1920out_nomem:
1921 while (--j >= 0)
1922 kfree(port->irqstr[j]);
f43dc23d 1923
e1910fcd 1924 return ret;
1da177e4
LT		 1925}
1926
e1910fcd 1927static void sci_free_irq(struct sci_port *port)
1da177e4 1928{
4d95987a 1929 int i, j;
1da177e4 1930
e1910fcd
GU		 1931 /*
1932 * Intentionally in reverse order so we iterate over the muxed
1933 * IRQ first.
1934 */
1935 for (i = 0; i < SCIx_NR_IRQS; i++) {
1936 int irq = port->irqs[i];
f43dc23d 1937
e1910fcd
GU		 1938 /*
1939 * Certain port types won't support all of the available
1940 * interrupt sources.
1941 */
1942 if (unlikely(irq < 0))
1943 continue;
f43dc23d 1944
4d95987a
CB		 1945 /* Check if already freed (irq was muxed) */
1946 for (j = 0; j < i; j++)
1947 if (port->irqs[j] == irq)
1948 j = i + 1;
1949 if (j > i)
1950 continue;
1951
e1910fcd
GU		 1952 free_irq(port->irqs[i], port);
1953 kfree(port->irqstr[i]);
f43dc23d 1954
e1910fcd
GU		 1955 if (SCIx_IRQ_IS_MUXED(port)) {
1956 /* If there's only one IRQ, we're done. */
1957 return;
1958 }
1959 }
1da177e4
LT		 1960}
1961
e1910fcd 1962static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1963{
e1910fcd
GU		 1964 unsigned short status = serial_port_in(port, SCxSR);
1965 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1966
e1910fcd 1967 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1968}
1969
33f50ffc
GU		 1970static void sci_set_rts(struct uart_port *port, bool state)
1971{
1972 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1973 u16 data = serial_port_in(port, SCPDR);
1974
1975 /* Active low */
1976 if (state)
1977 data &= ~SCPDR_RTSD;
1978 else
1979 data |= SCPDR_RTSD;
1980 serial_port_out(port, SCPDR, data);
1981
1982 /* RTS# is output */
1983 serial_port_out(port, SCPCR,
1984 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1985 } else if (sci_getreg(port, SCSPTR)->size) {
1986 u16 ctrl = serial_port_in(port, SCSPTR);
1987
1988 /* Active low */
1989 if (state)
1990 ctrl &= ~SCSPTR_RTSDT;
1991 else
1992 ctrl |= SCSPTR_RTSDT;
1993 serial_port_out(port, SCSPTR, ctrl);
1994 }
1995}
1996
1997static bool sci_get_cts(struct uart_port *port)
1998{
1999 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2000 /* Active low */
2001 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2002 } else if (sci_getreg(port, SCSPTR)->size) {
2003 /* Active low */
2004 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2005 }
2006
2007 return true;
2008}
2009
e1910fcd
GU		 2010/*
2011 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2012 * CTS/RTS is supported in hardware by at least one port and controlled
2013 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2014 * handled via the ->init_pins() op, which is a bit of a one-way street,
2015 * lacking any ability to defer pin control -- this will later be
2016 * converted over to the GPIO framework).
2017 *
2018 * Other modes (such as loopback) are supported generically on certain
2019 * port types, but not others. For these it's sufficient to test for the
2020 * existence of the support register and simply ignore the port type.
2021 */
2022static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 2023{
f907c9ea
GU		 2024 struct sci_port *s = to_sci_port(port);
2025
e1910fcd
GU		 2026 if (mctrl & TIOCM_LOOP) {
2027 const struct plat_sci_reg *reg;
f43dc23d 2028
e1910fcd
GU		 2029 /*
2030 * Standard loopback mode for SCFCR ports.
2031 */
2032 reg = sci_getreg(port, SCFCR);
2033 if (reg->size)
2034 serial_port_out(port, SCFCR,
2035 serial_port_in(port, SCFCR) |
2036 SCFCR_LOOP);
2037 }
f907c9ea
GU		 2038
2039 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 2040
97ed9790 2041 if (!s->has_rtscts)
33f50ffc
GU		 2042 return;
2043
2044 if (!(mctrl & TIOCM_RTS)) {
2045 /* Disable Auto RTS */
2046 serial_port_out(port, SCFCR,
2047 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2048
2049 /* Clear RTS */
2050 sci_set_rts(port, 0);
2051 } else if (s->autorts) {
2052 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2053 /* Enable RTS# pin function */
2054 serial_port_out(port, SCPCR,
2055 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2056 }
2057
2058 /* Enable Auto RTS */
2059 serial_port_out(port, SCFCR,
2060 serial_port_in(port, SCFCR) | SCFCR_MCE);
2061 } else {
2062 /* Set RTS */
2063 sci_set_rts(port, 1);
2064 }
e1910fcd 2065}
f43dc23d 2066
e1910fcd
GU		 2067static unsigned int sci_get_mctrl(struct uart_port *port)
2068{
f907c9ea
GU		 2069 struct sci_port *s = to_sci_port(port);
2070 struct mctrl_gpios *gpios = s->gpios;
2071 unsigned int mctrl = 0;
2072
2073 mctrl_gpio_get(gpios, &mctrl);
2074
e1910fcd
GU		 2075 /*
2076 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 2077 * else is wired up.
e1910fcd 2078 */
33f50ffc
GU		 2079 if (s->autorts) {
2080 if (sci_get_cts(port))
2081 mctrl |= TIOCM_CTS;
2082 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 2083 mctrl |= TIOCM_CTS;
33f50ffc 2084 }
f907c9ea
GU		 2085 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2086 mctrl |= TIOCM_DSR;
2087 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2088 mctrl |= TIOCM_CAR;
2089
2090 return mctrl;
2091}
2092
2093static void sci_enable_ms(struct uart_port *port)
2094{
2095 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2096}
2097
1da177e4
LT		 2098static void sci_break_ctl(struct uart_port *port, int break_state)
2099{
bbb4ce50 2100 unsigned short scscr, scsptr;
1be22663 2101 unsigned long flags;
bbb4ce50 2102
a4e02f6d 2103 /* check wheter the port has SCSPTR */
abbf121f 2104 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2105 /*
2106 * Not supported by hardware. Most parts couple break and rx
2107 * interrupts together, with break detection always enabled.
2108 */
a4e02f6d 2109 return;
bbb4ce50 2110 }
a4e02f6d 2111
1be22663 2112 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2113 scsptr = serial_port_in(port, SCSPTR);
2114 scscr = serial_port_in(port, SCSCR);
2115
2116 if (break_state == -1) {
2117 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2118 scscr &= ~SCSCR_TE;
2119 } else {
2120 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2121 scscr |= SCSCR_TE;
2122 }
2123
2124 serial_port_out(port, SCSPTR, scsptr);
2125 serial_port_out(port, SCSCR, scscr);
1be22663 2126 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2127}
2128
2129static int sci_startup(struct uart_port *port)
2130{
a5660ada 2131 struct sci_port *s = to_sci_port(port);
073e84c9 2132 int ret;
1da177e4 2133
73a19e4c
GL		 2134 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2135
3c910176
TA		 2136 sci_request_dma(port);
2137
073e84c9 2138 ret = sci_request_irq(s);
3c910176
TA		 2139 if (unlikely(ret < 0)) {
2140 sci_free_dma(port);
073e84c9 2141 return ret;
3c910176 2142 }
073e84c9 2143
1da177e4
LT		 2144 return 0;
2145}
2146
2147static void sci_shutdown(struct uart_port *port)
2148{
a5660ada 2149 struct sci_port *s = to_sci_port(port);
33b48e16 2150 unsigned long flags;
5fd2b6ee 2151 u16 scr;
1da177e4 2152
73a19e4c
GL		 2153 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2154
33f50ffc 2155 s->autorts = false;
f907c9ea
GU		 2156 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2157
33b48e16 2158 spin_lock_irqsave(&port->lock, flags);
1da177e4 2159 sci_stop_rx(port);
b129a8cc 2160 sci_stop_tx(port);
fa2abb03
UH		 2161 /*
2162 * Stop RX and TX, disable related interrupts, keep clock source
2163 * and HSCIF TOT bits
2164 */
5fd2b6ee 2165 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2166 serial_port_out(port, SCSCR, scr &
2167 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2168 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2169
9ab76556 2170#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235 2171 if (s->chan_rx_saved) {
9ab76556
AM		 2172 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2173 port->line);
b96408b4 2174 hrtimer_cancel(&s->rx_timer);
9ab76556
AM		 2175 }
2176#endif
2177
c5a9262f
GU		 2178 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2179 del_timer_sync(&s->rx_fifo_timer);
1da177e4 2180 sci_free_irq(s);
3c910176 2181 sci_free_dma(port);
1da177e4
LT		 2182}
2183
6af27bf2
GU		 2184static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2185 unsigned int *srr)
26c92f37 2186{
6af27bf2 2187 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2188 int err, min_err = INT_MAX;
69eee8e9 2189 unsigned int sr;
6af27bf2 2190
7b5c0c08
GU		 2191 if (s->port.type != PORT_HSCIF)
2192 freq *= 2;
6af27bf2 2193
69eee8e9 2194 for_each_sr(sr, s) {
6af27bf2
GU		 2195 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2196 if (abs(err) >= abs(min_err))
2197 continue;
2198
2199 min_err = err;
2200 *srr = sr - 1;
ec09c5eb 2201
6af27bf2
GU		 2202 if (!err)
2203 break;
2204 }
e8183a6c 2205
6af27bf2
GU		 2206 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2207 *srr + 1);
2208 return min_err;
26c92f37
PM		 2209}
2210
1270f865
GU		 2211static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2212 unsigned long freq, unsigned int *dlr,
2213 unsigned int *srr)
730c4e78 2214{
1270f865 2215 int err, min_err = INT_MAX;
69eee8e9 2216 unsigned int sr, dl;
730c4e78 2217
7b5c0c08
GU		 2218 if (s->port.type != PORT_HSCIF)
2219 freq *= 2;
730c4e78 2220
69eee8e9 2221 for_each_sr(sr, s) {
1270f865
GU		 2222 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2223 dl = clamp(dl, 1U, 65535U);
2224
2225 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2226 if (abs(err) >= abs(min_err))
2227 continue;
2228
2229 min_err = err;
2230 *dlr = dl;
2231 *srr = sr - 1;
2232
2233 if (!err)
2234 break;
2235 }
730c4e78 2236
1270f865
GU		 2237 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2238 min_err, *dlr, *srr + 1);
2239 return min_err;
2240}
730c4e78 2241
b4a5c459 2242/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2243static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2244 unsigned int *brr, unsigned int *srr,
2245 unsigned int *cks)
f303b364 2246{
f4998e55 2247 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2248 unsigned int sr, br, prediv, scrate, c;
6c51332d 2249 int err, min_err = INT_MAX;
f303b364 2250
7b5c0c08
GU		 2251 if (s->port.type != PORT_HSCIF)
2252 freq *= 2;
b4a5c459 2253
6c51332d
GU		 2254 /*
2255 * Find the combination of sample rate and clock select with the
2256 * smallest deviation from the desired baud rate.
2257 * Prefer high sample rates to maximise the receive margin.
2258 *
2259 * M: Receive margin (%)
2260 * N: Ratio of bit rate to clock (N = sampling rate)
2261 * D: Clock duty (D = 0 to 1.0)
2262 * L: Frame length (L = 9 to 12)
2263 * F: Absolute value of clock frequency deviation
2264 *
2265 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2266 * (|D - 0.5| / N * (1 + F))|
2267 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2268 */
69eee8e9 2269 for_each_sr(sr, s) {
f303b364
UH		 2270 for (c = 0; c <= 3; c++) {
2271 /* integerized formulas from HSCIF documentation */
7b5c0c08 2272 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2273
2274 /*
2275 * We need to calculate:
2276 *
2277 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2278 * err = freq / (br * prediv) - bps
730c4e78 2279 *
de01e6cd
GU		 2280 * Watch out for overflow when calculating the desired
2281 * sampling clock rate!
730c4e78 2282 */
de01e6cd
GU		 2283 if (bps > UINT_MAX / prediv)
2284 break;
2285
2286 scrate = prediv * bps;
2287 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2288 br = clamp(br, 1U, 256U);
6c51332d 2289
881a7489 2290 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2291 if (abs(err) >= abs(min_err))
730c4e78
NI		 2292 continue;
2293
6c51332d 2294 min_err = err;
95a2703e 2295 *brr = br - 1;
730c4e78
NI		 2296 *srr = sr - 1;
2297 *cks = c;
6c51332d
GU		 2298
2299 if (!err)
2300 goto found;
f303b364
UH		 2301 }
2302 }
2303
6c51332d 2304found:
881a7489
GU		 2305 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2306 min_err, *brr, *srr + 1, *cks);
f4998e55 2307 return min_err;
f303b364
UH		 2308}
2309
1ba76220
MD		 2310static void sci_reset(struct uart_port *port)
2311{
d3184e68 2312 const struct plat_sci_reg *reg;
1ba76220 2313 unsigned int status;
18e8cf15 2314 struct sci_port *s = to_sci_port(port);
1ba76220 2315
fa2abb03 2316 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2317
0979e0e6
PM		 2318 reg = sci_getreg(port, SCFCR);
2319 if (reg->size)
b12bb29f 2320 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2321
2322 sci_clear_SCxSR(port,
2323 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2324 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2325 if (sci_getreg(port, SCLSR)->size) {
2326 status = serial_port_in(port, SCLSR);
2327 status &= ~(SCLSR_TO | SCLSR_ORER);
2328 serial_port_out(port, SCLSR, status);
2329 }
18e8cf15 2330
03940376
UH		 2331 if (s->rx_trigger > 1) {
2332 if (s->rx_fifo_timeout) {
2333 scif_set_rtrg(port, 1);
e99e88a9 2334 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
03940376 2335 } else {
90afa525
UH		 2336 if (port->type == PORT_SCIFA ||
2337 port->type == PORT_SCIFB)
2338 scif_set_rtrg(port, 1);
2339 else
2340 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2341 }
2342 }
1ba76220
MD		 2343}
2344
606d099c
AC		 2345static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2346 struct ktermios *old)
1da177e4 2347{
03940376 2348 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2349 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2350 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2351 struct sci_port *s = to_sci_port(port);
d3184e68 2352 const struct plat_sci_reg *reg;
f4998e55
GU		 2353 int min_err = INT_MAX, err;
2354 unsigned long max_freq = 0;
2355 int best_clk = -1;
1be22663 2356 unsigned long flags;
1da177e4 2357
730c4e78
NI		 2358 if ((termios->c_cflag & CSIZE) == CS7)
2359 smr_val |= SCSMR_CHR;
2360 if (termios->c_cflag & PARENB)
2361 smr_val |= SCSMR_PE;
2362 if (termios->c_cflag & PARODD)
2363 smr_val |= SCSMR_PE | SCSMR_ODD;
2364 if (termios->c_cflag & CSTOPB)
2365 smr_val |= SCSMR_STOP;
2366
154280fd
MD		 2367 /*
2368 * earlyprintk comes here early on with port->uartclk set to zero.
2369 * the clock framework is not up and running at this point so here
2370 * we assume that 115200 is the maximum baud rate. please note that
2371 * the baud rate is not programmed during earlyprintk - it is assumed
2372 * that the previous boot loader has enabled required clocks and
2373 * setup the baud rate generator hardware for us already.
2374 */
f4998e55
GU		 2375 if (!port->uartclk) {
2376 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2377 goto done;
2378 }
1da177e4 2379
f4998e55
GU		 2380 for (i = 0; i < SCI_NUM_CLKS; i++)
2381 max_freq = max(max_freq, s->clk_rates[i]);
2382
69eee8e9 2383 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2384 if (!baud)
2385 goto done;
2386
2387 /*
2388 * There can be multiple sources for the sampling clock. Find the one
2389 * that gives us the smallest deviation from the desired baud rate.
2390 */
2391
6af27bf2
GU		 2392 /* Optional Undivided External Clock */
2393 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2394 port->type != PORT_SCIFB) {
2395 err = sci_sck_calc(s, baud, &srr1);
2396 if (abs(err) < abs(min_err)) {
2397 best_clk = SCI_SCK;
2398 scr_val = SCSCR_CKE1;
2399 sccks = SCCKS_CKS;
2400 min_err = err;
2401 srr = srr1;
2402 if (!err)
2403 goto done;
2404 }
2405 }
2406
1270f865
GU		 2407 /* Optional BRG Frequency Divided External Clock */
2408 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2409 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2410 &srr1);
2411 if (abs(err) < abs(min_err)) {
2412 best_clk = SCI_SCIF_CLK;
2413 scr_val = SCSCR_CKE1;
2414 sccks = 0;
2415 min_err = err;
2416 dl = dl1;
2417 srr = srr1;
2418 if (!err)
2419 goto done;
2420 }
2421 }
2422
2423 /* Optional BRG Frequency Divided Internal Clock */
2424 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2425 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2426 &srr1);
2427 if (abs(err) < abs(min_err)) {
2428 best_clk = SCI_BRG_INT;
2429 scr_val = SCSCR_CKE1;
2430 sccks = SCCKS_XIN;
2431 min_err = err;
2432 dl = dl1;
2433 srr = srr1;
2434 if (!min_err)
2435 goto done;
f303b364
UH		 2436 }
2437 }
e108b2ca 2438
f4998e55
GU		 2439 /* Divided Functional Clock using standard Bit Rate Register */
2440 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2441 if (abs(err) < abs(min_err)) {
2442 best_clk = SCI_FCK;
6af27bf2 2443 scr_val = 0;
f4998e55
GU		 2444 min_err = err;
2445 brr = brr1;
2446 srr = srr1;
2447 cks = cks1;
2448 }
2449
2450done:
2451 if (best_clk >= 0)
2452 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2453 s->clks[best_clk], baud, min_err);
e108b2ca 2454
23241d43 2455 sci_port_enable(s);
36003386 2456
6af27bf2
GU		 2457 /*
2458 * Program the optional External Baud Rate Generator (BRG) first.
2459 * It controls the mux to select (H)SCK or frequency divided clock.
2460 */
1270f865
GU		 2461 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2462 serial_port_out(port, SCDL, dl);
6af27bf2 2463 serial_port_out(port, SCCKS, sccks);
1270f865 2464 }
1da177e4 2465
1be22663
TA		 2466 spin_lock_irqsave(&port->lock, flags);
2467
1ba76220 2468 sci_reset(port);
1da177e4
LT		 2469
2470 uart_update_timeout(port, termios->c_cflag, baud);
2471
63ba1e00
UH		 2472 /* byte size and parity */
2473 switch (termios->c_cflag & CSIZE) {
2474 case CS5:
2475 bits = 7;
2476 break;
2477 case CS6:
2478 bits = 8;
2479 break;
2480 case CS7:
2481 bits = 9;
2482 break;
2483 default:
2484 bits = 10;
2485 break;
2486 }
2487
2488 if (termios->c_cflag & CSTOPB)
2489 bits++;
2490 if (termios->c_cflag & PARENB)
2491 bits++;
2492
f4998e55 2493 if (best_clk >= 0) {
92a05748
GU		 2494 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2495 switch (srr + 1) {
2496 case 5: smr_val |= SCSMR_SRC_5; break;
2497 case 7: smr_val |= SCSMR_SRC_7; break;
2498 case 11: smr_val |= SCSMR_SRC_11; break;
2499 case 13: smr_val |= SCSMR_SRC_13; break;
2500 case 16: smr_val |= SCSMR_SRC_16; break;
2501 case 17: smr_val |= SCSMR_SRC_17; break;
2502 case 19: smr_val |= SCSMR_SRC_19; break;
2503 case 27: smr_val |= SCSMR_SRC_27; break;
2504 }
f4998e55 2505 smr_val |= cks;
fa2abb03 2506 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2507 serial_port_out(port, SCSMR, smr_val);
2508 serial_port_out(port, SCBRR, brr);
63ba1e00
UH		 2509 if (sci_getreg(port, HSSRR)->size) {
2510 unsigned int hssrr = srr | HSCIF_SRE;
2511 /* Calculate deviation from intended rate at the
2512 * center of the last stop bit in sampling clocks.
2513 */
2514 int last_stop = bits * 2 - 1;
2515 int deviation = min_err * srr * last_stop / 2 / baud;
2516
2517 if (abs(deviation) >= 2) {
2518 /* At least two sampling clocks off at the
2519 * last stop bit; we can increase the error
2520 * margin by shifting the sampling point.
2521 */
2522 int shift = min(-8, max(7, deviation / 2));
2523
2524 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2525 HSCIF_SRHP_MASK;
2526 hssrr |= HSCIF_SRDE;
2527 }
2528 serial_port_out(port, HSSRR, hssrr);
2529 }
f4998e55
GU		 2530
2531 /* Wait one bit interval */
2532 udelay((1000000 + (baud - 1)) / baud);
2533 } else {
2534 /* Don't touch the bit rate configuration */
2535 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2536 smr_val |= serial_port_in(port, SCSMR) &
2537 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2538 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2539 serial_port_out(port, SCSMR, smr_val);
f4998e55 2540 }
1da177e4 2541
d5701647 2542 sci_init_pins(port, termios->c_cflag);
0979e0e6 2543
33f50ffc
GU		 2544 port->status &= ~UPSTAT_AUTOCTS;
2545 s->autorts = false;
73c3d53f
PM		 2546 reg = sci_getreg(port, SCFCR);
2547 if (reg->size) {
b12bb29f 2548 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2549
33f50ffc
GU		 2550 if ((port->flags & UPF_HARD_FLOW) &&
2551 (termios->c_cflag & CRTSCTS)) {
2552 /* There is no CTS interrupt to restart the hardware */
2553 port->status |= UPSTAT_AUTOCTS;
2554 /* MCE is enabled when RTS is raised */
2555 s->autorts = true;
faf02f8f 2556 }
73c3d53f
PM		 2557
2558 /*
2559 * As we've done a sci_reset() above, ensure we don't
2560 * interfere with the FIFOs while toggling MCE. As the
2561 * reset values could still be set, simply mask them out.
2562 */
2563 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2564
b12bb29f 2565 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2566 }
5f76895e
GU		 2567 if (port->flags & UPF_HARD_FLOW) {
2568 /* Refresh (Auto) RTS */
2569 sci_set_mctrl(port, port->mctrl);
2570 }
b7a76e4b 2571
9f8325b3
LP		 2572 scr_val |= SCSCR_RE | SCSCR_TE |
2573 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2574 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2575 if ((srr + 1 == 5) &&
2576 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2577 /*
2578 * In asynchronous mode, when the sampling rate is 1/5, first
2579 * received data may become invalid on some SCIFA and SCIFB.
2580 * To avoid this problem wait more than 1 serial data time (1
2581 * bit time x serial data number) after setting SCSCR.RE = 1.
2582 */
2583 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2584 }
1da177e4 2585
3089f381 2586 /*
5f6d8515 2587 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2588 * See serial_core.c::uart_update_timeout().
2589 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2590 * function calculates 1 jiffie for the data plus 5 jiffies for the
2591 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2592 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2593 * value obtained by this formula is too small. Therefore, if the value
2594 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2595 */
b96408b4 2596 s->rx_frame = (10000 * bits) / (baud / 100);
03940376 2597#ifdef CONFIG_SERIAL_SH_SCI_DMA
b96408b4
UH		 2598 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2599 if (s->rx_timeout < 20)
2600 s->rx_timeout = 20;
3089f381
GL		 2601#endif
2602
1da177e4 2603 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2604 sci_start_rx(port);
36003386 2605
1be22663
TA		 2606 spin_unlock_irqrestore(&port->lock, flags);
2607
23241d43 2608 sci_port_disable(s);
f907c9ea
GU		 2609
2610 if (UART_ENABLE_MS(port, termios->c_cflag))
2611 sci_enable_ms(port);
1da177e4
LT		 2612}
2613
0174e5ca
TK		 2614static void sci_pm(struct uart_port *port, unsigned int state,
2615 unsigned int oldstate)
2616{
2617 struct sci_port *sci_port = to_sci_port(port);
2618
2619 switch (state) {
d3dfe5d9 2620 case UART_PM_STATE_OFF:
0174e5ca
TK		 2621 sci_port_disable(sci_port);
2622 break;
2623 default:
2624 sci_port_enable(sci_port);
2625 break;
2626 }
2627}
2628
1da177e4
LT		 2629static const char *sci_type(struct uart_port *port)
2630{
2631 switch (port->type) {
e7c98dc7
MT		 2632 case PORT_IRDA:
2633 return "irda";
2634 case PORT_SCI:
2635 return "sci";
2636 case PORT_SCIF:
2637 return "scif";
2638 case PORT_SCIFA:
2639 return "scifa";
d1d4b10c
GL		 2640 case PORT_SCIFB:
2641 return "scifb";
f303b364
UH		 2642 case PORT_HSCIF:
2643 return "hscif";
1da177e4
LT		 2644 }
2645
fa43972f 2646 return NULL;
1da177e4
LT		 2647}
2648
f6e9495d
PM		 2649static int sci_remap_port(struct uart_port *port)
2650{
e4d6f911 2651 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2652
2653 /*
2654 * Nothing to do if there's already an established membase.
2655 */
2656 if (port->membase)
2657 return 0;
2658
3d73f32b 2659 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2660 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2661 if (unlikely(!port->membase)) {
2662 dev_err(port->dev, "can't remap port#%d\n", port->line);
2663 return -ENXIO;
2664 }
2665 } else {
2666 /*
2667 * For the simple (and majority of) cases where we don't
2668 * need to do any remapping, just cast the cookie
2669 * directly.
2670 */
3af4e960 2671 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2672 }
2673
2674 return 0;
2675}
2676
e2651647 2677static void sci_release_port(struct uart_port *port)
1da177e4 2678{
e4d6f911
YS		 2679 struct sci_port *sport = to_sci_port(port);
2680
3d73f32b 2681 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2682 iounmap(port->membase);
2683 port->membase = NULL;
2684 }
2685
e4d6f911 2686 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2687}
2688
e2651647 2689static int sci_request_port(struct uart_port *port)
1da177e4 2690{
e2651647 2691 struct resource *res;
e4d6f911 2692 struct sci_port *sport = to_sci_port(port);
f6e9495d 2693 int ret;
1da177e4 2694
e4d6f911
YS		 2695 res = request_mem_region(port->mapbase, sport->reg_size,
2696 dev_name(port->dev));
2697 if (unlikely(res == NULL)) {
2698 dev_err(port->dev, "request_mem_region failed.");
e2651647 2699 return -EBUSY;
e4d6f911 2700 }
1da177e4 2701
f6e9495d
PM		 2702 ret = sci_remap_port(port);
2703 if (unlikely(ret != 0)) {
2704 release_resource(res);
2705 return ret;
7ff731ae 2706 }
e2651647
PM		 2707
2708 return 0;
2709}
2710
2711static void sci_config_port(struct uart_port *port, int flags)
2712{
2713 if (flags & UART_CONFIG_TYPE) {
2714 struct sci_port *sport = to_sci_port(port);
2715
2716 port->type = sport->cfg->type;
2717 sci_request_port(port);
2718 }
1da177e4
LT		 2719}
2720
2721static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2722{
1da177e4
LT		 2723 if (ser->baud_base < 2400)
2724 /* No paper tape reader for Mitch.. */
2725 return -EINVAL;
2726
2727 return 0;
2728}
2729
069a47e5 2730static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2731 .tx_empty = sci_tx_empty,
2732 .set_mctrl = sci_set_mctrl,
2733 .get_mctrl = sci_get_mctrl,
2734 .start_tx = sci_start_tx,
2735 .stop_tx = sci_stop_tx,
2736 .stop_rx = sci_stop_rx,
f907c9ea 2737 .enable_ms = sci_enable_ms,
1da177e4
LT		 2738 .break_ctl = sci_break_ctl,
2739 .startup = sci_startup,
2740 .shutdown = sci_shutdown,
1cf4a7ef 2741 .flush_buffer = sci_flush_buffer,
1da177e4 2742 .set_termios = sci_set_termios,
0174e5ca 2743 .pm = sci_pm,
1da177e4
LT		 2744 .type = sci_type,
2745 .release_port = sci_release_port,
2746 .request_port = sci_request_port,
2747 .config_port = sci_config_port,
2748 .verify_port = sci_verify_port,
07d2a1a1
PM		 2749#ifdef CONFIG_CONSOLE_POLL
2750 .poll_get_char = sci_poll_get_char,
2751 .poll_put_char = sci_poll_put_char,
2752#endif
1da177e4
LT		 2753};
2754
a9ec81f4
LP		 2755static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2756{
f4998e55
GU		 2757 const char *clk_names[] = {
2758 [SCI_FCK] = "fck",
6af27bf2 2759 [SCI_SCK] = "sck",
1270f865
GU		 2760 [SCI_BRG_INT] = "brg_int",
2761 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2762 };
2763 struct clk *clk;
2764 unsigned int i;
a9ec81f4 2765
6af27bf2
GU		 2766 if (sci_port->cfg->type == PORT_HSCIF)
2767 clk_names[SCI_SCK] = "hsck";
2768
f4998e55
GU		 2769 for (i = 0; i < SCI_NUM_CLKS; i++) {
2770 clk = devm_clk_get(dev, clk_names[i]);
2771 if (PTR_ERR(clk) == -EPROBE_DEFER)
2772 return -EPROBE_DEFER;
a9ec81f4 2773
f4998e55
GU		 2774 if (IS_ERR(clk) && i == SCI_FCK) {
2775 /*
2776 * "fck" used to be called "sci_ick", and we need to
2777 * maintain DT backward compatibility.
2778 */
2779 clk = devm_clk_get(dev, "sci_ick");
2780 if (PTR_ERR(clk) == -EPROBE_DEFER)
2781 return -EPROBE_DEFER;
a9ec81f4 2782
f4998e55
GU		 2783 if (!IS_ERR(clk))
2784 goto found;
a9ec81f4 2785
f4998e55
GU		 2786 /*
2787 * Not all SH platforms declare a clock lookup entry
2788 * for SCI devices, in which case we need to get the
2789 * global "peripheral_clk" clock.
2790 */
2791 clk = devm_clk_get(dev, "peripheral_clk");
2792 if (!IS_ERR(clk))
2793 goto found;
2794
2795 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2796 PTR_ERR(clk));
2797 return PTR_ERR(clk);
2798 }
2799
2800found:
2801 if (IS_ERR(clk))
2802 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2803 PTR_ERR(clk));
2804 else
d63c16f8
GU		 2805 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2806 clk, clk_get_rate(clk));
f4998e55
GU		 2807 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2808 }
2809 return 0;
a9ec81f4
LP		 2810}
2811
daf5a895
LP		 2812static const struct sci_port_params *
2813sci_probe_regmap(const struct plat_sci_port *cfg)
2814{
2815 unsigned int regtype;
2816
2817 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2818 return &sci_port_params[cfg->regtype];
2819
2820 switch (cfg->type) {
2821 case PORT_SCI:
2822 regtype = SCIx_SCI_REGTYPE;
2823 break;
2824 case PORT_IRDA:
2825 regtype = SCIx_IRDA_REGTYPE;
2826 break;
2827 case PORT_SCIFA:
2828 regtype = SCIx_SCIFA_REGTYPE;
2829 break;
2830 case PORT_SCIFB:
2831 regtype = SCIx_SCIFB_REGTYPE;
2832 break;
2833 case PORT_SCIF:
2834 /*
2835 * The SH-4 is a bit of a misnomer here, although that's
2836 * where this particular port layout originated. This
2837 * configuration (or some slight variation thereof)
2838 * remains the dominant model for all SCIFs.
2839 */
2840 regtype = SCIx_SH4_SCIF_REGTYPE;
2841 break;
2842 case PORT_HSCIF:
2843 regtype = SCIx_HSCIF_REGTYPE;
2844 break;
2845 default:
2846 pr_err("Can't probe register map for given port\n");
2847 return NULL;
2848 }
2849
2850 return &sci_port_params[regtype];
2851}
2852
9671f099 2853static int sci_init_single(struct platform_device *dev,
1fcc91a6 2854 struct sci_port *sci_port, unsigned int index,
daf5a895 2855 const struct plat_sci_port *p, bool early)
e108b2ca 2856{
73a19e4c 2857 struct uart_port *port = &sci_port->port;
1fcc91a6 2858 const struct resource *res;
a1c2fd7e 2859 unsigned int i;
3127c6b2 2860 int ret;
e108b2ca 2861
50f0959a
PM		 2862 sci_port->cfg = p;
2863
73a19e4c
GL		 2864 port->ops = &sci_uart_ops;
2865 port->iotype = UPIO_MEM;
2866 port->line = index;
75136d48 2867
89b5c1ab
LP		 2868 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2869 if (res == NULL)
2870 return -ENOMEM;
1fcc91a6 2871
89b5c1ab 2872 port->mapbase = res->start;
e4d6f911 2873 sci_port->reg_size = resource_size(res);
1fcc91a6 2874
89b5c1ab
LP		 2875 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2876 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2877
89b5c1ab
LP		 2878 /* The SCI generates several interrupts. They can be muxed together or
2879 * connected to different interrupt lines. In the muxed case only one
628c534a
CB		 2880 * interrupt resource is specified as there is only one interrupt ID.
2881 * In the non-muxed case, up to 6 interrupt signals might be generated
2882 * from the SCI, however those signals might have their own individual
2883 * interrupt ID numbers, or muxed together with another interrupt.
89b5c1ab
LP		 2884 */
2885 if (sci_port->irqs[0] < 0)
2886 return -ENXIO;
1fcc91a6 2887
628c534a
CB		 2888 if (sci_port->irqs[1] < 0)
2889 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2890 sci_port->irqs[i] = sci_port->irqs[0];
1fcc91a6 2891
daf5a895
LP		 2892 sci_port->params = sci_probe_regmap(p);
2893 if (unlikely(sci_port->params == NULL))
2894 return -EINVAL;
e095ee6b 2895
18e8cf15
UH		 2896 switch (p->type) {
2897 case PORT_SCIFB:
2898 sci_port->rx_trigger = 48;
2899 break;
2900 case PORT_HSCIF:
2901 sci_port->rx_trigger = 64;
2902 break;
2903 case PORT_SCIFA:
2904 sci_port->rx_trigger = 32;
2905 break;
2906 case PORT_SCIF:
2907 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2908 /* RX triggering not implemented for this IP */
2909 sci_port->rx_trigger = 1;
2910 else
2911 sci_port->rx_trigger = 8;
2912 break;
2913 default:
2914 sci_port->rx_trigger = 1;
2915 break;
2916 }
2917
03940376 2918 sci_port->rx_fifo_timeout = 0;
fa2abb03 2919 sci_port->hscif_tot = 0;
03940376 2920
878fbb91
LP		 2921 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2922 * match the SoC datasheet, this should be investigated. Let platform
2923 * data override the sampling rate for now.
ec09c5eb 2924 */
b2f20ed9
LP		 2925 sci_port->sampling_rate_mask = p->sampling_rate
2926 ? SCI_SR(p->sampling_rate)
2927 : sci_port->params->sampling_rate_mask;
ec09c5eb 2928
1fcc91a6 2929 if (!early) {
a9ec81f4
LP		 2930 ret = sci_init_clocks(sci_port, &dev->dev);
2931 if (ret < 0)
2932 return ret;
c7ed1ab3 2933
73a19e4c 2934 port->dev = &dev->dev;
5e50d2d6
MD		 2935
2936 pm_runtime_enable(&dev->dev);
7b6fd3bf 2937 }
e108b2ca 2938
ce6738b6 2939 port->type = p->type;
3d73f32b 2940 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2941 port->fifosize = sci_port->params->fifosize;
73a19e4c 2942
dfc80387
LP		 2943 if (port->type == PORT_SCI) {
2944 if (sci_port->reg_size >= 0x20)
2945 port->regshift = 2;
2946 else
2947 port->regshift = 1;
2948 }
2949
ce6738b6 2950 /*
61a6976b 2951 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2952 * for the multi-IRQ ports, which is where we are primarily
2953 * concerned with the shutdown path synchronization.
2954 *
2955 * For the muxed case there's nothing more to do.
2956 */
1fcc91a6 2957 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2958 port->irqflags = 0;
73a19e4c 2959
61a6976b
PM		 2960 port->serial_in = sci_serial_in;
2961 port->serial_out = sci_serial_out;
2962
c7ed1ab3 2963 return 0;
e108b2ca
PM		 2964}
2965
6dae1421
LP		 2966static void sci_cleanup_single(struct sci_port *port)
2967{
6dae1421
LP		 2968 pm_runtime_disable(port->port.dev);
2969}
2970
0b0cced1
YS		 2971#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2972 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2973static void serial_console_putchar(struct uart_port *port, int ch)
2974{
2975 sci_poll_put_char(port, ch);
2976}
2977
1da177e4
LT		 2978/*
2979 * Print a string to the serial port trying not to disturb
2980 * any possible real use of the port...
2981 */
2982static void serial_console_write(struct console *co, const char *s,
2983 unsigned count)
2984{
906b17dc
PM		 2985 struct sci_port *sci_port = &sci_ports[co->index];
2986 struct uart_port *port = &sci_port->port;
a67969b5 2987 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2988 unsigned long flags;
2989 int locked = 1;
2990
0b0cced1 2991#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2992 if (port->sysrq)
2993 locked = 0;
0b0cced1
YS		 2994 else
2995#endif
2996 if (oops_in_progress)
8afb1d2c 2997 locked = spin_trylock_irqsave(&port->lock, flags);
40f70c03 2998 else
8afb1d2c 2999 spin_lock_irqsave(&port->lock, flags);
40f70c03 3000
a67969b5 3001 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 3002 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 3003 ctrl_temp = SCSCR_RE | SCSCR_TE |
3004 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 3005 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 3006 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 3007
501b825d 3008 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 3009
3010 /* wait until fifo is empty and last bit has been transmitted */
3011 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 3012 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 3013 cpu_relax();
40f70c03
SK		 3014
3015 /* restore the SCSCR */
3016 serial_port_out(port, SCSCR, ctrl);
3017
3018 if (locked)
8afb1d2c 3019 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 3020}
3021
9671f099 3022static int serial_console_setup(struct console *co, char *options)
1da177e4 3023{
dc8e6f5b 3024 struct sci_port *sci_port;
1da177e4
LT		 3025 struct uart_port *port;
3026 int baud = 115200;
3027 int bits = 8;
3028 int parity = 'n';
3029 int flow = 'n';
3030 int ret;
3031
e108b2ca 3032 /*
906b17dc 3033 * Refuse to handle any bogus ports.
1da177e4 3034 */
906b17dc 3035 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 3036 return -ENODEV;
e108b2ca 3037
906b17dc
PM		 3038 sci_port = &sci_ports[co->index];
3039 port = &sci_port->port;
3040
b2267a6b
AC		 3041 /*
3042 * Refuse to handle uninitialized ports.
3043 */
3044 if (!port->ops)
3045 return -ENODEV;
3046
f6e9495d
PM		 3047 ret = sci_remap_port(port);
3048 if (unlikely(ret != 0))
3049 return ret;
e108b2ca 3050
1da177e4
LT		 3051 if (options)
3052 uart_parse_options(options, &baud, &parity, &bits, &flow);
3053
ab7cfb55 3054 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 3055}
3056
3057static struct console serial_console = {
3058 .name = "ttySC",
906b17dc 3059 .device = uart_console_device,
1da177e4
LT		 3060 .write = serial_console_write,
3061 .setup = serial_console_setup,
fa5da2f7 3062 .flags = CON_PRINTBUFFER,
1da177e4 3063 .index = -1,
906b17dc 3064 .data = &sci_uart_driver,
1da177e4
LT		 3065};
3066
7b6fd3bf
MD		 3067static struct console early_serial_console = {
3068 .name = "early_ttySC",
3069 .write = serial_console_write,
3070 .flags = CON_PRINTBUFFER,
906b17dc 3071 .index = -1,
7b6fd3bf 3072};
ecdf8a46 3073
7b6fd3bf
MD		 3074static char early_serial_buf[32];
3075
9671f099 3076static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 3077{
daf5a895 3078 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 3079
3080 if (early_serial_console.data)
3081 return -EEXIST;
3082
3083 early_serial_console.index = pdev->id;
ecdf8a46 3084
1fcc91a6 3085 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 3086
3087 serial_console_setup(&early_serial_console, early_serial_buf);
3088
3089 if (!strstr(early_serial_buf, "keep"))
3090 early_serial_console.flags |= CON_BOOT;
3091
3092 register_console(&early_serial_console);
3093 return 0;
3094}
6a8c9799
NI		 3095
3096#define SCI_CONSOLE (&serial_console)
3097
ecdf8a46 3098#else
9671f099 3099static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 3100{
3101 return -EINVAL;
3102}
1da177e4 3103
6a8c9799
NI		 3104#define SCI_CONSOLE NULL
3105
0b0cced1 3106#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 3107
6c13d5d2 3108static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 3109
352b9266 3110static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3111static struct uart_driver sci_uart_driver = {
3112 .owner = THIS_MODULE,
3113 .driver_name = "sci",
1da177e4
LT		 3114 .dev_name = "ttySC",
3115 .major = SCI_MAJOR,
3116 .minor = SCI_MINOR_START,
e108b2ca 3117 .nr = SCI_NPORTS,
1da177e4
LT		 3118 .cons = SCI_CONSOLE,
3119};
3120
54507f6e 3121static int sci_remove(struct platform_device *dev)
e552de24 3122{
d535a230 3123 struct sci_port *port = platform_get_drvdata(dev);
641a41db 3124 unsigned int type = port->port.type; /* uart_remove_... clears it */
e552de24 3125
7678f4c2 3126 sci_ports_in_use &= ~BIT(port->port.line);
d535a230
PM		 3127 uart_remove_one_port(&sci_uart_driver, &port->port);
3128
6dae1421 3129 sci_cleanup_single(port);
e552de24 3130
5d23188a
UH		 3131 if (port->port.fifosize > 1) {
3132 sysfs_remove_file(&dev->dev.kobj,
3133 &dev_attr_rx_fifo_trigger.attr);
3134 }
641a41db 3135 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
5d23188a
UH		 3136 sysfs_remove_file(&dev->dev.kobj,
3137 &dev_attr_rx_fifo_timeout.attr);
3138 }
3139
e552de24
MD		 3140 return 0;
3141}
3142
bd2238fb
GU		 3143
3144#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3145#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3146#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3147
3148static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3149 /* SoC-specific types */
3150 {
3151 .compatible = "renesas,scif-r7s72100",
3152 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3153 },
10c63443
GU		 3154 {
3155 .compatible = "renesas,scif-r7s9210",
3156 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3157 },
9ed44bb2
GU		 3158 /* Family-specific types */
3159 {
3160 .compatible = "renesas,rcar-gen1-scif",
3161 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3162 }, {
3163 .compatible = "renesas,rcar-gen2-scif",
3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3165 }, {
3166 .compatible = "renesas,rcar-gen3-scif",
3167 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3168 },
f443ff80 3169 /* Generic types */
20bdcab8
BH		 3170 {
3171 .compatible = "renesas,scif",
bd2238fb 3172 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3173 }, {
3174 .compatible = "renesas,scifa",
bd2238fb 3175 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3176 }, {
3177 .compatible = "renesas,scifb",
bd2238fb 3178 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3179 }, {
3180 .compatible = "renesas,hscif",
bd2238fb 3181 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3182 }, {
3183 .compatible = "renesas,sci",
bd2238fb 3184 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3185 }, {
3186 /* Terminator */
3187 },
3188};
3189MODULE_DEVICE_TABLE(of, of_sci_match);
3190
54b12c48
GU		 3191static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3192 unsigned int *dev_id)
20bdcab8
BH		 3193{
3194 struct device_node *np = pdev->dev.of_node;
20bdcab8 3195 struct plat_sci_port *p;
97ed9790 3196 struct sci_port *sp;
6e605a01 3197 const void *data;
20bdcab8
BH		 3198 int id;
3199
3200 if (!IS_ENABLED(CONFIG_OF) || !np)
3201 return NULL;
3202
6e605a01 3203 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3204
20bdcab8 3205 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3206 if (!p)
20bdcab8 3207 return NULL;
20bdcab8 3208
2095fc76 3209 /* Get the line number from the aliases node. */
20bdcab8 3210 id = of_alias_get_id(np, "serial");
7678f4c2
GU		 3211 if (id < 0 && ~sci_ports_in_use)
3212 id = ffz(sci_ports_in_use);
20bdcab8
BH		 3213 if (id < 0) {
3214 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3215 return NULL;
3216 }
090fa4b0
GU		 3217 if (id >= ARRAY_SIZE(sci_ports)) {
3218 dev_err(&pdev->dev, "serial%d out of range\n", id);
3219 return NULL;
3220 }
20bdcab8 3221
97ed9790 3222 sp = &sci_ports[id];
20bdcab8
BH		 3223 *dev_id = id;
3224
6e605a01
GU		 3225 p->type = SCI_OF_TYPE(data);
3226 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3227
43c61286 3228 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3229
20bdcab8
BH		 3230 return p;
3231}
3232
9671f099 3233static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3234 unsigned int index,
3235 struct plat_sci_port *p,
3236 struct sci_port *sciport)
3237{
0ee70712
MD		 3238 int ret;
3239
3240 /* Sanity check */
3241 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3242 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3243 index+1, SCI_NPORTS);
9b971cd2 3244 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3245 return -EINVAL;
0ee70712 3246 }
7678f4c2
GU		 3247 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3248 if (sci_ports_in_use & BIT(index))
3249 return -EBUSY;
0ee70712 3250
352b9266
SS		 3251 mutex_lock(&sci_uart_registration_lock);
3252 if (!sci_uart_driver.state) {
3253 ret = uart_register_driver(&sci_uart_driver);
3254 if (ret) {
3255 mutex_unlock(&sci_uart_registration_lock);
3256 return ret;
3257 }
3258 }
3259 mutex_unlock(&sci_uart_registration_lock);
3260
1fcc91a6 3261 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3262 if (ret)
3263 return ret;
0ee70712 3264
f907c9ea
GU		 3265 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3266 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3267 return PTR_ERR(sciport->gpios);
3268
97ed9790 3269 if (sciport->has_rtscts) {
f907c9ea
GU		 3270 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3271 UART_GPIO_CTS)) ||
3272 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3273 UART_GPIO_RTS))) {
3274 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3275 return -EINVAL;
3276 }
33f50ffc 3277 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3278 }
3279
6dae1421
LP		 3280 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3281 if (ret) {
3282 sci_cleanup_single(sciport);
3283 return ret;
3284 }
3285
3286 return 0;
0ee70712
MD		 3287}
3288
9671f099 3289static int sci_probe(struct platform_device *dev)
1da177e4 3290{
20bdcab8
BH		 3291 struct plat_sci_port *p;
3292 struct sci_port *sp;
3293 unsigned int dev_id;
ecdf8a46 3294 int ret;
d535a230 3295
ecdf8a46
PM		 3296 /*
3297 * If we've come here via earlyprintk initialization, head off to
3298 * the special early probe. We don't have sufficient device state
3299 * to make it beyond this yet.
3300 */
3301 if (is_early_platform_device(dev))
3302 return sci_probe_earlyprintk(dev);
7b6fd3bf 3303
20bdcab8
BH		 3304 if (dev->dev.of_node) {
3305 p = sci_parse_dt(dev, &dev_id);
3306 if (p == NULL)
3307 return -EINVAL;
3308 } else {
3309 p = dev->dev.platform_data;
3310 if (p == NULL) {
3311 dev_err(&dev->dev, "no platform data supplied\n");
3312 return -EINVAL;
3313 }
3314
3315 dev_id = dev->id;
3316 }
3317
3318 sp = &sci_ports[dev_id];
d535a230 3319 platform_set_drvdata(dev, sp);
e552de24 3320
20bdcab8 3321 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3322 if (ret)
6dae1421 3323 return ret;
e552de24 3324
5d23188a
UH		 3325 if (sp->port.fifosize > 1) {
3326 ret = sysfs_create_file(&dev->dev.kobj,
3327 &dev_attr_rx_fifo_trigger.attr);
3328 if (ret)
3329 return ret;
3330 }
fa2abb03
UH		 3331 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3332 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3333 ret = sysfs_create_file(&dev->dev.kobj,
3334 &dev_attr_rx_fifo_timeout.attr);
3335 if (ret) {
3336 if (sp->port.fifosize > 1) {
3337 sysfs_remove_file(&dev->dev.kobj,
3338 &dev_attr_rx_fifo_trigger.attr);
3339 }
3340 return ret;
3341 }
3342 }
3343
1da177e4
LT		 3344#ifdef CONFIG_SH_STANDARD_BIOS
3345 sh_bios_gdb_detach();
3346#endif
3347
7678f4c2 3348 sci_ports_in_use |= BIT(dev_id);
e108b2ca 3349 return 0;
1da177e4
LT		 3350}
3351
cb876341 3352static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3353{
d535a230 3354 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3355
d535a230
PM		 3356 if (sport)
3357 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3358
e108b2ca
PM		 3359 return 0;
3360}
1da177e4 3361
cb876341 3362static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3363{
d535a230 3364 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3365
d535a230
PM		 3366 if (sport)
3367 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3368
3369 return 0;
3370}
3371
cb876341 3372static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3373
e108b2ca
PM		 3374static struct platform_driver sci_driver = {
3375 .probe = sci_probe,
b9e39c89 3376 .remove = sci_remove,
e108b2ca
PM		 3377 .driver = {
3378 .name = "sh-sci",
6daa79b3 3379 .pm = &sci_dev_pm_ops,
20bdcab8 3380 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3381 },
3382};
3383
3384static int __init sci_init(void)
3385{
6c13d5d2 3386 pr_info("%s\n", banner);
e108b2ca 3387
352b9266 3388 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3389}
3390
3391static void __exit sci_exit(void)
3392{
3393 platform_driver_unregister(&sci_driver);
352b9266
SS		 3394
3395 if (sci_uart_driver.state)
3396 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3397}
3398
7b6fd3bf
MD		 3399#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3400early_platform_init_buffer("earlyprintk", &sci_driver,
3401 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3402#endif
0b0cced1 3403#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3404static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3405
3406static int __init early_console_setup(struct earlycon_device *device,
3407 int type)
3408{
3409 if (!device->port.membase)
3410 return -ENODEV;
3411
3412 device->port.serial_in = sci_serial_in;
3413 device->port.serial_out = sci_serial_out;
3414 device->port.type = type;
3415 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3416 port_cfg.type = type;
0b0cced1 3417 sci_ports[0].cfg = &port_cfg;
daf5a895 3418 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3419 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3420 sci_serial_out(&sci_ports[0].port, SCSCR,
3421 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3422
3423 device->con->write = serial_console_write;
3424 return 0;
3425}
3426static int __init sci_early_console_setup(struct earlycon_device *device,
3427 const char *opt)
3428{
3429 return early_console_setup(device, PORT_SCI);
3430}
3431static int __init scif_early_console_setup(struct earlycon_device *device,
3432 const char *opt)
3433{
3434 return early_console_setup(device, PORT_SCIF);
3435}
3d8b43ad
CB		 3436static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3437 const char *opt)
3438{
3439 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3440 return early_console_setup(device, PORT_SCIF);
3441}
0b0cced1
YS		 3442static int __init scifa_early_console_setup(struct earlycon_device *device,
3443 const char *opt)
3444{
3445 return early_console_setup(device, PORT_SCIFA);
3446}
3447static int __init scifb_early_console_setup(struct earlycon_device *device,
3448 const char *opt)
3449{
3450 return early_console_setup(device, PORT_SCIFB);
3451}
3452static int __init hscif_early_console_setup(struct earlycon_device *device,
3453 const char *opt)
3454{
3455 return early_console_setup(device, PORT_HSCIF);
3456}
3457
0b0cced1 3458OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3459OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3d8b43ad 3460OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
0b0cced1 3461OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3462OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3463OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3464#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3465
1da177e4
LT		 3466module_init(sci_init);
3467module_exit(sci_exit);
3468
e108b2ca 3469MODULE_LICENSE("GPL");
e169c139 3470MODULE_ALIAS("platform:sh-sci");
7f405f9c 3471MODULE_AUTHOR("Paul Mundt");
f303b364 3472MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git