[thirdparty/kernel/stable.git] / sound / soc / intel / skylake / skl-sst-ipc.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Intel SKL IPC Support
 *
 * Copyright (C) 2014-15, Intel Corporation.
 */

#ifndef __SKL_IPC_H
#define __SKL_IPC_H

#include <linux/irqreturn.h>
#include "../common/sst-ipc.h"

struct sst_dsp;
struct skl_sst;
struct sst_generic_ipc;

enum skl_ipc_pipeline_state {
	PPL_INVALID_STATE =	0,
	PPL_UNINITIALIZED =	1,
	PPL_RESET =		2,
	PPL_PAUSED =		3,
	PPL_RUNNING =		4,
	PPL_ERROR_STOP =	5,
	PPL_SAVED =		6,
	PPL_RESTORED =		7
};

struct skl_ipc_dxstate_info {
	u32 core_mask;
	u32 dx_mask;
};

struct skl_ipc_header {
	u32 primary;
	u32 extension;
};

struct skl_dsp_cores {
	unsigned int count;
	enum skl_dsp_states *state;
	int *usage_count;
};

/**
 * skl_d0i3_data: skl D0i3 counters data struct
 *
 * @streaming: Count of usecases that can attempt streaming D0i3
 * @non_streaming: Count of usecases that can attempt non-streaming D0i3
 * @non_d0i3: Count of usecases that cannot attempt D0i3
 * @state: current state
 * @work: D0i3 worker thread
 */
struct skl_d0i3_data {
	int streaming;
	int non_streaming;
	int non_d0i3;
	enum skl_dsp_d0i3_states state;
	struct delayed_work work;
};

#define SKL_LIB_NAME_LENGTH 128
#define SKL_MAX_LIB 16

struct skl_lib_info {
	char name[SKL_LIB_NAME_LENGTH];
	const struct firmware *fw;
};

struct skl_sst {
	struct device *dev;
	struct sst_dsp *dsp;

	/* boot */
	wait_queue_head_t boot_wait;
	bool boot_complete;

	/* module load */
	wait_queue_head_t mod_load_wait;
	bool mod_load_complete;
	bool mod_load_status;

	/* IPC messaging */
	struct sst_generic_ipc ipc;

	/* callback for miscbdge */
	void (*enable_miscbdcge)(struct device *dev, bool enable);
	/* Is CGCTL.MISCBDCGE disabled */
	bool miscbdcg_disabled;

	/* Populate module information */
	struct list_head uuid_list;

	/* Is firmware loaded */
	bool fw_loaded;

	/* first boot ? */
	bool is_first_boot;

	/* multi-core */
	struct skl_dsp_cores cores;

	/* library info */
	struct skl_lib_info  lib_info[SKL_MAX_LIB];
	int lib_count;

	/* Callback to update D0i3C register */
	void (*update_d0i3c)(struct device *dev, bool enable);

	struct skl_d0i3_data d0i3;

	const struct skl_dsp_ops *dsp_ops;

	/* Callback to update dynamic clock and power gating registers */
	void (*clock_power_gating)(struct device *dev, bool enable);
};

struct skl_ipc_init_instance_msg {
	u32 module_id;
	u32 instance_id;
	u16 param_data_size;
	u8 ppl_instance_id;
	u8 core_id;
	u8 domain;
};

struct skl_ipc_bind_unbind_msg {
	u32 module_id;
	u32 instance_id;
	u32 dst_module_id;
	u32 dst_instance_id;
	u8 src_queue;
	u8 dst_queue;
	bool bind;
};

struct skl_ipc_large_config_msg {
	u32 module_id;
	u32 instance_id;
	u32 large_param_id;
	u32 param_data_size;
};

struct skl_ipc_d0ix_msg {
	u32 module_id;
	u32 instance_id;
	u8 streaming;
	u8 wake;
};

#define SKL_IPC_BOOT_MSECS		3000

#define SKL_IPC_D3_MASK	0
#define SKL_IPC_D0_MASK	3

irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);

int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
		u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode);

int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);

int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
		u8 instance_id,	enum skl_ipc_pipeline_state state);

int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
		u8 instance_id, int dma_id);

int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);

int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_init_instance_msg *msg, void *param_data);

int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
		struct skl_ipc_bind_unbind_msg *msg);

int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
				u8 module_cnt, void *data);

int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
		u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);

int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
		struct skl_ipc_large_config_msg *msg, u32 *param);

int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
			u8 dma_id, u8 table_id, bool wait);

int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc,
		struct skl_ipc_d0ix_msg *msg);

int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state);

void skl_ipc_int_enable(struct sst_dsp *dsp);
void skl_ipc_op_int_enable(struct sst_dsp *ctx);
void skl_ipc_op_int_disable(struct sst_dsp *ctx);
void skl_ipc_int_disable(struct sst_dsp *dsp);

bool skl_ipc_int_status(struct sst_dsp *dsp);
void skl_ipc_free(struct sst_generic_ipc *ipc);
int skl_ipc_init(struct device *dev, struct skl_sst *skl);
void skl_clear_module_cnt(struct sst_dsp *ctx);

void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
		struct skl_ipc_header header);
int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
		struct skl_ipc_header header);
void skl_ipc_tx_data_copy(struct ipc_message *msg, char *tx_data,
		size_t tx_size);
#endif /* __SKL_IPC_H */
Commit	Line	Data
47d7195d	1	/* SPDX-License-Identifier: GPL-2.0-only */
b81fd263 SP	2	/*
	3	* Intel SKL IPC Support
	4	*
	5	* Copyright (C) 2014-15, Intel Corporation.
b81fd263 SP	6	*/
	7
	8	#ifndef __SKL_IPC_H
	9	#define __SKL_IPC_H
	10
b81fd263 SP	11	#include <linux/irqreturn.h>
	12	#include "../common/sst-ipc.h"
	13
	14	struct sst_dsp;
	15	struct skl_sst;
	16	struct sst_generic_ipc;
	17
	18	enum skl_ipc_pipeline_state {
	19	PPL_INVALID_STATE = 0,
	20	PPL_UNINITIALIZED = 1,
	21	PPL_RESET = 2,
	22	PPL_PAUSED = 3,
	23	PPL_RUNNING = 4,
	24	PPL_ERROR_STOP = 5,
	25	PPL_SAVED = 6,
	26	PPL_RESTORED = 7
	27	};
	28
	29	struct skl_ipc_dxstate_info {
	30	u32 core_mask;
	31	u32 dx_mask;
	32	};
	33
	34	struct skl_ipc_header {
	35	u32 primary;
	36	u32 extension;
	37	};
	38
052f103c J	39	struct skl_dsp_cores {
052f103c J	40	unsigned int count;
f0a550a8 GS	41	enum skl_dsp_states *state;
f0a550a8 GS	42	int *usage_count;
052f103c J	43	};
052f103c J	44
5bb4cd46 J	45	/**
	46	* skl_d0i3_data: skl D0i3 counters data struct
	47	*
	48	* @streaming: Count of usecases that can attempt streaming D0i3
	49	* @non_streaming: Count of usecases that can attempt non-streaming D0i3
	50	* @non_d0i3: Count of usecases that cannot attempt D0i3
	51	* @state: current state
	52	* @work: D0i3 worker thread
	53	*/
	54	struct skl_d0i3_data {
	55	int streaming;
	56	int non_streaming;
	57	int non_d0i3;
	58	enum skl_dsp_d0i3_states state;
	59	struct delayed_work work;
	60	};
	61
b26199ea JK	62	#define SKL_LIB_NAME_LENGTH 128
	63	#define SKL_MAX_LIB 16
	64
	65	struct skl_lib_info {
	66	char name[SKL_LIB_NAME_LENGTH];
	67	const struct firmware *fw;
	68	};
	69
b81fd263 SP	70	struct skl_sst {
	71	struct device *dev;
	72	struct sst_dsp *dsp;
	73
	74	/* boot */
	75	wait_queue_head_t boot_wait;
	76	bool boot_complete;
	77
b7d0254c JK	78	/* module load */
	79	wait_queue_head_t mod_load_wait;
	80	bool mod_load_complete;
	81	bool mod_load_status;
	82
b81fd263 SP	83	/* IPC messaging */
b81fd263 SP	84	struct sst_generic_ipc ipc;
0c8ba9d2 J	85
	86	/* callback for miscbdge */
	87	void (enable_miscbdcge)(struct device dev, bool enable);
8d983be8	88	/* Is CGCTL.MISCBDCGE disabled */
0c8ba9d2	89	bool miscbdcg_disabled;
ea6b3e94 SN	90
	91	/* Populate module information */
	92	struct list_head uuid_list;
1665c177 J	93
	94	/* Is firmware loaded */
	95	bool fw_loaded;
052f103c	96
78cdbbda VK	97	/* first boot ? */
	98	bool is_first_boot;
	99
052f103c J	100	/* multi-core */
052f103c J	101	struct skl_dsp_cores cores;
15ecaba9	102
eee0e16f JK	103	/* library info */
	104	struct skl_lib_info lib_info[SKL_MAX_LIB];
	105	int lib_count;
a26a3f53 PS	106
	107	/* Callback to update D0i3C register */
	108	void (update_d0i3c)(struct device dev, bool enable);
5bb4cd46 J	109
5bb4cd46 J	110	struct skl_d0i3_data d0i3;
7bd86a30 K	111
7bd86a30 K	112	const struct skl_dsp_ops *dsp_ops;
fc9fdd61 SK	113
	114	/* Callback to update dynamic clock and power gating registers */
	115	void (clock_power_gating)(struct device dev, bool enable);
b81fd263 SP	116	};
	117
	118	struct skl_ipc_init_instance_msg {
	119	u32 module_id;
	120	u32 instance_id;
	121	u16 param_data_size;
	122	u8 ppl_instance_id;
	123	u8 core_id;
3d4006cd	124	u8 domain;
b81fd263 SP	125	};
	126
	127	struct skl_ipc_bind_unbind_msg {
	128	u32 module_id;
	129	u32 instance_id;
	130	u32 dst_module_id;
	131	u32 dst_instance_id;
	132	u8 src_queue;
	133	u8 dst_queue;
	134	bool bind;
	135	};
	136
	137	struct skl_ipc_large_config_msg {
	138	u32 module_id;
	139	u32 instance_id;
	140	u32 large_param_id;
	141	u32 param_data_size;
	142	};
	143
41b7523f PS	144	struct skl_ipc_d0ix_msg {
	145	u32 module_id;
	146	u32 instance_id;
	147	u8 streaming;
	148	u8 wake;
	149	};
	150
b81fd263 SP	151	#define SKL_IPC_BOOT_MSECS 3000
	152
	153	#define SKL_IPC_D3_MASK 0
	154	#define SKL_IPC_D0_MASK 3
	155
	156	irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);
	157
	158	int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
8a0cb236	159	u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode);
b81fd263 SP	160
	161	int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);
	162
	163	int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
	164	u8 instance_id, enum skl_ipc_pipeline_state state);
	165
	166	int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
	167	u8 instance_id, int dma_id);
	168
	169	int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);
	170
	171	int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
	172	struct skl_ipc_init_instance_msg msg, void param_data);
	173
	174	int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
	175	struct skl_ipc_bind_unbind_msg *msg);
	176
6c5768b3 D	177	int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
	178	u8 module_cnt, void *data);
	179
	180	int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
	181	u8 module_cnt, void *data);
	182
b81fd263 SP	183	int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
	184	u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);
	185
	186	int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
	187	struct skl_ipc_large_config_msg msg, u32 param);
	188
cce1c7f3 MJ	189	int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
	190	struct skl_ipc_large_config_msg msg, u32 param);
	191
20fb2fbd	192	int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
100e7f39	193	u8 dma_id, u8 table_id, bool wait);
20fb2fbd	194
41b7523f PS	195	int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc,
	196	struct skl_ipc_d0ix_msg *msg);
	197
a83e3b4c VK	198	int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state);
a83e3b4c VK	199
b81fd263 SP	200	void skl_ipc_int_enable(struct sst_dsp *dsp);
b81fd263 SP	201	void skl_ipc_op_int_enable(struct sst_dsp *ctx);
84c9e283	202	void skl_ipc_op_int_disable(struct sst_dsp *ctx);
b81fd263 SP	203	void skl_ipc_int_disable(struct sst_dsp *dsp);
	204
	205	bool skl_ipc_int_status(struct sst_dsp *dsp);
	206	void skl_ipc_free(struct sst_generic_ipc *ipc);
	207	int skl_ipc_init(struct device dev, struct skl_sst skl);
fe3f4442	208	void skl_clear_module_cnt(struct sst_dsp *ctx);
b81fd263	209
4bdb04f0 GS	210	void skl_ipc_process_reply(struct sst_generic_ipc *ipc,
	211	struct skl_ipc_header header);
	212	int skl_ipc_process_notification(struct sst_generic_ipc *ipc,
	213	struct skl_ipc_header header);
	214	void skl_ipc_tx_data_copy(struct ipc_message msg, char tx_data,
	215	size_t tx_size);
b81fd263	216	#endif /* __SKL_IPC_H */