[thirdparty/linux.git] / arch / arc / boot / dts / axc001.dtsi

/*
 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

/*
 * Device tree for AXC001 770D/EM6/AS221 CPU card
 * Note that this file only supports the 770D CPU
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "snps,arc";
	#address-cells = <2>;
	#size-cells = <2>;

	cpu_card {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;

		core_clk: core_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <750000000>;
		};

		core_intc: arc700-intc@cpu {
			compatible = "snps,arc700-intc";
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		/*
		 * this GPIO block ORs all interrupts on CPU card (creg,..)
		 * to uplink only 1 IRQ to ARC core intc
		 */
		dw-apb-gpio@2000 {
			compatible = "snps,dw-apb-gpio";
			reg = < 0x2000 0x80 >;
			#address-cells = <1>;
			#size-cells = <0>;

			ictl_intc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <30>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&core_intc>;
				interrupts = <15>;
			};
		};

		debug_uart: dw-apb-uart@5000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x5000 0x100>;
			clock-frequency = <33333000>;
			interrupt-parent = <&ictl_intc>;
			interrupts = <19 4>;
			baud = <115200>;
			reg-shift = <2>;
			reg-io-width = <4>;
		};

		arcpct0: pct {
			compatible = "snps,arc700-pct";
		};
	};

	/*
	 * This INTC is actually connected to DW APB GPIO
	 * which acts as a wire between MB INTC and CPU INTC.
	 * GPIO INTC is configured in platform init code
	 * and here we mimic direct connection from MB INTC to
	 * CPU INTC, thus we set "interrupts = <7>" instead of
	 * "interrupts = <12>"
	 *
	 * This intc actually resides on MB, but we move it here to
	 * avoid duplicating the MB dtsi file given that IRQ from
	 * this intc to cpu intc are different for axs101 and axs103
	 */
	mb_intc: dw-apb-ictl@e0012000 {
		#interrupt-cells = <1>;
		compatible = "snps,dw-apb-ictl";
		reg = < 0x0 0xe0012000 0x0 0x200 >;
		interrupt-controller;
		interrupt-parent = <&core_intc>;
		interrupts = < 7 >;
	};

	memory {
		device_type = "memory";
		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
		reg = <0x0 0x80000000 0x0 0x1b000000>;	/* (512 - 32) MiB */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		/*
		 * We just move frame buffer area to the very end of
		 * available DDR. And even though in case of ARC770 there's
		 * no strict requirement for a frame-buffer to be in any
		 * particular location it allows us to use the same
		 * base board's DT node for ARC PGU as for ARc HS38.
		 */
		frame_buffer: frame_buffer@9e000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9e000000 0x0 0x2000000>;
			no-map;
		};
	};
};
Commit	Line	Data
556cc1c5 AB	1	/*
	2	* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	/*
	10	* Device tree for AXC001 770D/EM6/AS221 CPU card
	11	* Note that this file only supports the 770D CPU
	12	*/
	13
2e8cd938 VG	14	/include/ "skeleton.dtsi"
2e8cd938 VG	15
556cc1c5 AB	16	/ {
556cc1c5 AB	17	compatible = "snps,arc";
f862b315 EP	18	#address-cells = <2>;
f862b315 EP	19	#size-cells = <2>;
556cc1c5 AB	20
	21	cpu_card {
	22	compatible = "simple-bus";
	23	#address-cells = <1>;
	24	#size-cells = <1>;
	25
f862b315	26	ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
556cc1c5	27
b3d6aba8 VG	28	core_clk: core_clk {
	29	#clock-cells = <0>;
	30	compatible = "fixed-clock";
	31	clock-frequency = <750000000>;
	32	};
	33
9ba7648c	34	core_intc: arc700-intc@cpu {
556cc1c5 AB	35	compatible = "snps,arc700-intc";
	36	interrupt-controller;
	37	#interrupt-cells = <1>;
	38	};
	39
	40	/*
	41	* this GPIO block ORs all interrupts on CPU card (creg,..)
	42	* to uplink only 1 IRQ to ARC core intc
	43	*/
ef4c54c3	44	dw-apb-gpio@2000 {
556cc1c5 AB	45	compatible = "snps,dw-apb-gpio";
	46	reg = < 0x2000 0x80 >;
	47	#address-cells = <1>;
	48	#size-cells = <0>;
	49
	50	ictl_intc: gpio-controller@0 {
	51	compatible = "snps,dw-apb-gpio-port";
	52	gpio-controller;
	53	#gpio-cells = <2>;
	54	snps,nr-gpios = <30>;
	55	reg = <0>;
	56	interrupt-controller;
	57	#interrupt-cells = <2>;
9ba7648c	58	interrupt-parent = <&core_intc>;
556cc1c5 AB	59	interrupts = <15>;
	60	};
	61	};
	62
ef4c54c3	63	debug_uart: dw-apb-uart@5000 {
556cc1c5 AB	64	compatible = "snps,dw-apb-uart";
	65	reg = <0x5000 0x100>;
	66	clock-frequency = <33333000>;
	67	interrupt-parent = <&ictl_intc>;
	68	interrupts = <19 4>;
	69	baud = <115200>;
	70	reg-shift = <2>;
	71	reg-io-width = <4>;
	72	};
	73
6227e9f0	74	arcpct0: pct {
556cc1c5 AB	75	compatible = "snps,arc700-pct";
	76	};
	77	};
	78
e0183f52 AB	79	/*
	80	* This INTC is actually connected to DW APB GPIO
	81	* which acts as a wire between MB INTC and CPU INTC.
	82	* GPIO INTC is configured in platform init code
	83	* and here we mimic direct connection from MB INTC to
	84	* CPU INTC, thus we set "interrupts = <7>" instead of
	85	* "interrupts = <12>"
	86	*
	87	* This intc actually resides on MB, but we move it here to
	88	* avoid duplicating the MB dtsi file given that IRQ from
	89	* this intc to cpu intc are different for axs101 and axs103
	90	*/
ef4c54c3	91	mb_intc: dw-apb-ictl@e0012000 {
e0183f52 AB	92	#interrupt-cells = <1>;
e0183f52 AB	93	compatible = "snps,dw-apb-ictl";
f862b315	94	reg = < 0x0 0xe0012000 0x0 0x200 >;
e0183f52	95	interrupt-controller;
9ba7648c	96	interrupt-parent = <&core_intc>;
e0183f52 AB	97	interrupts = < 7 >;
	98	};
	99
556cc1c5	100	memory {
556cc1c5	101	device_type = "memory";
9ed68785	102	/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
f862b315	103	reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
cb2ad5e5 AB	104	};
	105
	106	reserved-memory {
f862b315 EP	107	#address-cells = <2>;
f862b315 EP	108	#size-cells = <2>;
cb2ad5e5 AB	109	ranges;
	110	/*
	111	* We just move frame buffer area to the very end of
	112	* available DDR. And even though in case of ARC770 there's
	113	* no strict requirement for a frame-buffer to be in any
	114	* particular location it allows us to use the same
	115	* base board's DT node for ARC PGU as for ARc HS38.
	116	*/
	117	frame_buffer: frame_buffer@9e000000 {
	118	compatible = "shared-dma-pool";
f862b315	119	reg = <0x0 0x9e000000 0x0 0x2000000>;
cb2ad5e5 AB	120	no-map;
cb2ad5e5 AB	121	};
556cc1c5 AB	122	};
556cc1c5 AB	123	};