projects / thirdparty / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3b20eb23 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 285f5fa7 DW |
2 | /* |
| 3 | * iq81340mc board support | |
| 4 | * Copyright (c) 2005-2006, Intel Corporation. | |
| 285f5fa7 DW |
5 | */ |
| 6 | #include <linux/pci.h> | |
| 7 | ||
| a09e64fb | 8 | #include <mach/hardware.h> |
| 285f5fa7 DW |
9 | #include <asm/irq.h> |
| 10 | #include <asm/mach/pci.h> | |
| 11 | #include <asm/mach-types.h> | |
| 12 | #include <asm/mach/arch.h> | |
| c11fc349 | 13 | #include "pci.h" |
| 285f5fa7 | 14 | #include <asm/mach/time.h> |
| a09e64fb | 15 | #include <mach/time.h> |
| 285f5fa7 DW |
16 | |
| 17 | extern int init_atu; /* Flag to select which ATU(s) to initialize / disable */ | |
| 18 | ||
| 19 | static int __init | |
| d5341942 | 20 | iq81340mc_pcix_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) |
| 285f5fa7 DW |
21 | { |
| 22 | switch (idsel) { | |
| 23 | case 1: | |
| 24 | switch (pin) { | |
| 25 | case 1: return ATUX_INTB; | |
| 26 | case 2: return ATUX_INTC; | |
| 27 | case 3: return ATUX_INTD; | |
| 28 | case 4: return ATUX_INTA; | |
| 29 | default: return -1; | |
| 30 | } | |
| 31 | case 2: | |
| 32 | switch (pin) { | |
| 33 | case 1: return ATUX_INTC; | |
| 34 | case 2: return ATUX_INTD; | |
| 35 | case 3: return ATUX_INTC; | |
| 36 | case 4: return ATUX_INTD; | |
| 37 | default: return -1; | |
| 38 | } | |
| 39 | default: return -1; | |
| 40 | } | |
| 41 | } | |
| 42 | ||
| 43 | static struct hw_pci iq81340mc_pci __initdata = { | |
| 285f5fa7 DW |
44 | .nr_controllers = 0, |
| 45 | .setup = iop13xx_pci_setup, | |
| 46 | .map_irq = iq81340mc_pcix_map_irq, | |
| 47 | .scan = iop13xx_scan_bus, | |
| 48 | .preinit = iop13xx_pci_init, | |
| 49 | }; | |
| 50 | ||
| 51 | static int __init iq81340mc_pci_init(void) | |
| 52 | { | |
| 53 | iop13xx_atu_select(&iq81340mc_pci); | |
| 54 | pci_common_init(&iq81340mc_pci); | |
| 55 | iop13xx_map_pci_memory(); | |
| 56 | ||
| 57 | return 0; | |
| 58 | } | |
| 59 | ||
| 60 | static void __init iq81340mc_init(void) | |
| 61 | { | |
| 62 | iop13xx_platform_init(); | |
| 63 | iq81340mc_pci_init(); | |
| d2dd8b1f | 64 | iop13xx_add_tpmi_devices(); |
| 285f5fa7 DW |
65 | } |
| 66 | ||
| 67 | static void __init iq81340mc_timer_init(void) | |
| 68 | { | |
| 84c981ff | 69 | unsigned long bus_freq = iop13xx_core_freq() / iop13xx_xsi_bus_ratio(); |
| 8e86f427 | 70 | printk(KERN_DEBUG "%s: bus frequency: %lu\n", __func__, bus_freq); |
| 84c981ff | 71 | iop_init_time(bus_freq); |
| 285f5fa7 DW |
72 | } |
| 73 | ||
| 285f5fa7 DW |
74 | MACHINE_START(IQ81340MC, "Intel IQ81340MC") |
| 75 | /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ | |
| d304c54e | 76 | .atag_offset = 0x100, |
| 1dfe34ae | 77 | .init_early = iop13xx_init_early, |
| 285f5fa7 DW |
78 | .map_io = iop13xx_map_io, |
| 79 | .init_irq = iop13xx_init_irq, | |
| 6bb27d73 | 80 | .init_time = iq81340mc_timer_init, |
| 285f5fa7 | 81 | .init_machine = iq81340mc_init, |
| 00aa78ee | 82 | .restart = iop13xx_restart, |
| 37ebbcff | 83 | .nr_irqs = NR_IOP13XX_IRQS, |
| 285f5fa7 | 84 | MACHINE_END |