[thirdparty/linux.git] / arch / arm / mach-ixp4xx / include / mach / ixp4xx-regs.h

/*
 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
 *
 * Register definitions for IXP4xx chipset. This file contains 
 * register location and bit definitions only. Platform specific 
 * definitions and helper function declarations are in platform.h 
 * and machine-name.h.
 *
 * Copyright (C) 2002 Intel Corporation.
 * Copyright (C) 2003-2004 MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef _ASM_ARM_IXP4XX_H_
#define _ASM_ARM_IXP4XX_H_

/*
 * IXP4xx Linux Memory Map:
 *
 * Phy		Size		Virt		Description
 * =========================================================================
 *
 * 0x00000000	0x10000000(max)	PAGE_OFFSET	System RAM
 *
 * 0x48000000	0x04000000	ioremap'd	PCI Memory Space
 *
 * 0x50000000	0x10000000	ioremap'd	EXP BUS
 *
 * 0xC8000000	0x00013000	0xFEF00000	On-Chip Peripherals
 *
 * 0xC0000000	0x00001000	0xFEF13000	PCI CFG
 *
 * 0xC4000000	0x00001000	0xFEF14000	EXP CFG
 *
 * 0x60000000	0x00004000	0xFEF15000	QMgr
 */

/*
 * Queue Manager
 */
#define IXP4XX_QMGR_BASE_PHYS		0x60000000
#define IXP4XX_QMGR_BASE_VIRT		IOMEM(0xFEF15000)
#define IXP4XX_QMGR_REGION_SIZE		0x00004000

/*
 * Peripheral space, including debug UART. Must be section-aligned so that
 * it can be used with the low-level debug code.
 */
#define IXP4XX_PERIPHERAL_BASE_PHYS	0xC8000000
#define IXP4XX_PERIPHERAL_BASE_VIRT	IOMEM(0xFEF00000)
#define IXP4XX_PERIPHERAL_REGION_SIZE	0x00013000

/*
 * PCI Config registers
 */
#define IXP4XX_PCI_CFG_BASE_PHYS	0xC0000000
#define IXP4XX_PCI_CFG_BASE_VIRT	IOMEM(0xFEF13000)
#define IXP4XX_PCI_CFG_REGION_SIZE	0x00001000

/*
 * Expansion BUS Configuration registers
 */
#define IXP4XX_EXP_CFG_BASE_PHYS	0xC4000000
#define IXP4XX_EXP_CFG_BASE_VIRT	0xFEF14000
#define IXP4XX_EXP_CFG_REGION_SIZE	0x00001000

#define IXP4XX_EXP_CS0_OFFSET	0x00
#define IXP4XX_EXP_CS1_OFFSET   0x04
#define IXP4XX_EXP_CS2_OFFSET   0x08
#define IXP4XX_EXP_CS3_OFFSET   0x0C
#define IXP4XX_EXP_CS4_OFFSET   0x10
#define IXP4XX_EXP_CS5_OFFSET   0x14
#define IXP4XX_EXP_CS6_OFFSET   0x18
#define IXP4XX_EXP_CS7_OFFSET   0x1C
#define IXP4XX_EXP_CFG0_OFFSET	0x20
#define IXP4XX_EXP_CFG1_OFFSET	0x24
#define IXP4XX_EXP_CFG2_OFFSET	0x28
#define IXP4XX_EXP_CFG3_OFFSET	0x2C

/*
 * Expansion Bus Controller registers.
 */
#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))

#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 
#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     
#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)

#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 
#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 
#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 
#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)


/*
 * Peripheral Space Register Region Base Addresses
 */
#define IXP4XX_UART1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
#define IXP4XX_UART2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
#define IXP4XX_PMU_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
#define IXP4XX_INTC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
#define IXP4XX_GPIO_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
#define IXP4XX_TIMER_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
#define IXP4XX_NPEA_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
#define IXP4XX_NPEB_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
#define IXP4XX_NPEC_BASE_PHYS   	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
#define IXP4XX_EthB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
#define IXP4XX_EthC_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
#define IXP4XX_USB_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
/* ixp46X only */
#define IXP4XX_EthA_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
#define IXP4XX_EthB1_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
#define IXP4XX_EthB2_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
#define IXP4XX_EthB3_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
#define IXP4XX_TIMESYNC_BASE_PHYS	(IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
#define IXP4XX_I2C_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
#define IXP4XX_SSP_BASE_PHYS		(IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)


#define IXP4XX_UART1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
#define IXP4XX_UART2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
#define IXP4XX_PMU_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
#define IXP4XX_INTC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
#define IXP4XX_GPIO_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
#define IXP4XX_TIMER_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
#define IXP4XX_EthB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
#define IXP4XX_EthC_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
#define IXP4XX_USB_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
/* ixp46X only */
#define IXP4XX_EthA_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
#define IXP4XX_EthB1_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
#define IXP4XX_EthB2_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
#define IXP4XX_EthB3_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
#define IXP4XX_TIMESYNC_BASE_VIRT	(IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
#define IXP4XX_I2C_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
#define IXP4XX_SSP_BASE_VIRT		(IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)

/*
 * Constants to make it easy to access Timer Control/Status registers
 */
#define IXP4XX_OSTS_OFFSET	0x00  /* Continious TimeStamp */
#define IXP4XX_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
#define IXP4XX_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
#define IXP4XX_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
#define IXP4XX_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
#define IXP4XX_OSWT_OFFSET	0x14  /* Watchdog Timer */
#define IXP4XX_OSWE_OFFSET	0x18  /* Watchdog Enable */
#define IXP4XX_OSWK_OFFSET	0x1C  /* Watchdog Key */
#define IXP4XX_OSST_OFFSET	0x20  /* Timer Status */

/*
 * Operating System Timer Register Definitions.
 */

#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))

#define IXP4XX_OSTS	IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
#define IXP4XX_OST1	IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
#define IXP4XX_OSRT1	IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
#define IXP4XX_OST2	IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
#define IXP4XX_OSRT2	IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
#define IXP4XX_OSWT	IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
#define IXP4XX_OSWE	IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
#define IXP4XX_OSWK	IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
#define IXP4XX_OSST	IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)

/*
 * Timer register values and bit definitions 
 */
#define IXP4XX_OST_ENABLE		0x00000001
#define IXP4XX_OST_ONE_SHOT		0x00000002
/* Low order bits of reload value ignored */
#define IXP4XX_OST_RELOAD_MASK		0x00000003
#define IXP4XX_OST_DISABLED		0x00000000
#define IXP4XX_OSST_TIMER_1_PEND	0x00000001
#define IXP4XX_OSST_TIMER_2_PEND	0x00000002
#define IXP4XX_OSST_TIMER_TS_PEND	0x00000004
#define IXP4XX_OSST_TIMER_WDOG_PEND	0x00000008
#define IXP4XX_OSST_TIMER_WARM_RESET	0x00000010

#define	IXP4XX_WDT_KEY			0x0000482E

#define	IXP4XX_WDT_RESET_ENABLE		0x00000001
#define	IXP4XX_WDT_IRQ_ENABLE		0x00000002
#define	IXP4XX_WDT_COUNT_ENABLE		0x00000004


/*
 * Constants to make it easy to access PCI Control/Status registers
 */
#define PCI_NP_AD_OFFSET            0x00
#define PCI_NP_CBE_OFFSET           0x04
#define PCI_NP_WDATA_OFFSET         0x08
#define PCI_NP_RDATA_OFFSET         0x0c
#define PCI_CRP_AD_CBE_OFFSET       0x10
#define PCI_CRP_WDATA_OFFSET        0x14
#define PCI_CRP_RDATA_OFFSET        0x18
#define PCI_CSR_OFFSET              0x1c
#define PCI_ISR_OFFSET              0x20
#define PCI_INTEN_OFFSET            0x24
#define PCI_DMACTRL_OFFSET          0x28
#define PCI_AHBMEMBASE_OFFSET       0x2c
#define PCI_AHBIOBASE_OFFSET        0x30
#define PCI_PCIMEMBASE_OFFSET       0x34
#define PCI_AHBDOORBELL_OFFSET      0x38
#define PCI_PCIDOORBELL_OFFSET      0x3C
#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
#define PCI_ATPDMA1_LENADDR_OFFSET	0x54

/*
 * PCI Control/Status Registers
 */
#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))

#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 
#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)

/*
 * PCI register values and bit definitions 
 */

/* CSR bit definitions */
#define PCI_CSR_HOST    	0x00000001
#define PCI_CSR_ARBEN   	0x00000002
#define PCI_CSR_ADS     	0x00000004
#define PCI_CSR_PDS     	0x00000008
#define PCI_CSR_ABE     	0x00000010
#define PCI_CSR_DBT     	0x00000020
#define PCI_CSR_ASE     	0x00000100
#define PCI_CSR_IC      	0x00008000

/* ISR (Interrupt status) Register bit definitions */
#define PCI_ISR_PSE     	0x00000001
#define PCI_ISR_PFE     	0x00000002
#define PCI_ISR_PPE     	0x00000004
#define PCI_ISR_AHBE    	0x00000008
#define PCI_ISR_APDC    	0x00000010
#define PCI_ISR_PADC    	0x00000020
#define PCI_ISR_ADB     	0x00000040
#define PCI_ISR_PDB     	0x00000080

/* INTEN (Interrupt Enable) Register bit definitions */
#define PCI_INTEN_PSE   	0x00000001
#define PCI_INTEN_PFE   	0x00000002
#define PCI_INTEN_PPE   	0x00000004
#define PCI_INTEN_AHBE  	0x00000008
#define PCI_INTEN_APDC  	0x00000010
#define PCI_INTEN_PADC  	0x00000020
#define PCI_INTEN_ADB   	0x00000040
#define PCI_INTEN_PDB   	0x00000080

/*
 * Shift value for byte enable on NP cmd/byte enable register
 */
#define IXP4XX_PCI_NP_CBE_BESL		4

/*
 * PCI commands supported by NP access unit
 */
#define NP_CMD_IOREAD			0x2
#define NP_CMD_IOWRITE			0x3
#define NP_CMD_CONFIGREAD		0xa
#define NP_CMD_CONFIGWRITE		0xb
#define NP_CMD_MEMREAD			0x6
#define	NP_CMD_MEMWRITE			0x7

/*
 * Constants for CRP access into local config space
 */
#define CRP_AD_CBE_BESL         20
#define CRP_AD_CBE_WRITE	0x00010000

#define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */

/* "fuse" bits of IXP_EXP_CFG2 */
/* All IXP4xx CPUs */
#define IXP4XX_FEATURE_RCOMP		(1 << 0)
#define IXP4XX_FEATURE_USB_DEVICE	(1 << 1)
#define IXP4XX_FEATURE_HASH		(1 << 2)
#define IXP4XX_FEATURE_AES		(1 << 3)
#define IXP4XX_FEATURE_DES		(1 << 4)
#define IXP4XX_FEATURE_HDLC		(1 << 5)
#define IXP4XX_FEATURE_AAL		(1 << 6)
#define IXP4XX_FEATURE_HSS		(1 << 7)
#define IXP4XX_FEATURE_UTOPIA		(1 << 8)
#define IXP4XX_FEATURE_NPEB_ETH0	(1 << 9)
#define IXP4XX_FEATURE_NPEC_ETH		(1 << 10)
#define IXP4XX_FEATURE_RESET_NPEA	(1 << 11)
#define IXP4XX_FEATURE_RESET_NPEB	(1 << 12)
#define IXP4XX_FEATURE_RESET_NPEC	(1 << 13)
#define IXP4XX_FEATURE_PCI		(1 << 14)
#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT	(3 << 16)
#define IXP4XX_FEATURE_XSCALE_MAX_FREQ	(3 << 22)
#define IXP42X_FEATURE_MASK		(IXP4XX_FEATURE_RCOMP            | \
					 IXP4XX_FEATURE_USB_DEVICE       | \
					 IXP4XX_FEATURE_HASH             | \
					 IXP4XX_FEATURE_AES              | \
					 IXP4XX_FEATURE_DES              | \
					 IXP4XX_FEATURE_HDLC             | \
					 IXP4XX_FEATURE_AAL              | \
					 IXP4XX_FEATURE_HSS              | \
					 IXP4XX_FEATURE_UTOPIA           | \
					 IXP4XX_FEATURE_NPEB_ETH0        | \
					 IXP4XX_FEATURE_NPEC_ETH         | \
					 IXP4XX_FEATURE_RESET_NPEA       | \
					 IXP4XX_FEATURE_RESET_NPEB       | \
					 IXP4XX_FEATURE_RESET_NPEC       | \
					 IXP4XX_FEATURE_PCI              | \
					 IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \
					 IXP4XX_FEATURE_XSCALE_MAX_FREQ)


/* IXP43x/46x CPUs */
#define IXP4XX_FEATURE_ECC_TIMESYNC	(1 << 15)
#define IXP4XX_FEATURE_USB_HOST		(1 << 18)
#define IXP4XX_FEATURE_NPEA_ETH		(1 << 19)
#define IXP43X_FEATURE_MASK		(IXP42X_FEATURE_MASK             | \
					 IXP4XX_FEATURE_ECC_TIMESYNC     | \
					 IXP4XX_FEATURE_USB_HOST         | \
					 IXP4XX_FEATURE_NPEA_ETH)

/* IXP46x CPU (including IXP455) only */
#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3	(1 << 20)
#define IXP4XX_FEATURE_RSA		(1 << 21)
#define IXP46X_FEATURE_MASK		(IXP43X_FEATURE_MASK             | \
					 IXP4XX_FEATURE_NPEB_ETH_1_TO_3  | \
					 IXP4XX_FEATURE_RSA)

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
1da177e4 LT	3	*
	4	* Register definitions for IXP4xx chipset. This file contains
	5	* register location and bit definitions only. Platform specific
	6	* definitions and helper function declarations are in platform.h
	7	* and machine-name.h.
	8	*
	9	* Copyright (C) 2002 Intel Corporation.
	10	* Copyright (C) 2003-2004 MontaVista Software, Inc.
	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*
	16	*/
	17
1da177e4 LT	18	#ifndef _ASM_ARM_IXP4XX_H_
	19	#define _ASM_ARM_IXP4XX_H_
	20
	21	/*
	22	* IXP4xx Linux Memory Map:
	23	*
	24	* Phy Size Virt Description
	25	* =========================================================================
	26	*
	27	* 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
	28	*
	29	* 0x48000000 0x04000000 ioremap'd PCI Memory Space
	30	*
	31	* 0x50000000 0x10000000 ioremap'd EXP BUS
	32	*
b7b23db7	33	* 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals
1da177e4	34	*
b7b23db7	35	* 0xC0000000 0x00001000 0xFEF13000 PCI CFG
1da177e4	36	*
b7b23db7	37	* 0xC4000000 0x00001000 0xFEF14000 EXP CFG
1da177e4	38	*
b7b23db7	39	* 0x60000000 0x00004000 0xFEF15000 QMgr
1da177e4 LT	40	*/
	41
	42	/*
	43	* Queue Manager
	44	*/
b7b23db7 KH	45	#define IXP4XX_QMGR_BASE_PHYS 0x60000000
	46	#define IXP4XX_QMGR_BASE_VIRT IOMEM(0xFEF15000)
	47	#define IXP4XX_QMGR_REGION_SIZE 0x00004000
1da177e4 LT	48
1da177e4 LT	49	/*
b7b23db7 KH	50	* Peripheral space, including debug UART. Must be section-aligned so that
b7b23db7 KH	51	* it can be used with the low-level debug code.
1da177e4	52	*/
b7b23db7 KH	53	#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000
	54	#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000)
	55	#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000
1da177e4 LT	56
	57	/*
	58	* PCI Config registers
	59	*/
b7b23db7 KH	60	#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000
	61	#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000)
	62	#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000
1da177e4	63
5932ae3f	64	/*
b7b23db7	65	* Expansion BUS Configuration registers
5932ae3f	66	*/
b7b23db7 KH	67	#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000
	68	#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000
	69	#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000
5932ae3f	70
1da177e4 LT	71	#define IXP4XX_EXP_CS0_OFFSET 0x00
	72	#define IXP4XX_EXP_CS1_OFFSET 0x04
	73	#define IXP4XX_EXP_CS2_OFFSET 0x08
	74	#define IXP4XX_EXP_CS3_OFFSET 0x0C
	75	#define IXP4XX_EXP_CS4_OFFSET 0x10
	76	#define IXP4XX_EXP_CS5_OFFSET 0x14
	77	#define IXP4XX_EXP_CS6_OFFSET 0x18
	78	#define IXP4XX_EXP_CS7_OFFSET 0x1C
	79	#define IXP4XX_EXP_CFG0_OFFSET 0x20
	80	#define IXP4XX_EXP_CFG1_OFFSET 0x24
	81	#define IXP4XX_EXP_CFG2_OFFSET 0x28
	82	#define IXP4XX_EXP_CFG3_OFFSET 0x2C
	83
	84	/*
	85	* Expansion Bus Controller registers.
	86	*/
13ec32f4	87	#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
1da177e4 LT	88
	89	#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
	90	#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
	91	#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
	92	#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
	93	#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
	94	#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
	95	#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
	96	#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
	97
	98	#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
	99	#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
	100	#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
	101	#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
	102
	103
	104	/*
	105	* Peripheral Space Register Region Base Addresses
	106	*/
c514e58c KT	107	#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
	108	#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
	109	#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
	110	#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
	111	#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
	112	#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
	113	#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000)
	114	#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000)
	115	#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000)
	116	#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
	117	#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
	118	#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
	119	/* ixp46X only */
	120	#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000)
	121	#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000)
	122	#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000)
	123	#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000)
	124	#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000)
	125	#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000)
	126	#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000)
	127
	128
	129	#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
	130	#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
	131	#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
	132	#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
	133	#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
	134	#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
c514e58c KT	135	#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
	136	#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
	137	#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
	138	/* ixp46X only */
	139	#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000)
	140	#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000)
	141	#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000)
	142	#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000)
	143	#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000)
	144	#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000)
	145	#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000)
1da177e4	146
1da177e4 LT	147	/*
	148	* Constants to make it easy to access Timer Control/Status registers
	149	*/
	150	#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
	151	#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
	152	#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
	153	#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
	154	#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
	155	#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
	156	#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
	157	#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
	158	#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
	159
	160	/*
	161	* Operating System Timer Register Definitions.
	162	*/
	163
	164	#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
	165
	166	#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
	167	#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
	168	#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
	169	#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
	170	#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
	171	#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
	172	#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
	173	#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
	174	#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
	175
	176	/*
	177	* Timer register values and bit definitions
	178	*/
	179	#define IXP4XX_OST_ENABLE 0x00000001
	180	#define IXP4XX_OST_ONE_SHOT 0x00000002
	181	/* Low order bits of reload value ignored */
	182	#define IXP4XX_OST_RELOAD_MASK 0x00000003
	183	#define IXP4XX_OST_DISABLED 0x00000000
	184	#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
	185	#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
	186	#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
	187	#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
	188	#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
	189
	190	#define IXP4XX_WDT_KEY 0x0000482E
	191
	192	#define IXP4XX_WDT_RESET_ENABLE 0x00000001
	193	#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
	194	#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
	195
	196
	197	/*
	198	* Constants to make it easy to access PCI Control/Status registers
	199	*/
	200	#define PCI_NP_AD_OFFSET 0x00
	201	#define PCI_NP_CBE_OFFSET 0x04
	202	#define PCI_NP_WDATA_OFFSET 0x08
	203	#define PCI_NP_RDATA_OFFSET 0x0c
	204	#define PCI_CRP_AD_CBE_OFFSET 0x10
	205	#define PCI_CRP_WDATA_OFFSET 0x14
	206	#define PCI_CRP_RDATA_OFFSET 0x18
	207	#define PCI_CSR_OFFSET 0x1c
	208	#define PCI_ISR_OFFSET 0x20
	209	#define PCI_INTEN_OFFSET 0x24
	210	#define PCI_DMACTRL_OFFSET 0x28
211	#define PCI_AHBMEMBASE_OFFSET 0x2c
212	#define PCI_AHBIOBASE_OFFSET 0x30
213	#define PCI_PCIMEMBASE_OFFSET 0x34
214	#define PCI_AHBDOORBELL_OFFSET 0x38
215	#define PCI_PCIDOORBELL_OFFSET 0x3C
216	#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
217	#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
218	#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
219	#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
220	#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
221	#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
222
223	/*
224	* PCI Control/Status Registers
225	*/
226	#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
227
228	#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
229	#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
230	#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
231	#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
232	#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
233	#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
234	#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
235	#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
236	#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
237	#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
238	#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
239	#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
240	#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
241	#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
242	#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
243	#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
244	#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
245	#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
246	#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
247	#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
248	#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
249	#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
250
251	/*
252	* PCI register values and bit definitions
253	*/
254
255	/* CSR bit definitions */
256	#define PCI_CSR_HOST 0x00000001
257	#define PCI_CSR_ARBEN 0x00000002
258	#define PCI_CSR_ADS 0x00000004
259	#define PCI_CSR_PDS 0x00000008
260	#define PCI_CSR_ABE 0x00000010
261	#define PCI_CSR_DBT 0x00000020
262	#define PCI_CSR_ASE 0x00000100
263	#define PCI_CSR_IC 0x00008000
264
265	/* ISR (Interrupt status) Register bit definitions */
266	#define PCI_ISR_PSE 0x00000001
267	#define PCI_ISR_PFE 0x00000002
268	#define PCI_ISR_PPE 0x00000004
269	#define PCI_ISR_AHBE 0x00000008
270	#define PCI_ISR_APDC 0x00000010
271	#define PCI_ISR_PADC 0x00000020
272	#define PCI_ISR_ADB 0x00000040
273	#define PCI_ISR_PDB 0x00000080
274
275	/* INTEN (Interrupt Enable) Register bit definitions */
276	#define PCI_INTEN_PSE 0x00000001
277	#define PCI_INTEN_PFE 0x00000002
278	#define PCI_INTEN_PPE 0x00000004
279	#define PCI_INTEN_AHBE 0x00000008
280	#define PCI_INTEN_APDC 0x00000010
281	#define PCI_INTEN_PADC 0x00000020
282	#define PCI_INTEN_ADB 0x00000040
283	#define PCI_INTEN_PDB 0x00000080
284
285	/*
286	* Shift value for byte enable on NP cmd/byte enable register
287	*/
288	#define IXP4XX_PCI_NP_CBE_BESL 4
289
290	/*
291	* PCI commands supported by NP access unit
292	*/
293	#define NP_CMD_IOREAD 0x2
294	#define NP_CMD_IOWRITE 0x3
295	#define NP_CMD_CONFIGREAD 0xa
296	#define NP_CMD_CONFIGWRITE 0xb
297	#define NP_CMD_MEMREAD 0x6
298	#define NP_CMD_MEMWRITE 0x7
299
300	/*
301	* Constants for CRP access into local config space
302	*/
303	#define CRP_AD_CBE_BESL 20
304	#define CRP_AD_CBE_WRITE 0x00010000
305
1da177e4 LT	306	#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
1da177e4 LT	307
c18f6581	308	/* "fuse" bits of IXP_EXP_CFG2 */
de3ce856	309	/* All IXP4xx CPUs */
c18f6581 KH	310	#define IXP4XX_FEATURE_RCOMP (1 << 0)
	311	#define IXP4XX_FEATURE_USB_DEVICE (1 << 1)
	312	#define IXP4XX_FEATURE_HASH (1 << 2)
	313	#define IXP4XX_FEATURE_AES (1 << 3)
	314	#define IXP4XX_FEATURE_DES (1 << 4)
	315	#define IXP4XX_FEATURE_HDLC (1 << 5)
	316	#define IXP4XX_FEATURE_AAL (1 << 6)
	317	#define IXP4XX_FEATURE_HSS (1 << 7)
	318	#define IXP4XX_FEATURE_UTOPIA (1 << 8)
	319	#define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9)
	320	#define IXP4XX_FEATURE_NPEC_ETH (1 << 10)
	321	#define IXP4XX_FEATURE_RESET_NPEA (1 << 11)
	322	#define IXP4XX_FEATURE_RESET_NPEB (1 << 12)
	323	#define IXP4XX_FEATURE_RESET_NPEC (1 << 13)
	324	#define IXP4XX_FEATURE_PCI (1 << 14)
c18f6581	325	#define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16)
de3ce856 KH	326	#define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22)
	327	#define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP \| \
	328	IXP4XX_FEATURE_USB_DEVICE \| \
	329	IXP4XX_FEATURE_HASH \| \
	330	IXP4XX_FEATURE_AES \| \
	331	IXP4XX_FEATURE_DES \| \
	332	IXP4XX_FEATURE_HDLC \| \
	333	IXP4XX_FEATURE_AAL \| \
	334	IXP4XX_FEATURE_HSS \| \
	335	IXP4XX_FEATURE_UTOPIA \| \
	336	IXP4XX_FEATURE_NPEB_ETH0 \| \
	337	IXP4XX_FEATURE_NPEC_ETH \| \
	338	IXP4XX_FEATURE_RESET_NPEA \| \
	339	IXP4XX_FEATURE_RESET_NPEB \| \
	340	IXP4XX_FEATURE_RESET_NPEC \| \
	341	IXP4XX_FEATURE_PCI \| \
	342	IXP4XX_FEATURE_UTOPIA_PHY_LIMIT \| \
	343	IXP4XX_FEATURE_XSCALE_MAX_FREQ)
	344
	345
	346	/* IXP43x/46x CPUs */
	347	#define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15)
c18f6581 KH	348	#define IXP4XX_FEATURE_USB_HOST (1 << 18)
c18f6581 KH	349	#define IXP4XX_FEATURE_NPEA_ETH (1 << 19)
de3ce856 KH	350	#define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK \| \
	351	IXP4XX_FEATURE_ECC_TIMESYNC \| \
	352	IXP4XX_FEATURE_USB_HOST \| \
	353	IXP4XX_FEATURE_NPEA_ETH)
	354
	355	/* IXP46x CPU (including IXP455) only */
c18f6581 KH	356	#define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20)
c18f6581 KH	357	#define IXP4XX_FEATURE_RSA (1 << 21)
de3ce856 KH	358	#define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK \| \
	359	IXP4XX_FEATURE_NPEB_ETH_1_TO_3 \| \
	360	IXP4XX_FEATURE_RSA)
c18f6581	361
1da177e4	362	#endif