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3145d8a6 RW |
1 | /* |
2 | * arch/arm/mach-ixp4xx/nas100d-pci.c | |
3 | * | |
4 | * NAS 100d board-level PCI initialization | |
5 | * | |
6 | * based on ixdp425-pci.c: | |
7 | * Copyright (C) 2002 Intel Corporation. | |
8 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
9 | * | |
10 | * Maintainer: http://www.nslu2-linux.org/ | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | */ | |
17 | ||
3145d8a6 RW |
18 | #include <linux/pci.h> |
19 | #include <linux/init.h> | |
698dfe2b | 20 | #include <linux/irq.h> |
3145d8a6 RW |
21 | #include <asm/mach/pci.h> |
22 | #include <asm/mach-types.h> | |
23 | ||
dc8ef8cd LW |
24 | #include "irqs.h" |
25 | ||
8d3fdf31 KH |
26 | #define MAX_DEV 3 |
27 | #define IRQ_LINES 3 | |
23fa6846 KH |
28 | |
29 | /* PCI controller GPIO to IRQ pin mappings */ | |
8d3fdf31 KH |
30 | #define INTA 11 |
31 | #define INTB 10 | |
32 | #define INTC 9 | |
33 | #define INTD 8 | |
34 | #define INTE 7 | |
23fa6846 | 35 | |
3145d8a6 RW |
36 | void __init nas100d_pci_preinit(void) |
37 | { | |
6845664a TG |
38 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
39 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
40 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); | |
41 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); | |
42 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); | |
3145d8a6 RW |
43 | ixp4xx_pci_preinit(); |
44 | } | |
45 | ||
d5341942 | 46 | static int __init nas100d_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
3145d8a6 | 47 | { |
8d3fdf31 KH |
48 | static int pci_irq_table[MAX_DEV][IRQ_LINES] = { |
49 | { IXP4XX_GPIO_IRQ(INTA), -1, -1 }, | |
50 | { IXP4XX_GPIO_IRQ(INTB), -1, -1 }, | |
51 | { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), | |
52 | IXP4XX_GPIO_IRQ(INTE) }, | |
3145d8a6 RW |
53 | }; |
54 | ||
8d3fdf31 KH |
55 | if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES) |
56 | return pci_irq_table[slot - 1][pin - 1]; | |
3145d8a6 | 57 | |
8d3fdf31 | 58 | return -1; |
3145d8a6 RW |
59 | } |
60 | ||
61 | struct hw_pci __initdata nas100d_pci = { | |
62 | .nr_controllers = 1, | |
c23bfc38 | 63 | .ops = &ixp4xx_ops, |
3145d8a6 | 64 | .preinit = nas100d_pci_preinit, |
3145d8a6 | 65 | .setup = ixp4xx_setup, |
3145d8a6 RW |
66 | .map_irq = nas100d_map_irq, |
67 | }; | |
68 | ||
69 | int __init nas100d_pci_init(void) | |
70 | { | |
71 | if (machine_is_nas100d()) | |
72 | pci_common_init(&nas100d_pci); | |
73 | ||
74 | return 0; | |
75 | } | |
76 | ||
77 | subsys_initcall(nas100d_pci_init); |