projects / thirdparty / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ee977c2c MZ |
1 | /* |
| 2 | * arch/arch/mach-ixp4xx/vulcan-pci.c | |
| 3 | * | |
| 4 | * Vulcan board-level PCI initialization | |
| 5 | * | |
| 6 | * Copyright (C) 2010 Marc Zyngier <maz@misterjones.org> | |
| 7 | * | |
| 8 | * based on ixdp425-pci.c: | |
| 9 | * Copyright (C) 2002 Intel Corporation. | |
| 10 | * Copyright (C) 2003-2004 MontaVista Software, Inc. | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | * | |
| 16 | */ | |
| 17 | ||
| 18 | #include <linux/pci.h> | |
| 19 | #include <linux/init.h> | |
| 20 | #include <linux/irq.h> | |
| 21 | #include <asm/mach/pci.h> | |
| 22 | #include <asm/mach-types.h> | |
| 23 | ||
| 140d9009 AB |
24 | #include "irqs.h" |
| 25 | ||
| ee977c2c MZ |
26 | /* PCI controller GPIO to IRQ pin mappings */ |
| 27 | #define INTA 2 | |
| 28 | #define INTB 3 | |
| 29 | ||
| 30 | void __init vulcan_pci_preinit(void) | |
| 31 | { | |
| 32 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | |
| 33 | /* | |
| 34 | * Cardbus bridge wants way more than the SoC can actually offer, | |
| 35 | * and leaves the whole PCI bus in a mess. Artificially limit it | |
| 36 | * to 8MB per region. Of course indirect mode doesn't have this | |
| 37 | * limitation... | |
| 38 | */ | |
| 39 | pci_cardbus_mem_size = SZ_8M; | |
| 40 | pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", | |
| 41 | (int)(pci_cardbus_mem_size >> 20)); | |
| 42 | #endif | |
| 6845664a TG |
43 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); |
| 44 | irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); | |
| ee977c2c MZ |
45 | ixp4xx_pci_preinit(); |
| 46 | } | |
| 47 | ||
| d5341942 | 48 | static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| ee977c2c MZ |
49 | { |
| 50 | if (slot == 1) | |
| 51 | return IXP4XX_GPIO_IRQ(INTA); | |
| 52 | ||
| 53 | if (slot == 2) | |
| 54 | return IXP4XX_GPIO_IRQ(INTB); | |
| 55 | ||
| 56 | return -1; | |
| 57 | } | |
| 58 | ||
| 59 | struct hw_pci vulcan_pci __initdata = { | |
| 60 | .nr_controllers = 1, | |
| c23bfc38 | 61 | .ops = &ixp4xx_ops, |
| ee977c2c | 62 | .preinit = vulcan_pci_preinit, |
| ee977c2c | 63 | .setup = ixp4xx_setup, |
| ee977c2c MZ |
64 | .map_irq = vulcan_map_irq, |
| 65 | }; | |
| 66 | ||
| 67 | int __init vulcan_pci_init(void) | |
| 68 | { | |
| 69 | if (machine_is_arcom_vulcan()) | |
| 70 | pci_common_init(&vulcan_pci); | |
| 71 | return 0; | |
| 72 | } | |
| 73 | ||
| 74 | subsys_initcall(vulcan_pci_init); |