]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0f279ebd TR |
2 | /dts-v1/; |
3 | ||
4 | #include <dt-bindings/input/input.h> | |
5 | #include "tegra132.dtsi" | |
6 | ||
7 | / { | |
8 | model = "NVIDIA Tegra132 Norrin"; | |
9 | compatible = "nvidia,norrin", "nvidia,tegra132", "nvidia,tegra124"; | |
10 | ||
11 | aliases { | |
be70771d TR |
12 | rtc0 = "/i2c@7000d000/as3722@40"; |
13 | rtc1 = "/rtc@7000e000"; | |
69e29bd1 | 14 | serial0 = &uarta; |
0f279ebd TR |
15 | }; |
16 | ||
69e29bd1 JH |
17 | chosen { |
18 | stdout-path = "serial0:115200n8"; | |
19 | }; | |
43acf831 | 20 | |
772a6a7b | 21 | memory@80000000 { |
0f279ebd TR |
22 | device_type = "memory"; |
23 | reg = <0x0 0x80000000 0x0 0x80000000>; | |
24 | }; | |
25 | ||
be70771d TR |
26 | host1x@50000000 { |
27 | hdmi@54280000 { | |
0f279ebd TR |
28 | status = "disabled"; |
29 | ||
30 | vdd-supply = <&vdd_3v3_hdmi>; | |
31 | pll-supply = <&vdd_hdmi_pll>; | |
32 | hdmi-supply = <&vdd_5v0_hdmi>; | |
33 | ||
34 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
35 | nvidia,hpd-gpio = | |
36 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
37 | }; | |
38 | ||
be70771d | 39 | sor@54540000 { |
0f279ebd TR |
40 | status = "okay"; |
41 | ||
eb93bd8d TR |
42 | avdd-io-hdmi-dp-supply = <&vdd_3v3_hdmi>; |
43 | vdd-hdmi-dp-pll-supply = <&vdd_hdmi_pll>; | |
44 | ||
0f279ebd TR |
45 | nvidia,dpaux = <&dpaux>; |
46 | nvidia,panel = <&panel>; | |
47 | }; | |
48 | ||
be70771d | 49 | dpaux: dpaux@545c0000 { |
0f279ebd TR |
50 | vdd-supply = <&vdd_3v3_panel>; |
51 | status = "okay"; | |
52 | }; | |
53 | }; | |
54 | ||
be70771d | 55 | gpu@57000000 { |
0f279ebd TR |
56 | status = "okay"; |
57 | ||
58 | vdd-supply = <&vdd_gpu>; | |
59 | }; | |
60 | ||
be70771d | 61 | pinmux@70000868 { |
0f279ebd TR |
62 | pinctrl-names = "default"; |
63 | pinctrl-0 = <&pinmux_default>; | |
64 | ||
efe499d8 | 65 | pinmux_default: pinmux { |
0f279ebd TR |
66 | dap_mclk1_pw4 { |
67 | nvidia,pins = "dap_mclk1_pw4"; | |
68 | nvidia,function = "extperiph1"; | |
69 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
70 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
71 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
72 | }; | |
73 | dap2_din_pa4 { | |
74 | nvidia,pins = "dap2_din_pa4"; | |
75 | nvidia,function = "i2s1"; | |
76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
78 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
79 | }; | |
80 | dap2_dout_pa5 { | |
81 | nvidia,pins = "dap2_dout_pa5", | |
82 | "dap2_fs_pa2", | |
83 | "dap2_sclk_pa3"; | |
84 | nvidia,function = "i2s1"; | |
85 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
86 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
87 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
88 | }; | |
89 | dap3_dout_pp2 { | |
90 | nvidia,pins = "dap3_dout_pp2"; | |
91 | nvidia,function = "i2s2"; | |
92 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
93 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
94 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
95 | }; | |
96 | dvfs_pwm_px0 { | |
97 | nvidia,pins = "dvfs_pwm_px0", | |
98 | "dvfs_clk_px2"; | |
99 | nvidia,function = "cldvfs"; | |
100 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
101 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
102 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
103 | }; | |
104 | ulpi_clk_py0 { | |
105 | nvidia,pins = "ulpi_clk_py0", | |
106 | "ulpi_nxt_py2", | |
107 | "ulpi_stp_py3"; | |
108 | nvidia,function = "spi1"; | |
109 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
110 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
111 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
112 | }; | |
113 | ulpi_dir_py1 { | |
114 | nvidia,pins = "ulpi_dir_py1"; | |
115 | nvidia,function = "spi1"; | |
116 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
118 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
119 | }; | |
120 | cam_i2c_scl_pbb1 { | |
121 | nvidia,pins = "cam_i2c_scl_pbb1", | |
122 | "cam_i2c_sda_pbb2"; | |
123 | nvidia,function = "i2c3"; | |
124 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
125 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
126 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
127 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
128 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
129 | }; | |
130 | gen2_i2c_scl_pt5 { | |
131 | nvidia,pins = "gen2_i2c_scl_pt5", | |
132 | "gen2_i2c_sda_pt6"; | |
133 | nvidia,function = "i2c2"; | |
134 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
135 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
136 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
137 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
138 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
139 | }; | |
140 | pj7 { | |
141 | nvidia,pins = "pj7"; | |
142 | nvidia,function = "uartd"; | |
143 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
144 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
145 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
146 | }; | |
147 | spdif_in_pk6 { | |
148 | nvidia,pins = "spdif_in_pk6"; | |
149 | nvidia,function = "spdif"; | |
150 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
151 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
152 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
153 | }; | |
154 | pk7 { | |
155 | nvidia,pins = "pk7"; | |
156 | nvidia,function = "uartd"; | |
157 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
158 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
159 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
160 | }; | |
161 | pg4 { | |
162 | nvidia,pins = "pg4", | |
163 | "pg5", | |
164 | "pg6", | |
165 | "pi3"; | |
166 | nvidia,function = "spi4"; | |
167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
170 | }; | |
171 | pg7 { | |
172 | nvidia,pins = "pg7"; | |
173 | nvidia,function = "spi4"; | |
174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
175 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
176 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
177 | }; | |
178 | ph1 { | |
179 | nvidia,pins = "ph1"; | |
180 | nvidia,function = "pwm1"; | |
181 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
182 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
183 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
184 | }; | |
185 | pk0 { | |
186 | nvidia,pins = "pk0", | |
187 | "kb_row15_ps7", | |
188 | "clk_32k_out_pa0"; | |
189 | nvidia,function = "soc"; | |
190 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
192 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
193 | }; | |
194 | sdmmc1_clk_pz0 { | |
195 | nvidia,pins = "sdmmc1_clk_pz0"; | |
196 | nvidia,function = "sdmmc1"; | |
197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
199 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
200 | }; | |
201 | sdmmc1_cmd_pz1 { | |
202 | nvidia,pins = "sdmmc1_cmd_pz1", | |
203 | "sdmmc1_dat0_py7", | |
204 | "sdmmc1_dat1_py6", | |
205 | "sdmmc1_dat2_py5", | |
206 | "sdmmc1_dat3_py4"; | |
207 | nvidia,function = "sdmmc1"; | |
208 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
209 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
210 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
211 | }; | |
212 | sdmmc3_clk_pa6 { | |
213 | nvidia,pins = "sdmmc3_clk_pa6"; | |
214 | nvidia,function = "sdmmc3"; | |
215 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
216 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
217 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
218 | }; | |
219 | sdmmc3_cmd_pa7 { | |
220 | nvidia,pins = "sdmmc3_cmd_pa7", | |
221 | "sdmmc3_dat0_pb7", | |
222 | "sdmmc3_dat1_pb6", | |
223 | "sdmmc3_dat2_pb5", | |
224 | "sdmmc3_dat3_pb4", | |
225 | "kb_col4_pq4", | |
226 | "sdmmc3_clk_lb_out_pee4", | |
227 | "sdmmc3_clk_lb_in_pee5", | |
228 | "sdmmc3_cd_n_pv2"; | |
229 | nvidia,function = "sdmmc3"; | |
230 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
231 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
232 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
233 | }; | |
234 | sdmmc4_clk_pcc4 { | |
235 | nvidia,pins = "sdmmc4_clk_pcc4"; | |
236 | nvidia,function = "sdmmc4"; | |
237 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
238 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
239 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
240 | }; | |
241 | sdmmc4_cmd_pt7 { | |
242 | nvidia,pins = "sdmmc4_cmd_pt7", | |
243 | "sdmmc4_dat0_paa0", | |
244 | "sdmmc4_dat1_paa1", | |
245 | "sdmmc4_dat2_paa2", | |
246 | "sdmmc4_dat3_paa3", | |
247 | "sdmmc4_dat4_paa4", | |
248 | "sdmmc4_dat5_paa5", | |
249 | "sdmmc4_dat6_paa6", | |
250 | "sdmmc4_dat7_paa7"; | |
251 | nvidia,function = "sdmmc4"; | |
252 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
253 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
254 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
255 | }; | |
256 | mic_det_l { | |
257 | nvidia,pins = "kb_row7_pr7"; | |
258 | nvidia,function = "rsvd2"; | |
259 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
260 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
261 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
262 | }; | |
263 | kb_row10_ps2 { | |
264 | nvidia,pins = "kb_row10_ps2"; | |
265 | nvidia,function = "uarta"; | |
266 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
268 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
269 | }; | |
270 | kb_row9_ps1 { | |
271 | nvidia,pins = "kb_row9_ps1"; | |
272 | nvidia,function = "uarta"; | |
273 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
274 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
275 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
276 | }; | |
277 | pwr_i2c_scl_pz6 { | |
278 | nvidia,pins = "pwr_i2c_scl_pz6", | |
279 | "pwr_i2c_sda_pz7"; | |
280 | nvidia,function = "i2cpwr"; | |
281 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
282 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
283 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
284 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
285 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
286 | }; | |
287 | jtag_rtck { | |
288 | nvidia,pins = "jtag_rtck"; | |
289 | nvidia,function = "rtck"; | |
290 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
293 | }; | |
294 | clk_32k_in { | |
295 | nvidia,pins = "clk_32k_in"; | |
296 | nvidia,function = "clk"; | |
297 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
298 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
299 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
300 | }; | |
301 | core_pwr_req { | |
302 | nvidia,pins = "core_pwr_req"; | |
303 | nvidia,function = "pwron"; | |
304 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
305 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
306 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
307 | }; | |
308 | cpu_pwr_req { | |
309 | nvidia,pins = "cpu_pwr_req"; | |
310 | nvidia,function = "cpu"; | |
311 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
312 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
313 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
314 | }; | |
315 | kb_col0_ap { | |
316 | nvidia,pins = "kb_col0_pq0"; | |
317 | nvidia,function = "rsvd4"; | |
318 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
319 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
320 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
321 | }; | |
322 | en_vdd_sd { | |
323 | nvidia,pins = "kb_row0_pr0"; | |
324 | nvidia,function = "rsvd4"; | |
325 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
326 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
327 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
328 | }; | |
329 | lid_open { | |
330 | nvidia,pins = "kb_row4_pr4"; | |
331 | nvidia,function = "rsvd3"; | |
332 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
333 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
334 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
335 | }; | |
336 | pwr_int_n { | |
337 | nvidia,pins = "pwr_int_n"; | |
338 | nvidia,function = "pmi"; | |
339 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
340 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
341 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
342 | }; | |
343 | reset_out_n { | |
344 | nvidia,pins = "reset_out_n"; | |
345 | nvidia,function = "reset_out_n"; | |
346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
348 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
349 | }; | |
350 | clk3_out_pee0 { | |
351 | nvidia,pins = "clk3_out_pee0"; | |
352 | nvidia,function = "extperiph3"; | |
353 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
354 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
355 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
356 | }; | |
357 | gen1_i2c_scl_pc4 { | |
358 | nvidia,pins = "gen1_i2c_scl_pc4", | |
359 | "gen1_i2c_sda_pc5"; | |
360 | nvidia,function = "i2c1"; | |
361 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
362 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
363 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
364 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
365 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
366 | }; | |
367 | hdmi_cec_pee3 { | |
368 | nvidia,pins = "hdmi_cec_pee3"; | |
369 | nvidia,function = "cec"; | |
370 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
371 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
372 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
373 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
374 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
375 | }; | |
376 | hdmi_int_pn7 { | |
377 | nvidia,pins = "hdmi_int_pn7"; | |
378 | nvidia,function = "rsvd1"; | |
379 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
381 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
382 | }; | |
383 | ddc_scl_pv4 { | |
384 | nvidia,pins = "ddc_scl_pv4", | |
385 | "ddc_sda_pv5"; | |
386 | nvidia,function = "i2c4"; | |
387 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
388 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
389 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
390 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
391 | nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; | |
392 | }; | |
393 | usb_vbus_en0_pn4 { | |
394 | nvidia,pins = "usb_vbus_en0_pn4", | |
395 | "usb_vbus_en1_pn5", | |
396 | "usb_vbus_en2_pff1"; | |
397 | nvidia,function = "usb"; | |
398 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
399 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
400 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
401 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
402 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
403 | }; | |
404 | drive_sdio1 { | |
405 | nvidia,pins = "drive_sdio1"; | |
406 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
407 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
408 | nvidia,pull-down-strength = <36>; | |
409 | nvidia,pull-up-strength = <20>; | |
410 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; | |
411 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; | |
412 | }; | |
413 | drive_sdio3 { | |
414 | nvidia,pins = "drive_sdio3"; | |
415 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
416 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
417 | nvidia,pull-down-strength = <22>; | |
418 | nvidia,pull-up-strength = <36>; | |
419 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
420 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
421 | }; | |
422 | drive_gma { | |
423 | nvidia,pins = "drive_gma"; | |
424 | nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; | |
425 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; | |
426 | nvidia,pull-down-strength = <2>; | |
427 | nvidia,pull-up-strength = <1>; | |
428 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
429 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; | |
430 | nvidia,drive-type = <1>; | |
431 | }; | |
432 | ac_ok { | |
433 | nvidia,pins = "pj0"; | |
434 | nvidia,function = "gmi"; | |
435 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
436 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
438 | }; | |
439 | codec_irq_l { | |
440 | nvidia,pins = "ph4"; | |
441 | nvidia,function = "gmi"; | |
442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
445 | }; | |
446 | lcd_bl_en { | |
447 | nvidia,pins = "ph2"; | |
448 | nvidia,function = "gmi"; | |
449 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
451 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
452 | }; | |
453 | touch_irq_l { | |
454 | nvidia,pins = "gpio_w3_aud_pw3"; | |
455 | nvidia,function = "spi6"; | |
456 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
458 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
459 | }; | |
460 | tpm_davint_l { | |
461 | nvidia,pins = "ph6"; | |
462 | nvidia,function = "gmi"; | |
463 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
465 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
466 | }; | |
467 | ts_irq_l { | |
468 | nvidia,pins = "pk2"; | |
469 | nvidia,function = "gmi"; | |
470 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
471 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
472 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
473 | }; | |
474 | ts_reset_l { | |
475 | nvidia,pins = "pk4"; | |
476 | nvidia,function = "gmi"; | |
477 | nvidia,pull = <1>; | |
478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
479 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
480 | }; | |
481 | ts_shdn_l { | |
482 | nvidia,pins = "pk1"; | |
483 | nvidia,function = "gmi"; | |
484 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
485 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
486 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
487 | }; | |
488 | ph7 { | |
489 | nvidia,pins = "ph7"; | |
490 | nvidia,function = "gmi"; | |
491 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
492 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
493 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
494 | }; | |
495 | sensor_irq_l { | |
496 | nvidia,pins = "pi6"; | |
497 | nvidia,function = "gmi"; | |
498 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
499 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
500 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
501 | }; | |
502 | wifi_en { | |
503 | nvidia,pins = "gpio_x7_aud_px7"; | |
504 | nvidia,function = "rsvd4"; | |
505 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
506 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
507 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
508 | }; | |
509 | chromeos_write_protect { | |
510 | nvidia,pins = "kb_row1_pr1"; | |
511 | nvidia,function = "rsvd4"; | |
512 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
513 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
514 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
515 | }; | |
516 | hp_det_l { | |
517 | nvidia,pins = "pi7"; | |
518 | nvidia,function = "rsvd1"; | |
519 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
520 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
521 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
522 | }; | |
523 | soc_warm_reset_l { | |
524 | nvidia,pins = "pi5"; | |
525 | nvidia,function = "gmi"; | |
526 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
527 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
528 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
529 | }; | |
530 | }; | |
531 | }; | |
532 | ||
be70771d | 533 | serial@70006000 { |
6b53039e TR |
534 | /delete-property/ dmas; |
535 | /delete-property/ dma-names; | |
0f279ebd TR |
536 | status = "okay"; |
537 | }; | |
538 | ||
be70771d | 539 | pwm: pwm@7000a000 { |
0f279ebd TR |
540 | status = "okay"; |
541 | }; | |
542 | ||
543 | /* HDMI DDC */ | |
be70771d | 544 | hdmi_ddc: i2c@7000c700 { |
0f279ebd TR |
545 | status = "okay"; |
546 | clock-frequency = <100000>; | |
547 | }; | |
548 | ||
be70771d | 549 | i2c@7000d000 { |
0f279ebd TR |
550 | status = "okay"; |
551 | clock-frequency = <400000>; | |
552 | ||
553 | as3722: pmic@40 { | |
554 | compatible = "ams,as3722"; | |
555 | reg = <0x40>; | |
556 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
557 | ||
558 | ams,system-power-controller; | |
559 | ||
560 | #interrupt-cells = <2>; | |
561 | interrupt-controller; | |
562 | ||
563 | #gpio-cells = <2>; | |
564 | gpio-controller; | |
565 | ||
566 | pinctrl-names = "default"; | |
567 | pinctrl-0 = <&as3722_default>; | |
568 | ||
2c6fd24d | 569 | as3722_default: pinmux { |
0f279ebd TR |
570 | gpio0 { |
571 | pins = "gpio0"; | |
572 | function = "gpio"; | |
573 | bias-pull-down; | |
574 | }; | |
575 | ||
576 | gpio1 { | |
577 | pins = "gpio1"; | |
578 | function = "gpio"; | |
579 | bias-pull-up; | |
580 | }; | |
581 | ||
582 | gpio2_4_7 { | |
583 | pins = "gpio2", "gpio4", "gpio7"; | |
584 | function = "gpio"; | |
585 | bias-pull-up; | |
586 | }; | |
587 | ||
588 | gpio3 { | |
589 | pins = "gpio3"; | |
590 | function = "gpio"; | |
591 | bias-high-impedance; | |
592 | }; | |
593 | ||
594 | gpio5 { | |
595 | pins = "gpio5"; | |
596 | function = "clk32k-out"; | |
597 | bias-pull-down; | |
598 | }; | |
599 | ||
600 | gpio6 { | |
601 | pins = "gpio6"; | |
602 | function = "clk32k-out"; | |
603 | bias-pull-down; | |
604 | }; | |
605 | }; | |
606 | ||
607 | regulators { | |
608 | vsup-sd2-supply = <&vdd_5v0_sys>; | |
609 | vsup-sd3-supply = <&vdd_5v0_sys>; | |
610 | vsup-sd4-supply = <&vdd_5v0_sys>; | |
611 | vsup-sd5-supply = <&vdd_5v0_sys>; | |
612 | vin-ldo0-supply = <&vdd_1v35_lp0>; | |
613 | vin-ldo1-6-supply = <&vdd_3v3_sys>; | |
614 | vin-ldo2-5-7-supply = <&vddio_1v8>; | |
615 | vin-ldo3-4-supply = <&vdd_3v3_sys>; | |
616 | vin-ldo9-10-supply = <&vdd_5v0_sys>; | |
617 | vin-ldo11-supply = <&vdd_3v3_run>; | |
618 | ||
619 | sd0 { | |
620 | regulator-name = "+VDD_CPU_AP"; | |
621 | regulator-min-microvolt = <700000>; | |
622 | regulator-max-microvolt = <1350000>; | |
623 | regulator-max-microamp = <3500000>; | |
624 | regulator-always-on; | |
625 | regulator-boot-on; | |
626 | ams,ext-control = <2>; | |
627 | }; | |
628 | ||
629 | sd1 { | |
630 | regulator-name = "+VDD_CORE"; | |
631 | regulator-min-microvolt = <700000>; | |
632 | regulator-max-microvolt = <1350000>; | |
633 | regulator-max-microamp = <4000000>; | |
634 | regulator-always-on; | |
635 | regulator-boot-on; | |
636 | ams,ext-control = <1>; | |
637 | }; | |
638 | ||
639 | vdd_1v35_lp0: sd2 { | |
640 | regulator-name = "+1.35V_LP0(sd2)"; | |
641 | regulator-min-microvolt = <1350000>; | |
642 | regulator-max-microvolt = <1350000>; | |
643 | regulator-always-on; | |
644 | regulator-boot-on; | |
645 | }; | |
646 | ||
647 | sd3 { | |
648 | regulator-name = "+1.35V_LP0(sd3)"; | |
649 | regulator-min-microvolt = <1350000>; | |
650 | regulator-max-microvolt = <1350000>; | |
651 | regulator-always-on; | |
652 | regulator-boot-on; | |
653 | }; | |
654 | ||
655 | vdd_1v05_run: sd4 { | |
656 | regulator-name = "+1.05V_RUN"; | |
657 | regulator-min-microvolt = <1050000>; | |
658 | regulator-max-microvolt = <1050000>; | |
659 | }; | |
660 | ||
661 | vddio_1v8: sd5 { | |
662 | regulator-name = "+1.8V_VDDIO"; | |
663 | regulator-min-microvolt = <1800000>; | |
664 | regulator-max-microvolt = <1800000>; | |
665 | regulator-always-on; | |
666 | regulator-boot-on; | |
667 | }; | |
668 | ||
669 | vdd_gpu: sd6 { | |
670 | regulator-name = "+VDD_GPU_AP"; | |
671 | regulator-min-microvolt = <800000>; | |
672 | regulator-max-microvolt = <1200000>; | |
673 | regulator-min-microamp = <3500000>; | |
674 | regulator-max-microamp = <3500000>; | |
675 | regulator-always-on; | |
676 | regulator-boot-on; | |
677 | }; | |
678 | ||
574d9cff | 679 | avdd_1v05_run: ldo0 { |
0f279ebd TR |
680 | regulator-name = "+1.05_RUN_AVDD"; |
681 | regulator-min-microvolt = <1050000>; | |
682 | regulator-max-microvolt = <1050000>; | |
683 | regulator-always-on; | |
684 | regulator-boot-on; | |
685 | ams,ext-control = <1>; | |
686 | }; | |
687 | ||
688 | ldo1 { | |
689 | regulator-name = "+1.8V_RUN_CAM"; | |
690 | regulator-min-microvolt = <1800000>; | |
691 | regulator-max-microvolt = <1800000>; | |
692 | }; | |
693 | ||
694 | ldo2 { | |
695 | regulator-name = "+1.2V_GEN_AVDD"; | |
696 | regulator-min-microvolt = <1200000>; | |
697 | regulator-max-microvolt = <1200000>; | |
698 | regulator-always-on; | |
699 | regulator-boot-on; | |
700 | }; | |
701 | ||
702 | ldo3 { | |
703 | regulator-name = "+1.00V_LP0_VDD_RTC"; | |
704 | regulator-min-microvolt = <1000000>; | |
705 | regulator-max-microvolt = <1000000>; | |
706 | regulator-always-on; | |
707 | regulator-boot-on; | |
708 | ams,enable-tracking; | |
709 | }; | |
710 | ||
711 | vdd_run_cam: ldo4 { | |
712 | regulator-name = "+2.8V_RUN_CAM"; | |
713 | regulator-min-microvolt = <2800000>; | |
714 | regulator-max-microvolt = <2800000>; | |
715 | }; | |
716 | ||
717 | ldo5 { | |
718 | regulator-name = "+1.2V_RUN_CAM_FRONT"; | |
719 | regulator-min-microvolt = <1200000>; | |
720 | regulator-max-microvolt = <1200000>; | |
721 | }; | |
722 | ||
723 | vddio_sdmmc3: ldo6 { | |
724 | regulator-name = "+VDDIO_SDMMC3"; | |
725 | regulator-min-microvolt = <1800000>; | |
726 | regulator-max-microvolt = <3300000>; | |
727 | }; | |
728 | ||
729 | ldo7 { | |
730 | regulator-name = "+1.05V_RUN_CAM_REAR"; | |
731 | regulator-min-microvolt = <1050000>; | |
732 | regulator-max-microvolt = <1050000>; | |
733 | }; | |
734 | ||
735 | ldo9 { | |
736 | regulator-name = "+2.8V_RUN_TOUCH"; | |
737 | regulator-min-microvolt = <2800000>; | |
738 | regulator-max-microvolt = <2800000>; | |
739 | }; | |
740 | ||
741 | ldo10 { | |
742 | regulator-name = "+2.8V_RUN_CAM_AF"; | |
743 | regulator-min-microvolt = <2800000>; | |
744 | regulator-max-microvolt = <2800000>; | |
745 | }; | |
746 | ||
747 | ldo11 { | |
748 | regulator-name = "+1.8V_RUN_VPP_FUSE"; | |
749 | regulator-min-microvolt = <1800000>; | |
750 | regulator-max-microvolt = <1800000>; | |
751 | }; | |
752 | }; | |
753 | }; | |
754 | }; | |
755 | ||
be70771d | 756 | spi@7000d400 { |
0f279ebd TR |
757 | status = "okay"; |
758 | ||
759 | ec: cros-ec@0 { | |
760 | compatible = "google,cros-ec-spi"; | |
761 | spi-max-frequency = <3000000>; | |
762 | interrupt-parent = <&gpio>; | |
763 | interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; | |
764 | reg = <0>; | |
765 | ||
766 | google,cros-ec-spi-msg-delay = <2000>; | |
767 | ||
768 | i2c_20: i2c-tunnel { | |
769 | compatible = "google,cros-ec-i2c-tunnel"; | |
770 | #address-cells = <1>; | |
771 | #size-cells = <0>; | |
772 | ||
773 | google,remote-bus = <0>; | |
774 | ||
2c6fd24d | 775 | charger: bq24735@9 { |
0f279ebd TR |
776 | compatible = "ti,bq24735"; |
777 | reg = <0x9>; | |
778 | interrupt-parent = <&gpio>; | |
779 | interrupts = <TEGRA_GPIO(J, 0) | |
780 | GPIO_ACTIVE_HIGH>; | |
781 | ti,ac-detect-gpios = <&gpio | |
782 | TEGRA_GPIO(J, 0) | |
783 | GPIO_ACTIVE_HIGH>; | |
784 | }; | |
785 | ||
2c6fd24d | 786 | battery: smart-battery@b { |
0f279ebd TR |
787 | compatible = "sbs,sbs-battery"; |
788 | reg = <0xb>; | |
0f279ebd TR |
789 | sbs,i2c-retry-count = <2>; |
790 | sbs,poll-retry-count = <10>; | |
791 | /* power-supplies = <&charger>; */ | |
792 | }; | |
793 | }; | |
794 | ||
795 | keyboard-controller { | |
796 | compatible = "google,cros-ec-keyb"; | |
797 | keypad,num-rows = <8>; | |
798 | keypad,num-columns = <13>; | |
799 | google,needs-ghost-filter; | |
800 | linux,keymap = | |
801 | <MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) | |
802 | MATRIX_KEY(0x00, 0x02, KEY_F1) | |
803 | MATRIX_KEY(0x00, 0x03, KEY_B) | |
804 | MATRIX_KEY(0x00, 0x04, KEY_F10) | |
805 | MATRIX_KEY(0x00, 0x06, KEY_N) | |
806 | MATRIX_KEY(0x00, 0x08, KEY_EQUAL) | |
807 | MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) | |
808 | ||
809 | MATRIX_KEY(0x01, 0x01, KEY_ESC) | |
810 | MATRIX_KEY(0x01, 0x02, KEY_F4) | |
811 | MATRIX_KEY(0x01, 0x03, KEY_G) | |
812 | MATRIX_KEY(0x01, 0x04, KEY_F7) | |
813 | MATRIX_KEY(0x01, 0x06, KEY_H) | |
814 | MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) | |
815 | MATRIX_KEY(0x01, 0x09, KEY_F9) | |
816 | MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) | |
817 | ||
818 | MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) | |
819 | MATRIX_KEY(0x02, 0x01, KEY_TAB) | |
820 | MATRIX_KEY(0x02, 0x02, KEY_F3) | |
821 | MATRIX_KEY(0x02, 0x03, KEY_T) | |
822 | MATRIX_KEY(0x02, 0x04, KEY_F6) | |
823 | MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) | |
824 | MATRIX_KEY(0x02, 0x06, KEY_Y) | |
825 | MATRIX_KEY(0x02, 0x07, KEY_102ND) | |
826 | MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) | |
827 | MATRIX_KEY(0x02, 0x09, KEY_F8) | |
828 | ||
829 | MATRIX_KEY(0x03, 0x01, KEY_GRAVE) | |
830 | MATRIX_KEY(0x03, 0x02, KEY_F2) | |
831 | MATRIX_KEY(0x03, 0x03, KEY_5) | |
832 | MATRIX_KEY(0x03, 0x04, KEY_F5) | |
833 | MATRIX_KEY(0x03, 0x06, KEY_6) | |
834 | MATRIX_KEY(0x03, 0x08, KEY_MINUS) | |
835 | MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) | |
836 | ||
837 | MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) | |
838 | MATRIX_KEY(0x04, 0x01, KEY_A) | |
839 | MATRIX_KEY(0x04, 0x02, KEY_D) | |
840 | MATRIX_KEY(0x04, 0x03, KEY_F) | |
841 | MATRIX_KEY(0x04, 0x04, KEY_S) | |
842 | MATRIX_KEY(0x04, 0x05, KEY_K) | |
843 | MATRIX_KEY(0x04, 0x06, KEY_J) | |
844 | MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) | |
845 | MATRIX_KEY(0x04, 0x09, KEY_L) | |
846 | MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) | |
847 | MATRIX_KEY(0x04, 0x0b, KEY_ENTER) | |
848 | ||
849 | MATRIX_KEY(0x05, 0x01, KEY_Z) | |
850 | MATRIX_KEY(0x05, 0x02, KEY_C) | |
851 | MATRIX_KEY(0x05, 0x03, KEY_V) | |
852 | MATRIX_KEY(0x05, 0x04, KEY_X) | |
853 | MATRIX_KEY(0x05, 0x05, KEY_COMMA) | |
854 | MATRIX_KEY(0x05, 0x06, KEY_M) | |
855 | MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) | |
856 | MATRIX_KEY(0x05, 0x08, KEY_SLASH) | |
857 | MATRIX_KEY(0x05, 0x09, KEY_DOT) | |
858 | MATRIX_KEY(0x05, 0x0b, KEY_SPACE) | |
859 | ||
860 | MATRIX_KEY(0x06, 0x01, KEY_1) | |
861 | MATRIX_KEY(0x06, 0x02, KEY_3) | |
862 | MATRIX_KEY(0x06, 0x03, KEY_4) | |
863 | MATRIX_KEY(0x06, 0x04, KEY_2) | |
864 | MATRIX_KEY(0x06, 0x05, KEY_8) | |
865 | MATRIX_KEY(0x06, 0x06, KEY_7) | |
866 | MATRIX_KEY(0x06, 0x08, KEY_0) | |
867 | MATRIX_KEY(0x06, 0x09, KEY_9) | |
868 | MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) | |
869 | MATRIX_KEY(0x06, 0x0b, KEY_DOWN) | |
870 | MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) | |
871 | ||
872 | MATRIX_KEY(0x07, 0x01, KEY_Q) | |
873 | MATRIX_KEY(0x07, 0x02, KEY_E) | |
874 | MATRIX_KEY(0x07, 0x03, KEY_R) | |
875 | MATRIX_KEY(0x07, 0x04, KEY_W) | |
876 | MATRIX_KEY(0x07, 0x05, KEY_I) | |
877 | MATRIX_KEY(0x07, 0x06, KEY_U) | |
878 | MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) | |
879 | MATRIX_KEY(0x07, 0x08, KEY_P) | |
880 | MATRIX_KEY(0x07, 0x09, KEY_O) | |
881 | MATRIX_KEY(0x07, 0x0b, KEY_UP) | |
882 | MATRIX_KEY(0x07, 0x0c, KEY_LEFT)>; | |
883 | }; | |
884 | }; | |
885 | }; | |
886 | ||
be70771d | 887 | pmc@7000e400 { |
0f279ebd TR |
888 | nvidia,invert-interrupt; |
889 | nvidia,suspend-mode = <0>; | |
0f279ebd TR |
890 | nvidia,cpu-pwr-good-time = <500>; |
891 | nvidia,cpu-pwr-off-time = <300>; | |
892 | nvidia,core-pwr-good-time = <641 3845>; | |
893 | nvidia,core-pwr-off-time = <61036>; | |
894 | nvidia,core-power-req-active-high; | |
895 | nvidia,sys-clock-req-active-high; | |
0f279ebd TR |
896 | }; |
897 | ||
574d9cff TR |
898 | usb@70090000 { |
899 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */ | |
900 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */ | |
901 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */ | |
902 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */ | |
903 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */ | |
904 | phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1"; | |
905 | ||
906 | avddio-pex-supply = <&vdd_1v05_run>; | |
907 | dvddio-pex-supply = <&vdd_1v05_run>; | |
908 | avdd-usb-supply = <&vdd_3v3_lp0>; | |
909 | hvdd-usb-ss-supply = <&vdd_3v3_lp0>; | |
910 | ||
911 | status = "okay"; | |
912 | }; | |
913 | ||
914 | padctl@7009f000 { | |
915 | avdd-pll-utmip-supply = <&vddio_1v8>; | |
916 | avdd-pll-erefe-supply = <&avdd_1v05_run>; | |
917 | avdd-pex-pll-supply = <&vdd_1v05_run>; | |
918 | hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; | |
919 | ||
920 | pads { | |
921 | usb2 { | |
922 | status = "okay"; | |
923 | ||
924 | lanes { | |
925 | usb2-0 { | |
926 | nvidia,function = "xusb"; | |
927 | status = "okay"; | |
928 | }; | |
929 | ||
930 | usb2-1 { | |
931 | nvidia,function = "xusb"; | |
932 | status = "okay"; | |
933 | }; | |
934 | ||
935 | usb2-2 { | |
936 | nvidia,function = "xusb"; | |
937 | status = "okay"; | |
938 | }; | |
939 | }; | |
940 | }; | |
941 | ||
942 | pcie { | |
943 | status = "okay"; | |
944 | ||
945 | lanes { | |
946 | pcie-0 { | |
947 | nvidia,function = "usb3-ss"; | |
948 | status = "okay"; | |
949 | }; | |
950 | ||
951 | pcie-1 { | |
952 | nvidia,function = "usb3-ss"; | |
953 | status = "okay"; | |
954 | }; | |
955 | }; | |
956 | }; | |
957 | }; | |
958 | ||
959 | ports { | |
960 | usb2-0 { | |
961 | status = "okay"; | |
962 | mode = "otg"; | |
963 | ||
964 | vbus-supply = <&vdd_usb1_vbus>; | |
965 | }; | |
966 | ||
967 | usb2-1 { | |
968 | status = "okay"; | |
969 | mode = "host"; | |
970 | ||
971 | vbus-supply = <&vdd_run_cam>; | |
972 | }; | |
973 | ||
974 | usb2-2 { | |
975 | status = "okay"; | |
976 | mode = "host"; | |
977 | ||
978 | vbus-supply = <&vdd_usb3_vbus>; | |
979 | }; | |
980 | ||
981 | usb3-0 { | |
982 | nvidia,usb2-companion = <0>; | |
983 | status = "okay"; | |
984 | }; | |
985 | ||
986 | usb3-1 { | |
987 | nvidia,usb2-companion = <2>; | |
988 | status = "okay"; | |
989 | }; | |
990 | }; | |
991 | }; | |
992 | ||
0f279ebd | 993 | /* WIFI/BT module */ |
67bb17f6 | 994 | mmc@700b0000 { |
0f279ebd TR |
995 | status = "disabled"; |
996 | }; | |
997 | ||
998 | /* external SD/MMC */ | |
67bb17f6 | 999 | mmc@700b0400 { |
0f279ebd TR |
1000 | cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
1001 | power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; | |
1002 | wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; | |
1003 | status = "okay"; | |
1004 | bus-width = <4>; | |
1005 | vqmmc-supply = <&vddio_sdmmc3>; | |
1006 | }; | |
1007 | ||
1008 | /* EMMC 4.51 */ | |
67bb17f6 | 1009 | mmc@700b0600 { |
0f279ebd TR |
1010 | status = "okay"; |
1011 | bus-width = <8>; | |
1012 | non-removable; | |
1013 | }; | |
1014 | ||
0f279ebd TR |
1015 | backlight: backlight { |
1016 | compatible = "pwm-backlight"; | |
1017 | ||
1018 | enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; | |
1019 | power-supply = <&vdd_led>; | |
1020 | pwms = <&pwm 1 1000000>; | |
1021 | ||
1022 | brightness-levels = <0 4 8 16 32 64 128 255>; | |
1023 | default-brightness-level = <6>; | |
0f279ebd TR |
1024 | }; |
1025 | ||
4cc3e3e1 | 1026 | clk32k_in: clock-32k { |
393a403e TR |
1027 | compatible = "fixed-clock"; |
1028 | clock-frequency = <32768>; | |
1029 | #clock-cells = <0>; | |
0f279ebd TR |
1030 | }; |
1031 | ||
1032 | gpio-keys { | |
1033 | compatible = "gpio-keys"; | |
1034 | ||
79ed18d9 TR |
1035 | key-power { |
1036 | label = "Power"; | |
1037 | gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; | |
1038 | linux,code = <KEY_POWER>; | |
1039 | debounce-interval = <10>; | |
1040 | wakeup-source; | |
1041 | }; | |
1042 | ||
012877d0 | 1043 | switch-lid { |
0f279ebd TR |
1044 | label = "Lid"; |
1045 | gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; | |
1046 | linux,input-type = <5>; | |
1047 | linux,code = <0>; | |
1048 | debounce-interval = <1>; | |
81d22e89 | 1049 | wakeup-source; |
0f279ebd | 1050 | }; |
0f279ebd TR |
1051 | }; |
1052 | ||
1053 | panel: panel { | |
d3cd7d02 | 1054 | compatible = "innolux,n116bge"; |
7eb04544 | 1055 | power-supply = <&vdd_3v3_panel>; |
0f279ebd TR |
1056 | backlight = <&backlight>; |
1057 | ddc-i2c-bus = <&dpaux>; | |
1058 | }; | |
1059 | ||
097e01c6 | 1060 | vdd_mux: regulator-vdd-mux { |
7517248a TR |
1061 | compatible = "regulator-fixed"; |
1062 | regulator-name = "+VDD_MUX"; | |
1063 | regulator-min-microvolt = <19000000>; | |
1064 | regulator-max-microvolt = <19000000>; | |
1065 | regulator-always-on; | |
1066 | regulator-boot-on; | |
1067 | }; | |
0f279ebd | 1068 | |
097e01c6 | 1069 | vdd_5v0_sys: regulator-vdd-5v0-sys { |
7517248a TR |
1070 | compatible = "regulator-fixed"; |
1071 | regulator-name = "+5V_SYS"; | |
1072 | regulator-min-microvolt = <5000000>; | |
1073 | regulator-max-microvolt = <5000000>; | |
1074 | regulator-always-on; | |
1075 | regulator-boot-on; | |
1076 | vin-supply = <&vdd_mux>; | |
1077 | }; | |
0f279ebd | 1078 | |
097e01c6 | 1079 | vdd_3v3_sys: regulator-vdd-3v3-sys { |
7517248a TR |
1080 | compatible = "regulator-fixed"; |
1081 | regulator-name = "+3.3V_SYS"; | |
1082 | regulator-min-microvolt = <3300000>; | |
1083 | regulator-max-microvolt = <3300000>; | |
1084 | regulator-always-on; | |
1085 | regulator-boot-on; | |
1086 | vin-supply = <&vdd_mux>; | |
1087 | }; | |
0f279ebd | 1088 | |
097e01c6 | 1089 | vdd_3v3_run: regulator-vdd-3v3-run { |
7517248a TR |
1090 | compatible = "regulator-fixed"; |
1091 | regulator-name = "+3.3V_RUN"; | |
1092 | regulator-min-microvolt = <3300000>; | |
1093 | regulator-max-microvolt = <3300000>; | |
1094 | regulator-always-on; | |
1095 | regulator-boot-on; | |
1096 | gpio = <&as3722 1 GPIO_ACTIVE_HIGH>; | |
1097 | enable-active-high; | |
1098 | vin-supply = <&vdd_3v3_sys>; | |
1099 | }; | |
0f279ebd | 1100 | |
097e01c6 | 1101 | vdd_3v3_hdmi: regulator-vdd-3v3-hdmi { |
7517248a TR |
1102 | compatible = "regulator-fixed"; |
1103 | regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; | |
1104 | regulator-min-microvolt = <3300000>; | |
1105 | regulator-max-microvolt = <3300000>; | |
1106 | vin-supply = <&vdd_3v3_run>; | |
1107 | }; | |
0f279ebd | 1108 | |
097e01c6 | 1109 | vdd_led: regulator-vdd-led { |
7517248a TR |
1110 | compatible = "regulator-fixed"; |
1111 | regulator-name = "+VDD_LED"; | |
1112 | regulator-min-microvolt = <3300000>; | |
1113 | regulator-max-microvolt = <3300000>; | |
1114 | gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; | |
1115 | enable-active-high; | |
1116 | vin-supply = <&vdd_mux>; | |
1117 | }; | |
0f279ebd | 1118 | |
097e01c6 | 1119 | vdd_usb1_vbus: regulator-vdd-usb1-vbus { |
7517248a TR |
1120 | compatible = "regulator-fixed"; |
1121 | regulator-name = "+5V_USB_HS"; | |
1122 | regulator-min-microvolt = <5000000>; | |
1123 | regulator-max-microvolt = <5000000>; | |
1124 | gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; | |
1125 | enable-active-high; | |
1126 | gpio-open-drain; | |
1127 | vin-supply = <&vdd_5v0_sys>; | |
1128 | }; | |
0f279ebd | 1129 | |
097e01c6 | 1130 | vdd_usb3_vbus: regulator-vdd-usb3-vbus { |
7517248a TR |
1131 | compatible = "regulator-fixed"; |
1132 | regulator-name = "+5V_USB_SS"; | |
1133 | regulator-min-microvolt = <5000000>; | |
1134 | regulator-max-microvolt = <5000000>; | |
1135 | gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; | |
1136 | enable-active-high; | |
1137 | gpio-open-drain; | |
1138 | vin-supply = <&vdd_5v0_sys>; | |
1139 | }; | |
0f279ebd | 1140 | |
097e01c6 | 1141 | vdd_3v3_panel: regulator-vdd-3v3-panel { |
7517248a TR |
1142 | compatible = "regulator-fixed"; |
1143 | regulator-name = "+3.3V_PANEL"; | |
1144 | regulator-min-microvolt = <3300000>; | |
1145 | regulator-max-microvolt = <3300000>; | |
1146 | gpio = <&as3722 4 GPIO_ACTIVE_HIGH>; | |
1147 | enable-active-high; | |
1148 | vin-supply = <&vdd_3v3_sys>; | |
1149 | }; | |
0f279ebd | 1150 | |
097e01c6 | 1151 | vdd_hdmi_pll: regulator-vdd-hdmi-pll { |
7517248a TR |
1152 | compatible = "regulator-fixed"; |
1153 | regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL_AP_GATE"; | |
1154 | regulator-min-microvolt = <1050000>; | |
1155 | regulator-max-microvolt = <1050000>; | |
1156 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; | |
1157 | vin-supply = <&vdd_1v05_run>; | |
1158 | }; | |
0f279ebd | 1159 | |
097e01c6 | 1160 | vdd_5v0_hdmi: regulator-vdd-5v0-hdmi { |
7517248a TR |
1161 | compatible = "regulator-fixed"; |
1162 | regulator-name = "+5V_HDMI_CON"; | |
1163 | regulator-min-microvolt = <5000000>; | |
1164 | regulator-max-microvolt = <5000000>; | |
1165 | gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; | |
1166 | enable-active-high; | |
1167 | vin-supply = <&vdd_5v0_sys>; | |
1168 | }; | |
0f279ebd | 1169 | |
097e01c6 | 1170 | vdd_5v0_ts: regulator-vdd-5v0-ts { |
7517248a TR |
1171 | compatible = "regulator-fixed"; |
1172 | regulator-name = "+5V_VDD_TS"; | |
1173 | regulator-min-microvolt = <5000000>; | |
1174 | regulator-max-microvolt = <5000000>; | |
1175 | regulator-always-on; | |
1176 | regulator-boot-on; | |
1177 | gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; | |
1178 | enable-active-high; | |
1179 | }; | |
574d9cff | 1180 | |
097e01c6 | 1181 | vdd_3v3_lp0: regulator-vdd-3v3-lp0 { |
7517248a TR |
1182 | compatible = "regulator-fixed"; |
1183 | regulator-name = "+3.3V_LP0"; | |
1184 | regulator-min-microvolt = <3300000>; | |
1185 | regulator-max-microvolt = <3300000>; | |
1186 | /* | |
1187 | * TODO: find a way to wire this up with the USB EHCI | |
1188 | * controllers so that it can be enabled on demand. | |
1189 | */ | |
1190 | regulator-always-on; | |
1191 | gpio = <&as3722 2 GPIO_ACTIVE_HIGH>; | |
1192 | enable-active-high; | |
1193 | vin-supply = <&vdd_3v3_sys>; | |
0f279ebd TR |
1194 | }; |
1195 | }; |