]> git.ipfire.org Git - thirdparty/linux.git/blame - arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
arm64: tegra: Remove dmas and dma-names for debug UART
[thirdparty/linux.git] / arch / arm64 / boot / dts / nvidia / tegra210-p2180.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
77934269
TR
2#include <dt-bindings/mfd/max77620.h>
3
9e71045f
TR
4#include "tegra210.dtsi"
5
6/ {
7 model = "NVIDIA Jetson TX1";
8 compatible = "nvidia,p2180", "nvidia,tegra210";
9
10 aliases {
77934269 11 rtc0 = "/i2c@7000d000/pmic@3c";
be70771d 12 rtc1 = "/rtc@7000e000";
9e71045f
TR
13 serial0 = &uarta;
14 };
15
5593eb76
TR
16 chosen {
17 stdout-path = "serial0:115200n8";
18 };
19
772a6a7b 20 memory@80000000 {
9e71045f
TR
21 device_type = "memory";
22 reg = <0x0 0x80000000 0x1 0x0>;
23 };
24
5e6b9a89
AC
25 gpu@57000000 {
26 vdd-supply = <&vdd_gpu>;
27 };
28
9e71045f 29 /* debug port */
be70771d 30 serial@70006000 {
6b53039e
TR
31 /delete-property/ dmas;
32 /delete-property/ dma-names;
9e71045f
TR
33 status = "okay";
34 };
35
79ed18d9
TR
36 i2c@7000c500 {
37 status = "okay";
38
39 /* module ID EEPROM */
40 eeprom@50 {
41 compatible = "atmel,24c02";
42 reg = <0x50>;
43
44 label = "module";
45 vcc-supply = <&vdd_1v8>;
46 address-width = <8>;
47 pagesize = <8>;
48 size = <256>;
49 read-only;
50 };
51 };
52
77934269
TR
53 i2c@7000d000 {
54 status = "okay";
55 clock-frequency = <400000>;
56
57 pmic: pmic@3c {
58 compatible = "maxim,max77620";
59 reg = <0x3c>;
358a6777
JH
60 interrupt-parent = <&tegra_pmc>;
61 interrupts = <51 IRQ_TYPE_LEVEL_LOW>;
77934269
TR
62
63 #interrupt-cells = <2>;
64 interrupt-controller;
65
66 #gpio-cells = <2>;
67 gpio-controller;
68
69 pinctrl-names = "default";
70 pinctrl-0 = <&max77620_default>;
71
79ed18d9
TR
72 fps {
73 fps0 {
74 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
75 maxim,suspend-fps-time-period-us = <1280>;
76 };
77
78 fps1 {
79 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
80 maxim,suspend-fps-time-period-us = <1280>;
81 };
82
83 fps2 {
84 maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
85 };
86 };
87
77934269
TR
88 max77620_default: pinmux {
89 gpio0 {
90 pins = "gpio0";
91 function = "gpio";
92 };
93
94 gpio1 {
95 pins = "gpio1";
96 function = "fps-out";
2f477ee3 97 drive-push-pull = <1>;
77934269
TR
98 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
99 maxim,active-fps-power-up-slot = <7>;
100 maxim,active-fps-power-down-slot = <0>;
101 };
102
103 gpio2_3 {
104 pins = "gpio2", "gpio3";
105 function = "fps-out";
2f477ee3 106 drive-open-drain = <1>;
77934269
TR
107 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
108 };
109
110 gpio4 {
111 pins = "gpio4";
112 function = "32k-out1";
113 };
114
115 gpio5_6_7 {
116 pins = "gpio5", "gpio6", "gpio7";
117 function = "gpio";
2f477ee3 118 drive-push-pull = <1>;
77934269
TR
119 };
120 };
121
77934269
TR
122 regulators {
123 in-ldo0-1-supply = <&vdd_pre>;
124 in-ldo7-8-supply = <&vdd_pre>;
125 in-sd3-supply = <&vdd_5v0_sys>;
126
127 vdd_soc: sd0 {
128 regulator-name = "VDD_SOC";
129 regulator-min-microvolt = <600000>;
130 regulator-max-microvolt = <1400000>;
131 regulator-always-on;
132 regulator-boot-on;
133
134 regulator-enable-ramp-delay = <146>;
135 regulator-ramp-delay = <27500>;
136
137 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
138 };
139
140 vdd_ddr: sd1 {
141 regulator-name = "VDD_DDR_1V1_PMIC";
142 regulator-always-on;
143 regulator-boot-on;
144
145 regulator-enable-ramp-delay = <130>;
146 regulator-ramp-delay = <27500>;
147
148 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
149 };
150
151 vdd_pre: sd2 {
152 regulator-name = "VDD_PRE_REG_1V35";
153 regulator-min-microvolt = <1350000>;
154 regulator-max-microvolt = <1350000>;
155
156 regulator-enable-ramp-delay = <176>;
157 regulator-ramp-delay = <27500>;
158
159 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
160 };
161
162 vdd_1v8: sd3 {
163 regulator-name = "VDD_1V8";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-always-on;
167 regulator-boot-on;
168
169 regulator-enable-ramp-delay = <242>;
170 regulator-ramp-delay = <27500>;
171
172 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
173 };
174
175 vdd_sys_1v2: ldo0 {
176 regulator-name = "AVDD_SYS_1V2";
177 regulator-min-microvolt = <1200000>;
178 regulator-max-microvolt = <1200000>;
179 regulator-always-on;
180 regulator-boot-on;
181
182 regulator-enable-ramp-delay = <26>;
183 regulator-ramp-delay = <100000>;
184
185 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
186 };
187
188 vdd_pex_1v05: ldo1 {
189 regulator-name = "VDD_PEX_1V05";
190 regulator-min-microvolt = <1050000>;
191 regulator-max-microvolt = <1050000>;
192
193 regulator-enable-ramp-delay = <22>;
194 regulator-ramp-delay = <100000>;
195
196 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
197 };
198
199 vddio_sdmmc: ldo2 {
200 regulator-name = "VDDIO_SDMMC";
41cc3771 201 regulator-min-microvolt = <1800000>;
77934269
TR
202 regulator-max-microvolt = <3300000>;
203 regulator-always-on;
204 regulator-boot-on;
205
206 regulator-enable-ramp-delay = <62>;
207 regulator-ramp-delay = <100000>;
208
209 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
210 };
211
212 vdd_cam_hv: ldo3 {
213 regulator-name = "VDD_CAM_HV";
214 regulator-min-microvolt = <2800000>;
215 regulator-max-microvolt = <2800000>;
216
217 regulator-enable-ramp-delay = <50>;
218 regulator-ramp-delay = <100000>;
219
220 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
221 };
222
223 vdd_rtc: ldo4 {
224 regulator-name = "VDD_RTC";
225 regulator-min-microvolt = <850000>;
226 regulator-max-microvolt = <850000>;
227 regulator-always-on;
228 regulator-boot-on;
229
230 regulator-enable-ramp-delay = <22>;
231 regulator-ramp-delay = <100000>;
232
233 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
234 };
235
236 vdd_ts_hv: ldo5 {
237 regulator-name = "VDD_TS_HV";
238 regulator-min-microvolt = <3300000>;
239 regulator-max-microvolt = <3300000>;
240
241 regulator-enable-ramp-delay = <62>;
242 regulator-ramp-delay = <100000>;
243
244 maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>;
245 };
246
247 vdd_ts: ldo6 {
248 regulator-name = "VDD_TS_1V8";
249 regulator-min-microvolt = <1800000>;
250 regulator-max-microvolt = <1800000>;
251
252 regulator-enable-ramp-delay = <36>;
253 regulator-ramp-delay = <100000>;
254
255 maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
256 maxim,active-fps-power-up-slot = <7>;
257 maxim,active-fps-power-down-slot = <0>;
258 };
259
260 avdd_1v05_pll: ldo7 {
261 regulator-name = "AVDD_1V05_PLL";
262 regulator-min-microvolt = <1050000>;
263 regulator-max-microvolt = <1050000>;
264 regulator-always-on;
265 regulator-boot-on;
266
267 regulator-enable-ramp-delay = <24>;
268 regulator-ramp-delay = <100000>;
269
270 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
271 };
272
273 avdd_1v05: ldo8 {
274 regulator-name = "AVDD_SATA_HDMI_DP_1V05";
275 regulator-min-microvolt = <1050000>;
276 regulator-max-microvolt = <1050000>;
277
278 regulator-enable-ramp-delay = <22>;
279 regulator-ramp-delay = <100000>;
280
281 maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
282 };
283 };
284 };
285 };
286
be70771d 287 pmc@7000e400 {
9e71045f 288 nvidia,invert-interrupt;
106f7a06
SK
289 nvidia,suspend-mode = <0>;
290 nvidia,cpu-pwr-good-time = <0>;
291 nvidia,cpu-pwr-off-time = <0>;
292 nvidia,core-pwr-good-time = <4587 3876>;
293 nvidia,core-pwr-off-time = <39065>;
294 nvidia,core-power-req-active-high;
295 nvidia,sys-clock-req-active-high;
9e71045f
TR
296 };
297
298 /* eMMC */
67bb17f6 299 mmc@700b0600 {
9e71045f
TR
300 status = "okay";
301 bus-width = <8>;
302 non-removable;
6ff7705d 303 vqmmc-supply = <&vdd_1v8>;
9e71045f
TR
304 };
305
4cc3e3e1 306 clk32k_in: clock-32k {
393a403e
TR
307 compatible = "fixed-clock";
308 clock-frequency = <32768>;
309 #clock-cells = <0>;
9e71045f 310 };
5e6b9a89 311
2fdb74fe
JH
312 cpus {
313 cpu@0 {
314 enable-method = "psci";
315 };
316
317 cpu@1 {
318 enable-method = "psci";
319 };
320
321 cpu@2 {
322 enable-method = "psci";
323 };
324
325 cpu@3 {
326 enable-method = "psci";
327 };
d2c19dd7
JL
328
329 idle-states {
330 cpu-sleep {
331 status = "okay";
332 };
333 };
2fdb74fe
JH
334 };
335
336 psci {
337 compatible = "arm,psci-0.2";
338 method = "smc";
339 };
340
097e01c6 341 vdd_gpu: regulator-vdd-gpu {
7517248a 342 compatible = "pwm-regulator";
562da8b4 343 pwms = <&pwm 1 8000>;
7517248a
TR
344 regulator-name = "VDD_GPU";
345 regulator-min-microvolt = <710000>;
346 regulator-max-microvolt = <1320000>;
347 enable-gpios = <&pmic 6 GPIO_ACTIVE_HIGH>;
348 regulator-ramp-delay = <80>;
349 regulator-enable-ramp-delay = <2000>;
350 regulator-settling-time-us = <160>;
5e6b9a89 351 };
9e71045f 352};