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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
08e875c1 CM |
2 | /* |
3 | * SMP initialisation and IPI support | |
4 | * Based on arch/arm/kernel/smp.c | |
5 | * | |
6 | * Copyright (C) 2012 ARM Ltd. | |
08e875c1 CM |
7 | */ |
8 | ||
0f078336 | 9 | #include <linux/acpi.h> |
f5df2696 | 10 | #include <linux/arm_sdei.h> |
08e875c1 CM |
11 | #include <linux/delay.h> |
12 | #include <linux/init.h> | |
13 | #include <linux/spinlock.h> | |
68e21be2 | 14 | #include <linux/sched/mm.h> |
ef8bd77f | 15 | #include <linux/sched/hotplug.h> |
68db0cf1 | 16 | #include <linux/sched/task_stack.h> |
08e875c1 CM |
17 | #include <linux/interrupt.h> |
18 | #include <linux/cache.h> | |
19 | #include <linux/profile.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/cpu.h> | |
24 | #include <linux/smp.h> | |
25 | #include <linux/seq_file.h> | |
26 | #include <linux/irq.h> | |
e7932188 | 27 | #include <linux/irqchip/arm-gic-v3.h> |
08e875c1 CM |
28 | #include <linux/percpu.h> |
29 | #include <linux/clockchips.h> | |
30 | #include <linux/completion.h> | |
31 | #include <linux/of.h> | |
eb631bb5 | 32 | #include <linux/irq_work.h> |
78fd584c | 33 | #include <linux/kexec.h> |
08e875c1 | 34 | |
e039ee4e | 35 | #include <asm/alternative.h> |
08e875c1 CM |
36 | #include <asm/atomic.h> |
37 | #include <asm/cacheflush.h> | |
df857416 | 38 | #include <asm/cpu.h> |
08e875c1 | 39 | #include <asm/cputype.h> |
cd1aebf5 | 40 | #include <asm/cpu_ops.h> |
0fbeb318 | 41 | #include <asm/daifflags.h> |
08e875c1 | 42 | #include <asm/mmu_context.h> |
1a2db300 | 43 | #include <asm/numa.h> |
08e875c1 CM |
44 | #include <asm/pgtable.h> |
45 | #include <asm/pgalloc.h> | |
46 | #include <asm/processor.h> | |
4c7aa002 | 47 | #include <asm/smp_plat.h> |
08e875c1 CM |
48 | #include <asm/sections.h> |
49 | #include <asm/tlbflush.h> | |
50 | #include <asm/ptrace.h> | |
377bcff9 | 51 | #include <asm/virt.h> |
08e875c1 | 52 | |
45ed695a NP |
53 | #define CREATE_TRACE_POINTS |
54 | #include <trace/events/ipi.h> | |
55 | ||
57c82954 MR |
56 | DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number); |
57 | EXPORT_PER_CPU_SYMBOL(cpu_number); | |
58 | ||
08e875c1 CM |
59 | /* |
60 | * as from 2.5, kernels no longer have an init_tasks structure | |
61 | * so we need some other way of telling a new secondary core | |
62 | * where to place its SVC stack | |
63 | */ | |
64 | struct secondary_data secondary_data; | |
bb905274 SP |
65 | /* Number of CPUs which aren't online, but looping in kernel text. */ |
66 | int cpus_stuck_in_kernel; | |
08e875c1 CM |
67 | |
68 | enum ipi_msg_type { | |
69 | IPI_RESCHEDULE, | |
70 | IPI_CALL_FUNC, | |
08e875c1 | 71 | IPI_CPU_STOP, |
78fd584c | 72 | IPI_CPU_CRASH_STOP, |
1f85008e | 73 | IPI_TIMER, |
eb631bb5 | 74 | IPI_IRQ_WORK, |
5e89c55e | 75 | IPI_WAKEUP |
08e875c1 CM |
76 | }; |
77 | ||
bb905274 SP |
78 | #ifdef CONFIG_HOTPLUG_CPU |
79 | static int op_cpu_kill(unsigned int cpu); | |
80 | #else | |
81 | static inline int op_cpu_kill(unsigned int cpu) | |
82 | { | |
83 | return -ENOSYS; | |
84 | } | |
85 | #endif | |
86 | ||
87 | ||
08e875c1 CM |
88 | /* |
89 | * Boot a secondary CPU, and assign it the specified idle task. | |
90 | * This also gives us the initial stack to use for this CPU. | |
91 | */ | |
b8c6453a | 92 | static int boot_secondary(unsigned int cpu, struct task_struct *idle) |
08e875c1 | 93 | { |
652af899 MR |
94 | if (cpu_ops[cpu]->cpu_boot) |
95 | return cpu_ops[cpu]->cpu_boot(cpu); | |
08e875c1 | 96 | |
652af899 | 97 | return -EOPNOTSUPP; |
08e875c1 CM |
98 | } |
99 | ||
100 | static DECLARE_COMPLETION(cpu_running); | |
101 | ||
b8c6453a | 102 | int __cpu_up(unsigned int cpu, struct task_struct *idle) |
08e875c1 CM |
103 | { |
104 | int ret; | |
bb905274 | 105 | long status; |
08e875c1 CM |
106 | |
107 | /* | |
108 | * We need to tell the secondary core where to find its stack and the | |
109 | * page tables. | |
110 | */ | |
c02433dd | 111 | secondary_data.task = idle; |
34be98f4 | 112 | secondary_data.stack = task_stack_page(idle) + THREAD_SIZE; |
bb905274 | 113 | update_cpu_boot_status(CPU_MMU_OFF); |
08e875c1 CM |
114 | __flush_dcache_area(&secondary_data, sizeof(secondary_data)); |
115 | ||
116 | /* | |
117 | * Now bring the CPU into our world. | |
118 | */ | |
119 | ret = boot_secondary(cpu, idle); | |
120 | if (ret == 0) { | |
121 | /* | |
122 | * CPU was successfully started, wait for it to come online or | |
123 | * time out. | |
124 | */ | |
125 | wait_for_completion_timeout(&cpu_running, | |
126 | msecs_to_jiffies(1000)); | |
127 | ||
128 | if (!cpu_online(cpu)) { | |
129 | pr_crit("CPU%u: failed to come online\n", cpu); | |
130 | ret = -EIO; | |
131 | } | |
132 | } else { | |
133 | pr_err("CPU%u: failed to boot: %d\n", cpu, ret); | |
f357b3a7 | 134 | return ret; |
08e875c1 CM |
135 | } |
136 | ||
c02433dd | 137 | secondary_data.task = NULL; |
08e875c1 | 138 | secondary_data.stack = NULL; |
bb905274 SP |
139 | status = READ_ONCE(secondary_data.status); |
140 | if (ret && status) { | |
141 | ||
142 | if (status == CPU_MMU_OFF) | |
143 | status = READ_ONCE(__early_cpu_boot_status); | |
144 | ||
66f16a24 | 145 | switch (status & CPU_BOOT_STATUS_MASK) { |
bb905274 SP |
146 | default: |
147 | pr_err("CPU%u: failed in unknown state : 0x%lx\n", | |
148 | cpu, status); | |
149 | break; | |
150 | case CPU_KILL_ME: | |
151 | if (!op_cpu_kill(cpu)) { | |
152 | pr_crit("CPU%u: died during early boot\n", cpu); | |
153 | break; | |
154 | } | |
bb905274 | 155 | pr_crit("CPU%u: may not have shut down cleanly\n", cpu); |
66554739 | 156 | /* Fall through */ |
bb905274 SP |
157 | case CPU_STUCK_IN_KERNEL: |
158 | pr_crit("CPU%u: is stuck in kernel\n", cpu); | |
66f16a24 WD |
159 | if (status & CPU_STUCK_REASON_52_BIT_VA) |
160 | pr_crit("CPU%u: does not support 52-bit VAs\n", cpu); | |
161 | if (status & CPU_STUCK_REASON_NO_GRAN) | |
162 | pr_crit("CPU%u: does not support %luK granule \n", cpu, PAGE_SIZE / SZ_1K); | |
bb905274 SP |
163 | cpus_stuck_in_kernel++; |
164 | break; | |
165 | case CPU_PANIC_KERNEL: | |
166 | panic("CPU%u detected unsupported configuration\n", cpu); | |
167 | } | |
168 | } | |
08e875c1 CM |
169 | |
170 | return ret; | |
171 | } | |
172 | ||
e7932188 JT |
173 | static void init_gic_priority_masking(void) |
174 | { | |
175 | u32 cpuflags; | |
176 | ||
177 | if (WARN_ON(!gic_enable_sre())) | |
178 | return; | |
179 | ||
180 | cpuflags = read_sysreg(daif); | |
181 | ||
182 | WARN_ON(!(cpuflags & PSR_I_BIT)); | |
183 | ||
e1d22385 | 184 | gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); |
e7932188 JT |
185 | } |
186 | ||
08e875c1 CM |
187 | /* |
188 | * This is the secondary CPU boot entry. We're using this CPUs | |
189 | * idle thread stack, but a set of temporary page tables. | |
190 | */ | |
b154886f | 191 | asmlinkage notrace void secondary_start_kernel(void) |
08e875c1 | 192 | { |
ccaac162 | 193 | u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; |
08e875c1 | 194 | struct mm_struct *mm = &init_mm; |
580efaa7 MR |
195 | unsigned int cpu; |
196 | ||
197 | cpu = task_cpu(current); | |
198 | set_my_cpu_offset(per_cpu_offset(cpu)); | |
08e875c1 | 199 | |
08e875c1 CM |
200 | /* |
201 | * All kernel threads share the same mm context; grab a | |
202 | * reference and switch to it. | |
203 | */ | |
f1f10076 | 204 | mmgrab(mm); |
08e875c1 | 205 | current->active_mm = mm; |
08e875c1 CM |
206 | |
207 | /* | |
208 | * TTBR0 is only used for the identity mapping at this stage. Make it | |
209 | * point to zero page to avoid speculatively fetching new entries. | |
210 | */ | |
9e8e865b | 211 | cpu_uninstall_idmap(); |
08e875c1 | 212 | |
e7932188 JT |
213 | if (system_uses_irq_prio_masking()) |
214 | init_gic_priority_masking(); | |
215 | ||
08e875c1 CM |
216 | preempt_disable(); |
217 | trace_hardirqs_off(); | |
218 | ||
dbb4e152 SP |
219 | /* |
220 | * If the system has established the capabilities, make sure | |
221 | * this CPU ticks all of those. If it doesn't, the CPU will | |
222 | * fail to come online. | |
223 | */ | |
c47a1900 | 224 | check_local_cpu_capabilities(); |
dbb4e152 | 225 | |
652af899 MR |
226 | if (cpu_ops[cpu]->cpu_postboot) |
227 | cpu_ops[cpu]->cpu_postboot(); | |
08e875c1 | 228 | |
df857416 MR |
229 | /* |
230 | * Log the CPU info before it is marked online and might get read. | |
231 | */ | |
232 | cpuinfo_store_cpu(); | |
233 | ||
7ade67b5 MZ |
234 | /* |
235 | * Enable GIC and timers. | |
236 | */ | |
237 | notify_cpu_starting(cpu); | |
238 | ||
c18df0ad | 239 | store_cpu_topology(cpu); |
97fd6016 | 240 | numa_add_cpu(cpu); |
f6e763b9 | 241 | |
08e875c1 CM |
242 | /* |
243 | * OK, now it's safe to let the boot CPU continue. Wait for | |
244 | * the CPU migration code to notice that the CPU is online | |
245 | * before we continue. | |
246 | */ | |
ccaac162 MR |
247 | pr_info("CPU%u: Booted secondary processor 0x%010lx [0x%08x]\n", |
248 | cpu, (unsigned long)mpidr, | |
249 | read_cpuid_id()); | |
bb905274 | 250 | update_cpu_boot_status(CPU_BOOT_SUCCESS); |
08e875c1 | 251 | set_cpu_online(cpu, true); |
b3770b32 | 252 | complete(&cpu_running); |
08e875c1 | 253 | |
41bd5b5d | 254 | local_daif_restore(DAIF_PROCCTX); |
53ae3acd | 255 | |
08e875c1 CM |
256 | /* |
257 | * OK, it's off to the idle thread for us | |
258 | */ | |
fc6d73d6 | 259 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
08e875c1 CM |
260 | } |
261 | ||
9327e2c6 MR |
262 | #ifdef CONFIG_HOTPLUG_CPU |
263 | static int op_cpu_disable(unsigned int cpu) | |
264 | { | |
265 | /* | |
266 | * If we don't have a cpu_die method, abort before we reach the point | |
267 | * of no return. CPU0 may not have an cpu_ops, so test for it. | |
268 | */ | |
269 | if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_die) | |
270 | return -EOPNOTSUPP; | |
271 | ||
272 | /* | |
273 | * We may need to abort a hot unplug for some other mechanism-specific | |
274 | * reason. | |
275 | */ | |
276 | if (cpu_ops[cpu]->cpu_disable) | |
277 | return cpu_ops[cpu]->cpu_disable(cpu); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | /* | |
283 | * __cpu_disable runs on the processor to be shutdown. | |
284 | */ | |
285 | int __cpu_disable(void) | |
286 | { | |
287 | unsigned int cpu = smp_processor_id(); | |
288 | int ret; | |
289 | ||
290 | ret = op_cpu_disable(cpu); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
7f9545aa SH |
294 | remove_cpu_topology(cpu); |
295 | numa_remove_cpu(cpu); | |
296 | ||
9327e2c6 MR |
297 | /* |
298 | * Take this CPU offline. Once we clear this, we can't return, | |
299 | * and we must not schedule until we're ready to give up the cpu. | |
300 | */ | |
301 | set_cpu_online(cpu, false); | |
302 | ||
303 | /* | |
304 | * OK - migrate IRQs away from this CPU | |
305 | */ | |
217d453d YY |
306 | irq_migrate_all_off_this_cpu(); |
307 | ||
9327e2c6 MR |
308 | return 0; |
309 | } | |
310 | ||
c814ca02 AC |
311 | static int op_cpu_kill(unsigned int cpu) |
312 | { | |
313 | /* | |
314 | * If we have no means of synchronising with the dying CPU, then assume | |
315 | * that it is really dead. We can only wait for an arbitrary length of | |
316 | * time and hope that it's dead, so let's skip the wait and just hope. | |
317 | */ | |
318 | if (!cpu_ops[cpu]->cpu_kill) | |
6b99c68c | 319 | return 0; |
c814ca02 AC |
320 | |
321 | return cpu_ops[cpu]->cpu_kill(cpu); | |
322 | } | |
323 | ||
9327e2c6 MR |
324 | /* |
325 | * called on the thread which is asking for a CPU to be shutdown - | |
326 | * waits until shutdown has completed, or it is timed out. | |
327 | */ | |
328 | void __cpu_die(unsigned int cpu) | |
329 | { | |
6b99c68c MR |
330 | int err; |
331 | ||
05981277 | 332 | if (!cpu_wait_death(cpu, 5)) { |
9327e2c6 MR |
333 | pr_crit("CPU%u: cpu didn't die\n", cpu); |
334 | return; | |
335 | } | |
336 | pr_notice("CPU%u: shutdown\n", cpu); | |
c814ca02 AC |
337 | |
338 | /* | |
339 | * Now that the dying CPU is beyond the point of no return w.r.t. | |
340 | * in-kernel synchronisation, try to get the firwmare to help us to | |
341 | * verify that it has really left the kernel before we consider | |
342 | * clobbering anything it might still be using. | |
343 | */ | |
6b99c68c MR |
344 | err = op_cpu_kill(cpu); |
345 | if (err) | |
346 | pr_warn("CPU%d may not have shut down cleanly: %d\n", | |
347 | cpu, err); | |
9327e2c6 MR |
348 | } |
349 | ||
350 | /* | |
351 | * Called from the idle thread for the CPU which has been shutdown. | |
352 | * | |
9327e2c6 MR |
353 | */ |
354 | void cpu_die(void) | |
355 | { | |
356 | unsigned int cpu = smp_processor_id(); | |
357 | ||
358 | idle_task_exit(); | |
359 | ||
0fbeb318 | 360 | local_daif_mask(); |
9327e2c6 MR |
361 | |
362 | /* Tell __cpu_die() that this CPU is now safe to dispose of */ | |
05981277 | 363 | (void)cpu_report_death(); |
9327e2c6 MR |
364 | |
365 | /* | |
366 | * Actually shutdown the CPU. This must never fail. The specific hotplug | |
367 | * mechanism must perform all required cache maintenance to ensure that | |
368 | * no dirty lines are lost in the process of shutting down the CPU. | |
369 | */ | |
370 | cpu_ops[cpu]->cpu_die(cpu); | |
371 | ||
372 | BUG(); | |
373 | } | |
374 | #endif | |
375 | ||
fce6361f SP |
376 | /* |
377 | * Kill the calling secondary CPU, early in bringup before it is turned | |
378 | * online. | |
379 | */ | |
380 | void cpu_die_early(void) | |
381 | { | |
382 | int cpu = smp_processor_id(); | |
383 | ||
384 | pr_crit("CPU%d: will not boot\n", cpu); | |
385 | ||
386 | /* Mark this CPU absent */ | |
387 | set_cpu_present(cpu, 0); | |
388 | ||
389 | #ifdef CONFIG_HOTPLUG_CPU | |
bb905274 | 390 | update_cpu_boot_status(CPU_KILL_ME); |
fce6361f SP |
391 | /* Check if we can park ourselves */ |
392 | if (cpu_ops[cpu] && cpu_ops[cpu]->cpu_die) | |
393 | cpu_ops[cpu]->cpu_die(cpu); | |
394 | #endif | |
bb905274 | 395 | update_cpu_boot_status(CPU_STUCK_IN_KERNEL); |
fce6361f SP |
396 | |
397 | cpu_park_loop(); | |
398 | } | |
399 | ||
377bcff9 JR |
400 | static void __init hyp_mode_check(void) |
401 | { | |
402 | if (is_hyp_mode_available()) | |
403 | pr_info("CPU: All CPU(s) started at EL2\n"); | |
404 | else if (is_hyp_mode_mismatched()) | |
405 | WARN_TAINT(1, TAINT_CPU_OUT_OF_SPEC, | |
406 | "CPU: CPUs started in inconsistent modes"); | |
407 | else | |
408 | pr_info("CPU: All CPU(s) started at EL1\n"); | |
409 | } | |
410 | ||
08e875c1 CM |
411 | void __init smp_cpus_done(unsigned int max_cpus) |
412 | { | |
326b16db | 413 | pr_info("SMP: Total of %d processors activated.\n", num_online_cpus()); |
3a75578e | 414 | setup_cpu_features(); |
377bcff9 JR |
415 | hyp_mode_check(); |
416 | apply_alternatives_all(); | |
5ea5306c | 417 | mark_linear_text_alias_ro(); |
08e875c1 CM |
418 | } |
419 | ||
420 | void __init smp_prepare_boot_cpu(void) | |
421 | { | |
9113c2aa | 422 | set_my_cpu_offset(per_cpu_offset(smp_processor_id())); |
4b998ff1 | 423 | cpuinfo_store_boot_cpu(); |
0ceb0d56 DT |
424 | |
425 | /* | |
426 | * We now know enough about the boot CPU to apply the | |
427 | * alternatives that cannot wait until interrupt handling | |
428 | * and/or scheduling is enabled. | |
429 | */ | |
430 | apply_boot_alternatives(); | |
e7932188 JT |
431 | |
432 | /* Conditionally switch to GIC PMR for interrupt masking */ | |
433 | if (system_uses_irq_prio_masking()) | |
434 | init_gic_priority_masking(); | |
08e875c1 CM |
435 | } |
436 | ||
0f078336 LP |
437 | static u64 __init of_get_cpu_mpidr(struct device_node *dn) |
438 | { | |
439 | const __be32 *cell; | |
440 | u64 hwid; | |
441 | ||
442 | /* | |
443 | * A cpu node with missing "reg" property is | |
444 | * considered invalid to build a cpu_logical_map | |
445 | * entry. | |
446 | */ | |
447 | cell = of_get_property(dn, "reg", NULL); | |
448 | if (!cell) { | |
a270f327 | 449 | pr_err("%pOF: missing reg property\n", dn); |
0f078336 LP |
450 | return INVALID_HWID; |
451 | } | |
452 | ||
453 | hwid = of_read_number(cell, of_n_addr_cells(dn)); | |
454 | /* | |
455 | * Non affinity bits must be set to 0 in the DT | |
456 | */ | |
457 | if (hwid & ~MPIDR_HWID_BITMASK) { | |
a270f327 | 458 | pr_err("%pOF: invalid reg property\n", dn); |
0f078336 LP |
459 | return INVALID_HWID; |
460 | } | |
461 | return hwid; | |
462 | } | |
463 | ||
464 | /* | |
465 | * Duplicate MPIDRs are a recipe for disaster. Scan all initialized | |
466 | * entries and check for duplicates. If any is found just ignore the | |
467 | * cpu. cpu_logical_map was initialized to INVALID_HWID to avoid | |
468 | * matching valid MPIDR values. | |
469 | */ | |
470 | static bool __init is_mpidr_duplicate(unsigned int cpu, u64 hwid) | |
471 | { | |
472 | unsigned int i; | |
473 | ||
474 | for (i = 1; (i < cpu) && (i < NR_CPUS); i++) | |
475 | if (cpu_logical_map(i) == hwid) | |
476 | return true; | |
477 | return false; | |
478 | } | |
479 | ||
819a8826 LP |
480 | /* |
481 | * Initialize cpu operations for a logical cpu and | |
482 | * set it in the possible mask on success | |
483 | */ | |
484 | static int __init smp_cpu_setup(int cpu) | |
485 | { | |
486 | if (cpu_read_ops(cpu)) | |
487 | return -ENODEV; | |
488 | ||
489 | if (cpu_ops[cpu]->cpu_init(cpu)) | |
490 | return -ENODEV; | |
491 | ||
492 | set_cpu_possible(cpu, true); | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
0f078336 LP |
497 | static bool bootcpu_valid __initdata; |
498 | static unsigned int cpu_count = 1; | |
499 | ||
500 | #ifdef CONFIG_ACPI | |
e0013aed MR |
501 | static struct acpi_madt_generic_interrupt cpu_madt_gicc[NR_CPUS]; |
502 | ||
503 | struct acpi_madt_generic_interrupt *acpi_cpu_get_madt_gicc(int cpu) | |
504 | { | |
505 | return &cpu_madt_gicc[cpu]; | |
506 | } | |
507 | ||
0f078336 LP |
508 | /* |
509 | * acpi_map_gic_cpu_interface - parse processor MADT entry | |
510 | * | |
511 | * Carry out sanity checks on MADT processor entry and initialize | |
512 | * cpu_logical_map on success | |
513 | */ | |
514 | static void __init | |
515 | acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) | |
516 | { | |
517 | u64 hwid = processor->arm_mpidr; | |
518 | ||
f9058929 HG |
519 | if (!(processor->flags & ACPI_MADT_ENABLED)) { |
520 | pr_debug("skipping disabled CPU entry with 0x%llx MPIDR\n", hwid); | |
0f078336 LP |
521 | return; |
522 | } | |
523 | ||
f9058929 HG |
524 | if (hwid & ~MPIDR_HWID_BITMASK || hwid == INVALID_HWID) { |
525 | pr_err("skipping CPU entry with invalid MPIDR 0x%llx\n", hwid); | |
0f078336 LP |
526 | return; |
527 | } | |
528 | ||
529 | if (is_mpidr_duplicate(cpu_count, hwid)) { | |
530 | pr_err("duplicate CPU MPIDR 0x%llx in MADT\n", hwid); | |
531 | return; | |
532 | } | |
533 | ||
534 | /* Check if GICC structure of boot CPU is available in the MADT */ | |
535 | if (cpu_logical_map(0) == hwid) { | |
536 | if (bootcpu_valid) { | |
537 | pr_err("duplicate boot CPU MPIDR: 0x%llx in MADT\n", | |
538 | hwid); | |
539 | return; | |
540 | } | |
541 | bootcpu_valid = true; | |
e0013aed | 542 | cpu_madt_gicc[0] = *processor; |
0f078336 LP |
543 | return; |
544 | } | |
545 | ||
546 | if (cpu_count >= NR_CPUS) | |
547 | return; | |
548 | ||
549 | /* map the logical cpu id to cpu MPIDR */ | |
550 | cpu_logical_map(cpu_count) = hwid; | |
551 | ||
e0013aed MR |
552 | cpu_madt_gicc[cpu_count] = *processor; |
553 | ||
5e89c55e LP |
554 | /* |
555 | * Set-up the ACPI parking protocol cpu entries | |
556 | * while initializing the cpu_logical_map to | |
557 | * avoid parsing MADT entries multiple times for | |
558 | * nothing (ie a valid cpu_logical_map entry should | |
559 | * contain a valid parking protocol data set to | |
560 | * initialize the cpu if the parking protocol is | |
561 | * the only available enable method). | |
562 | */ | |
563 | acpi_set_mailbox_entry(cpu_count, processor); | |
564 | ||
0f078336 LP |
565 | cpu_count++; |
566 | } | |
567 | ||
568 | static int __init | |
60574d1e | 569 | acpi_parse_gic_cpu_interface(union acpi_subtable_headers *header, |
0f078336 LP |
570 | const unsigned long end) |
571 | { | |
572 | struct acpi_madt_generic_interrupt *processor; | |
573 | ||
574 | processor = (struct acpi_madt_generic_interrupt *)header; | |
99e3e3ae | 575 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
0f078336 LP |
576 | return -EINVAL; |
577 | ||
60574d1e | 578 | acpi_table_print_madt_entry(&header->common); |
0f078336 LP |
579 | |
580 | acpi_map_gic_cpu_interface(processor); | |
581 | ||
582 | return 0; | |
583 | } | |
e1896249 LP |
584 | |
585 | static void __init acpi_parse_and_init_cpus(void) | |
586 | { | |
587 | int i; | |
588 | ||
589 | /* | |
590 | * do a walk of MADT to determine how many CPUs | |
591 | * we have including disabled CPUs, and get information | |
592 | * we need for SMP init. | |
593 | */ | |
594 | acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, | |
595 | acpi_parse_gic_cpu_interface, 0); | |
596 | ||
597 | /* | |
598 | * In ACPI, SMP and CPU NUMA information is provided in separate | |
599 | * static tables, namely the MADT and the SRAT. | |
600 | * | |
601 | * Thus, it is simpler to first create the cpu logical map through | |
602 | * an MADT walk and then map the logical cpus to their node ids | |
603 | * as separate steps. | |
604 | */ | |
605 | acpi_map_cpus_to_nodes(); | |
606 | ||
607 | for (i = 0; i < nr_cpu_ids; i++) | |
608 | early_map_cpu_to_node(i, acpi_numa_get_nid(i)); | |
609 | } | |
0f078336 | 610 | #else |
e1896249 | 611 | #define acpi_parse_and_init_cpus(...) do { } while (0) |
0f078336 LP |
612 | #endif |
613 | ||
08e875c1 | 614 | /* |
4c7aa002 JM |
615 | * Enumerate the possible CPU set from the device tree and build the |
616 | * cpu logical map array containing MPIDR values related to logical | |
617 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
08e875c1 | 618 | */ |
29b8302b | 619 | static void __init of_parse_and_init_cpus(void) |
08e875c1 | 620 | { |
3d29a9a0 | 621 | struct device_node *dn; |
08e875c1 | 622 | |
de76e70a | 623 | for_each_of_cpu_node(dn) { |
0f078336 | 624 | u64 hwid = of_get_cpu_mpidr(dn); |
4c7aa002 | 625 | |
0f078336 | 626 | if (hwid == INVALID_HWID) |
4c7aa002 | 627 | goto next; |
4c7aa002 | 628 | |
0f078336 | 629 | if (is_mpidr_duplicate(cpu_count, hwid)) { |
a270f327 RH |
630 | pr_err("%pOF: duplicate cpu reg properties in the DT\n", |
631 | dn); | |
4c7aa002 JM |
632 | goto next; |
633 | } | |
634 | ||
4c7aa002 JM |
635 | /* |
636 | * The numbering scheme requires that the boot CPU | |
637 | * must be assigned logical id 0. Record it so that | |
638 | * the logical map built from DT is validated and can | |
639 | * be used. | |
640 | */ | |
641 | if (hwid == cpu_logical_map(0)) { | |
642 | if (bootcpu_valid) { | |
a270f327 RH |
643 | pr_err("%pOF: duplicate boot cpu reg property in DT\n", |
644 | dn); | |
4c7aa002 JM |
645 | goto next; |
646 | } | |
647 | ||
648 | bootcpu_valid = true; | |
7ba5f605 | 649 | early_map_cpu_to_node(0, of_node_to_nid(dn)); |
4c7aa002 JM |
650 | |
651 | /* | |
652 | * cpu_logical_map has already been | |
653 | * initialized and the boot cpu doesn't need | |
654 | * the enable-method so continue without | |
655 | * incrementing cpu. | |
656 | */ | |
657 | continue; | |
658 | } | |
659 | ||
0f078336 | 660 | if (cpu_count >= NR_CPUS) |
08e875c1 CM |
661 | goto next; |
662 | ||
4c7aa002 | 663 | pr_debug("cpu logical map 0x%llx\n", hwid); |
0f078336 | 664 | cpu_logical_map(cpu_count) = hwid; |
1a2db300 GK |
665 | |
666 | early_map_cpu_to_node(cpu_count, of_node_to_nid(dn)); | |
08e875c1 | 667 | next: |
0f078336 | 668 | cpu_count++; |
08e875c1 | 669 | } |
0f078336 LP |
670 | } |
671 | ||
672 | /* | |
673 | * Enumerate the possible CPU set from the device tree or ACPI and build the | |
674 | * cpu logical map array containing MPIDR values related to logical | |
675 | * cpus. Assumes that cpu_logical_map(0) has already been initialized. | |
676 | */ | |
677 | void __init smp_init_cpus(void) | |
678 | { | |
679 | int i; | |
680 | ||
681 | if (acpi_disabled) | |
682 | of_parse_and_init_cpus(); | |
683 | else | |
e1896249 | 684 | acpi_parse_and_init_cpus(); |
08e875c1 | 685 | |
50ee91bd | 686 | if (cpu_count > nr_cpu_ids) |
9b130ad5 | 687 | pr_warn("Number of cores (%d) exceeds configured maximum of %u - clipping\n", |
50ee91bd | 688 | cpu_count, nr_cpu_ids); |
4c7aa002 JM |
689 | |
690 | if (!bootcpu_valid) { | |
0f078336 | 691 | pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); |
4c7aa002 JM |
692 | return; |
693 | } | |
694 | ||
695 | /* | |
819a8826 LP |
696 | * We need to set the cpu_logical_map entries before enabling |
697 | * the cpus so that cpu processor description entries (DT cpu nodes | |
698 | * and ACPI MADT entries) can be retrieved by matching the cpu hwid | |
699 | * with entries in cpu_logical_map while initializing the cpus. | |
700 | * If the cpu set-up fails, invalidate the cpu_logical_map entry. | |
4c7aa002 | 701 | */ |
50ee91bd | 702 | for (i = 1; i < nr_cpu_ids; i++) { |
819a8826 LP |
703 | if (cpu_logical_map(i) != INVALID_HWID) { |
704 | if (smp_cpu_setup(i)) | |
705 | cpu_logical_map(i) = INVALID_HWID; | |
706 | } | |
707 | } | |
08e875c1 CM |
708 | } |
709 | ||
710 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
711 | { | |
cd1aebf5 | 712 | int err; |
44dbcc93 | 713 | unsigned int cpu; |
c18df0ad | 714 | unsigned int this_cpu; |
08e875c1 | 715 | |
f6e763b9 MB |
716 | init_cpu_topology(); |
717 | ||
c18df0ad DD |
718 | this_cpu = smp_processor_id(); |
719 | store_cpu_topology(this_cpu); | |
720 | numa_store_cpu_info(this_cpu); | |
97fd6016 | 721 | numa_add_cpu(this_cpu); |
f6e763b9 | 722 | |
e75118a7 SP |
723 | /* |
724 | * If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set | |
725 | * secondary CPUs present. | |
726 | */ | |
727 | if (max_cpus == 0) | |
728 | return; | |
729 | ||
08e875c1 CM |
730 | /* |
731 | * Initialise the present map (which describes the set of CPUs | |
732 | * actually populated at the present time) and release the | |
733 | * secondaries from the bootloader. | |
734 | */ | |
735 | for_each_possible_cpu(cpu) { | |
08e875c1 | 736 | |
57c82954 MR |
737 | per_cpu(cpu_number, cpu) = cpu; |
738 | ||
d329de3f MZ |
739 | if (cpu == smp_processor_id()) |
740 | continue; | |
741 | ||
cd1aebf5 | 742 | if (!cpu_ops[cpu]) |
08e875c1 CM |
743 | continue; |
744 | ||
cd1aebf5 | 745 | err = cpu_ops[cpu]->cpu_prepare(cpu); |
d329de3f MZ |
746 | if (err) |
747 | continue; | |
08e875c1 CM |
748 | |
749 | set_cpu_present(cpu, true); | |
c18df0ad | 750 | numa_store_cpu_info(cpu); |
08e875c1 | 751 | } |
08e875c1 CM |
752 | } |
753 | ||
36310736 | 754 | void (*__smp_cross_call)(const struct cpumask *, unsigned int); |
08e875c1 CM |
755 | |
756 | void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int)) | |
757 | { | |
45ed695a | 758 | __smp_cross_call = fn; |
08e875c1 CM |
759 | } |
760 | ||
45ed695a NP |
761 | static const char *ipi_types[NR_IPI] __tracepoint_string = { |
762 | #define S(x,s) [x] = s | |
08e875c1 CM |
763 | S(IPI_RESCHEDULE, "Rescheduling interrupts"), |
764 | S(IPI_CALL_FUNC, "Function call interrupts"), | |
08e875c1 | 765 | S(IPI_CPU_STOP, "CPU stop interrupts"), |
78fd584c | 766 | S(IPI_CPU_CRASH_STOP, "CPU stop (for crash dump) interrupts"), |
1f85008e | 767 | S(IPI_TIMER, "Timer broadcast interrupts"), |
eb631bb5 | 768 | S(IPI_IRQ_WORK, "IRQ work interrupts"), |
5e89c55e | 769 | S(IPI_WAKEUP, "CPU wake-up interrupts"), |
08e875c1 CM |
770 | }; |
771 | ||
45ed695a NP |
772 | static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) |
773 | { | |
774 | trace_ipi_raise(target, ipi_types[ipinr]); | |
775 | __smp_cross_call(target, ipinr); | |
776 | } | |
777 | ||
08e875c1 CM |
778 | void show_ipi_list(struct seq_file *p, int prec) |
779 | { | |
780 | unsigned int cpu, i; | |
781 | ||
782 | for (i = 0; i < NR_IPI; i++) { | |
45ed695a | 783 | seq_printf(p, "%*s%u:%s", prec - 1, "IPI", i, |
08e875c1 | 784 | prec >= 4 ? " " : ""); |
67317c26 | 785 | for_each_online_cpu(cpu) |
08e875c1 CM |
786 | seq_printf(p, "%10u ", |
787 | __get_irq_stat(cpu, ipi_irqs[i])); | |
788 | seq_printf(p, " %s\n", ipi_types[i]); | |
789 | } | |
790 | } | |
791 | ||
792 | u64 smp_irq_stat_cpu(unsigned int cpu) | |
793 | { | |
794 | u64 sum = 0; | |
795 | int i; | |
796 | ||
797 | for (i = 0; i < NR_IPI; i++) | |
798 | sum += __get_irq_stat(cpu, ipi_irqs[i]); | |
799 | ||
800 | return sum; | |
801 | } | |
802 | ||
45ed695a NP |
803 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
804 | { | |
805 | smp_cross_call(mask, IPI_CALL_FUNC); | |
806 | } | |
807 | ||
808 | void arch_send_call_function_single_ipi(int cpu) | |
809 | { | |
0aaf0dae | 810 | smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC); |
45ed695a NP |
811 | } |
812 | ||
5e89c55e LP |
813 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
814 | void arch_send_wakeup_ipi_mask(const struct cpumask *mask) | |
815 | { | |
816 | smp_cross_call(mask, IPI_WAKEUP); | |
817 | } | |
818 | #endif | |
819 | ||
45ed695a NP |
820 | #ifdef CONFIG_IRQ_WORK |
821 | void arch_irq_work_raise(void) | |
822 | { | |
823 | if (__smp_cross_call) | |
824 | smp_cross_call(cpumask_of(smp_processor_id()), IPI_IRQ_WORK); | |
825 | } | |
826 | #endif | |
827 | ||
d914d4d4 | 828 | static void local_cpu_stop(void) |
08e875c1 | 829 | { |
d914d4d4 | 830 | set_cpu_online(smp_processor_id(), false); |
08e875c1 | 831 | |
0fbeb318 | 832 | local_daif_mask(); |
f5df2696 | 833 | sdei_mask_local_cpu(); |
dccc9da2 | 834 | cpu_park_loop(); |
08e875c1 | 835 | } |
08e875c1 | 836 | |
d914d4d4 AK |
837 | /* |
838 | * We need to implement panic_smp_self_stop() for parallel panic() calls, so | |
839 | * that cpu_online_mask gets correctly updated and smp_send_stop() can skip | |
840 | * CPUs that have already stopped themselves. | |
841 | */ | |
842 | void panic_smp_self_stop(void) | |
843 | { | |
844 | local_cpu_stop(); | |
08e875c1 CM |
845 | } |
846 | ||
78fd584c AT |
847 | #ifdef CONFIG_KEXEC_CORE |
848 | static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); | |
849 | #endif | |
850 | ||
851 | static void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) | |
852 | { | |
853 | #ifdef CONFIG_KEXEC_CORE | |
854 | crash_save_cpu(regs, cpu); | |
855 | ||
856 | atomic_dec(&waiting_for_crash_ipi); | |
857 | ||
858 | local_irq_disable(); | |
f5df2696 | 859 | sdei_mask_local_cpu(); |
78fd584c AT |
860 | |
861 | #ifdef CONFIG_HOTPLUG_CPU | |
862 | if (cpu_ops[cpu]->cpu_die) | |
863 | cpu_ops[cpu]->cpu_die(cpu); | |
864 | #endif | |
865 | ||
866 | /* just in case */ | |
867 | cpu_park_loop(); | |
868 | #endif | |
869 | } | |
870 | ||
08e875c1 CM |
871 | /* |
872 | * Main handler for inter-processor interrupts | |
873 | */ | |
874 | void handle_IPI(int ipinr, struct pt_regs *regs) | |
875 | { | |
876 | unsigned int cpu = smp_processor_id(); | |
877 | struct pt_regs *old_regs = set_irq_regs(regs); | |
878 | ||
45ed695a | 879 | if ((unsigned)ipinr < NR_IPI) { |
be081d9b | 880 | trace_ipi_entry_rcuidle(ipi_types[ipinr]); |
45ed695a NP |
881 | __inc_irq_stat(cpu, ipi_irqs[ipinr]); |
882 | } | |
08e875c1 CM |
883 | |
884 | switch (ipinr) { | |
885 | case IPI_RESCHEDULE: | |
886 | scheduler_ipi(); | |
887 | break; | |
888 | ||
889 | case IPI_CALL_FUNC: | |
890 | irq_enter(); | |
891 | generic_smp_call_function_interrupt(); | |
892 | irq_exit(); | |
893 | break; | |
894 | ||
08e875c1 CM |
895 | case IPI_CPU_STOP: |
896 | irq_enter(); | |
d914d4d4 | 897 | local_cpu_stop(); |
08e875c1 CM |
898 | irq_exit(); |
899 | break; | |
900 | ||
78fd584c AT |
901 | case IPI_CPU_CRASH_STOP: |
902 | if (IS_ENABLED(CONFIG_KEXEC_CORE)) { | |
903 | irq_enter(); | |
904 | ipi_cpu_crash_stop(cpu, regs); | |
905 | ||
906 | unreachable(); | |
907 | } | |
908 | break; | |
909 | ||
1f85008e LP |
910 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
911 | case IPI_TIMER: | |
912 | irq_enter(); | |
913 | tick_receive_broadcast(); | |
914 | irq_exit(); | |
915 | break; | |
916 | #endif | |
917 | ||
eb631bb5 LB |
918 | #ifdef CONFIG_IRQ_WORK |
919 | case IPI_IRQ_WORK: | |
920 | irq_enter(); | |
921 | irq_work_run(); | |
922 | irq_exit(); | |
923 | break; | |
924 | #endif | |
925 | ||
5e89c55e LP |
926 | #ifdef CONFIG_ARM64_ACPI_PARKING_PROTOCOL |
927 | case IPI_WAKEUP: | |
928 | WARN_ONCE(!acpi_parking_protocol_valid(cpu), | |
929 | "CPU%u: Wake-up IPI outside the ACPI parking protocol\n", | |
930 | cpu); | |
931 | break; | |
932 | #endif | |
933 | ||
08e875c1 CM |
934 | default: |
935 | pr_crit("CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr); | |
936 | break; | |
937 | } | |
45ed695a NP |
938 | |
939 | if ((unsigned)ipinr < NR_IPI) | |
be081d9b | 940 | trace_ipi_exit_rcuidle(ipi_types[ipinr]); |
08e875c1 CM |
941 | set_irq_regs(old_regs); |
942 | } | |
943 | ||
944 | void smp_send_reschedule(int cpu) | |
945 | { | |
946 | smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE); | |
947 | } | |
948 | ||
1f85008e LP |
949 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
950 | void tick_broadcast(const struct cpumask *mask) | |
951 | { | |
952 | smp_cross_call(mask, IPI_TIMER); | |
953 | } | |
954 | #endif | |
955 | ||
08e875c1 CM |
956 | void smp_send_stop(void) |
957 | { | |
958 | unsigned long timeout; | |
959 | ||
960 | if (num_online_cpus() > 1) { | |
961 | cpumask_t mask; | |
962 | ||
963 | cpumask_copy(&mask, cpu_online_mask); | |
434ed7f4 | 964 | cpumask_clear_cpu(smp_processor_id(), &mask); |
08e875c1 | 965 | |
ef284f5c | 966 | if (system_state <= SYSTEM_RUNNING) |
82611c14 | 967 | pr_crit("SMP: stopping secondary CPUs\n"); |
08e875c1 CM |
968 | smp_cross_call(&mask, IPI_CPU_STOP); |
969 | } | |
970 | ||
971 | /* Wait up to one second for other CPUs to stop */ | |
972 | timeout = USEC_PER_SEC; | |
973 | while (num_online_cpus() > 1 && timeout--) | |
974 | udelay(1); | |
975 | ||
976 | if (num_online_cpus() > 1) | |
82611c14 JG |
977 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", |
978 | cpumask_pr_args(cpu_online_mask)); | |
f5df2696 JM |
979 | |
980 | sdei_mask_local_cpu(); | |
08e875c1 CM |
981 | } |
982 | ||
78fd584c | 983 | #ifdef CONFIG_KEXEC_CORE |
a88ce63b | 984 | void crash_smp_send_stop(void) |
78fd584c | 985 | { |
a88ce63b | 986 | static int cpus_stopped; |
78fd584c AT |
987 | cpumask_t mask; |
988 | unsigned long timeout; | |
989 | ||
a88ce63b HR |
990 | /* |
991 | * This function can be called twice in panic path, but obviously | |
992 | * we execute this only once. | |
993 | */ | |
994 | if (cpus_stopped) | |
995 | return; | |
996 | ||
997 | cpus_stopped = 1; | |
998 | ||
f5df2696 JM |
999 | if (num_online_cpus() == 1) { |
1000 | sdei_mask_local_cpu(); | |
78fd584c | 1001 | return; |
f5df2696 | 1002 | } |
78fd584c AT |
1003 | |
1004 | cpumask_copy(&mask, cpu_online_mask); | |
1005 | cpumask_clear_cpu(smp_processor_id(), &mask); | |
1006 | ||
1007 | atomic_set(&waiting_for_crash_ipi, num_online_cpus() - 1); | |
1008 | ||
1009 | pr_crit("SMP: stopping secondary CPUs\n"); | |
1010 | smp_cross_call(&mask, IPI_CPU_CRASH_STOP); | |
1011 | ||
1012 | /* Wait up to one second for other CPUs to stop */ | |
1013 | timeout = USEC_PER_SEC; | |
1014 | while ((atomic_read(&waiting_for_crash_ipi) > 0) && timeout--) | |
1015 | udelay(1); | |
1016 | ||
1017 | if (atomic_read(&waiting_for_crash_ipi) > 0) | |
1018 | pr_warning("SMP: failed to stop secondary CPUs %*pbl\n", | |
1019 | cpumask_pr_args(&mask)); | |
f5df2696 JM |
1020 | |
1021 | sdei_mask_local_cpu(); | |
78fd584c AT |
1022 | } |
1023 | ||
1024 | bool smp_crash_stop_failed(void) | |
1025 | { | |
1026 | return (atomic_read(&waiting_for_crash_ipi) > 0); | |
1027 | } | |
1028 | #endif | |
1029 | ||
08e875c1 CM |
1030 | /* |
1031 | * not supported here | |
1032 | */ | |
1033 | int setup_profiling_timer(unsigned int multiplier) | |
1034 | { | |
1035 | return -EINVAL; | |
1036 | } | |
5c492c3f JM |
1037 | |
1038 | static bool have_cpu_die(void) | |
1039 | { | |
1040 | #ifdef CONFIG_HOTPLUG_CPU | |
1041 | int any_cpu = raw_smp_processor_id(); | |
1042 | ||
335d2c2d | 1043 | if (cpu_ops[any_cpu] && cpu_ops[any_cpu]->cpu_die) |
5c492c3f JM |
1044 | return true; |
1045 | #endif | |
1046 | return false; | |
1047 | } | |
1048 | ||
1049 | bool cpus_are_stuck_in_kernel(void) | |
1050 | { | |
1051 | bool smp_spin_tables = (num_possible_cpus() > 1 && !have_cpu_die()); | |
1052 | ||
1053 | return !!cpus_stuck_in_kernel || smp_spin_tables; | |
1054 | } |