projects / thirdparty / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5d8544e2 PD |
1 | /* |
| 2 | * Copyright (C) 2015 Regents of the University of California | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or | |
| 5 | * modify it under the terms of the GNU General Public License | |
| 6 | * as published by the Free Software Foundation, version 2. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 11 | * GNU General Public License for more details. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef _ASM_RISCV_CSR_H | |
| 15 | #define _ASM_RISCV_CSR_H | |
| 16 | ||
| 17 | #include <linux/const.h> | |
| 18 | ||
| 19 | /* Status register flags */ | |
| 196a14d4 AP |
20 | #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ |
| 21 | #define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ | |
| 22 | #define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ | |
| 23 | #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ | |
| 5d8544e2 | 24 | |
| 196a14d4 AP |
25 | #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ |
| 26 | #define SR_FS_OFF _AC(0x00000000, UL) | |
| 27 | #define SR_FS_INITIAL _AC(0x00002000, UL) | |
| 28 | #define SR_FS_CLEAN _AC(0x00004000, UL) | |
| 29 | #define SR_FS_DIRTY _AC(0x00006000, UL) | |
| 5d8544e2 | 30 | |
| 196a14d4 AP |
31 | #define SR_XS _AC(0x00018000, UL) /* Extension Status */ |
| 32 | #define SR_XS_OFF _AC(0x00000000, UL) | |
| 33 | #define SR_XS_INITIAL _AC(0x00008000, UL) | |
| 34 | #define SR_XS_CLEAN _AC(0x00010000, UL) | |
| 35 | #define SR_XS_DIRTY _AC(0x00018000, UL) | |
| 5d8544e2 PD |
36 | |
| 37 | #ifndef CONFIG_64BIT | |
| 196a14d4 | 38 | #define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ |
| 5d8544e2 | 39 | #else |
| 196a14d4 | 40 | #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ |
| 5d8544e2 PD |
41 | #endif |
| 42 | ||
| 7549cdf5 | 43 | /* SATP flags */ |
| 196a14d4 AP |
44 | #ifndef CONFIG_64BIT |
| 45 | #define SATP_PPN _AC(0x003FFFFF, UL) | |
| 46 | #define SATP_MODE_32 _AC(0x80000000, UL) | |
| 47 | #define SATP_MODE SATP_MODE_32 | |
| 5d8544e2 | 48 | #else |
| 196a14d4 AP |
49 | #define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) |
| 50 | #define SATP_MODE_39 _AC(0x8000000000000000, UL) | |
| 51 | #define SATP_MODE SATP_MODE_39 | |
| 5d8544e2 PD |
52 | #endif |
| 53 | ||
| 6dcaf004 AP |
54 | /* SCAUSE */ |
| 55 | #define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) | |
| 56 | ||
| 57 | #define IRQ_U_SOFT 0 | |
| 58 | #define IRQ_S_SOFT 1 | |
| 59 | #define IRQ_M_SOFT 3 | |
| 60 | #define IRQ_U_TIMER 4 | |
| 61 | #define IRQ_S_TIMER 5 | |
| 62 | #define IRQ_M_TIMER 7 | |
| 63 | #define IRQ_U_EXT 8 | |
| 64 | #define IRQ_S_EXT 9 | |
| 65 | #define IRQ_M_EXT 11 | |
| 5d8544e2 | 66 | |
| 196a14d4 AP |
67 | #define EXC_INST_MISALIGNED 0 |
| 68 | #define EXC_INST_ACCESS 1 | |
| 69 | #define EXC_BREAKPOINT 3 | |
| 70 | #define EXC_LOAD_ACCESS 5 | |
| 71 | #define EXC_STORE_ACCESS 7 | |
| 72 | #define EXC_SYSCALL 8 | |
| 73 | #define EXC_INST_PAGE_FAULT 12 | |
| 74 | #define EXC_LOAD_PAGE_FAULT 13 | |
| 75 | #define EXC_STORE_PAGE_FAULT 15 | |
| 5d8544e2 | 76 | |
| 6dcaf004 AP |
77 | /* SIE (Interrupt Enable) and SIP (Interrupt Pending) flags */ |
| 78 | #define SIE_SSIE (_AC(0x1, UL) << IRQ_S_SOFT) | |
| 79 | #define SIE_STIE (_AC(0x1, UL) << IRQ_S_TIMER) | |
| 80 | #define SIE_SEIE (_AC(0x1, UL) << IRQ_S_EXT) | |
| 81 | ||
| 5d8544e2 PD |
82 | #ifndef __ASSEMBLY__ |
| 83 | ||
| 84 | #define csr_swap(csr, val) \ | |
| 85 | ({ \ | |
| 86 | unsigned long __v = (unsigned long)(val); \ | |
| 87 | __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \ | |
| 88 | : "=r" (__v) : "rK" (__v) \ | |
| 89 | : "memory"); \ | |
| 90 | __v; \ | |
| 91 | }) | |
| 92 | ||
| 93 | #define csr_read(csr) \ | |
| 94 | ({ \ | |
| 95 | register unsigned long __v; \ | |
| 96 | __asm__ __volatile__ ("csrr %0, " #csr \ | |
| 97 | : "=r" (__v) : \ | |
| 98 | : "memory"); \ | |
| 99 | __v; \ | |
| 100 | }) | |
| 101 | ||
| 102 | #define csr_write(csr, val) \ | |
| 103 | ({ \ | |
| 104 | unsigned long __v = (unsigned long)(val); \ | |
| 105 | __asm__ __volatile__ ("csrw " #csr ", %0" \ | |
| 106 | : : "rK" (__v) \ | |
| 107 | : "memory"); \ | |
| 108 | }) | |
| 109 | ||
| 110 | #define csr_read_set(csr, val) \ | |
| 111 | ({ \ | |
| 112 | unsigned long __v = (unsigned long)(val); \ | |
| 113 | __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \ | |
| 114 | : "=r" (__v) : "rK" (__v) \ | |
| 115 | : "memory"); \ | |
| 116 | __v; \ | |
| 117 | }) | |
| 118 | ||
| 119 | #define csr_set(csr, val) \ | |
| 120 | ({ \ | |
| 121 | unsigned long __v = (unsigned long)(val); \ | |
| 122 | __asm__ __volatile__ ("csrs " #csr ", %0" \ | |
| 123 | : : "rK" (__v) \ | |
| 124 | : "memory"); \ | |
| 125 | }) | |
| 126 | ||
| 127 | #define csr_read_clear(csr, val) \ | |
| 128 | ({ \ | |
| 129 | unsigned long __v = (unsigned long)(val); \ | |
| 130 | __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \ | |
| 131 | : "=r" (__v) : "rK" (__v) \ | |
| 132 | : "memory"); \ | |
| 133 | __v; \ | |
| 134 | }) | |
| 135 | ||
| 136 | #define csr_clear(csr, val) \ | |
| 137 | ({ \ | |
| 138 | unsigned long __v = (unsigned long)(val); \ | |
| 139 | __asm__ __volatile__ ("csrc " #csr ", %0" \ | |
| 140 | : : "rK" (__v) \ | |
| 141 | : "memory"); \ | |
| 142 | }) | |
| 143 | ||
| 144 | #endif /* __ASSEMBLY__ */ | |
| 145 | ||
| 146 | #endif /* _ASM_RISCV_CSR_H */ |