[thirdparty/linux.git] / arch / x86 / kernel / cpu / mce / severity.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * MCE grading rules.
 * Copyright 2008, 2009 Intel Corporation.
 *
 * Author: Andi Kleen
 */
#include <linux/kernel.h>
#include <linux/seq_file.h>
#include <linux/init.h>
#include <linux/debugfs.h>
#include <asm/mce.h>
#include <linux/uaccess.h>

#include "internal.h"

/*
 * Grade an mce by severity. In general the most severe ones are processed
 * first. Since there are quite a lot of combinations test the bits in a
 * table-driven way. The rules are simply processed in order, first
 * match wins.
 *
 * Note this is only used for machine check exceptions, the corrected
 * errors use much simpler rules. The exceptions still check for the corrected
 * errors, but only to leave them alone for the CMCI handler (except for
 * panic situations)
 */

enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 };
enum ser { SER_REQUIRED = 1, NO_SER = 2 };
enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };

static struct severity {
	u64 mask;
	u64 result;
	unsigned char sev;
	unsigned char mcgmask;
	unsigned char mcgres;
	unsigned char ser;
	unsigned char context;
	unsigned char excp;
	unsigned char covered;
	char *msg;
} severities[] = {
#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
#define  KERNEL		.context = IN_KERNEL
#define  USER		.context = IN_USER
#define  KERNEL_RECOV	.context = IN_KERNEL_RECOV
#define  SER		.ser = SER_REQUIRED
#define  NOSER		.ser = NO_SER
#define  EXCP		.excp = EXCP_CONTEXT
#define  NOEXCP		.excp = NO_EXCP
#define  BITCLR(x)	.mask = x, .result = 0
#define  BITSET(x)	.mask = x, .result = x
#define  MCGMASK(x, y)	.mcgmask = x, .mcgres = y
#define  MASK(x, y)	.mask = x, .result = y
#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
#define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR)
#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
#define	MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)

	MCESEV(
		NO, "Invalid",
		BITCLR(MCI_STATUS_VAL)
		),
	MCESEV(
		NO, "Not enabled",
		EXCP, BITCLR(MCI_STATUS_EN)
		),
	MCESEV(
		PANIC, "Processor context corrupt",
		BITSET(MCI_STATUS_PCC)
		),
	/* When MCIP is not set something is very confused */
	MCESEV(
		PANIC, "MCIP not set in MCA handler",
		EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
		),
	/* Neither return not error IP -- no chance to recover -> PANIC */
	MCESEV(
		PANIC, "Neither restart nor error IP",
		EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0)
		),
	MCESEV(
		PANIC, "In kernel and no restart IP",
		EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
		),
	MCESEV(
		PANIC, "In kernel and no restart IP",
		EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
		),
	MCESEV(
		DEFERRED, "Deferred error",
		NOSER, MASK(MCI_STATUS_UC|MCI_STATUS_DEFERRED|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
		),
	MCESEV(
		KEEP, "Corrected error",
		NOSER, BITCLR(MCI_STATUS_UC)
		),

	/*
	 * known AO MCACODs reported via MCE or CMC:
	 *
	 * SRAO could be signaled either via a machine check exception or
	 * CMCI with the corresponding bit S 1 or 0. So we don't need to
	 * check bit S for SRAO.
	 */
	MCESEV(
		AO, "Action optional: memory scrubbing error",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
		),
	MCESEV(
		AO, "Action optional: last level cache writeback error",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
		),

	/* ignore OVER for UCNA */
	MCESEV(
		UCNA, "Uncorrected no action required",
		SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
		),
	MCESEV(
		PANIC, "Illegal combination (UCNA with AR=1)",
		SER,
		MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR)
		),
	MCESEV(
		KEEP, "Non signalled machine check",
		SER, BITCLR(MCI_STATUS_S)
		),

	MCESEV(
		PANIC, "Action required with lost events",
		SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR)
		),

	/* known AR MCACODs: */
#ifdef	CONFIG_MEMORY_FAILURE
	MCESEV(
		KEEP, "Action required but unaffected thread is continuable",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR),
		MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV)
		),
	MCESEV(
		AR, "Action required: data load in error recoverable area of kernel",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
		KERNEL_RECOV
		),
	MCESEV(
		AR, "Action required: data load error in a user process",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
		USER
		),
	MCESEV(
		AR, "Action required: instruction fetch error in a user process",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
		USER
		),
	MCESEV(
		PANIC, "Data load in unrecoverable area of kernel",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
		KERNEL
		),
	MCESEV(
		PANIC, "Instruction fetch error in kernel",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
		KERNEL
		),
#endif
	MCESEV(
		PANIC, "Action required: unknown MCACOD",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR)
		),

	MCESEV(
		SOME, "Action optional: unknown MCACOD",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S)
		),
	MCESEV(
		SOME, "Action optional with lost events",
		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S)
		),

	MCESEV(
		PANIC, "Overflowed uncorrected",
		BITSET(MCI_STATUS_OVER|MCI_STATUS_UC)
		),
	MCESEV(
		UC, "Uncorrected",
		BITSET(MCI_STATUS_UC)
		),
	MCESEV(
		SOME, "No match",
		BITSET(0)
		)	/* always matches. keep at end */
};

#define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \
				(MCG_STATUS_RIPV|MCG_STATUS_EIPV))

/*
 * If mcgstatus indicated that ip/cs on the stack were
 * no good, then "m->cs" will be zero and we will have
 * to assume the worst case (IN_KERNEL) as we actually
 * have no idea what we were executing when the machine
 * check hit.
 * If we do have a good "m->cs" (or a faked one in the
 * case we were executing in VM86 mode) we can use it to
 * distinguish an exception taken in user from from one
 * taken in the kernel.
 */
static int error_context(struct mce *m)
{
	if ((m->cs & 3) == 3)
		return IN_USER;
	if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip))
		return IN_KERNEL_RECOV;
	return IN_KERNEL;
}

static int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
{
	u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
	u32 low, high;

	/*
	 * We need to look at the following bits:
	 * - "succor" bit (data poisoning support), and
	 * - TCC bit (Task Context Corrupt)
	 * in MCi_STATUS to determine error severity.
	 */
	if (!mce_flags.succor)
		return MCE_PANIC_SEVERITY;

	if (rdmsr_safe(addr, &low, &high))
		return MCE_PANIC_SEVERITY;

	/* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
	if ((low & MCI_CONFIG_MCAX) &&
	    (m->status & MCI_STATUS_TCC) &&
	    (err_ctx == IN_KERNEL))
		return MCE_PANIC_SEVERITY;

	 /* ...otherwise invoke hwpoison handler. */
	return MCE_AR_SEVERITY;
}

/*
 * See AMD Error Scope Hierarchy table in a newer BKDG. For example
 * 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
 */
static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_excp)
{
	enum context ctx = error_context(m);

	/* Processor Context Corrupt, no need to fumble too much, die! */
	if (m->status & MCI_STATUS_PCC)
		return MCE_PANIC_SEVERITY;

	if (m->status & MCI_STATUS_UC) {

		if (ctx == IN_KERNEL)
			return MCE_PANIC_SEVERITY;

		/*
		 * On older systems where overflow_recov flag is not present, we
		 * should simply panic if an error overflow occurs. If
		 * overflow_recov flag is present and set, then software can try
		 * to at least kill process to prolong system operation.
		 */
		if (mce_flags.overflow_recov) {
			if (mce_flags.smca)
				return mce_severity_amd_smca(m, ctx);

			/* kill current process */
			return MCE_AR_SEVERITY;
		} else {
			/* at least one error was not logged */
			if (m->status & MCI_STATUS_OVER)
				return MCE_PANIC_SEVERITY;
		}

		/*
		 * For any other case, return MCE_UC_SEVERITY so that we log the
		 * error and exit #MC handler.
		 */
		return MCE_UC_SEVERITY;
	}

	/*
	 * deferred error: poll handler catches these and adds to mce_ring so
	 * memory-failure can take recovery actions.
	 */
	if (m->status & MCI_STATUS_DEFERRED)
		return MCE_DEFERRED_SEVERITY;

	/*
	 * corrected error: poll handler catches these and passes responsibility
	 * of decoding the error to EDAC
	 */
	return MCE_KEEP_SEVERITY;
}

static int mce_severity_intel(struct mce *m, int tolerant, char **msg, bool is_excp)
{
	enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
	enum context ctx = error_context(m);
	struct severity *s;

	for (s = severities;; s++) {
		if ((m->status & s->mask) != s->result)
			continue;
		if ((m->mcgstatus & s->mcgmask) != s->mcgres)
			continue;
		if (s->ser == SER_REQUIRED && !mca_cfg.ser)
			continue;
		if (s->ser == NO_SER && mca_cfg.ser)
			continue;
		if (s->context && ctx != s->context)
			continue;
		if (s->excp && excp != s->excp)
			continue;
		if (msg)
			*msg = s->msg;
		s->covered = 1;
		if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) {
			if (tolerant < 1)
				return MCE_PANIC_SEVERITY;
		}
		return s->sev;
	}
}

/* Default to mce_severity_intel */
int (*mce_severity)(struct mce *m, int tolerant, char **msg, bool is_excp) =
		    mce_severity_intel;

void __init mcheck_vendor_init_severity(void)
{
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
		mce_severity = mce_severity_amd;
}

#ifdef CONFIG_DEBUG_FS
static void *s_start(struct seq_file *f, loff_t *pos)
{
	if (*pos >= ARRAY_SIZE(severities))
		return NULL;
	return &severities[*pos];
}

static void *s_next(struct seq_file *f, void *data, loff_t *pos)
{
	if (++(*pos) >= ARRAY_SIZE(severities))
		return NULL;
	return &severities[*pos];
}

static void s_stop(struct seq_file *f, void *data)
{
}

static int s_show(struct seq_file *f, void *data)
{
	struct severity *ser = data;
	seq_printf(f, "%d\t%s\n", ser->covered, ser->msg);
	return 0;
}

static const struct seq_operations severities_seq_ops = {
	.start	= s_start,
	.next	= s_next,
	.stop	= s_stop,
	.show	= s_show,
};

static int severities_coverage_open(struct inode *inode, struct file *file)
{
	return seq_open(file, &severities_seq_ops);
}

static ssize_t severities_coverage_write(struct file *file,
					 const char __user *ubuf,
					 size_t count, loff_t *ppos)
{
	int i;
	for (i = 0; i < ARRAY_SIZE(severities); i++)
		severities[i].covered = 0;
	return count;
}

static const struct file_operations severities_coverage_fops = {
	.open		= severities_coverage_open,
	.release	= seq_release,
	.read		= seq_read,
	.write		= severities_coverage_write,
	.llseek		= seq_lseek,
};

static int __init severities_debugfs_init(void)
{
	struct dentry *dmce, *fsev;

	dmce = mce_get_debugfs_dir();
	if (!dmce)
		goto err_out;

	fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
				   &severities_coverage_fops);
	if (!fsev)
		goto err_out;

	return 0;

err_out:
	return -ENOMEM;
}
late_initcall(severities_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
Commit	Line	Data
b886d83c	1	// SPDX-License-Identifier: GPL-2.0-only
817f32d0 AK	2	/*
	3	* MCE grading rules.
	4	* Copyright 2008, 2009 Intel Corporation.
	5	*
817f32d0 AK	6	* Author: Andi Kleen
	7	*/
	8	#include <linux/kernel.h>
4611a6fa HY	9	#include <linux/seq_file.h>
	10	#include <linux/init.h>
	11	#include <linux/debugfs.h>
817f32d0	12	#include <asm/mce.h>
7c0f6ba6	13	#include <linux/uaccess.h>
817f32d0	14
21afaf18	15	#include "internal.h"
817f32d0 AK	16
	17	/*
	18	* Grade an mce by severity. In general the most severe ones are processed
	19	* first. Since there are quite a lot of combinations test the bits in a
	20	* table-driven way. The rules are simply processed in order, first
	21	* match wins.
ed7290d0 AK	22	*
	23	* Note this is only used for machine check exceptions, the corrected
	24	* errors use much simpler rules. The exceptions still check for the corrected
	25	* errors, but only to leave them alone for the CMCI handler (except for
	26	* panic situations)
817f32d0 AK	27	*/
817f32d0 AK	28
b2f9d678	29	enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 };
ed7290d0	30	enum ser { SER_REQUIRED = 1, NO_SER = 2 };
e3480271	31	enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 };
ed7290d0	32
817f32d0 AK	33	static struct severity {
	34	u64 mask;
	35	u64 result;
	36	unsigned char sev;
	37	unsigned char mcgmask;
	38	unsigned char mcgres;
ed7290d0 AK	39	unsigned char ser;
ed7290d0 AK	40	unsigned char context;
e3480271	41	unsigned char excp;
4611a6fa	42	unsigned char covered;
817f32d0 AK	43	char *msg;
817f32d0 AK	44	} severities[] = {
a17957cd HS	45	#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
	46	#define KERNEL .context = IN_KERNEL
	47	#define USER .context = IN_USER
b2f9d678	48	#define KERNEL_RECOV .context = IN_KERNEL_RECOV
a17957cd HS	49	#define SER .ser = SER_REQUIRED
a17957cd HS	50	#define NOSER .ser = NO_SER
e3480271 CY	51	#define EXCP .excp = EXCP_CONTEXT
e3480271 CY	52	#define NOEXCP .excp = NO_EXCP
a17957cd HS	53	#define BITCLR(x) .mask = x, .result = 0
	54	#define BITSET(x) .mask = x, .result = x
	55	#define MCGMASK(x, y) .mcgmask = x, .mcgres = y
	56	#define MASK(x, y) .mask = x, .result = y
ed7290d0	57	#define MCI_UC_S (MCI_STATUS_UC\|MCI_STATUS_S)
e085ac7a	58	#define MCI_UC_AR (MCI_STATUS_UC\|MCI_STATUS_AR)
ed7290d0	59	#define MCI_UC_SAR (MCI_STATUS_UC\|MCI_STATUS_S\|MCI_STATUS_AR)
5f7b88d5	60	#define MCI_ADDR (MCI_STATUS_ADDRV\|MCI_STATUS_MISCV)
ed7290d0	61
a17957cd HS	62	MCESEV(
	63	NO, "Invalid",
	64	BITCLR(MCI_STATUS_VAL)
901d7691	65	),
a17957cd HS	66	MCESEV(
a17957cd HS	67	NO, "Not enabled",
e3480271	68	EXCP, BITCLR(MCI_STATUS_EN)
901d7691	69	),
a17957cd HS	70	MCESEV(
	71	PANIC, "Processor context corrupt",
	72	BITSET(MCI_STATUS_PCC)
901d7691	73	),
ed7290d0	74	/* When MCIP is not set something is very confused */
a17957cd HS	75	MCESEV(
a17957cd HS	76	PANIC, "MCIP not set in MCA handler",
e3480271	77	EXCP, MCGMASK(MCG_STATUS_MCIP, 0)
901d7691	78	),
ed7290d0	79	/* Neither return not error IP -- no chance to recover -> PANIC */
a17957cd HS	80	MCESEV(
a17957cd HS	81	PANIC, "Neither restart nor error IP",
e3480271	82	EXCP, MCGMASK(MCG_STATUS_RIPV\|MCG_STATUS_EIPV, 0)
901d7691	83	),
a17957cd	84	MCESEV(
901d7691	85	PANIC, "In kernel and no restart IP",
e3480271 CY	86	EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0)
e3480271 CY	87	),
b2f9d678 TL	88	MCESEV(
	89	PANIC, "In kernel and no restart IP",
	90	EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0)
	91	),
e3480271 CY	92	MCESEV(
	93	DEFERRED, "Deferred error",
	94	NOSER, MASK(MCI_STATUS_UC\|MCI_STATUS_DEFERRED\|MCI_STATUS_POISON, MCI_STATUS_DEFERRED)
901d7691	95	),
a17957cd	96	MCESEV(
901d7691	97	KEEP, "Corrected error",
a17957cd	98	NOSER, BITCLR(MCI_STATUS_UC)
901d7691	99	),
ed7290d0	100
e085ac7a XX	101	/*
	102	* known AO MCACODs reported via MCE or CMC:
	103	*
	104	* SRAO could be signaled either via a machine check exception or
	105	* CMCI with the corresponding bit S 1 or 0. So we don't need to
	106	* check bit S for SRAO.
	107	*/
	108	MCESEV(
	109	AO, "Action optional: memory scrubbing error",
	110	SER, MASK(MCI_STATUS_OVER\|MCI_UC_AR\|MCACOD_SCRUBMSK, MCI_STATUS_UC\|MCACOD_SCRUB)
	111	),
	112	MCESEV(
	113	AO, "Action optional: last level cache writeback error",
	114	SER, MASK(MCI_STATUS_OVER\|MCI_UC_AR\|MCACOD, MCI_STATUS_UC\|MCACOD_L3WB)
	115	),
	116
ed7290d0	117	/* ignore OVER for UCNA */
a17957cd	118	MCESEV(
e3480271	119	UCNA, "Uncorrected no action required",
a17957cd	120	SER, MASK(MCI_UC_SAR, MCI_STATUS_UC)
901d7691	121	),
a17957cd	122	MCESEV(
901d7691	123	PANIC, "Illegal combination (UCNA with AR=1)",
a17957cd HS	124	SER,
a17957cd HS	125	MASK(MCI_STATUS_OVER\|MCI_UC_SAR, MCI_STATUS_UC\|MCI_STATUS_AR)
901d7691	126	),
a17957cd	127	MCESEV(
901d7691	128	KEEP, "Non signalled machine check",
7639bfc7	129	SER, BITCLR(MCI_STATUS_S)
901d7691	130	),
ed7290d0	131
a17957cd	132	MCESEV(
901d7691	133	PANIC, "Action required with lost events",
7639bfc7	134	SER, BITSET(MCI_STATUS_OVER\|MCI_UC_SAR)
901d7691	135	),
5f7b88d5 TL	136
	137	/* known AR MCACODs: */
	138	#ifdef CONFIG_MEMORY_FAILURE
	139	MCESEV(
33d7885b	140	KEEP, "Action required but unaffected thread is continuable",
1a7f0e3c TL	141	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR, MCI_UC_SAR\|MCI_ADDR),
1a7f0e3c TL	142	MCGMASK(MCG_STATUS_RIPV\|MCG_STATUS_EIPV, MCG_STATUS_RIPV)
5f7b88d5	143	),
b2f9d678 TL	144	MCESEV(
	145	AR, "Action required: data load in error recoverable area of kernel",
	146	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR\|MCACOD, MCI_UC_SAR\|MCI_ADDR\|MCACOD_DATA),
	147	KERNEL_RECOV
	148	),
5f7b88d5	149	MCESEV(
33d7885b	150	AR, "Action required: data load error in a user process",
08dda402	151	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR\|MCACOD, MCI_UC_SAR\|MCI_ADDR\|MCACOD_DATA),
5f7b88d5 TL	152	USER
5f7b88d5 TL	153	),
37c3459b	154	MCESEV(
33d7885b	155	AR, "Action required: instruction fetch error in a user process",
37c3459b TL	156	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR\|MCACOD, MCI_UC_SAR\|MCI_ADDR\|MCACOD_INSTR),
	157	USER
	158	),
c7d606f5 TL	159	MCESEV(
	160	PANIC, "Data load in unrecoverable area of kernel",
	161	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR\|MCACOD, MCI_UC_SAR\|MCI_ADDR\|MCACOD_DATA),
	162	KERNEL
	163	),
41f035a8 TL	164	MCESEV(
	165	PANIC, "Instruction fetch error in kernel",
	166	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR\|MCI_ADDR\|MCACOD, MCI_UC_SAR\|MCI_ADDR\|MCACOD_INSTR),
	167	KERNEL
	168	),
5f7b88d5	169	#endif
a17957cd	170	MCESEV(
7639bfc7	171	PANIC, "Action required: unknown MCACOD",
a17957cd	172	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR, MCI_UC_SAR)
901d7691	173	),
ed7290d0	174
a17957cd	175	MCESEV(
7639bfc7	176	SOME, "Action optional: unknown MCACOD",
a17957cd	177	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR, MCI_UC_S)
901d7691	178	),
a17957cd	179	MCESEV(
901d7691	180	SOME, "Action optional with lost events",
7639bfc7	181	SER, MASK(MCI_STATUS_OVER\|MCI_UC_SAR, MCI_STATUS_OVER\|MCI_UC_S)
901d7691	182	),
a17957cd HS	183
	184	MCESEV(
	185	PANIC, "Overflowed uncorrected",
7639bfc7	186	BITSET(MCI_STATUS_OVER\|MCI_STATUS_UC)
901d7691	187	),
a17957cd HS	188	MCESEV(
	189	UC, "Uncorrected",
	190	BITSET(MCI_STATUS_UC)
901d7691	191	),
a17957cd HS	192	MCESEV(
	193	SOME, "No match",
	194	BITSET(0)
901d7691	195	) /* always matches. keep at end */
817f32d0 AK	196	};
817f32d0 AK	197
b2f9d678 TL	198	#define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV\|MCG_STATUS_EIPV)) == \
	199	(MCG_STATUS_RIPV\|MCG_STATUS_EIPV))
	200
ed7290d0	201	/*
875e2664 TL	202	* If mcgstatus indicated that ip/cs on the stack were
	203	* no good, then "m->cs" will be zero and we will have
	204	* to assume the worst case (IN_KERNEL) as we actually
	205	* have no idea what we were executing when the machine
	206	* check hit.
	207	* If we do have a good "m->cs" (or a faked one in the
	208	* case we were executing in VM86 mode) we can use it to
	209	* distinguish an exception taken in user from from one
	210	* taken in the kernel.
ed7290d0 AK	211	*/
	212	static int error_context(struct mce *m)
	213	{
b2f9d678 TL	214	if ((m->cs & 3) == 3)
	215	return IN_USER;
	216	if (mc_recoverable(m->mcgstatus) && ex_has_fault_handler(m->ip))
	217	return IN_KERNEL_RECOV;
	218	return IN_KERNEL;
ed7290d0 AK	219	}
ed7290d0 AK	220
783ca517	221	static int mce_severity_amd_smca(struct mce *m, enum context err_ctx)
6bda529e AG	222	{
	223	u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
	224	u32 low, high;
	225
	226	/*
	227	* We need to look at the following bits:
	228	* - "succor" bit (data poisoning support), and
	229	* - TCC bit (Task Context Corrupt)
	230	* in MCi_STATUS to determine error severity.
	231	*/
	232	if (!mce_flags.succor)
	233	return MCE_PANIC_SEVERITY;
	234
	235	if (rdmsr_safe(addr, &low, &high))
	236	return MCE_PANIC_SEVERITY;
	237
	238	/* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */
	239	if ((low & MCI_CONFIG_MCAX) &&
	240	(m->status & MCI_STATUS_TCC) &&
	241	(err_ctx == IN_KERNEL))
	242	return MCE_PANIC_SEVERITY;
	243
	244	/* ...otherwise invoke hwpoison handler. */
	245	return MCE_AR_SEVERITY;
	246	}
	247
bf80bbd7 AG	248	/*
	249	* See AMD Error Scope Hierarchy table in a newer BKDG. For example
	250	* 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"
	251	*/
43eaa2a1	252	static int mce_severity_amd(struct mce m, int tolerant, char *msg, bool is_excp)
bf80bbd7	253	{
43eaa2a1 AG	254	enum context ctx = error_context(m);
43eaa2a1 AG	255
bf80bbd7 AG	256	/* Processor Context Corrupt, no need to fumble too much, die! */
	257	if (m->status & MCI_STATUS_PCC)
	258	return MCE_PANIC_SEVERITY;
	259
	260	if (m->status & MCI_STATUS_UC) {
	261
d65dfc81 YG	262	if (ctx == IN_KERNEL)
	263	return MCE_PANIC_SEVERITY;
	264
bf80bbd7 AG	265	/*
	266	* On older systems where overflow_recov flag is not present, we
	267	* should simply panic if an error overflow occurs. If
	268	* overflow_recov flag is present and set, then software can try
	269	* to at least kill process to prolong system operation.
	270	*/
	271	if (mce_flags.overflow_recov) {
6bda529e AG	272	if (mce_flags.smca)
	273	return mce_severity_amd_smca(m, ctx);
	274
cee8f5a6 AG	275	/* kill current process */
cee8f5a6 AG	276	return MCE_AR_SEVERITY;
bf80bbd7 AG	277	} else {
	278	/* at least one error was not logged */
	279	if (m->status & MCI_STATUS_OVER)
	280	return MCE_PANIC_SEVERITY;
	281	}
	282
	283	/*
	284	* For any other case, return MCE_UC_SEVERITY so that we log the
	285	* error and exit #MC handler.
	286	*/
	287	return MCE_UC_SEVERITY;
	288	}
	289
	290	/*
	291	* deferred error: poll handler catches these and adds to mce_ring so
	292	* memory-failure can take recovery actions.
	293	*/
	294	if (m->status & MCI_STATUS_DEFERRED)
	295	return MCE_DEFERRED_SEVERITY;
	296
	297	/*
	298	* corrected error: poll handler catches these and passes responsibility
	299	* of decoding the error to EDAC
	300	*/
	301	return MCE_KEEP_SEVERITY;
	302	}
	303
43eaa2a1	304	static int mce_severity_intel(struct mce m, int tolerant, char *msg, bool is_excp)
817f32d0	305	{
e3480271	306	enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP);
7639bfc7	307	enum context ctx = error_context(m);
817f32d0	308	struct severity *s;
ed7290d0	309
817f32d0	310	for (s = severities;; s++) {
7639bfc7	311	if ((m->status & s->mask) != s->result)
817f32d0	312	continue;
7639bfc7	313	if ((m->mcgstatus & s->mcgmask) != s->mcgres)
817f32d0	314	continue;
1462594b	315	if (s->ser == SER_REQUIRED && !mca_cfg.ser)
ed7290d0	316	continue;
1462594b	317	if (s->ser == NO_SER && mca_cfg.ser)
ed7290d0 AK	318	continue;
	319	if (s->context && ctx != s->context)
	320	continue;
e3480271 CY	321	if (s->excp && excp != s->excp)
e3480271 CY	322	continue;
817f32d0 AK	323	if (msg)
817f32d0 AK	324	*msg = s->msg;
4611a6fa	325	s->covered = 1;
ed7290d0	326	if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) {
f5e886ef	327	if (tolerant < 1)
ed7290d0 AK	328	return MCE_PANIC_SEVERITY;
ed7290d0 AK	329	}
817f32d0 AK	330	return s->sev;
	331	}
	332	}
4611a6fa	333
43eaa2a1 AG	334	/* Default to mce_severity_intel */
	335	int (mce_severity)(struct mce m, int tolerant, char **msg, bool is_excp) =
	336	mce_severity_intel;
	337
	338	void __init mcheck_vendor_init_severity(void)
	339	{
ac78bd72 PW	340	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD \|\|
ac78bd72 PW	341	boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
43eaa2a1 AG	342	mce_severity = mce_severity_amd;
	343	}
	344
e34e77ce	345	#ifdef CONFIG_DEBUG_FS
4611a6fa HY	346	static void s_start(struct seq_file f, loff_t *pos)
	347	{
	348	if (*pos >= ARRAY_SIZE(severities))
	349	return NULL;
	350	return &severities[*pos];
	351	}
	352
	353	static void s_next(struct seq_file f, void data, loff_t pos)
	354	{
	355	if (++(*pos) >= ARRAY_SIZE(severities))
	356	return NULL;
	357	return &severities[*pos];
	358	}
	359
	360	static void s_stop(struct seq_file f, void data)
	361	{
	362	}
	363
	364	static int s_show(struct seq_file f, void data)
	365	{
	366	struct severity *ser = data;
	367	seq_printf(f, "%d\t%s\n", ser->covered, ser->msg);
	368	return 0;
	369	}
	370
	371	static const struct seq_operations severities_seq_ops = {
	372	.start = s_start,
	373	.next = s_next,
	374	.stop = s_stop,
	375	.show = s_show,
	376	};
	377
	378	static int severities_coverage_open(struct inode inode, struct file file)
	379	{
	380	return seq_open(file, &severities_seq_ops);
	381	}
	382
	383	static ssize_t severities_coverage_write(struct file *file,
	384	const char __user *ubuf,
	385	size_t count, loff_t *ppos)
	386	{
	387	int i;
	388	for (i = 0; i < ARRAY_SIZE(severities); i++)
	389	severities[i].covered = 0;
	390	return count;
	391	}
	392
	393	static const struct file_operations severities_coverage_fops = {
	394	.open = severities_coverage_open,
	395	.release = seq_release,
	396	.read = seq_read,
	397	.write = severities_coverage_write,
6038f373	398	.llseek = seq_lseek,
4611a6fa HY	399	};
	400
	401	static int __init severities_debugfs_init(void)
	402	{
7639bfc7	403	struct dentry dmce, fsev;
4611a6fa	404
5be9ed25	405	dmce = mce_get_debugfs_dir();
7639bfc7	406	if (!dmce)
4611a6fa	407	goto err_out;
7639bfc7 HS	408
	409	fsev = debugfs_create_file("severities-coverage", 0444, dmce, NULL,
	410	&severities_coverage_fops);
	411	if (!fsev)
4611a6fa HY	412	goto err_out;
	413
	414	return 0;
	415
	416	err_out:
4611a6fa HY	417	return -ENOMEM;
	418	}
	419	late_initcall(severities_debugfs_init);
7639bfc7	420	#endif /* CONFIG_DEBUG_FS */