[thirdparty/linux.git] / arch / xtensa / kernel / setup.c

/*
 * arch/xtensa/kernel/setup.c
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1995  Linus Torvalds
 * Copyright (C) 2001 - 2005  Tensilica Inc.
 * Copyright (C) 2014 - 2016  Cadence Design Systems Inc.
 *
 * Chris Zankel	<chris@zankel.net>
 * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
 * Kevin Chea
 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
 */

#include <linux/errno.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/screen_info.h>
#include <linux/kernel.h>
#include <linux/percpu.h>
#include <linux/cpu.h>
#include <linux/of.h>
#include <linux/of_fdt.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
# include <linux/console.h>
#endif

#ifdef CONFIG_PROC_FS
# include <linux/seq_file.h>
#endif

#include <asm/bootparam.h>
#include <asm/kasan.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/timex.h>
#include <asm/platform.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/param.h>
#include <asm/smp.h>
#include <asm/sysmem.h>

#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
struct screen_info screen_info = {
	.orig_x = 0,
	.orig_y = 24,
	.orig_video_cols = 80,
	.orig_video_lines = 24,
	.orig_video_isVGA = 1,
	.orig_video_points = 16,
};
#endif

#ifdef CONFIG_BLK_DEV_INITRD
extern unsigned long initrd_start;
extern unsigned long initrd_end;
int initrd_is_mapped = 0;
extern int initrd_below_start_ok;
#endif

#ifdef CONFIG_OF
void *dtb_start = __dtb_start;
#endif

extern unsigned long loops_per_jiffy;

/* Command line specified as configuration option. */

static char __initdata command_line[COMMAND_LINE_SIZE];

#ifdef CONFIG_CMDLINE_BOOL
static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
#endif

#ifdef CONFIG_PARSE_BOOTPARAM
/*
 * Boot parameter parsing.
 *
 * The Xtensa port uses a list of variable-sized tags to pass data to
 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
 * to be recognised. The list is terminated with a zero-sized
 * BP_TAG_LAST tag.
 */

typedef struct tagtable {
	u32 tag;
	int (*parse)(const bp_tag_t*);
} tagtable_t;

#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
	__attribute__((used, section(".taglist"))) = { tag, fn }

/* parse current tag */

static int __init parse_tag_mem(const bp_tag_t *tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
		return -1;

	return memblock_add(mi->start, mi->end - mi->start);
}

__tagtable(BP_TAG_MEMORY, parse_tag_mem);

#ifdef CONFIG_BLK_DEV_INITRD

static int __init parse_tag_initrd(const bp_tag_t* tag)
{
	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);

	initrd_start = (unsigned long)__va(mi->start);
	initrd_end = (unsigned long)__va(mi->end);

	return 0;
}

__tagtable(BP_TAG_INITRD, parse_tag_initrd);

#endif /* CONFIG_BLK_DEV_INITRD */

#ifdef CONFIG_OF

static int __init parse_tag_fdt(const bp_tag_t *tag)
{
	dtb_start = __va(tag->data[0]);
	return 0;
}

__tagtable(BP_TAG_FDT, parse_tag_fdt);

#endif /* CONFIG_OF */

static int __init parse_tag_cmdline(const bp_tag_t* tag)
{
	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
	return 0;
}

__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);

static int __init parse_bootparam(const bp_tag_t* tag)
{
	extern tagtable_t __tagtable_begin, __tagtable_end;
	tagtable_t *t;

	/* Boot parameters must start with a BP_TAG_FIRST tag. */

	if (tag->id != BP_TAG_FIRST) {
		pr_warn("Invalid boot parameters!\n");
		return 0;
	}

	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);

	/* Parse all tags. */

	while (tag != NULL && tag->id != BP_TAG_LAST) {
		for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
			if (tag->id == t->tag) {
				t->parse(tag);
				break;
			}
		}
		if (t == &__tagtable_end)
			pr_warn("Ignoring tag 0x%08x\n", tag->id);
		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	}

	return 0;
}
#else
static int __init parse_bootparam(const bp_tag_t *tag)
{
	pr_info("Ignoring boot parameters at %p\n", tag);
	return 0;
}
#endif

#ifdef CONFIG_OF

#if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
EXPORT_SYMBOL(xtensa_kio_paddr);

static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	const __be32 *ranges;
	int len;

	if (depth > 1)
		return 0;

	if (!of_flat_dt_is_compatible(node, "simple-bus"))
		return 0;

	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	if (!ranges)
		return 1;
	if (len == 0)
		return 1;

	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	/* round down to nearest 256MB boundary */
	xtensa_kio_paddr &= 0xf0000000;

	init_kio();

	return 1;
}
#else
static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
		int depth, void *data)
{
	return 1;
}
#endif

void __init early_init_devtree(void *params)
{
	early_init_dt_scan(params);
	of_scan_flat_dt(xtensa_dt_io_area, NULL);

	if (!command_line[0])
		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
}

#endif /* CONFIG_OF */

/*
 * Initialize architecture. (Early stage)
 */

void __init init_arch(bp_tag_t *bp_start)
{
	/* Initialize MMU. */

	init_mmu();

	/* Initialize initial KASAN shadow map */

	kasan_early_init();

	/* Parse boot parameters */

	if (bp_start)
		parse_bootparam(bp_start);

#ifdef CONFIG_OF
	early_init_devtree(dtb_start);
#endif

#ifdef CONFIG_CMDLINE_BOOL
	if (!command_line[0])
		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
#endif

	/* Early hook for platforms */

	platform_init(bp_start);
}

/*
 * Initialize system. Setup memory and reserve regions.
 */

extern char _end[];
extern char _stext[];
extern char _WindowVectors_text_start;
extern char _WindowVectors_text_end;
extern char _DebugInterruptVector_text_start;
extern char _DebugInterruptVector_text_end;
extern char _KernelExceptionVector_text_start;
extern char _KernelExceptionVector_text_end;
extern char _UserExceptionVector_text_start;
extern char _UserExceptionVector_text_end;
extern char _DoubleExceptionVector_text_start;
extern char _DoubleExceptionVector_text_end;
#if XCHAL_EXCM_LEVEL >= 2
extern char _Level2InterruptVector_text_start;
extern char _Level2InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 3
extern char _Level3InterruptVector_text_start;
extern char _Level3InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 4
extern char _Level4InterruptVector_text_start;
extern char _Level4InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 5
extern char _Level5InterruptVector_text_start;
extern char _Level5InterruptVector_text_end;
#endif
#if XCHAL_EXCM_LEVEL >= 6
extern char _Level6InterruptVector_text_start;
extern char _Level6InterruptVector_text_end;
#endif
#ifdef CONFIG_SMP
extern char _SecondaryResetVector_text_start;
extern char _SecondaryResetVector_text_end;
#endif

static inline int __init_memblock mem_reserve(unsigned long start,
					      unsigned long end)
{
	return memblock_reserve(start, end - start);
}

void __init setup_arch(char **cmdline_p)
{
	pr_info("config ID: %08x:%08x\n",
		xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
	if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
	    xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
		pr_info("built for config ID: %08x:%08x\n",
			XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);

	*cmdline_p = command_line;
	platform_setup(cmdline_p);
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);

	/* Reserve some memory regions */

#ifdef CONFIG_BLK_DEV_INITRD
	if (initrd_start < initrd_end) {
		initrd_is_mapped = mem_reserve(__pa(initrd_start),
					       __pa(initrd_end)) == 0;
		initrd_below_start_ok = 1;
	} else {
		initrd_start = 0;
	}
#endif

	mem_reserve(__pa(_stext), __pa(_end));

#ifdef CONFIG_VECTORS_OFFSET
	mem_reserve(__pa(&_WindowVectors_text_start),
		    __pa(&_WindowVectors_text_end));

	mem_reserve(__pa(&_DebugInterruptVector_text_start),
		    __pa(&_DebugInterruptVector_text_end));

	mem_reserve(__pa(&_KernelExceptionVector_text_start),
		    __pa(&_KernelExceptionVector_text_end));

	mem_reserve(__pa(&_UserExceptionVector_text_start),
		    __pa(&_UserExceptionVector_text_end));

	mem_reserve(__pa(&_DoubleExceptionVector_text_start),
		    __pa(&_DoubleExceptionVector_text_end));

#if XCHAL_EXCM_LEVEL >= 2
	mem_reserve(__pa(&_Level2InterruptVector_text_start),
		    __pa(&_Level2InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 3
	mem_reserve(__pa(&_Level3InterruptVector_text_start),
		    __pa(&_Level3InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 4
	mem_reserve(__pa(&_Level4InterruptVector_text_start),
		    __pa(&_Level4InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 5
	mem_reserve(__pa(&_Level5InterruptVector_text_start),
		    __pa(&_Level5InterruptVector_text_end));
#endif
#if XCHAL_EXCM_LEVEL >= 6
	mem_reserve(__pa(&_Level6InterruptVector_text_start),
		    __pa(&_Level6InterruptVector_text_end));
#endif

#endif /* CONFIG_VECTORS_OFFSET */

#ifdef CONFIG_SMP
	mem_reserve(__pa(&_SecondaryResetVector_text_start),
		    __pa(&_SecondaryResetVector_text_end));
#endif
	parse_early_param();
	bootmem_init();
	kasan_init();
	unflatten_and_copy_device_tree();

#ifdef CONFIG_SMP
	smp_init_cpus();
#endif

	paging_init();
	zones_init();

#ifdef CONFIG_VT
# if defined(CONFIG_VGA_CONSOLE)
	conswitchp = &vga_con;
# elif defined(CONFIG_DUMMY_CONSOLE)
	conswitchp = &dummy_con;
# endif
#endif
}

static DEFINE_PER_CPU(struct cpu, cpu_data);

static int __init topology_init(void)
{
	int i;

	for_each_possible_cpu(i) {
		struct cpu *cpu = &per_cpu(cpu_data, i);
		cpu->hotpluggable = !!i;
		register_cpu(cpu, i);
	}

	return 0;
}
subsys_initcall(topology_init);

void cpu_reset(void)
{
#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
	local_irq_disable();
	/*
	 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
	 * be flushed.
	 * Way 4 is not currently used by linux.
	 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
	 * Way 5 shall be flushed and way 6 shall be set to identity mapping
	 * on MMUv3.
	 */
	local_flush_tlb_all();
	invalidate_page_directory();
#if XCHAL_HAVE_SPANNING_WAY
	/* MMU v3 */
	{
		unsigned long vaddr = (unsigned long)cpu_reset;
		unsigned long paddr = __pa(vaddr);
		unsigned long tmpaddr = vaddr + SZ_512M;
		unsigned long tmp0, tmp1, tmp2, tmp3;

		/*
		 * Find a place for the temporary mapping. It must not be
		 * in the same 512MB region with vaddr or paddr, otherwise
		 * there may be multihit exception either on entry to the
		 * temporary mapping, or on entry to the identity mapping.
		 * (512MB is the biggest page size supported by TLB.)
		 */
		while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
			tmpaddr += SZ_512M;

		/* Invalidate mapping in the selected temporary area */
		if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
			invalidate_itlb_entry(itlb_probe(tmpaddr));
		if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
			invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));

		/*
		 * Map two consecutive pages starting at the physical address
		 * of this function to the temporary mapping area.
		 */
		write_itlb_entry(__pte((paddr & PAGE_MASK) |
				       _PAGE_HW_VALID |
				       _PAGE_HW_EXEC |
				       _PAGE_CA_BYPASS),
				 tmpaddr & PAGE_MASK);
		write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
				       _PAGE_HW_VALID |
				       _PAGE_HW_EXEC |
				       _PAGE_CA_BYPASS),
				 (tmpaddr & PAGE_MASK) + PAGE_SIZE);

		/* Reinitialize TLB */
		__asm__ __volatile__ ("movi	%0, 1f\n\t"
				      "movi	%3, 2f\n\t"
				      "add	%0, %0, %4\n\t"
				      "add	%3, %3, %5\n\t"
				      "jx	%0\n"
				      /*
				       * No literal, data or stack access
				       * below this point
				       */
				      "1:\n\t"
				      /* Initialize *tlbcfg */
				      "movi	%0, 0\n\t"
				      "wsr	%0, itlbcfg\n\t"
				      "wsr	%0, dtlbcfg\n\t"
				      /* Invalidate TLB way 5 */
				      "movi	%0, 4\n\t"
				      "movi	%1, 5\n"
				      "1:\n\t"
				      "iitlb	%1\n\t"
				      "idtlb	%1\n\t"
				      "add	%1, %1, %6\n\t"
				      "addi	%0, %0, -1\n\t"
				      "bnez	%0, 1b\n\t"
				      /* Initialize TLB way 6 */
				      "movi	%0, 7\n\t"
				      "addi	%1, %9, 3\n\t"
				      "addi	%2, %9, 6\n"
				      "1:\n\t"
				      "witlb	%1, %2\n\t"
				      "wdtlb	%1, %2\n\t"
				      "add	%1, %1, %7\n\t"
				      "add	%2, %2, %7\n\t"
				      "addi	%0, %0, -1\n\t"
				      "bnez	%0, 1b\n\t"
				      "isync\n\t"
				      /* Jump to identity mapping */
				      "jx	%3\n"
				      "2:\n\t"
				      /* Complete way 6 initialization */
				      "witlb	%1, %2\n\t"
				      "wdtlb	%1, %2\n\t"
				      /* Invalidate temporary mapping */
				      "sub	%0, %9, %7\n\t"
				      "iitlb	%0\n\t"
				      "add	%0, %0, %8\n\t"
				      "iitlb	%0"
				      : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
					"=&a"(tmp3)
				      : "a"(tmpaddr - vaddr),
					"a"(paddr - vaddr),
					"a"(SZ_128M), "a"(SZ_512M),
					"a"(PAGE_SIZE),
					"a"((tmpaddr + SZ_512M) & PAGE_MASK)
				      : "memory");
	}
#endif
#endif
	__asm__ __volatile__ ("movi	a2, 0\n\t"
			      "wsr	a2, icountlevel\n\t"
			      "movi	a2, 0\n\t"
			      "wsr	a2, icount\n\t"
#if XCHAL_NUM_IBREAK > 0
			      "wsr	a2, ibreakenable\n\t"
#endif
#if XCHAL_HAVE_LOOPS
			      "wsr	a2, lcount\n\t"
#endif
			      "movi	a2, 0x1f\n\t"
			      "wsr	a2, ps\n\t"
			      "isync\n\t"
			      "jx	%0\n\t"
			      :
			      : "a" (XCHAL_RESET_VECTOR_VADDR)
			      : "a2");
	for (;;)
		;
}

void machine_restart(char * cmd)
{
	platform_restart();
}

void machine_halt(void)
{
	platform_halt();
	while (1);
}

void machine_power_off(void)
{
	platform_power_off();
	while (1);
}
#ifdef CONFIG_PROC_FS

/*
 * Display some core information through /proc/cpuinfo.
 */

static int
c_show(struct seq_file *f, void *slot)
{
	/* high-level stuff */
	seq_printf(f, "CPU count\t: %u\n"
		      "CPU list\t: %*pbl\n"
		      "vendor_id\t: Tensilica\n"
		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
		      "core ID\t\t: " XCHAL_CORE_ID "\n"
		      "build ID\t: 0x%x\n"
		      "config ID\t: %08x:%08x\n"
		      "byte order\t: %s\n"
		      "cpu MHz\t\t: %lu.%02lu\n"
		      "bogomips\t: %lu.%02lu\n",
		      num_online_cpus(),
		      cpumask_pr_args(cpu_online_mask),
		      XCHAL_BUILD_UNIQUE_ID,
		      xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
		      XCHAL_HAVE_BE ?  "big" : "little",
		      ccount_freq/1000000,
		      (ccount_freq/10000) % 100,
		      loops_per_jiffy/(500000/HZ),
		      (loops_per_jiffy/(5000/HZ)) % 100);
	seq_puts(f, "flags\t\t: "
#if XCHAL_HAVE_NMI
		     "nmi "
#endif
#if XCHAL_HAVE_DEBUG
		     "debug "
# if XCHAL_HAVE_OCD
		     "ocd "
# endif
#endif
#if XCHAL_HAVE_DENSITY
	    	     "density "
#endif
#if XCHAL_HAVE_BOOLEANS
		     "boolean "
#endif
#if XCHAL_HAVE_LOOPS
		     "loop "
#endif
#if XCHAL_HAVE_NSA
		     "nsa "
#endif
#if XCHAL_HAVE_MINMAX
		     "minmax "
#endif
#if XCHAL_HAVE_SEXT
		     "sext "
#endif
#if XCHAL_HAVE_CLAMPS
		     "clamps "
#endif
#if XCHAL_HAVE_MAC16
		     "mac16 "
#endif
#if XCHAL_HAVE_MUL16
		     "mul16 "
#endif
#if XCHAL_HAVE_MUL32
		     "mul32 "
#endif
#if XCHAL_HAVE_MUL32_HIGH
		     "mul32h "
#endif
#if XCHAL_HAVE_FP
		     "fpu "
#endif
#if XCHAL_HAVE_S32C1I
		     "s32c1i "
#endif
#if XCHAL_HAVE_EXCLUSIVE
		     "exclusive "
#endif
		     "\n");

	/* Registers. */
	seq_printf(f,"physical aregs\t: %d\n"
		     "misc regs\t: %d\n"
		     "ibreak\t\t: %d\n"
		     "dbreak\t\t: %d\n",
		     XCHAL_NUM_AREGS,
		     XCHAL_NUM_MISC_REGS,
		     XCHAL_NUM_IBREAK,
		     XCHAL_NUM_DBREAK);


	/* Interrupt. */
	seq_printf(f,"num ints\t: %d\n"
		     "ext ints\t: %d\n"
		     "int levels\t: %d\n"
		     "timers\t\t: %d\n"
		     "debug level\t: %d\n",
		     XCHAL_NUM_INTERRUPTS,
		     XCHAL_NUM_EXTINTERRUPTS,
		     XCHAL_NUM_INTLEVELS,
		     XCHAL_NUM_TIMERS,
		     XCHAL_DEBUGLEVEL);

	/* Cache */
	seq_printf(f,"icache line size: %d\n"
		     "icache ways\t: %d\n"
		     "icache size\t: %d\n"
		     "icache flags\t: "
#if XCHAL_ICACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n"
		     "dcache line size: %d\n"
		     "dcache ways\t: %d\n"
		     "dcache size\t: %d\n"
		     "dcache flags\t: "
#if XCHAL_DCACHE_IS_WRITEBACK
		     "writeback "
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
		     "lock "
#endif
		     "\n",
		     XCHAL_ICACHE_LINESIZE,
		     XCHAL_ICACHE_WAYS,
		     XCHAL_ICACHE_SIZE,
		     XCHAL_DCACHE_LINESIZE,
		     XCHAL_DCACHE_WAYS,
		     XCHAL_DCACHE_SIZE);

	return 0;
}

/*
 * We show only CPU #0 info.
 */
static void *
c_start(struct seq_file *f, loff_t *pos)
{
	return (*pos == 0) ? (void *)1 : NULL;
}

static void *
c_next(struct seq_file *f, void *v, loff_t *pos)
{
	return NULL;
}

static void
c_stop(struct seq_file *f, void *v)
{
}

const struct seq_operations cpuinfo_op =
{
	.start	= c_start,
	.next	= c_next,
	.stop	= c_stop,
	.show	= c_show,
};

#endif /* CONFIG_PROC_FS */
Commit	Line	Data
5a0015d6	1	/*
f30c2269	2	* arch/xtensa/kernel/setup.c
5a0015d6 CZ	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 1995 Linus Torvalds
	9	* Copyright (C) 2001 - 2005 Tensilica Inc.
0e46c111	10	* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
5a0015d6 CZ	11	*
	12	* Chris Zankel <chris@zankel.net>
	13	* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
	14	* Kevin Chea
	15	* Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
	16	*/
	17
5a0015d6 CZ	18	#include <linux/errno.h>
5a0015d6 CZ	19	#include <linux/init.h>
27ac792c	20	#include <linux/mm.h>
5a0015d6	21	#include <linux/proc_fs.h>
894673ee	22	#include <linux/screen_info.h>
5a0015d6	23	#include <linux/kernel.h>
f615136c MF	24	#include <linux/percpu.h>
f615136c MF	25	#include <linux/cpu.h>
d02014b2	26	#include <linux/of.h>
da844a81	27	#include <linux/of_fdt.h>
da844a81	28
5a0015d6 CZ	29	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
	30	# include <linux/console.h>
	31	#endif
	32
5a0015d6 CZ	33	#ifdef CONFIG_PROC_FS
	34	# include <linux/seq_file.h>
	35	#endif
	36
5a0015d6	37	#include <asm/bootparam.h>
c633544a	38	#include <asm/kasan.h>
c8f3a7dc	39	#include <asm/mmu_context.h>
5a0015d6 CZ	40	#include <asm/pgtable.h>
	41	#include <asm/processor.h>
	42	#include <asm/timex.h>
	43	#include <asm/platform.h>
	44	#include <asm/page.h>
	45	#include <asm/setup.h>
de4f6e5b	46	#include <asm/param.h>
f615136c	47	#include <asm/smp.h>
9ba067f9	48	#include <asm/sysmem.h>
5a0015d6	49
5a0015d6	50	#if defined(CONFIG_VGA_CONSOLE) \|\| defined(CONFIG_DUMMY_CONSOLE)
03eae3ac MF	51	struct screen_info screen_info = {
	52	.orig_x = 0,
	53	.orig_y = 24,
	54	.orig_video_cols = 80,
	55	.orig_video_lines = 24,
	56	.orig_video_isVGA = 1,
	57	.orig_video_points = 16,
	58	};
5a0015d6 CZ	59	#endif
5a0015d6 CZ	60
5a0015d6	61	#ifdef CONFIG_BLK_DEV_INITRD
29eb45a9 RH	62	extern unsigned long initrd_start;
29eb45a9 RH	63	extern unsigned long initrd_end;
5a0015d6 CZ	64	int initrd_is_mapped = 0;
	65	extern int initrd_below_start_ok;
	66	#endif
	67
da844a81	68	#ifdef CONFIG_OF
da844a81 MF	69	void *dtb_start = __dtb_start;
	70	#endif
	71
5a0015d6 CZ	72	extern unsigned long loops_per_jiffy;
	73
	74	/* Command line specified as configuration option. */
	75
d3e9ccea	76	static char __initdata command_line[COMMAND_LINE_SIZE];
5a0015d6 CZ	77
	78	#ifdef CONFIG_CMDLINE_BOOL
	79	static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
	80	#endif
	81
baac1d36	82	#ifdef CONFIG_PARSE_BOOTPARAM
5a0015d6 CZ	83	/*
	84	* Boot parameter parsing.
	85	*
	86	* The Xtensa port uses a list of variable-sized tags to pass data to
	87	* the kernel. The first tag must be a BP_TAG_FIRST tag for the list
	88	* to be recognised. The list is terminated with a zero-sized
	89	* BP_TAG_LAST tag.
	90	*/
	91
	92	typedef struct tagtable {
	93	u32 tag;
	94	int (parse)(const bp_tag_t);
	95	} tagtable_t;
	96
	97	#define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \
f4349b6e	98	__attribute__((used, section(".taglist"))) = { tag, fn }
5a0015d6 CZ	99
	100	/* parse current tag */
	101
da844a81 MF	102	static int __init parse_tag_mem(const bp_tag_t *tag)
da844a81 MF	103	{
9ba067f9	104	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
da844a81 MF	105
	106	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
	107	return -1;
	108
0e46c111	109	return memblock_add(mi->start, mi->end - mi->start);
da844a81 MF	110	}
da844a81 MF	111
5a0015d6 CZ	112	__tagtable(BP_TAG_MEMORY, parse_tag_mem);
	113
	114	#ifdef CONFIG_BLK_DEV_INITRD
	115
	116	static int __init parse_tag_initrd(const bp_tag_t* tag)
	117	{
9ba067f9 MF	118	struct bp_meminfo mi = (struct bp_meminfo )(tag->data);
9ba067f9 MF	119
29eb45a9 RH	120	initrd_start = (unsigned long)__va(mi->start);
29eb45a9 RH	121	initrd_end = (unsigned long)__va(mi->end);
5a0015d6 CZ	122
	123	return 0;
	124	}
	125
	126	__tagtable(BP_TAG_INITRD, parse_tag_initrd);
	127
4ab18701 MF	128	#endif /* CONFIG_BLK_DEV_INITRD */
4ab18701 MF	129
da844a81 MF	130	#ifdef CONFIG_OF
	131
	132	static int __init parse_tag_fdt(const bp_tag_t *tag)
	133	{
c5a771d0	134	dtb_start = __va(tag->data[0]);
da844a81 MF	135	return 0;
	136	}
	137
	138	__tagtable(BP_TAG_FDT, parse_tag_fdt);
	139
da844a81 MF	140	#endif /* CONFIG_OF */
da844a81 MF	141
5a0015d6 CZ	142	static int __init parse_tag_cmdline(const bp_tag_t* tag)
5a0015d6 CZ	143	{
da844a81	144	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
5a0015d6 CZ	145	return 0;
	146	}
	147
	148	__tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
	149
	150	static int __init parse_bootparam(const bp_tag_t* tag)
	151	{
	152	extern tagtable_t __tagtable_begin, __tagtable_end;
	153	tagtable_t *t;
	154
	155	/* Boot parameters must start with a BP_TAG_FIRST tag. */
	156
	157	if (tag->id != BP_TAG_FIRST) {
c130d3be	158	pr_warn("Invalid boot parameters!\n");
5a0015d6 CZ	159	return 0;
	160	}
	161
	162	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
	163
	164	/* Parse all tags. */
	165
	166	while (tag != NULL && tag->id != BP_TAG_LAST) {
c130d3be	167	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
5a0015d6 CZ	168	if (tag->id == t->tag) {
	169	t->parse(tag);
	170	break;
	171	}
	172	}
	173	if (t == &__tagtable_end)
c130d3be	174	pr_warn("Ignoring tag 0x%08x\n", tag->id);
5a0015d6 CZ	175	tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
	176	}
	177
	178	return 0;
	179	}
baac1d36 MF	180	#else
	181	static int __init parse_bootparam(const bp_tag_t *tag)
	182	{
	183	pr_info("Ignoring boot parameters at %p\n", tag);
	184	return 0;
	185	}
	186	#endif
5a0015d6	187
da844a81 MF	188	#ifdef CONFIG_OF
da844a81 MF	189
260c64bb	190	#if !XCHAL_HAVE_PTP_MMU \|\| XCHAL_HAVE_SPANNING_WAY
6cb97111 BS	191	unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
	192	EXPORT_SYMBOL(xtensa_kio_paddr);
	193
	194	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	195	int depth, void *data)
	196	{
	197	const __be32 *ranges;
9d0c4dfe	198	int len;
6cb97111 BS	199
	200	if (depth > 1)
	201	return 0;
	202
	203	if (!of_flat_dt_is_compatible(node, "simple-bus"))
	204	return 0;
	205
	206	ranges = of_get_flat_dt_prop(node, "ranges", &len);
	207	if (!ranges)
	208	return 1;
	209	if (len == 0)
	210	return 1;
	211
	212	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
	213	/* round down to nearest 256MB boundary */
	214	xtensa_kio_paddr &= 0xf0000000;
	215
c2edb35a MF	216	init_kio();
c2edb35a MF	217
6cb97111 BS	218	return 1;
	219	}
	220	#else
	221	static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
	222	int depth, void *data)
	223	{
	224	return 1;
	225	}
	226	#endif
	227
da844a81 MF	228	void __init early_init_devtree(void *params)
da844a81 MF	229	{
7745fc1f	230	early_init_dt_scan(params);
6cb97111	231	of_scan_flat_dt(xtensa_dt_io_area, NULL);
da844a81	232
7745fc1f RH	233	if (!command_line[0])
7745fc1f RH	234	strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
da844a81 MF	235	}
da844a81 MF	236
da844a81 MF	237	#endif /* CONFIG_OF */
da844a81 MF	238
5a0015d6 CZ	239	/*
	240	* Initialize architecture. (Early stage)
	241	*/
	242
	243	void __init init_arch(bp_tag_t *bp_start)
	244	{
c2edb35a MF	245	/* Initialize MMU. */
	246
	247	init_mmu();
	248
c633544a MF	249	/* Initialize initial KASAN shadow map */
	250
	251	kasan_early_init();
	252
5a0015d6 CZ	253	/* Parse boot parameters */
5a0015d6 CZ	254
c4c4594b	255	if (bp_start)
da844a81 MF	256	parse_bootparam(bp_start);
	257
	258	#ifdef CONFIG_OF
	259	early_init_devtree(dtb_start);
	260	#endif
5a0015d6	261
da844a81 MF	262	#ifdef CONFIG_CMDLINE_BOOL
	263	if (!command_line[0])
	264	strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
	265	#endif
	266
5a0015d6 CZ	267	/* Early hook for platforms */
	268
	269	platform_init(bp_start);
5a0015d6 CZ	270	}
	271
	272	/*
	273	* Initialize system. Setup memory and reserve regions.
	274	*/
	275
18244362 MH	276	extern char _end[];
18244362 MH	277	extern char _stext[];
5a0015d6 CZ	278	extern char _WindowVectors_text_start;
5a0015d6 CZ	279	extern char _WindowVectors_text_end;
f8f02ca7	280	extern char _DebugInterruptVector_text_start;
5a0015d6	281	extern char _DebugInterruptVector_text_end;
f8f02ca7	282	extern char _KernelExceptionVector_text_start;
5a0015d6	283	extern char _KernelExceptionVector_text_end;
f8f02ca7	284	extern char _UserExceptionVector_text_start;
5a0015d6	285	extern char _UserExceptionVector_text_end;
f8f02ca7	286	extern char _DoubleExceptionVector_text_start;
5a0015d6	287	extern char _DoubleExceptionVector_text_end;
2d1c645c MG	288	#if XCHAL_EXCM_LEVEL >= 2
	289	extern char _Level2InterruptVector_text_start;
	290	extern char _Level2InterruptVector_text_end;
	291	#endif
	292	#if XCHAL_EXCM_LEVEL >= 3
	293	extern char _Level3InterruptVector_text_start;
	294	extern char _Level3InterruptVector_text_end;
	295	#endif
	296	#if XCHAL_EXCM_LEVEL >= 4
	297	extern char _Level4InterruptVector_text_start;
	298	extern char _Level4InterruptVector_text_end;
	299	#endif
	300	#if XCHAL_EXCM_LEVEL >= 5
	301	extern char _Level5InterruptVector_text_start;
	302	extern char _Level5InterruptVector_text_end;
	303	#endif
	304	#if XCHAL_EXCM_LEVEL >= 6
	305	extern char _Level6InterruptVector_text_start;
	306	extern char _Level6InterruptVector_text_end;
	307	#endif
ab45fb14 MF	308	#ifdef CONFIG_SMP
	309	extern char _SecondaryResetVector_text_start;
	310	extern char _SecondaryResetVector_text_end;
	311	#endif
5a0015d6	312
adefd051 GR	313	static inline int __init_memblock mem_reserve(unsigned long start,
adefd051 GR	314	unsigned long end)
0e46c111 MF	315	{
	316	return memblock_reserve(start, end - start);
	317	}
00273125	318
5a0015d6 CZ	319	void __init setup_arch(char **cmdline_p)
5a0015d6 CZ	320	{
aa6476f7	321	pr_info("config ID: %08x:%08x\n",
cad6fade MF	322	xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
	323	if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 \|\|
	324	xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
aa6476f7 MF	325	pr_info("built for config ID: %08x:%08x\n",
	326	XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
	327
5a0015d6	328	*cmdline_p = command_line;
fbe22d28 MF	329	platform_setup(cmdline_p);
fbe22d28 MF	330	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
5a0015d6 CZ	331
	332	/* Reserve some memory regions */
	333
	334	#ifdef CONFIG_BLK_DEV_INITRD
	335	if (initrd_start < initrd_end) {
	336	initrd_is_mapped = mem_reserve(__pa(initrd_start),
0e46c111	337	__pa(initrd_end)) == 0;
5a0015d6	338	initrd_below_start_ok = 1;
c4c4594b	339	} else {
5a0015d6 CZ	340	initrd_start = 0;
	341	}
	342	#endif
	343
18244362	344	mem_reserve(__pa(_stext), __pa(_end));
5a0015d6	345
b46dcfa3	346	#ifdef CONFIG_VECTORS_OFFSET
5a0015d6	347	mem_reserve(__pa(&_WindowVectors_text_start),
0e46c111	348	__pa(&_WindowVectors_text_end));
5a0015d6	349
f8f02ca7	350	mem_reserve(__pa(&_DebugInterruptVector_text_start),
0e46c111	351	__pa(&_DebugInterruptVector_text_end));
5a0015d6	352
f8f02ca7	353	mem_reserve(__pa(&_KernelExceptionVector_text_start),
0e46c111	354	__pa(&_KernelExceptionVector_text_end));
5a0015d6	355
f8f02ca7	356	mem_reserve(__pa(&_UserExceptionVector_text_start),
0e46c111	357	__pa(&_UserExceptionVector_text_end));
5a0015d6	358
f8f02ca7	359	mem_reserve(__pa(&_DoubleExceptionVector_text_start),
0e46c111	360	__pa(&_DoubleExceptionVector_text_end));
5a0015d6	361
2d1c645c MG	362	#if XCHAL_EXCM_LEVEL >= 2
2d1c645c MG	363	mem_reserve(__pa(&_Level2InterruptVector_text_start),
0e46c111	364	__pa(&_Level2InterruptVector_text_end));
2d1c645c MG	365	#endif
	366	#if XCHAL_EXCM_LEVEL >= 3
	367	mem_reserve(__pa(&_Level3InterruptVector_text_start),
0e46c111	368	__pa(&_Level3InterruptVector_text_end));
2d1c645c MG	369	#endif
	370	#if XCHAL_EXCM_LEVEL >= 4
	371	mem_reserve(__pa(&_Level4InterruptVector_text_start),
0e46c111	372	__pa(&_Level4InterruptVector_text_end));
2d1c645c MG	373	#endif
	374	#if XCHAL_EXCM_LEVEL >= 5
	375	mem_reserve(__pa(&_Level5InterruptVector_text_start),
0e46c111	376	__pa(&_Level5InterruptVector_text_end));
2d1c645c MG	377	#endif
	378	#if XCHAL_EXCM_LEVEL >= 6
	379	mem_reserve(__pa(&_Level6InterruptVector_text_start),
0e46c111	380	__pa(&_Level6InterruptVector_text_end));
2d1c645c MG	381	#endif
2d1c645c MG	382
b46dcfa3 MF	383	#endif /* CONFIG_VECTORS_OFFSET */
b46dcfa3 MF	384
ab45fb14 MF	385	#ifdef CONFIG_SMP
ab45fb14 MF	386	mem_reserve(__pa(&_SecondaryResetVector_text_start),
0e46c111	387	__pa(&_SecondaryResetVector_text_end));
ab45fb14	388	#endif
06bd2824	389	parse_early_param();
5a0015d6	390	bootmem_init();
c633544a	391	kasan_init();
3104021c	392	unflatten_and_copy_device_tree();
5a0015d6	393
f615136c MF	394	#ifdef CONFIG_SMP
	395	smp_init_cpus();
	396	#endif
	397
5a0015d6	398	paging_init();
e5083a63	399	zones_init();
5a0015d6 CZ	400
	401	#ifdef CONFIG_VT
	402	# if defined(CONFIG_VGA_CONSOLE)
	403	conswitchp = &vga_con;
	404	# elif defined(CONFIG_DUMMY_CONSOLE)
	405	conswitchp = &dummy_con;
	406	# endif
	407	#endif
5a0015d6 CZ	408	}
5a0015d6 CZ	409
f615136c MF	410	static DEFINE_PER_CPU(struct cpu, cpu_data);
	411
	412	static int __init topology_init(void)
	413	{
	414	int i;
	415
	416	for_each_possible_cpu(i) {
	417	struct cpu *cpu = &per_cpu(cpu_data, i);
49b424fe	418	cpu->hotpluggable = !!i;
f615136c MF	419	register_cpu(cpu, i);
	420	}
	421
	422	return 0;
	423	}
	424	subsys_initcall(topology_init);
	425
4f205687 MF	426	void cpu_reset(void)
4f205687 MF	427	{
4b3e6f2e	428	#if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
bf15f86b MF	429	local_irq_disable();
	430	/*
	431	* We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
	432	* be flushed.
	433	* Way 4 is not currently used by linux.
	434	* Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
	435	* Way 5 shall be flushed and way 6 shall be set to identity mapping
	436	* on MMUv3.
	437	*/
	438	local_flush_tlb_all();
	439	invalidate_page_directory();
	440	#if XCHAL_HAVE_SPANNING_WAY
	441	/* MMU v3 */
	442	{
	443	unsigned long vaddr = (unsigned long)cpu_reset;
	444	unsigned long paddr = __pa(vaddr);
	445	unsigned long tmpaddr = vaddr + SZ_512M;
	446	unsigned long tmp0, tmp1, tmp2, tmp3;
	447
	448	/*
	449	* Find a place for the temporary mapping. It must not be
	450	* in the same 512MB region with vaddr or paddr, otherwise
	451	* there may be multihit exception either on entry to the
	452	* temporary mapping, or on entry to the identity mapping.
	453	* (512MB is the biggest page size supported by TLB.)
	454	*/
	455	while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
	456	tmpaddr += SZ_512M;
	457
	458	/* Invalidate mapping in the selected temporary area */
60e22cff	459	if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
bf15f86b	460	invalidate_itlb_entry(itlb_probe(tmpaddr));
60e22cff	461	if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
bf15f86b MF	462	invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
	463
	464	/*
	465	* Map two consecutive pages starting at the physical address
	466	* of this function to the temporary mapping area.
	467	*/
	468	write_itlb_entry(__pte((paddr & PAGE_MASK) \|
	469	_PAGE_HW_VALID \|
	470	_PAGE_HW_EXEC \|
	471	_PAGE_CA_BYPASS),
	472	tmpaddr & PAGE_MASK);
	473	write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) \|
	474	_PAGE_HW_VALID \|
	475	_PAGE_HW_EXEC \|
	476	_PAGE_CA_BYPASS),
	477	(tmpaddr & PAGE_MASK) + PAGE_SIZE);
	478
	479	/* Reinitialize TLB */
	480	__asm__ __volatile__ ("movi %0, 1f\n\t"
	481	"movi %3, 2f\n\t"
	482	"add %0, %0, %4\n\t"
	483	"add %3, %3, %5\n\t"
	484	"jx %0\n"
	485	/*
	486	* No literal, data or stack access
	487	* below this point
	488	*/
	489	"1:\n\t"
	490	/* Initialize tlbcfg /
	491	"movi %0, 0\n\t"
	492	"wsr %0, itlbcfg\n\t"
	493	"wsr %0, dtlbcfg\n\t"
	494	/* Invalidate TLB way 5 */
	495	"movi %0, 4\n\t"
	496	"movi %1, 5\n"
	497	"1:\n\t"
	498	"iitlb %1\n\t"
	499	"idtlb %1\n\t"
	500	"add %1, %1, %6\n\t"
	501	"addi %0, %0, -1\n\t"
	502	"bnez %0, 1b\n\t"
	503	/* Initialize TLB way 6 */
	504	"movi %0, 7\n\t"
	505	"addi %1, %9, 3\n\t"
	506	"addi %2, %9, 6\n"
	507	"1:\n\t"
	508	"witlb %1, %2\n\t"
	509	"wdtlb %1, %2\n\t"
	510	"add %1, %1, %7\n\t"
	511	"add %2, %2, %7\n\t"
	512	"addi %0, %0, -1\n\t"
	513	"bnez %0, 1b\n\t"
cd8869f4	514	"isync\n\t"
bf15f86b MF	515	/* Jump to identity mapping */
	516	"jx %3\n"
	517	"2:\n\t"
	518	/* Complete way 6 initialization */
	519	"witlb %1, %2\n\t"
	520	"wdtlb %1, %2\n\t"
	521	/* Invalidate temporary mapping */
	522	"sub %0, %9, %7\n\t"
	523	"iitlb %0\n\t"
	524	"add %0, %0, %8\n\t"
	525	"iitlb %0"
	526	: "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
	527	"=&a"(tmp3)
	528	: "a"(tmpaddr - vaddr),
	529	"a"(paddr - vaddr),
	530	"a"(SZ_128M), "a"(SZ_512M),
	531	"a"(PAGE_SIZE),
	532	"a"((tmpaddr + SZ_512M) & PAGE_MASK)
	533	: "memory");
	534	}
	535	#endif
	536	#endif
ea951c34	537	__asm__ __volatile__ ("movi a2, 0\n\t"
4f205687 MF	538	"wsr a2, icountlevel\n\t"
	539	"movi a2, 0\n\t"
	540	"wsr a2, icount\n\t"
	541	#if XCHAL_NUM_IBREAK > 0
	542	"wsr a2, ibreakenable\n\t"
	543	#endif
	544	#if XCHAL_HAVE_LOOPS
	545	"wsr a2, lcount\n\t"
	546	#endif
	547	"movi a2, 0x1f\n\t"
	548	"wsr a2, ps\n\t"
	549	"isync\n\t"
	550	"jx %0\n\t"
	551	:
	552	: "a" (XCHAL_RESET_VECTOR_VADDR)
	553	: "a2");
	554	for (;;)
	555	;
	556	}
	557
5a0015d6 CZ	558	void machine_restart(char * cmd)
	559	{
	560	platform_restart();
	561	}
	562
	563	void machine_halt(void)
	564	{
	565	platform_halt();
	566	while (1);
	567	}
	568
	569	void machine_power_off(void)
	570	{
	571	platform_power_off();
	572	while (1);
	573	}
	574	#ifdef CONFIG_PROC_FS
	575
	576	/*
	577	* Display some core information through /proc/cpuinfo.
	578	*/
	579
	580	static int
	581	c_show(struct seq_file f, void slot)
	582	{
	583	/* high-level stuff */
f615136c	584	seq_printf(f, "CPU count\t: %u\n"
62518994	585	"CPU list\t: %*pbl\n"
f615136c MF	586	"vendor_id\t: Tensilica\n"
	587	"model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
	588	"core ID\t\t: " XCHAL_CORE_ID "\n"
	589	"build ID\t: 0x%x\n"
aa6476f7	590	"config ID\t: %08x:%08x\n"
f615136c MF	591	"byte order\t: %s\n"
	592	"cpu MHz\t\t: %lu.%02lu\n"
	593	"bogomips\t: %lu.%02lu\n",
	594	num_online_cpus(),
62518994	595	cpumask_pr_args(cpu_online_mask),
f615136c	596	XCHAL_BUILD_UNIQUE_ID,
cad6fade	597	xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
f615136c MF	598	XCHAL_HAVE_BE ? "big" : "little",
	599	ccount_freq/1000000,
	600	(ccount_freq/10000) % 100,
	601	loops_per_jiffy/(500000/HZ),
	602	(loops_per_jiffy/(5000/HZ)) % 100);
c32537d4	603	seq_puts(f, "flags\t\t: "
5a0015d6 CZ	604	#if XCHAL_HAVE_NMI
	605	"nmi "
	606	#endif
	607	#if XCHAL_HAVE_DEBUG
	608	"debug "
	609	# if XCHAL_HAVE_OCD
	610	"ocd "
	611	# endif
	612	#endif
	613	#if XCHAL_HAVE_DENSITY
	614	"density "
	615	#endif
	616	#if XCHAL_HAVE_BOOLEANS
	617	"boolean "
	618	#endif
	619	#if XCHAL_HAVE_LOOPS
	620	"loop "
	621	#endif
	622	#if XCHAL_HAVE_NSA
	623	"nsa "
	624	#endif
	625	#if XCHAL_HAVE_MINMAX
	626	"minmax "
	627	#endif
	628	#if XCHAL_HAVE_SEXT
	629	"sext "
	630	#endif
	631	#if XCHAL_HAVE_CLAMPS
	632	"clamps "
	633	#endif
	634	#if XCHAL_HAVE_MAC16
	635	"mac16 "
	636	#endif
	637	#if XCHAL_HAVE_MUL16
	638	"mul16 "
	639	#endif
	640	#if XCHAL_HAVE_MUL32
	641	"mul32 "
	642	#endif
	643	#if XCHAL_HAVE_MUL32_HIGH
	644	"mul32h "
	645	#endif
	646	#if XCHAL_HAVE_FP
	647	"fpu "
2f6ea6a7 MF	648	#endif
	649	#if XCHAL_HAVE_S32C1I
	650	"s32c1i "
f7c34874 MF	651	#endif
	652	#if XCHAL_HAVE_EXCLUSIVE
	653	"exclusive "
5a0015d6 CZ	654	#endif
	655	"\n");
	656
	657	/* Registers. */
	658	seq_printf(f,"physical aregs\t: %d\n"
	659	"misc regs\t: %d\n"
	660	"ibreak\t\t: %d\n"
	661	"dbreak\t\t: %d\n",
	662	XCHAL_NUM_AREGS,
	663	XCHAL_NUM_MISC_REGS,
	664	XCHAL_NUM_IBREAK,
	665	XCHAL_NUM_DBREAK);
	666
	667
	668	/* Interrupt. */
	669	seq_printf(f,"num ints\t: %d\n"
	670	"ext ints\t: %d\n"
	671	"int levels\t: %d\n"
	672	"timers\t\t: %d\n"
	673	"debug level\t: %d\n",
	674	XCHAL_NUM_INTERRUPTS,
	675	XCHAL_NUM_EXTINTERRUPTS,
	676	XCHAL_NUM_INTLEVELS,
	677	XCHAL_NUM_TIMERS,
	678	XCHAL_DEBUGLEVEL);
	679
5a0015d6 CZ	680	/* Cache */
	681	seq_printf(f,"icache line size: %d\n"
	682	"icache ways\t: %d\n"
	683	"icache size\t: %d\n"
	684	"icache flags\t: "
	685	#if XCHAL_ICACHE_LINE_LOCKABLE
415217ef	686	"lock "
5a0015d6 CZ	687	#endif
	688	"\n"
	689	"dcache line size: %d\n"
	690	"dcache ways\t: %d\n"
	691	"dcache size\t: %d\n"
	692	"dcache flags\t: "
	693	#if XCHAL_DCACHE_IS_WRITEBACK
415217ef	694	"writeback "
5a0015d6 CZ	695	#endif
5a0015d6 CZ	696	#if XCHAL_DCACHE_LINE_LOCKABLE
415217ef	697	"lock "
5a0015d6 CZ	698	#endif
	699	"\n",
	700	XCHAL_ICACHE_LINESIZE,
	701	XCHAL_ICACHE_WAYS,
	702	XCHAL_ICACHE_SIZE,
	703	XCHAL_DCACHE_LINESIZE,
	704	XCHAL_DCACHE_WAYS,
	705	XCHAL_DCACHE_SIZE);
	706
5a0015d6 CZ	707	return 0;
	708	}
	709
	710	/*
	711	* We show only CPU #0 info.
	712	*/
	713	static void *
	714	c_start(struct seq_file f, loff_t pos)
	715	{
f615136c	716	return (pos == 0) ? (void )1 : NULL;
5a0015d6 CZ	717	}
	718
	719	static void *
	720	c_next(struct seq_file f, void v, loff_t *pos)
	721	{
	722	return NULL;
	723	}
	724
	725	static void
	726	c_stop(struct seq_file f, void v)
	727	{
	728	}
	729
03a44825	730	const struct seq_operations cpuinfo_op =
5a0015d6	731	{
f615136c MF	732	.start = c_start,
	733	.next = c_next,
	734	.stop = c_stop,
	735	.show = c_show,
5a0015d6 CZ	736	};
	737
	738	#endif /* CONFIG_PROC_FS */