[thirdparty/linux.git] / drivers / bus / brcmstb_gisb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-2021 Broadcom
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/panic_notifier.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/pm.h>
#include <linux/kernel.h>
#include <linux/kdebug.h>
#include <linux/notifier.h>

#ifdef CONFIG_MIPS
#include <asm/traps.h>
#endif

#define  ARB_ERR_CAP_CLEAR		(1 << 0)
#define  ARB_ERR_CAP_STATUS_TIMEOUT	(1 << 12)
#define  ARB_ERR_CAP_STATUS_TEA		(1 << 11)
#define  ARB_ERR_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_ERR_CAP_STATUS_VALID	(1 << 0)

#define  ARB_BP_CAP_CLEAR		(1 << 0)
#define  ARB_BP_CAP_STATUS_PROT_SHIFT	14
#define  ARB_BP_CAP_STATUS_TYPE		(1 << 13)
#define  ARB_BP_CAP_STATUS_RSP_SHIFT	10
#define  ARB_BP_CAP_STATUS_MASK		GENMASK(1, 0)
#define  ARB_BP_CAP_STATUS_BS_SHIFT	2
#define  ARB_BP_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_BP_CAP_STATUS_VALID	(1 << 0)

enum {
	ARB_TIMER,
	ARB_BP_CAP_CLR,
	ARB_BP_CAP_HI_ADDR,
	ARB_BP_CAP_ADDR,
	ARB_BP_CAP_STATUS,
	ARB_BP_CAP_MASTER,
	ARB_ERR_CAP_CLR,
	ARB_ERR_CAP_HI_ADDR,
	ARB_ERR_CAP_ADDR,
	ARB_ERR_CAP_STATUS,
	ARB_ERR_CAP_MASTER,
};

static const int gisb_offsets_bcm7038[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x0b8,
	[ARB_BP_CAP_STATUS]	= 0x0c0,
	[ARB_BP_CAP_MASTER]	= -1,
	[ARB_ERR_CAP_CLR]	= 0x0c4,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0c8,
	[ARB_ERR_CAP_STATUS]	= 0x0d0,
	[ARB_ERR_CAP_MASTER]	= -1,
};

static const int gisb_offsets_bcm7278[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_BP_CAP_CLR]	= 0x01c,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x220,
	[ARB_BP_CAP_STATUS]	= 0x230,
	[ARB_BP_CAP_MASTER]	= 0x234,
	[ARB_ERR_CAP_CLR]	= 0x7f8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x7e0,
	[ARB_ERR_CAP_STATUS]	= 0x7f0,
	[ARB_ERR_CAP_MASTER]	= 0x7f4,
};

static const int gisb_offsets_bcm7400[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x0b8,
	[ARB_BP_CAP_STATUS]	= 0x0c0,
	[ARB_BP_CAP_MASTER]	= 0x0c4,
	[ARB_ERR_CAP_CLR]	= 0x0c8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0cc,
	[ARB_ERR_CAP_STATUS]	= 0x0d4,
	[ARB_ERR_CAP_MASTER]	= 0x0d8,
};

static const int gisb_offsets_bcm74165[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_BP_CAP_CLR]	= 0x044,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x048,
	[ARB_BP_CAP_STATUS]	= 0x058,
	[ARB_BP_CAP_MASTER]	= 0x05c,
	[ARB_ERR_CAP_CLR]	= 0x038,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x020,
	[ARB_ERR_CAP_STATUS]	= 0x030,
	[ARB_ERR_CAP_MASTER]	= 0x034,
};

static const int gisb_offsets_bcm7435[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x158,
	[ARB_BP_CAP_STATUS]	= 0x160,
	[ARB_BP_CAP_MASTER]	= 0x164,
	[ARB_ERR_CAP_CLR]	= 0x168,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x16c,
	[ARB_ERR_CAP_STATUS]	= 0x174,
	[ARB_ERR_CAP_MASTER]	= 0x178,
};

static const int gisb_offsets_bcm7445[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_BP_CAP_CLR]	= 0x010,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x1d8,
	[ARB_BP_CAP_STATUS]	= 0x1e0,
	[ARB_BP_CAP_MASTER]	= 0x1e4,
	[ARB_ERR_CAP_CLR]	= 0x7e4,
	[ARB_ERR_CAP_HI_ADDR]	= 0x7e8,
	[ARB_ERR_CAP_ADDR]	= 0x7ec,
	[ARB_ERR_CAP_STATUS]	= 0x7f4,
	[ARB_ERR_CAP_MASTER]	= 0x7f8,
};

struct brcmstb_gisb_arb_device {
	void __iomem	*base;
	const int	*gisb_offsets;
	bool		big_endian;
	struct mutex	lock;
	struct list_head next;
	u32 valid_mask;
	const char *master_names[sizeof(u32) * BITS_PER_BYTE];
	u32 saved_timeout;
};

static LIST_HEAD(brcmstb_gisb_arb_device_list);

static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset < 0) {
		/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
		if (reg == ARB_ERR_CAP_MASTER)
			return 1;
		else
			return 0;
	}

	if (gdev->big_endian)
		return ioread32be(gdev->base + offset);
	else
		return ioread32(gdev->base + offset);
}

static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
{
	u64 value;

	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;

	return value;
}

static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
{
	u64 value;

	value = gisb_read(gdev, ARB_BP_CAP_ADDR);
	value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;

	return value;
}

static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset == -1)
		return;

	if (gdev->big_endian)
		iowrite32be(val, gdev->base + offset);
	else
		iowrite32(val, gdev->base + offset);
}

static ssize_t gisb_arb_get_timeout(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	u32 timeout;

	mutex_lock(&gdev->lock);
	timeout = gisb_read(gdev, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return sprintf(buf, "%d", timeout);
}

static ssize_t gisb_arb_set_timeout(struct device *dev,
				    struct device_attribute *attr,
				    const char *buf, size_t count)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	int val, ret;

	ret = kstrtoint(buf, 10, &val);
	if (ret < 0)
		return ret;

	if (val == 0 || val >= 0xffffffff)
		return -EINVAL;

	mutex_lock(&gdev->lock);
	gisb_write(gdev, val, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return count;
}

static const char *
brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
						u32 masters)
{
	u32 mask = gdev->valid_mask & masters;

	if (hweight_long(mask) != 1)
		return NULL;

	return gdev->master_names[ffs(mask) - 1];
}

static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
					const char *reason)
{
	u32 cap_status;
	u64 arb_addr;
	u32 master;
	const char *m_name;
	char m_fmt[11];

	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
		return 1;

	/* Read the address and master */
	arb_addr = gisb_read_address(gdev);
	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
		reason, arb_addr,
		cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
		cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return 0;
}

#ifdef CONFIG_MIPS
static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
{
	int ret = 0;
	struct brcmstb_gisb_arb_device *gdev;
	u32 cap_status;

	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
		cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

		/* Invalid captured address, bail out */
		if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
			is_fixup = 1;
			goto out;
		}

		ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	}
out:
	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
}
#endif

static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
{
	struct brcmstb_gisb_arb_device *gdev = dev_id;
	const char *m_name;
	u32 bp_status;
	u64 arb_addr;
	u32 master;
	char m_fmt[11];

	bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
		return IRQ_HANDLED;

	/* Read the address and master */
	arb_addr = gisb_read_bp_address(gdev);
	master = gisb_read(gdev, ARB_BP_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
		arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return IRQ_HANDLED;
}

/*
 * Dump out gisb errors on die or panic.
 */
static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p);

static struct notifier_block gisb_die_notifier = {
	.notifier_call = dump_gisb_error,
};

static struct notifier_block gisb_panic_notifier = {
	.notifier_call = dump_gisb_error,
};

static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p)
{
	struct brcmstb_gisb_arb_device *gdev;
	const char *reason = "panic";

	if (self == &gisb_die_notifier)
		reason = "die";

	/* iterate over each GISB arb registered handlers */
	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
		brcmstb_gisb_arb_decode_addr(gdev, reason);

	return NOTIFY_DONE;
}

static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
		gisb_arb_get_timeout, gisb_arb_set_timeout);

static struct attribute *gisb_arb_sysfs_attrs[] = {
	&dev_attr_gisb_arb_timeout.attr,
	NULL,
};

static struct attribute_group gisb_arb_sysfs_attr_group = {
	.attrs = gisb_arb_sysfs_attrs,
};

static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	{ .compatible = "brcm,gisb-arb",         .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
	{ .compatible = "brcm,bcm74165-gisb-arb", .data = gisb_offsets_bcm74165 },
	{ },
};
MODULE_DEVICE_TABLE(of, brcmstb_gisb_arb_of_match);

static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct brcmstb_gisb_arb_device *gdev;
	const struct of_device_id *of_id;
	int err, timeout_irq, tea_irq, bp_irq;
	unsigned int num_masters, j = 0;
	int i, first, last;

	timeout_irq = platform_get_irq(pdev, 0);
	tea_irq = platform_get_irq(pdev, 1);
	bp_irq = platform_get_irq(pdev, 2);

	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	if (!gdev)
		return -ENOMEM;

	mutex_init(&gdev->lock);
	INIT_LIST_HEAD(&gdev->next);

	gdev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
	if (IS_ERR(gdev->base))
		return PTR_ERR(gdev->base);

	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	if (!of_id) {
		pr_err("failed to look up compatible string\n");
		return -EINVAL;
	}
	gdev->gisb_offsets = of_id->data;
	gdev->big_endian = of_device_is_big_endian(dn);

	err = devm_request_irq(&pdev->dev, timeout_irq,
				brcmstb_gisb_timeout_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	err = devm_request_irq(&pdev->dev, tea_irq,
				brcmstb_gisb_tea_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	/* Interrupt is optional */
	if (bp_irq > 0) {
		err = devm_request_irq(&pdev->dev, bp_irq,
				       brcmstb_gisb_bp_handler, 0, pdev->name,
				       gdev);
		if (err < 0)
			return err;
	}

	/* If we do not have a valid mask, assume all masters are enabled */
	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
				&gdev->valid_mask))
		gdev->valid_mask = 0xffffffff;

	/* Proceed with reading the litteral names if we agree on the
	 * number of masters
	 */
	num_masters = of_property_count_strings(dn,
			"brcm,gisb-arb-master-names");
	if (hweight_long(gdev->valid_mask) == num_masters) {
		first = ffs(gdev->valid_mask) - 1;
		last = fls(gdev->valid_mask) - 1;

		for (i = first; i < last; i++) {
			if (!(gdev->valid_mask & BIT(i)))
				continue;

			of_property_read_string_index(dn,
					"brcm,gisb-arb-master-names", j,
					&gdev->master_names[i]);
			j++;
		}
	}

	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	if (err)
		return err;

	platform_set_drvdata(pdev, gdev);

	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);

#ifdef CONFIG_MIPS
	mips_set_be_handler(brcmstb_bus_error_handler);
#endif

	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
		register_die_notifier(&gisb_die_notifier);
		atomic_notifier_chain_register(&panic_notifier_list,
					       &gisb_panic_notifier);
	}

	dev_info(&pdev->dev, "registered irqs: %d, %d\n",
		 timeout_irq, tea_irq);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int brcmstb_gisb_arb_suspend(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);

	return 0;
}

/* Make sure we provide the same timeout value that was configured before, and
 * do this before the GISB timeout interrupt handler has any chance to run.
 */
static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);

	return 0;
}
#else
#define brcmstb_gisb_arb_suspend       NULL
#define brcmstb_gisb_arb_resume_noirq  NULL
#endif

static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	.suspend	= brcmstb_gisb_arb_suspend,
	.resume_noirq	= brcmstb_gisb_arb_resume_noirq,
};

static struct platform_driver brcmstb_gisb_arb_driver = {
	.driver = {
		.name	= "brcm-gisb-arb",
		.of_match_table = brcmstb_gisb_arb_of_match,
		.pm	= &brcmstb_gisb_arb_pm_ops,
	},
};

static int __init brcm_gisb_driver_init(void)
{
	return platform_driver_probe(&brcmstb_gisb_arb_driver,
				     brcmstb_gisb_arb_probe);
}

module_init(brcm_gisb_driver_init);

MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
44127b77	2	/*
707a4cdf	3	* Copyright (C) 2014-2021 Broadcom
44127b77 FF	4	*/
	5
	6	#include <linux/init.h>
	7	#include <linux/types.h>
	8	#include <linux/module.h>
f39650de	9	#include <linux/panic_notifier.h>
44127b77 FF	10	#include <linux/platform_device.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/sysfs.h>
	13	#include <linux/io.h>
	14	#include <linux/string.h>
	15	#include <linux/device.h>
	16	#include <linux/list.h>
	17	#include <linux/of.h>
	18	#include <linux/bitops.h>
203bb85e	19	#include <linux/pm.h>
9eb60880 DB	20	#include <linux/kernel.h>
	21	#include <linux/kdebug.h>
	22	#include <linux/notifier.h>
44127b77	23
c400d5eb FF	24	#ifdef CONFIG_MIPS
	25	#include <asm/traps.h>
	26	#endif
	27
44127b77	28	#define ARB_ERR_CAP_CLEAR (1 << 0)
44127b77 FF	29	#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
44127b77 FF	30	#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
44127b77 FF	31	#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
44127b77 FF	32	#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
f8083587	33
fb8a0b80 FF	34	#define ARB_BP_CAP_CLEAR (1 << 0)
	35	#define ARB_BP_CAP_STATUS_PROT_SHIFT 14
	36	#define ARB_BP_CAP_STATUS_TYPE (1 << 13)
	37	#define ARB_BP_CAP_STATUS_RSP_SHIFT 10
	38	#define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)
	39	#define ARB_BP_CAP_STATUS_BS_SHIFT 2
	40	#define ARB_BP_CAP_STATUS_WRITE (1 << 1)
	41	#define ARB_BP_CAP_STATUS_VALID (1 << 0)
	42
f8083587 KC	43	enum {
f8083587 KC	44	ARB_TIMER,
fb8a0b80 FF	45	ARB_BP_CAP_CLR,
	46	ARB_BP_CAP_HI_ADDR,
	47	ARB_BP_CAP_ADDR,
	48	ARB_BP_CAP_STATUS,
	49	ARB_BP_CAP_MASTER,
f8083587 KC	50	ARB_ERR_CAP_CLR,
	51	ARB_ERR_CAP_HI_ADDR,
	52	ARB_ERR_CAP_ADDR,
f8083587 KC	53	ARB_ERR_CAP_STATUS,
	54	ARB_ERR_CAP_MASTER,
	55	};
	56
d1d67868 KC	57	static const int gisb_offsets_bcm7038[] = {
d1d67868 KC	58	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	59	[ARB_BP_CAP_CLR] = 0x014,
	60	[ARB_BP_CAP_HI_ADDR] = -1,
	61	[ARB_BP_CAP_ADDR] = 0x0b8,
	62	[ARB_BP_CAP_STATUS] = 0x0c0,
	63	[ARB_BP_CAP_MASTER] = -1,
d1d67868 KC	64	[ARB_ERR_CAP_CLR] = 0x0c4,
	65	[ARB_ERR_CAP_HI_ADDR] = -1,
	66	[ARB_ERR_CAP_ADDR] = 0x0c8,
d1d67868 KC	67	[ARB_ERR_CAP_STATUS] = 0x0d0,
	68	[ARB_ERR_CAP_MASTER] = -1,
	69	};
	70
d523e0cf DB	71	static const int gisb_offsets_bcm7278[] = {
d523e0cf DB	72	[ARB_TIMER] = 0x008,
fb8a0b80 FF	73	[ARB_BP_CAP_CLR] = 0x01c,
	74	[ARB_BP_CAP_HI_ADDR] = -1,
	75	[ARB_BP_CAP_ADDR] = 0x220,
	76	[ARB_BP_CAP_STATUS] = 0x230,
	77	[ARB_BP_CAP_MASTER] = 0x234,
d523e0cf DB	78	[ARB_ERR_CAP_CLR] = 0x7f8,
	79	[ARB_ERR_CAP_HI_ADDR] = -1,
	80	[ARB_ERR_CAP_ADDR] = 0x7e0,
	81	[ARB_ERR_CAP_STATUS] = 0x7f0,
	82	[ARB_ERR_CAP_MASTER] = 0x7f4,
	83	};
	84
d1d67868 KC	85	static const int gisb_offsets_bcm7400[] = {
d1d67868 KC	86	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	87	[ARB_BP_CAP_CLR] = 0x014,
	88	[ARB_BP_CAP_HI_ADDR] = -1,
	89	[ARB_BP_CAP_ADDR] = 0x0b8,
	90	[ARB_BP_CAP_STATUS] = 0x0c0,
	91	[ARB_BP_CAP_MASTER] = 0x0c4,
d1d67868 KC	92	[ARB_ERR_CAP_CLR] = 0x0c8,
	93	[ARB_ERR_CAP_HI_ADDR] = -1,
	94	[ARB_ERR_CAP_ADDR] = 0x0cc,
d1d67868 KC	95	[ARB_ERR_CAP_STATUS] = 0x0d4,
	96	[ARB_ERR_CAP_MASTER] = 0x0d8,
	97	};
	98
86964bb6 FF	99	static const int gisb_offsets_bcm74165[] = {
	100	[ARB_TIMER] = 0x008,
	101	[ARB_BP_CAP_CLR] = 0x044,
	102	[ARB_BP_CAP_HI_ADDR] = -1,
	103	[ARB_BP_CAP_ADDR] = 0x048,
	104	[ARB_BP_CAP_STATUS] = 0x058,
	105	[ARB_BP_CAP_MASTER] = 0x05c,
	106	[ARB_ERR_CAP_CLR] = 0x038,
	107	[ARB_ERR_CAP_HI_ADDR] = -1,
	108	[ARB_ERR_CAP_ADDR] = 0x020,
	109	[ARB_ERR_CAP_STATUS] = 0x030,
	110	[ARB_ERR_CAP_MASTER] = 0x034,
	111	};
	112
d1d67868 KC	113	static const int gisb_offsets_bcm7435[] = {
d1d67868 KC	114	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	115	[ARB_BP_CAP_CLR] = 0x014,
	116	[ARB_BP_CAP_HI_ADDR] = -1,
	117	[ARB_BP_CAP_ADDR] = 0x158,
	118	[ARB_BP_CAP_STATUS] = 0x160,
	119	[ARB_BP_CAP_MASTER] = 0x164,
d1d67868 KC	120	[ARB_ERR_CAP_CLR] = 0x168,
	121	[ARB_ERR_CAP_HI_ADDR] = -1,
	122	[ARB_ERR_CAP_ADDR] = 0x16c,
d1d67868 KC	123	[ARB_ERR_CAP_STATUS] = 0x174,
	124	[ARB_ERR_CAP_MASTER] = 0x178,
	125	};
	126
f8083587 KC	127	static const int gisb_offsets_bcm7445[] = {
f8083587 KC	128	[ARB_TIMER] = 0x008,
fb8a0b80 FF	129	[ARB_BP_CAP_CLR] = 0x010,
	130	[ARB_BP_CAP_HI_ADDR] = -1,
	131	[ARB_BP_CAP_ADDR] = 0x1d8,
	132	[ARB_BP_CAP_STATUS] = 0x1e0,
	133	[ARB_BP_CAP_MASTER] = 0x1e4,
f8083587 KC	134	[ARB_ERR_CAP_CLR] = 0x7e4,
	135	[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
	136	[ARB_ERR_CAP_ADDR] = 0x7ec,
f8083587 KC	137	[ARB_ERR_CAP_STATUS] = 0x7f4,
	138	[ARB_ERR_CAP_MASTER] = 0x7f8,
	139	};
44127b77 FF	140
	141	struct brcmstb_gisb_arb_device {
	142	void __iomem *base;
f8083587	143	const int *gisb_offsets;
fbf4e262	144	bool big_endian;
44127b77 FF	145	struct mutex lock;
	146	struct list_head next;
	147	u32 valid_mask;
	148	const char master_names[sizeof(u32) BITS_PER_BYTE];
203bb85e	149	u32 saved_timeout;
44127b77 FF	150	};
	151
	152	static LIST_HEAD(brcmstb_gisb_arb_device_list);
	153
2b53eadc KC	154	static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
2b53eadc KC	155	{
f8083587 KC	156	int offset = gdev->gisb_offsets[reg];
f8083587 KC	157
0c2aa0e4 DB	158	if (offset < 0) {
	159	/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
	160	if (reg == ARB_ERR_CAP_MASTER)
	161	return 1;
	162	else
	163	return 0;
	164	}
f8083587	165
fbf4e262 KC	166	if (gdev->big_endian)
	167	return ioread32be(gdev->base + offset);
	168	else
	169	return ioread32(gdev->base + offset);
2b53eadc KC	170	}
2b53eadc KC	171
0c2aa0e4 DB	172	static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
	173	{
	174	u64 value;
	175
	176	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	177	value \|= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
	178
	179	return value;
	180	}
	181
fb8a0b80 FF	182	static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
	183	{
	184	u64 value;
	185
	186	value = gisb_read(gdev, ARB_BP_CAP_ADDR);
	187	value \|= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
	188
	189	return value;
	190	}
	191
2b53eadc KC	192	static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
2b53eadc KC	193	{
f8083587 KC	194	int offset = gdev->gisb_offsets[reg];
	195
	196	if (offset == -1)
	197	return;
fbf4e262 KC	198
fbf4e262 KC	199	if (gdev->big_endian)
856c7ccb	200	iowrite32be(val, gdev->base + offset);
fbf4e262	201	else
856c7ccb	202	iowrite32(val, gdev->base + offset);
2b53eadc KC	203	}
2b53eadc KC	204
44127b77 FF	205	static ssize_t gisb_arb_get_timeout(struct device *dev,
	206	struct device_attribute *attr,
	207	char *buf)
	208	{
0810d5cc	209	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	210	u32 timeout;
	211
	212	mutex_lock(&gdev->lock);
2b53eadc	213	timeout = gisb_read(gdev, ARB_TIMER);
44127b77 FF	214	mutex_unlock(&gdev->lock);
	215
	216	return sprintf(buf, "%d", timeout);
	217	}
	218
	219	static ssize_t gisb_arb_set_timeout(struct device *dev,
	220	struct device_attribute *attr,
	221	const char *buf, size_t count)
	222	{
0810d5cc	223	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	224	int val, ret;
	225
	226	ret = kstrtoint(buf, 10, &val);
	227	if (ret < 0)
	228	return ret;
	229
	230	if (val == 0 \|\| val >= 0xffffffff)
	231	return -EINVAL;
	232
	233	mutex_lock(&gdev->lock);
2b53eadc	234	gisb_write(gdev, val, ARB_TIMER);
44127b77 FF	235	mutex_unlock(&gdev->lock);
	236
	237	return count;
	238	}
	239
	240	static const char *
	241	brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
	242	u32 masters)
	243	{
	244	u32 mask = gdev->valid_mask & masters;
	245
	246	if (hweight_long(mask) != 1)
	247	return NULL;
	248
	249	return gdev->master_names[ffs(mask) - 1];
	250	}
	251
	252	static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
	253	const char *reason)
	254	{
	255	u32 cap_status;
0c2aa0e4	256	u64 arb_addr;
44127b77 FF	257	u32 master;
	258	const char *m_name;
	259	char m_fmt[11];
	260
2b53eadc	261	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
44127b77 FF	262
	263	/* Invalid captured address, bail out */
	264	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
	265	return 1;
	266
	267	/* Read the address and master */
0c2aa0e4	268	arb_addr = gisb_read_address(gdev);
2b53eadc	269	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
44127b77 FF	270
	271	m_name = brcmstb_gisb_master_to_str(gdev, master);
	272	if (!m_name) {
	273	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	274	m_name = m_fmt;
	275	}
	276
c9864df4 FF	277	pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
c9864df4 FF	278	reason, arb_addr,
44127b77 FF	279	cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
	280	cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
	281	m_name);
	282
	283	/* clear the GISB error */
2b53eadc	284	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
44127b77 FF	285
	286	return 0;
	287	}
	288
c400d5eb FF	289	#ifdef CONFIG_MIPS
	290	static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
	291	{
	292	int ret = 0;
	293	struct brcmstb_gisb_arb_device *gdev;
	294	u32 cap_status;
	295
	296	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
	297	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
	298
	299	/* Invalid captured address, bail out */
	300	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
	301	is_fixup = 1;
	302	goto out;
	303	}
	304
	305	ret \|= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	306	}
	307	out:
	308	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
	309	}
	310	#endif
	311
44127b77 FF	312	static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
	313	{
	314	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
	315
	316	return IRQ_HANDLED;
	317	}
	318
	319	static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
	320	{
	321	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
	322
	323	return IRQ_HANDLED;
	324	}
	325
fb8a0b80 FF	326	static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
	327	{
	328	struct brcmstb_gisb_arb_device *gdev = dev_id;
	329	const char *m_name;
	330	u32 bp_status;
	331	u64 arb_addr;
	332	u32 master;
	333	char m_fmt[11];
	334
	335	bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
	336
	337	/* Invalid captured address, bail out */
	338	if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
	339	return IRQ_HANDLED;
	340
	341	/* Read the address and master */
	342	arb_addr = gisb_read_bp_address(gdev);
	343	master = gisb_read(gdev, ARB_BP_CAP_MASTER);
	344
	345	m_name = brcmstb_gisb_master_to_str(gdev, master);
	346	if (!m_name) {
	347	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	348	m_name = m_fmt;
	349	}
	350
	351	pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
	352	arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
	353	m_name);
	354
	355	/* clear the GISB error */
	356	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
	357
	358	return IRQ_HANDLED;
	359	}
	360
9eb60880 DB	361	/*
	362	* Dump out gisb errors on die or panic.
	363	*/
	364	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	365	void *p);
	366
	367	static struct notifier_block gisb_die_notifier = {
	368	.notifier_call = dump_gisb_error,
	369	};
	370
	371	static struct notifier_block gisb_panic_notifier = {
	372	.notifier_call = dump_gisb_error,
	373	};
	374
	375	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	376	void *p)
	377	{
	378	struct brcmstb_gisb_arb_device *gdev;
	379	const char *reason = "panic";
	380
	381	if (self == &gisb_die_notifier)
	382	reason = "die";
	383
	384	/* iterate over each GISB arb registered handlers */
	385	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
	386	brcmstb_gisb_arb_decode_addr(gdev, reason);
	387
	388	return NOTIFY_DONE;
	389	}
	390
44127b77 FF	391	static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR \| S_IRUGO,
	392	gisb_arb_get_timeout, gisb_arb_set_timeout);
	393
	394	static struct attribute *gisb_arb_sysfs_attrs[] = {
	395	&dev_attr_gisb_arb_timeout.attr,
	396	NULL,
	397	};
	398
	399	static struct attribute_group gisb_arb_sysfs_attr_group = {
	400	.attrs = gisb_arb_sysfs_attrs,
	401	};
	402
d1d67868 KC	403	static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	404	{ .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
	405	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	406	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	407	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
d523e0cf	408	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
d1d67868	409	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
86964bb6	410	{ .compatible = "brcm,bcm74165-gisb-arb", .data = gisb_offsets_bcm74165 },
d1d67868 KC	411	{ },
d1d67868 KC	412	};
4cf39b01	413	MODULE_DEVICE_TABLE(of, brcmstb_gisb_arb_of_match);
d1d67868	414
2e8a29a1	415	static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
44127b77 FF	416	{
	417	struct device_node *dn = pdev->dev.of_node;
	418	struct brcmstb_gisb_arb_device *gdev;
d1d67868	419	const struct of_device_id *of_id;
fb8a0b80	420	int err, timeout_irq, tea_irq, bp_irq;
44127b77 FF	421	unsigned int num_masters, j = 0;
	422	int i, first, last;
	423
44127b77 FF	424	timeout_irq = platform_get_irq(pdev, 0);
44127b77 FF	425	tea_irq = platform_get_irq(pdev, 1);
fb8a0b80	426	bp_irq = platform_get_irq(pdev, 2);
44127b77 FF	427
	428	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	429	if (!gdev)
	430	return -ENOMEM;
	431
	432	mutex_init(&gdev->lock);
	433	INIT_LIST_HEAD(&gdev->next);
	434
9cf38a09	435	gdev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
c9d53c0f JH	436	if (IS_ERR(gdev->base))
c9d53c0f JH	437	return PTR_ERR(gdev->base);
44127b77	438
d1d67868 KC	439	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	440	if (!of_id) {
	441	pr_err("failed to look up compatible string\n");
	442	return -EINVAL;
	443	}
	444	gdev->gisb_offsets = of_id->data;
fbf4e262	445	gdev->big_endian = of_device_is_big_endian(dn);
f8083587	446
44127b77 FF	447	err = devm_request_irq(&pdev->dev, timeout_irq,
	448	brcmstb_gisb_timeout_handler, 0, pdev->name,
	449	gdev);
	450	if (err < 0)
	451	return err;
	452
	453	err = devm_request_irq(&pdev->dev, tea_irq,
	454	brcmstb_gisb_tea_handler, 0, pdev->name,
	455	gdev);
	456	if (err < 0)
	457	return err;
	458
fb8a0b80 FF	459	/* Interrupt is optional */
	460	if (bp_irq > 0) {
	461	err = devm_request_irq(&pdev->dev, bp_irq,
	462	brcmstb_gisb_bp_handler, 0, pdev->name,
	463	gdev);
	464	if (err < 0)
	465	return err;
	466	}
	467
44127b77 FF	468	/* If we do not have a valid mask, assume all masters are enabled */
	469	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
	470	&gdev->valid_mask))
	471	gdev->valid_mask = 0xffffffff;
	472
	473	/* Proceed with reading the litteral names if we agree on the
	474	* number of masters
	475	*/
	476	num_masters = of_property_count_strings(dn,
	477	"brcm,gisb-arb-master-names");
	478	if (hweight_long(gdev->valid_mask) == num_masters) {
	479	first = ffs(gdev->valid_mask) - 1;
	480	last = fls(gdev->valid_mask) - 1;
	481
	482	for (i = first; i < last; i++) {
	483	if (!(gdev->valid_mask & BIT(i)))
	484	continue;
	485
	486	of_property_read_string_index(dn,
	487	"brcm,gisb-arb-master-names", j,
	488	&gdev->master_names[i]);
	489	j++;
	490	}
	491	}
	492
	493	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	494	if (err)
	495	return err;
	496
	497	platform_set_drvdata(pdev, gdev);
	498
	499	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
	500
c400d5eb	501	#ifdef CONFIG_MIPS
1f761b3e	502	mips_set_be_handler(brcmstb_bus_error_handler);
c400d5eb	503	#endif
f1bee783	504
9eb60880 DB	505	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
	506	register_die_notifier(&gisb_die_notifier);
	507	atomic_notifier_chain_register(&panic_notifier_list,
	508	&gisb_panic_notifier);
	509	}
	510
3087974a FF	511	dev_info(&pdev->dev, "registered irqs: %d, %d\n",
3087974a FF	512	timeout_irq, tea_irq);
44127b77 FF	513
	514	return 0;
	515	}
	516
203bb85e FF	517	#ifdef CONFIG_PM_SLEEP
	518	static int brcmstb_gisb_arb_suspend(struct device *dev)
	519	{
0810d5cc	520	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	521
71354661	522	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
203bb85e FF	523
	524	return 0;
	525	}
	526
	527	/* Make sure we provide the same timeout value that was configured before, and
	528	* do this before the GISB timeout interrupt handler has any chance to run.
	529	*/
	530	static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
	531	{
0810d5cc	532	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	533
71354661	534	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
203bb85e FF	535
	536	return 0;
	537	}
	538	#else
	539	#define brcmstb_gisb_arb_suspend NULL
	540	#define brcmstb_gisb_arb_resume_noirq NULL
	541	#endif
	542
	543	static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	544	.suspend = brcmstb_gisb_arb_suspend,
	545	.resume_noirq = brcmstb_gisb_arb_resume_noirq,
	546	};
	547
44127b77	548	static struct platform_driver brcmstb_gisb_arb_driver = {
44127b77 FF	549	.driver = {
44127b77 FF	550	.name = "brcm-gisb-arb",
44127b77	551	.of_match_table = brcmstb_gisb_arb_of_match,
203bb85e	552	.pm = &brcmstb_gisb_arb_pm_ops,
44127b77 FF	553	},
	554	};
	555
	556	static int __init brcm_gisb_driver_init(void)
	557	{
2e8a29a1 FF	558	return platform_driver_probe(&brcmstb_gisb_arb_driver,
2e8a29a1 FF	559	brcmstb_gisb_arb_probe);
44127b77 FF	560	}
	561
	562	module_init(brcm_gisb_driver_init);
707a4cdf FF	563
	564	MODULE_AUTHOR("Broadcom");
	565	MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
	566	MODULE_LICENSE("GPL v2");