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drm/sun4i: dsi: Fix front vs back porch calculation
[thirdparty/linux.git] / drivers / gpu / drm / sun4i / sun6i_mipi_dsi.c
CommitLineData
133add5b
MR		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2016 Allwinnertech Co., Ltd.
4 * Copyright (C) 2017-2018 Bootlin
5 *
6 * Maxime Ripard <maxime.ripard@bootlin.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/component.h>
11#include <linux/crc-ccitt.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14#include <linux/regmap.h>
15#include <linux/reset.h>
c51756d5 16#include <linux/slab.h>
133add5b
MR		 17
18#include <linux/phy/phy.h>
bb3b6fcb 19#include <linux/phy/phy-mipi-dphy.h>
133add5b
MR		 20
21#include <drm/drmP.h>
22#include <drm/drm_atomic_helper.h>
133add5b
MR		 23#include <drm/drm_mipi_dsi.h>
24#include <drm/drm_panel.h>
fcd70cd3 25#include <drm/drm_probe_helper.h>
133add5b
MR		 26
27#include "sun4i_drv.h"
28#include "sun6i_mipi_dsi.h"
29
30#include <video/mipi_display.h>
31
32#define SUN6I_DSI_CTL_REG 0x000
33#define SUN6I_DSI_CTL_EN BIT(0)
34
35#define SUN6I_DSI_BASIC_CTL_REG 0x00c
36#define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2)
37#define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1)
38#define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0)
39
40#define SUN6I_DSI_BASIC_CTL0_REG 0x010
41#define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18)
42#define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17)
43#define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16)
44#define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0)
45
46#define SUN6I_DSI_BASIC_CTL1_REG 0x014
47#define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4)
48#define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2)
49#define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1)
50#define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0)
51
52#define SUN6I_DSI_BASIC_SIZE0_REG 0x018
53#define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16)
54#define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff)
55
56#define SUN6I_DSI_BASIC_SIZE1_REG 0x01c
57#define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16)
58#define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff)
59
60#define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04)
61#define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28)
62#define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24)
63#define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20)
64#define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4)
65#define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf)
66
67#define SUN6I_DSI_INST_LOOP_SEL_REG 0x040
68
69#define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10)
70#define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16)
71#define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff)
72
73#define SUN6I_DSI_INST_JUMP_SEL_REG 0x048
74
75#define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04)
76#define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20)
77#define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16)
78#define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff)
79
80#define SUN6I_DSI_TRANS_START_REG 0x060
81
82#define SUN6I_DSI_TRANS_ZERO_REG 0x078
83
84#define SUN6I_DSI_TCON_DRQ_REG 0x07c
85#define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28)
86#define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff)
87
88#define SUN6I_DSI_PIXEL_CTL0_REG 0x080
89#define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16)
90#define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf)
91
92#define SUN6I_DSI_PIXEL_CTL1_REG 0x084
93
94#define SUN6I_DSI_PIXEL_PH_REG 0x090
95#define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24)
96#define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8)
97#define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6)
98#define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f)
99
100#define SUN6I_DSI_PIXEL_PF0_REG 0x098
101#define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff)
102
103#define SUN6I_DSI_PIXEL_PF1_REG 0x09c
104#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16)
105#define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff)
106
107#define SUN6I_DSI_SYNC_HSS_REG 0x0b0
108
109#define SUN6I_DSI_SYNC_HSE_REG 0x0b4
110
111#define SUN6I_DSI_SYNC_VSS_REG 0x0b8
112
113#define SUN6I_DSI_SYNC_VSE_REG 0x0bc
114
115#define SUN6I_DSI_BLK_HSA0_REG 0x0c0
116
117#define SUN6I_DSI_BLK_HSA1_REG 0x0c4
118#define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16)
119#define SUN6I_DSI_BLK_PD(n) ((n) & 0xff)
120
121#define SUN6I_DSI_BLK_HBP0_REG 0x0c8
122
123#define SUN6I_DSI_BLK_HBP1_REG 0x0cc
124
125#define SUN6I_DSI_BLK_HFP0_REG 0x0d0
126
127#define SUN6I_DSI_BLK_HFP1_REG 0x0d4
128
129#define SUN6I_DSI_BLK_HBLK0_REG 0x0e0
130
131#define SUN6I_DSI_BLK_HBLK1_REG 0x0e4
132
133#define SUN6I_DSI_BLK_VBLK0_REG 0x0e8
134
135#define SUN6I_DSI_BLK_VBLK1_REG 0x0ec
136
137#define SUN6I_DSI_BURST_LINE_REG 0x0f0
138#define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16)
139#define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff)
140
141#define SUN6I_DSI_BURST_DRQ_REG 0x0f4
142#define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16)
143#define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff)
144
145#define SUN6I_DSI_CMD_CTL_REG 0x200
146#define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26)
147#define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25)
148#define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9)
149
150#define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04)
151
152#define SUN6I_DSI_DEBUG_DATA_REG 0x2f8
153
154#define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04)
155
156enum sun6i_dsi_start_inst {
157 DSI_START_LPRX,
158 DSI_START_LPTX,
159 DSI_START_HSC,
160 DSI_START_HSD,
161};
162
163enum sun6i_dsi_inst_id {
164 DSI_INST_ID_LP11 = 0,
165 DSI_INST_ID_TBA,
166 DSI_INST_ID_HSC,
167 DSI_INST_ID_HSD,
168 DSI_INST_ID_LPDT,
169 DSI_INST_ID_HSCEXIT,
170 DSI_INST_ID_NOP,
171 DSI_INST_ID_DLY,
172 DSI_INST_ID_END = 15,
173};
174
175enum sun6i_dsi_inst_mode {
176 DSI_INST_MODE_STOP = 0,
177 DSI_INST_MODE_TBA,
178 DSI_INST_MODE_HS,
179 DSI_INST_MODE_ESCAPE,
180 DSI_INST_MODE_HSCEXIT,
181 DSI_INST_MODE_NOP,
182};
183
184enum sun6i_dsi_inst_escape {
185 DSI_INST_ESCA_LPDT = 0,
186 DSI_INST_ESCA_ULPS,
187 DSI_INST_ESCA_UN1,
188 DSI_INST_ESCA_UN2,
189 DSI_INST_ESCA_RESET,
190 DSI_INST_ESCA_UN3,
191 DSI_INST_ESCA_UN4,
192 DSI_INST_ESCA_UN5,
193};
194
195enum sun6i_dsi_inst_packet {
196 DSI_INST_PACK_PIXEL = 0,
197 DSI_INST_PACK_COMMAND,
198};
199
200static const u32 sun6i_dsi_ecc_array[] = {
201 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) |
202 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) |
203 BIT(23)),
204 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) |
205 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) |
206 BIT(23)),
207 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) |
208 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)),
209 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) |
210 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)),
211 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) |
212 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)),
213 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) |
214 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) |
215 BIT(23)),
216};
217
218static u32 sun6i_dsi_ecc_compute(unsigned int data)
219{
220 int i;
221 u8 ecc = 0;
222
223 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) {
224 u32 field = sun6i_dsi_ecc_array[i];
225 bool init = false;
226 u8 val = 0;
227 int j;
228
229 for (j = 0; j < 24; j++) {
230 if (!(BIT(j) & field))
231 continue;
232
233 if (!init) {
234 val = (BIT(j) & data) ? 1 : 0;
235 init = true;
236 } else {
237 val ^= (BIT(j) & data) ? 1 : 0;
238 }
239 }
240
241 ecc |= val << i;
242 }
243
244 return ecc;
245}
246
247static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len)
248{
249 return crc_ccitt(0xffff, buffer, len);
250}
251
c51756d5 252static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len)
133add5b 253{
133add5b
MR		 254 memset(buffer, pd, len);
255
256 return sun6i_dsi_crc_compute(buffer, len);
257}
258
259static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1)
260{
261 u32 val = dt & 0x3f;
262
263 val |= (vc & 3) << 6;
264 val |= (d0 & 0xff) << 8;
265 val |= (d1 & 0xff) << 16;
266 val |= sun6i_dsi_ecc_compute(val) << 24;
267
268 return val;
269}
270
271static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc)
272{
273 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc,
274 wc & 0xff, wc >> 8);
275}
276
c51756d5 277static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len)
133add5b
MR		 278{
279 u32 val = SUN6I_DSI_BLK_PD(pd);
280
c51756d5 281 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len));
133add5b
MR		 282}
283
284static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi)
285{
286 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
287 SUN6I_DSI_BASIC_CTL0_INST_ST, 0);
288}
289
290static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi)
291{
292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
293 SUN6I_DSI_BASIC_CTL0_INST_ST,
294 SUN6I_DSI_BASIC_CTL0_INST_ST);
295}
296
297static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi)
298{
299 u32 val;
300
301 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
302 val,
303 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST),
304 100, 5000);
305}
306
307static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi,
308 enum sun6i_dsi_inst_id id,
309 enum sun6i_dsi_inst_mode mode,
310 bool clock, u8 data,
311 enum sun6i_dsi_inst_packet packet,
312 enum sun6i_dsi_inst_escape escape)
313{
314 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id),
315 SUN6I_DSI_INST_FUNC_INST_MODE(mode) |
316 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) |
317 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) |
318 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) |
319 SUN6I_DSI_INST_FUNC_LANE_DEN(data));
320}
321
322static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
323 struct mipi_dsi_device *device)
324{
325 u8 lanes_mask = GENMASK(device->lanes - 1, 0);
326
327 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP,
328 true, lanes_mask, 0, 0);
329
330 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA,
331 false, 1, 0, 0);
332
333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS,
334 true, 0, DSI_INST_PACK_PIXEL, 0);
335
336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS,
337 false, lanes_mask, DSI_INST_PACK_PIXEL, 0);
338
339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE,
340 false, 1, DSI_INST_PACK_COMMAND,
341 DSI_INST_ESCA_LPDT);
342
343 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT,
344 true, 0, 0, 0);
345
346 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP,
347 false, lanes_mask, 0, 0);
348
349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP,
350 true, lanes_mask, 0, 0);
351
352 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0),
353 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) |
354 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) |
355 SUN6I_DSI_INST_JUMP_CFG_NUM(1));
356};
357
358static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
359 struct drm_display_mode *mode)
360{
da676c6a 361 u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100);
efa31801 362 u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + start;
da676c6a 363
efa31801
MR		 364 if (delay > mode->vtotal)
365 delay = delay % mode->vtotal;
366
367 return max_t(u16, delay, 1);
133add5b
MR		 368}
369
370static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi,
371 struct drm_display_mode *mode)
372{
373 struct mipi_dsi_device *device = dsi->device;
374 u32 val = 0;
375
376 if ((mode->hsync_end - mode->hdisplay) > 20) {
377 /* Maaaaaagic */
378 u16 drq = (mode->hsync_end - mode->hdisplay) - 20;
379
380 drq *= mipi_dsi_pixel_format_to_bpp(device->format);
381 drq /= 32;
382
383 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE |
384 SUN6I_DSI_TCON_DRQ_SET(drq));
385 }
386
387 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val);
388}
389
390static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi,
391 struct drm_display_mode *mode)
392{
393 u16 delay = 50 - 1;
394
395 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0),
396 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
397 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
398 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1),
399 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) |
400 SUN6I_DSI_INST_LOOP_NUM_N1(delay));
401}
402
403static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi,
404 struct drm_display_mode *mode)
405{
406 struct mipi_dsi_device *device = dsi->device;
407 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel);
408 u8 dt, fmt;
409 u16 wc;
410
411 /*
412 * TODO: The format defines are only valid in video mode and
413 * change in command mode.
414 */
415 switch (device->format) {
416 case MIPI_DSI_FMT_RGB888:
417 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24;
418 fmt = 8;
419 break;
420 case MIPI_DSI_FMT_RGB666:
421 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
422 fmt = 9;
423 break;
424 case MIPI_DSI_FMT_RGB666_PACKED:
425 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18;
426 fmt = 10;
427 break;
428 case MIPI_DSI_FMT_RGB565:
429 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16;
430 fmt = 11;
431 break;
432 default:
433 return;
434 }
435 val |= SUN6I_DSI_PIXEL_PH_DT(dt);
436
437 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8;
438 val |= SUN6I_DSI_PIXEL_PH_WC(wc);
439 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val));
440
441 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val);
442
443 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG,
444 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff));
445
446 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG,
447 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) |
448 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff));
449
450 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG,
451 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE |
452 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt));
453}
454
455static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
456 struct drm_display_mode *mode)
457{
458 struct mipi_dsi_device *device = dsi->device;
459 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
460 u16 hbp, hfp, hsa, hblk, vblk;
c51756d5
KC		 461 size_t bytes;
462 u8 *buffer;
463
464 /* Do all timing calculations up front to allocate buffer space */
465
466 /*
467 * A sync period is composed of a blanking packet (4 bytes +
468 * payload + 2 bytes) and a sync event packet (4 bytes). Its
469 * minimal size is therefore 10 bytes
470 */
471#define HSA_PACKET_OVERHEAD 10
472 hsa = max((unsigned int)HSA_PACKET_OVERHEAD,
473 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD);
474
475 /*
476 * The backporch is set using a blanking packet (4 bytes +
477 * payload + 2 bytes). Its minimal size is therefore 6 bytes
478 */
479#define HBP_PACKET_OVERHEAD 6
480 hbp = max((unsigned int)HBP_PACKET_OVERHEAD,
2cfdc24d 481 (mode->htotal - mode->hsync_end) * Bpp - HBP_PACKET_OVERHEAD);
c51756d5
KC		 482
483 /*
484 * The frontporch is set using a blanking packet (4 bytes +
485 * payload + 2 bytes). Its minimal size is therefore 6 bytes
486 */
487#define HFP_PACKET_OVERHEAD 6
488 hfp = max((unsigned int)HFP_PACKET_OVERHEAD,
2cfdc24d 489 (mode->hsync_start - mode->hdisplay) * Bpp - HFP_PACKET_OVERHEAD);
c51756d5
KC		 490
491 /*
492 * hblk seems to be the line + porches length.
493 */
494 hblk = mode->htotal * Bpp - hsa;
495
496 /*
497 * And I'm not entirely sure what vblk is about. The driver in
498 * Allwinner BSP is using a rather convoluted calculation
499 * there only for 4 lanes. However, using 0 (the !4 lanes
500 * case) even with a 4 lanes screen seems to work...
501 */
502 vblk = 0;
503
504 /* How many bytes do we need to send all payloads? */
505 bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
506 buffer = kmalloc(bytes, GFP_KERNEL);
507 if (WARN_ON(!buffer))
508 return;
133add5b
MR		 509
510 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, 0);
511
512 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG,
513 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START,
514 device->channel,
515 0, 0));
516
517 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG,
518 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END,
519 device->channel,
520 0, 0));
521
522 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG,
523 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START,
524 device->channel,
525 0, 0));
526
527 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG,
528 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END,
529 device->channel,
530 0, 0));
531
532 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG,
533 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end -
534 mode->vsync_start) |
2cfdc24d
MR		 535 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal -
536 mode->vsync_end));
133add5b
MR		 537
538 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG,
539 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) |
540 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal));
541
c51756d5 542 /* sync */
133add5b
MR		 543 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG,
544 sun6i_dsi_build_blk0_pkt(device->channel, hsa));
545 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG,
c51756d5 546 sun6i_dsi_build_blk1_pkt(0, buffer, hsa));
133add5b 547
c51756d5 548 /* backporch */
133add5b
MR		 549 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG,
550 sun6i_dsi_build_blk0_pkt(device->channel, hbp));
551 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG,
c51756d5 552 sun6i_dsi_build_blk1_pkt(0, buffer, hbp));
133add5b 553
c51756d5 554 /* frontporch */
133add5b
MR		 555 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG,
556 sun6i_dsi_build_blk0_pkt(device->channel, hfp));
557 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG,
c51756d5 558 sun6i_dsi_build_blk1_pkt(0, buffer, hfp));
133add5b 559
c51756d5 560 /* hblk */
133add5b
MR		 561 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG,
562 sun6i_dsi_build_blk0_pkt(device->channel, hblk));
563 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG,
c51756d5 564 sun6i_dsi_build_blk1_pkt(0, buffer, hblk));
133add5b 565
c51756d5 566 /* vblk */
133add5b
MR		 567 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG,
568 sun6i_dsi_build_blk0_pkt(device->channel, vblk));
569 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG,
c51756d5
KC		 570 sun6i_dsi_build_blk1_pkt(0, buffer, vblk));
571
572 kfree(buffer);
133add5b
MR		 573}
574
575static int sun6i_dsi_start(struct sun6i_dsi *dsi,
576 enum sun6i_dsi_start_inst func)
577{
578 switch (func) {
579 case DSI_START_LPTX:
580 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
581 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
582 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT));
583 break;
584 case DSI_START_LPRX:
585 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
586 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) |
587 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) |
588 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) |
589 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA));
590 break;
591 case DSI_START_HSC:
592 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
593 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) |
594 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC));
595 break;
596 case DSI_START_HSD:
597 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
598 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) |
599 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) |
600 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) |
601 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) |
602 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT));
603 break;
604 default:
605 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG,
606 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11));
607 break;
608 }
609
610 sun6i_dsi_inst_abort(dsi);
611 sun6i_dsi_inst_commit(dsi);
612
613 if (func == DSI_START_HSC)
614 regmap_write_bits(dsi->regs,
615 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11),
616 SUN6I_DSI_INST_FUNC_LANE_CEN, 0);
617
618 return 0;
619}
620
621static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
622{
623 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
624 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
625 struct mipi_dsi_device *device = dsi->device;
bb3b6fcb
MR		 626 union phy_configure_opts opts = { 0 };
627 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
133add5b
MR		 628 u16 delay;
629
630 DRM_DEBUG_DRIVER("Enabling DSI output\n");
631
632 pm_runtime_get_sync(dsi->dev);
633
634 delay = sun6i_dsi_get_video_start_delay(dsi, mode);
635 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG,
636 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) |
637 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL |
638 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION |
639 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE);
640
641 sun6i_dsi_setup_burst(dsi, mode);
642 sun6i_dsi_setup_inst_loop(dsi, mode);
643 sun6i_dsi_setup_format(dsi, mode);
644 sun6i_dsi_setup_timings(dsi, mode);
645
bb3b6fcb
MR		 646 phy_init(dsi->dphy);
647
648 phy_mipi_dphy_get_default_config(mode->clock * 1000,
649 mipi_dsi_pixel_format_to_bpp(device->format),
650 device->lanes, cfg);
651
652 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
653 phy_configure(dsi->dphy, &opts);
654 phy_power_on(dsi->dphy);
133add5b
MR		 655
656 if (!IS_ERR(dsi->panel))
657 drm_panel_prepare(dsi->panel);
658
659 /*
660 * FIXME: This should be moved after the switch to HS mode.
661 *
662 * Unfortunately, once in HS mode, it seems like we're not
663 * able to send DCS commands anymore, which would prevent any
664 * panel to send any DCS command as part as their enable
665 * method, which is quite common.
666 *
667 * I haven't seen any artifact due to that sub-optimal
668 * ordering on the panels I've tested it with, so I guess this
669 * will do for now, until that IP is better understood.
670 */
671 if (!IS_ERR(dsi->panel))
672 drm_panel_enable(dsi->panel);
673
674 sun6i_dsi_start(dsi, DSI_START_HSC);
675
676 udelay(1000);
677
678 sun6i_dsi_start(dsi, DSI_START_HSD);
679}
680
681static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
682{
683 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
684
685 DRM_DEBUG_DRIVER("Disabling DSI output\n");
686
687 if (!IS_ERR(dsi->panel)) {
688 drm_panel_disable(dsi->panel);
689 drm_panel_unprepare(dsi->panel);
690 }
691
bb3b6fcb
MR		 692 phy_power_off(dsi->dphy);
693 phy_exit(dsi->dphy);
133add5b
MR		 694
695 pm_runtime_put(dsi->dev);
696}
697
698static int sun6i_dsi_get_modes(struct drm_connector *connector)
699{
700 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector);
701
702 return drm_panel_get_modes(dsi->panel);
703}
704
705static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = {
706 .get_modes = sun6i_dsi_get_modes,
707};
708
709static enum drm_connector_status
710sun6i_dsi_connector_detect(struct drm_connector *connector, bool force)
711{
712 return connector_status_connected;
713}
714
715static const struct drm_connector_funcs sun6i_dsi_connector_funcs = {
716 .detect = sun6i_dsi_connector_detect,
717 .fill_modes = drm_helper_probe_single_connector_modes,
718 .destroy = drm_connector_cleanup,
719 .reset = drm_atomic_helper_connector_reset,
720 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
721 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
722};
723
724static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = {
725 .disable = sun6i_dsi_encoder_disable,
726 .enable = sun6i_dsi_encoder_enable,
727};
728
729static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = {
730 .destroy = drm_encoder_cleanup,
731};
732
733static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi,
734 const struct mipi_dsi_msg *msg)
735{
736 u32 pkt = msg->type;
737
738 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) {
739 pkt |= ((msg->tx_len + 1) & 0xffff) << 8;
740 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16;
741 } else {
742 pkt |= (((u8 *)msg->tx_buf)[0] << 8);
743 if (msg->tx_len > 1)
744 pkt |= (((u8 *)msg->tx_buf)[1] << 16);
745 }
746
747 pkt |= sun6i_dsi_ecc_compute(pkt) << 24;
748
749 return pkt;
750}
751
752static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi,
753 const struct mipi_dsi_msg *msg)
754{
755 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
756 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
757 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
758 0xff, (4 - 1));
759
760 sun6i_dsi_start(dsi, DSI_START_LPTX);
761
762 return msg->tx_len;
763}
764
765static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi,
766 const struct mipi_dsi_msg *msg)
767{
768 int ret, len = 0;
769 u8 *bounce;
770 u16 crc;
771
772 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
773 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
774
775 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL);
776 if (!bounce)
777 return -ENOMEM;
778
779 memcpy(bounce, msg->tx_buf, msg->tx_len);
780 len += msg->tx_len;
781
782 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len);
783 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc));
784 len += sizeof(crc);
785
786 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len);
787 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1);
788 kfree(bounce);
789
790 sun6i_dsi_start(dsi, DSI_START_LPTX);
791
792 ret = sun6i_dsi_inst_wait_for_completion(dsi);
793 if (ret < 0) {
794 sun6i_dsi_inst_abort(dsi);
795 return ret;
796 }
797
798 /*
799 * TODO: There's some bits (reg 0x200, bits 8/9) that
800 * apparently can be used to check whether the data have been
801 * sent, but I couldn't get it to work reliably.
802 */
803 return msg->tx_len;
804}
805
806static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi,
807 const struct mipi_dsi_msg *msg)
808{
809 u32 val;
810 int ret;
811 u8 byte0;
812
813 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0),
814 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg));
815 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
816 (4 - 1));
817
818 sun6i_dsi_start(dsi, DSI_START_LPRX);
819
820 ret = sun6i_dsi_inst_wait_for_completion(dsi);
821 if (ret < 0) {
822 sun6i_dsi_inst_abort(dsi);
823 return ret;
824 }
825
826 /*
827 * TODO: There's some bits (reg 0x200, bits 24/25) that
828 * apparently can be used to check whether the data have been
829 * received, but I couldn't get it to work reliably.
830 */
831 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val);
832 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW)
833 return -EIO;
834
835 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val);
836 byte0 = val & 0xff;
837 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT)
838 return -EIO;
839
840 ((u8 *)msg->rx_buf)[0] = (val >> 8);
841
842 return 1;
843}
844
845static int sun6i_dsi_attach(struct mipi_dsi_host *host,
846 struct mipi_dsi_device *device)
847{
848 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
849
850 dsi->device = device;
851 dsi->panel = of_drm_find_panel(device->dev.of_node);
5fa8e4a2
BB		 852 if (IS_ERR(dsi->panel))
853 return PTR_ERR(dsi->panel);
133add5b
MR		 854
855 dev_info(host->dev, "Attached device %s\n", device->name);
856
857 return 0;
858}
859
860static int sun6i_dsi_detach(struct mipi_dsi_host *host,
861 struct mipi_dsi_device *device)
862{
863 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
864
865 dsi->panel = NULL;
866 dsi->device = NULL;
867
868 return 0;
869}
870
871static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host,
872 const struct mipi_dsi_msg *msg)
873{
874 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host);
875 int ret;
876
877 ret = sun6i_dsi_inst_wait_for_completion(dsi);
878 if (ret < 0)
879 sun6i_dsi_inst_abort(dsi);
880
881 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG,
882 SUN6I_DSI_CMD_CTL_RX_OVERFLOW |
883 SUN6I_DSI_CMD_CTL_RX_FLAG |
884 SUN6I_DSI_CMD_CTL_TX_FLAG);
885
886 switch (msg->type) {
887 case MIPI_DSI_DCS_SHORT_WRITE:
888 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
889 ret = sun6i_dsi_dcs_write_short(dsi, msg);
890 break;
891
892 case MIPI_DSI_DCS_LONG_WRITE:
893 ret = sun6i_dsi_dcs_write_long(dsi, msg);
894 break;
895
896 case MIPI_DSI_DCS_READ:
897 if (msg->rx_len == 1) {
898 ret = sun6i_dsi_dcs_read(dsi, msg);
899 break;
900 }
901
902 default:
903 ret = -EINVAL;
904 }
905
906 return ret;
907}
908
909static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = {
910 .attach = sun6i_dsi_attach,
911 .detach = sun6i_dsi_detach,
912 .transfer = sun6i_dsi_transfer,
913};
914
915static const struct regmap_config sun6i_dsi_regmap_config = {
916 .reg_bits = 32,
917 .val_bits = 32,
918 .reg_stride = 4,
919 .max_register = SUN6I_DSI_CMD_TX_REG(255),
920 .name = "mipi-dsi",
921};
922
923static int sun6i_dsi_bind(struct device *dev, struct device *master,
924 void *data)
925{
926 struct drm_device *drm = data;
927 struct sun4i_drv *drv = drm->dev_private;
928 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
929 int ret;
930
931 if (!dsi->panel)
932 return -EPROBE_DEFER;
933
934 dsi->drv = drv;
935
936 drm_encoder_helper_add(&dsi->encoder,
937 &sun6i_dsi_enc_helper_funcs);
938 ret = drm_encoder_init(drm,
939 &dsi->encoder,
940 &sun6i_dsi_enc_funcs,
941 DRM_MODE_ENCODER_DSI,
942 NULL);
943 if (ret) {
944 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n");
945 return ret;
946 }
947 dsi->encoder.possible_crtcs = BIT(0);
948
949 drm_connector_helper_add(&dsi->connector,
950 &sun6i_dsi_connector_helper_funcs);
951 ret = drm_connector_init(drm, &dsi->connector,
952 &sun6i_dsi_connector_funcs,
953 DRM_MODE_CONNECTOR_DSI);
954 if (ret) {
955 dev_err(dsi->dev,
956 "Couldn't initialise the DSI connector\n");
957 goto err_cleanup_connector;
958 }
959
cde4c44d 960 drm_connector_attach_encoder(&dsi->connector, &dsi->encoder);
133add5b
MR		 961 drm_panel_attach(dsi->panel, &dsi->connector);
962
963 return 0;
964
965err_cleanup_connector:
966 drm_encoder_cleanup(&dsi->encoder);
967 return ret;
968}
969
970static void sun6i_dsi_unbind(struct device *dev, struct device *master,
971 void *data)
972{
973 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
974
975 drm_panel_detach(dsi->panel);
976}
977
978static const struct component_ops sun6i_dsi_ops = {
979 .bind = sun6i_dsi_bind,
980 .unbind = sun6i_dsi_unbind,
981};
982
983static int sun6i_dsi_probe(struct platform_device *pdev)
984{
985 struct device *dev = &pdev->dev;
133add5b
MR		 986 struct sun6i_dsi *dsi;
987 struct resource *res;
988 void __iomem *base;
989 int ret;
990
991 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
992 if (!dsi)
993 return -ENOMEM;
994 dev_set_drvdata(dev, dsi);
995 dsi->dev = dev;
996 dsi->host.ops = &sun6i_dsi_host_ops;
997 dsi->host.dev = dev;
998
999 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1000 base = devm_ioremap_resource(dev, res);
1001 if (IS_ERR(base)) {
1002 dev_err(dev, "Couldn't map the DSI encoder registers\n");
1003 return PTR_ERR(base);
1004 }
1005
1006 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base,
1007 &sun6i_dsi_regmap_config);
1008 if (IS_ERR(dsi->regs)) {
1009 dev_err(dev, "Couldn't create the DSI encoder regmap\n");
1010 return PTR_ERR(dsi->regs);
1011 }
1012
1013 dsi->reset = devm_reset_control_get_shared(dev, NULL);
1014 if (IS_ERR(dsi->reset)) {
1015 dev_err(dev, "Couldn't get our reset line\n");
1016 return PTR_ERR(dsi->reset);
1017 }
1018
1019 dsi->mod_clk = devm_clk_get(dev, "mod");
1020 if (IS_ERR(dsi->mod_clk)) {
1021 dev_err(dev, "Couldn't get the DSI mod clock\n");
1022 return PTR_ERR(dsi->mod_clk);
1023 }
1024
1025 /*
1026 * In order to operate properly, that clock seems to be always
1027 * set to 297MHz.
1028 */
1029 clk_set_rate_exclusive(dsi->mod_clk, 297000000);
1030
bb3b6fcb
MR		 1031 dsi->dphy = devm_phy_get(dev, "dphy");
1032 if (IS_ERR(dsi->dphy)) {
133add5b 1033 dev_err(dev, "Couldn't get the MIPI D-PHY\n");
1c7c62a3 1034 ret = PTR_ERR(dsi->dphy);
133add5b
MR		 1035 goto err_unprotect_clk;
1036 }
1037
1038 pm_runtime_enable(dev);
1039
1040 ret = mipi_dsi_host_register(&dsi->host);
1041 if (ret) {
1042 dev_err(dev, "Couldn't register MIPI-DSI host\n");
bb3b6fcb 1043 goto err_pm_disable;
133add5b
MR		 1044 }
1045
1046 ret = component_add(&pdev->dev, &sun6i_dsi_ops);
1047 if (ret) {
1048 dev_err(dev, "Couldn't register our component\n");
1049 goto err_remove_dsi_host;
1050 }
1051
1052 return 0;
1053
1054err_remove_dsi_host:
1055 mipi_dsi_host_unregister(&dsi->host);
bb3b6fcb 1056err_pm_disable:
133add5b 1057 pm_runtime_disable(dev);
133add5b
MR		 1058err_unprotect_clk:
1059 clk_rate_exclusive_put(dsi->mod_clk);
1060 return ret;
1061}
1062
1063static int sun6i_dsi_remove(struct platform_device *pdev)
1064{
1065 struct device *dev = &pdev->dev;
1066 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1067
1068 component_del(&pdev->dev, &sun6i_dsi_ops);
1069 mipi_dsi_host_unregister(&dsi->host);
1070 pm_runtime_disable(dev);
133add5b
MR		 1071 clk_rate_exclusive_put(dsi->mod_clk);
1072
1073 return 0;
1074}
1075
6b1c5eaf 1076static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev)
133add5b
MR		 1077{
1078 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1079
1080 reset_control_deassert(dsi->reset);
1081 clk_prepare_enable(dsi->mod_clk);
1082
1083 /*
1084 * Enable the DSI block.
1085 *
1086 * Some part of it can only be done once we get a number of
1087 * lanes, see sun6i_dsi_inst_init
1088 */
1089 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN);
1090
1091 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG,
1092 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN);
1093
1094 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10);
1095 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0);
1096
1097 if (dsi->device)
1098 sun6i_dsi_inst_init(dsi, dsi->device);
1099
1100 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff);
1101
1102 return 0;
1103}
1104
6b1c5eaf 1105static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev)
133add5b
MR		 1106{
1107 struct sun6i_dsi *dsi = dev_get_drvdata(dev);
1108
1109 clk_disable_unprepare(dsi->mod_clk);
1110 reset_control_assert(dsi->reset);
1111
1112 return 0;
1113}
1114
1115static const struct dev_pm_ops sun6i_dsi_pm_ops = {
1116 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend,
1117 sun6i_dsi_runtime_resume,
1118 NULL)
1119};
1120
1121static const struct of_device_id sun6i_dsi_of_table[] = {
1122 { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
1123 { }
1124};
1125MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
1126
1127static struct platform_driver sun6i_dsi_platform_driver = {
1128 .probe = sun6i_dsi_probe,
1129 .remove = sun6i_dsi_remove,
1130 .driver = {
1131 .name = "sun6i-mipi-dsi",
1132 .of_match_table = sun6i_dsi_of_table,
1133 .pm = &sun6i_dsi_pm_ops,
1134 },
1135};
1136module_platform_driver(sun6i_dsi_platform_driver);
1137
1138MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1139MODULE_DESCRIPTION("Allwinner A31 DSI Driver");
1140MODULE_LICENSE("GPL");
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