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35e62ae8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e0000163 | 2 | /* |
35b7fa4d | 3 | * CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface |
e0000163 CP |
4 | * |
5 | * MCP2510 support and bug fixes by Christian Pellegrin | |
6 | * <chripell@evolware.org> | |
7 | * | |
8 | * Copyright 2009 Christian Pellegrin EVOL S.r.l. | |
9 | * | |
10 | * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved. | |
11 | * Written under contract by: | |
12 | * Chris Elston, Katalix Systems, Ltd. | |
13 | * | |
14 | * Based on Microchip MCP251x CAN controller driver written by | |
15 | * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. | |
16 | * | |
17 | * Based on CAN bus driver for the CCAN controller written by | |
18 | * - Sascha Hauer, Marc Kleine-Budde, Pengutronix | |
19 | * - Simon Kallweit, intefo AG | |
20 | * Copyright 2007 | |
21 | * | |
e0000163 CP |
22 | * Your platform definition file should specify something like: |
23 | * | |
24 | * static struct mcp251x_platform_data mcp251x_info = { | |
25 | * .oscillator_frequency = 8000000, | |
e0000163 CP |
26 | * }; |
27 | * | |
28 | * static struct spi_board_info spi_board_info[] = { | |
29 | * { | |
f1f8c6cb | 30 | * .modalias = "mcp2510", |
35b7fa4d | 31 | * // "mcp2515" or "mcp25625" depending on your controller |
e0000163 CP |
32 | * .platform_data = &mcp251x_info, |
33 | * .irq = IRQ_EINT13, | |
34 | * .max_speed_hz = 2*1000*1000, | |
35 | * .chip_select = 2, | |
36 | * }, | |
37 | * }; | |
38 | * | |
39 | * Please see mcp251x.h for a description of the fields in | |
40 | * struct mcp251x_platform_data. | |
e0000163 CP |
41 | */ |
42 | ||
e0000163 CP |
43 | #include <linux/can/core.h> |
44 | #include <linux/can/dev.h> | |
eb072a9b | 45 | #include <linux/can/led.h> |
e0000163 | 46 | #include <linux/can/platform/mcp251x.h> |
66606aaf | 47 | #include <linux/clk.h> |
e0000163 CP |
48 | #include <linux/completion.h> |
49 | #include <linux/delay.h> | |
50 | #include <linux/device.h> | |
51 | #include <linux/dma-mapping.h> | |
52 | #include <linux/freezer.h> | |
53 | #include <linux/interrupt.h> | |
54 | #include <linux/io.h> | |
55 | #include <linux/kernel.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/netdevice.h> | |
66606aaf AS |
58 | #include <linux/of.h> |
59 | #include <linux/of_device.h> | |
e0000163 | 60 | #include <linux/platform_device.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
e0000163 CP |
62 | #include <linux/spi/spi.h> |
63 | #include <linux/uaccess.h> | |
1ddff7da | 64 | #include <linux/regulator/consumer.h> |
e0000163 CP |
65 | |
66 | /* SPI interface instruction set */ | |
67 | #define INSTRUCTION_WRITE 0x02 | |
68 | #define INSTRUCTION_READ 0x03 | |
69 | #define INSTRUCTION_BIT_MODIFY 0x05 | |
70 | #define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n)) | |
71 | #define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94) | |
72 | #define INSTRUCTION_RESET 0xC0 | |
cab32f39 BL |
73 | #define RTS_TXB0 0x01 |
74 | #define RTS_TXB1 0x02 | |
75 | #define RTS_TXB2 0x04 | |
76 | #define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07)) | |
77 | ||
e0000163 CP |
78 | |
79 | /* MPC251x registers */ | |
80 | #define CANSTAT 0x0e | |
81 | #define CANCTRL 0x0f | |
82 | # define CANCTRL_REQOP_MASK 0xe0 | |
83 | # define CANCTRL_REQOP_CONF 0x80 | |
84 | # define CANCTRL_REQOP_LISTEN_ONLY 0x60 | |
85 | # define CANCTRL_REQOP_LOOPBACK 0x40 | |
86 | # define CANCTRL_REQOP_SLEEP 0x20 | |
87 | # define CANCTRL_REQOP_NORMAL 0x00 | |
88 | # define CANCTRL_OSM 0x08 | |
89 | # define CANCTRL_ABAT 0x10 | |
90 | #define TEC 0x1c | |
91 | #define REC 0x1d | |
92 | #define CNF1 0x2a | |
93 | # define CNF1_SJW_SHIFT 6 | |
94 | #define CNF2 0x29 | |
95 | # define CNF2_BTLMODE 0x80 | |
96 | # define CNF2_SAM 0x40 | |
97 | # define CNF2_PS1_SHIFT 3 | |
98 | #define CNF3 0x28 | |
99 | # define CNF3_SOF 0x08 | |
100 | # define CNF3_WAKFIL 0x04 | |
101 | # define CNF3_PHSEG2_MASK 0x07 | |
102 | #define CANINTE 0x2b | |
103 | # define CANINTE_MERRE 0x80 | |
104 | # define CANINTE_WAKIE 0x40 | |
105 | # define CANINTE_ERRIE 0x20 | |
106 | # define CANINTE_TX2IE 0x10 | |
107 | # define CANINTE_TX1IE 0x08 | |
108 | # define CANINTE_TX0IE 0x04 | |
109 | # define CANINTE_RX1IE 0x02 | |
110 | # define CANINTE_RX0IE 0x01 | |
111 | #define CANINTF 0x2c | |
112 | # define CANINTF_MERRF 0x80 | |
113 | # define CANINTF_WAKIF 0x40 | |
114 | # define CANINTF_ERRIF 0x20 | |
115 | # define CANINTF_TX2IF 0x10 | |
116 | # define CANINTF_TX1IF 0x08 | |
117 | # define CANINTF_TX0IF 0x04 | |
118 | # define CANINTF_RX1IF 0x02 | |
119 | # define CANINTF_RX0IF 0x01 | |
5601b2df MKB |
120 | # define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF) |
121 | # define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF) | |
122 | # define CANINTF_ERR (CANINTF_ERRIF) | |
e0000163 CP |
123 | #define EFLG 0x2d |
124 | # define EFLG_EWARN 0x01 | |
125 | # define EFLG_RXWAR 0x02 | |
126 | # define EFLG_TXWAR 0x04 | |
127 | # define EFLG_RXEP 0x08 | |
128 | # define EFLG_TXEP 0x10 | |
129 | # define EFLG_TXBO 0x20 | |
130 | # define EFLG_RX0OVR 0x40 | |
131 | # define EFLG_RX1OVR 0x80 | |
132 | #define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF) | |
133 | # define TXBCTRL_ABTF 0x40 | |
134 | # define TXBCTRL_MLOA 0x20 | |
135 | # define TXBCTRL_TXERR 0x10 | |
136 | # define TXBCTRL_TXREQ 0x08 | |
137 | #define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF) | |
138 | # define SIDH_SHIFT 3 | |
139 | #define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF) | |
140 | # define SIDL_SID_MASK 7 | |
141 | # define SIDL_SID_SHIFT 5 | |
142 | # define SIDL_EXIDE_SHIFT 3 | |
143 | # define SIDL_EID_SHIFT 16 | |
144 | # define SIDL_EID_MASK 3 | |
145 | #define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF) | |
146 | #define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF) | |
147 | #define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF) | |
148 | # define DLC_RTR_SHIFT 6 | |
149 | #define TXBCTRL_OFF 0 | |
150 | #define TXBSIDH_OFF 1 | |
151 | #define TXBSIDL_OFF 2 | |
152 | #define TXBEID8_OFF 3 | |
153 | #define TXBEID0_OFF 4 | |
154 | #define TXBDLC_OFF 5 | |
155 | #define TXBDAT_OFF 6 | |
156 | #define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF) | |
157 | # define RXBCTRL_BUKT 0x04 | |
158 | # define RXBCTRL_RXM0 0x20 | |
159 | # define RXBCTRL_RXM1 0x40 | |
160 | #define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF) | |
161 | # define RXBSIDH_SHIFT 3 | |
162 | #define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF) | |
163 | # define RXBSIDL_IDE 0x08 | |
b9958a95 | 164 | # define RXBSIDL_SRR 0x10 |
e0000163 CP |
165 | # define RXBSIDL_EID 3 |
166 | # define RXBSIDL_SHIFT 5 | |
167 | #define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF) | |
168 | #define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF) | |
169 | #define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF) | |
170 | # define RXBDLC_LEN_MASK 0x0f | |
171 | # define RXBDLC_RTR 0x40 | |
172 | #define RXBCTRL_OFF 0 | |
173 | #define RXBSIDH_OFF 1 | |
174 | #define RXBSIDL_OFF 2 | |
175 | #define RXBEID8_OFF 3 | |
176 | #define RXBEID0_OFF 4 | |
177 | #define RXBDLC_OFF 5 | |
178 | #define RXBDAT_OFF 6 | |
3d5db5e1 TK |
179 | #define RXFSID(n) ((n < 3) ? 0 : 4) |
180 | #define RXFSIDH(n) ((n) * 4 + RXFSID(n)) | |
181 | #define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n)) | |
182 | #define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n)) | |
183 | #define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n)) | |
bf66f373 CP |
184 | #define RXMSIDH(n) ((n) * 4 + 0x20) |
185 | #define RXMSIDL(n) ((n) * 4 + 0x21) | |
186 | #define RXMEID8(n) ((n) * 4 + 0x22) | |
187 | #define RXMEID0(n) ((n) * 4 + 0x23) | |
e0000163 CP |
188 | |
189 | #define GET_BYTE(val, byte) \ | |
190 | (((val) >> ((byte) * 8)) & 0xff) | |
191 | #define SET_BYTE(val, byte) \ | |
192 | (((val) & 0xff) << ((byte) * 8)) | |
193 | ||
194 | /* | |
195 | * Buffer size required for the largest SPI transfer (i.e., reading a | |
196 | * frame) | |
197 | */ | |
198 | #define CAN_FRAME_MAX_DATA_LEN 8 | |
199 | #define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN) | |
200 | #define CAN_FRAME_MAX_BITS 128 | |
201 | ||
202 | #define TX_ECHO_SKB_MAX 1 | |
203 | ||
ff06d611 AS |
204 | #define MCP251X_OST_DELAY_MS (5) |
205 | ||
e0000163 CP |
206 | #define DEVICE_NAME "mcp251x" |
207 | ||
208 | static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */ | |
d61e4038 | 209 | module_param(mcp251x_enable_dma, int, 0444); |
e0000163 CP |
210 | MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)"); |
211 | ||
194b9a4c | 212 | static const struct can_bittiming_const mcp251x_bittiming_const = { |
e0000163 CP |
213 | .name = DEVICE_NAME, |
214 | .tseg1_min = 3, | |
215 | .tseg1_max = 16, | |
216 | .tseg2_min = 2, | |
217 | .tseg2_max = 8, | |
218 | .sjw_max = 4, | |
219 | .brp_min = 1, | |
220 | .brp_max = 64, | |
221 | .brp_inc = 1, | |
222 | }; | |
223 | ||
f1f8c6cb MKB |
224 | enum mcp251x_model { |
225 | CAN_MCP251X_MCP2510 = 0x2510, | |
226 | CAN_MCP251X_MCP2515 = 0x2515, | |
35b7fa4d | 227 | CAN_MCP251X_MCP25625 = 0x25625, |
f1f8c6cb MKB |
228 | }; |
229 | ||
e0000163 CP |
230 | struct mcp251x_priv { |
231 | struct can_priv can; | |
232 | struct net_device *net; | |
233 | struct spi_device *spi; | |
f1f8c6cb | 234 | enum mcp251x_model model; |
e0000163 | 235 | |
bf66f373 CP |
236 | struct mutex mcp_lock; /* SPI device lock */ |
237 | ||
e0000163 CP |
238 | u8 *spi_tx_buf; |
239 | u8 *spi_rx_buf; | |
240 | dma_addr_t spi_tx_dma; | |
241 | dma_addr_t spi_rx_dma; | |
242 | ||
243 | struct sk_buff *tx_skb; | |
244 | int tx_len; | |
bf66f373 | 245 | |
e0000163 CP |
246 | struct workqueue_struct *wq; |
247 | struct work_struct tx_work; | |
bf66f373 CP |
248 | struct work_struct restart_work; |
249 | ||
e0000163 CP |
250 | int force_quit; |
251 | int after_suspend; | |
252 | #define AFTER_SUSPEND_UP 1 | |
253 | #define AFTER_SUSPEND_DOWN 2 | |
254 | #define AFTER_SUSPEND_POWER 4 | |
255 | #define AFTER_SUSPEND_RESTART 8 | |
256 | int restart_tx; | |
1ddff7da AS |
257 | struct regulator *power; |
258 | struct regulator *transceiver; | |
66606aaf | 259 | struct clk *clk; |
e0000163 CP |
260 | }; |
261 | ||
beab675c MKB |
262 | #define MCP251X_IS(_model) \ |
263 | static inline int mcp251x_is_##_model(struct spi_device *spi) \ | |
264 | { \ | |
fce5c293 | 265 | struct mcp251x_priv *priv = spi_get_drvdata(spi); \ |
beab675c MKB |
266 | return priv->model == CAN_MCP251X_MCP##_model; \ |
267 | } | |
268 | ||
269 | MCP251X_IS(2510); | |
beab675c | 270 | |
e0000163 CP |
271 | static void mcp251x_clean(struct net_device *net) |
272 | { | |
273 | struct mcp251x_priv *priv = netdev_priv(net); | |
274 | ||
bf66f373 CP |
275 | if (priv->tx_skb || priv->tx_len) |
276 | net->stats.tx_errors++; | |
e0000163 CP |
277 | if (priv->tx_skb) |
278 | dev_kfree_skb(priv->tx_skb); | |
279 | if (priv->tx_len) | |
280 | can_free_echo_skb(priv->net, 0); | |
281 | priv->tx_skb = NULL; | |
282 | priv->tx_len = 0; | |
283 | } | |
284 | ||
285 | /* | |
286 | * Note about handling of error return of mcp251x_spi_trans: accessing | |
287 | * registers via SPI is not really different conceptually than using | |
288 | * normal I/O assembler instructions, although it's much more | |
289 | * complicated from a practical POV. So it's not advisable to always | |
290 | * check the return value of this function. Imagine that every | |
291 | * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0) | |
292 | * error();", it would be a great mess (well there are some situation | |
293 | * when exception handling C++ like could be useful after all). So we | |
294 | * just check that transfers are OK at the beginning of our | |
295 | * conversation with the chip and to avoid doing really nasty things | |
296 | * (like injecting bogus packets in the network stack). | |
297 | */ | |
298 | static int mcp251x_spi_trans(struct spi_device *spi, int len) | |
299 | { | |
fce5c293 | 300 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
301 | struct spi_transfer t = { |
302 | .tx_buf = priv->spi_tx_buf, | |
303 | .rx_buf = priv->spi_rx_buf, | |
304 | .len = len, | |
305 | .cs_change = 0, | |
306 | }; | |
307 | struct spi_message m; | |
308 | int ret; | |
309 | ||
310 | spi_message_init(&m); | |
311 | ||
312 | if (mcp251x_enable_dma) { | |
313 | t.tx_dma = priv->spi_tx_dma; | |
314 | t.rx_dma = priv->spi_rx_dma; | |
315 | m.is_dma_mapped = 1; | |
316 | } | |
317 | ||
318 | spi_message_add_tail(&t, &m); | |
319 | ||
320 | ret = spi_sync(spi, &m); | |
321 | if (ret) | |
322 | dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret); | |
323 | return ret; | |
324 | } | |
325 | ||
326 | static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) | |
327 | { | |
fce5c293 | 328 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
329 | u8 val = 0; |
330 | ||
e0000163 CP |
331 | priv->spi_tx_buf[0] = INSTRUCTION_READ; |
332 | priv->spi_tx_buf[1] = reg; | |
333 | ||
334 | mcp251x_spi_trans(spi, 3); | |
335 | val = priv->spi_rx_buf[2]; | |
336 | ||
e0000163 CP |
337 | return val; |
338 | } | |
339 | ||
f3a3ed31 SH |
340 | static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, |
341 | uint8_t *v1, uint8_t *v2) | |
342 | { | |
fce5c293 | 343 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
f3a3ed31 SH |
344 | |
345 | priv->spi_tx_buf[0] = INSTRUCTION_READ; | |
346 | priv->spi_tx_buf[1] = reg; | |
347 | ||
348 | mcp251x_spi_trans(spi, 4); | |
349 | ||
350 | *v1 = priv->spi_rx_buf[2]; | |
351 | *v2 = priv->spi_rx_buf[3]; | |
352 | } | |
353 | ||
e0000163 CP |
354 | static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) |
355 | { | |
fce5c293 | 356 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 | 357 | |
e0000163 CP |
358 | priv->spi_tx_buf[0] = INSTRUCTION_WRITE; |
359 | priv->spi_tx_buf[1] = reg; | |
360 | priv->spi_tx_buf[2] = val; | |
361 | ||
362 | mcp251x_spi_trans(spi, 3); | |
e0000163 CP |
363 | } |
364 | ||
365 | static void mcp251x_write_bits(struct spi_device *spi, u8 reg, | |
366 | u8 mask, uint8_t val) | |
367 | { | |
fce5c293 | 368 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 | 369 | |
e0000163 CP |
370 | priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY; |
371 | priv->spi_tx_buf[1] = reg; | |
372 | priv->spi_tx_buf[2] = mask; | |
373 | priv->spi_tx_buf[3] = val; | |
374 | ||
375 | mcp251x_spi_trans(spi, 4); | |
e0000163 CP |
376 | } |
377 | ||
378 | static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf, | |
379 | int len, int tx_buf_idx) | |
380 | { | |
fce5c293 | 381 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 | 382 | |
beab675c | 383 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
384 | int i; |
385 | ||
386 | for (i = 1; i < TXBDAT_OFF + len; i++) | |
387 | mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i, | |
388 | buf[i]); | |
389 | } else { | |
e0000163 CP |
390 | memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len); |
391 | mcp251x_spi_trans(spi, TXBDAT_OFF + len); | |
e0000163 CP |
392 | } |
393 | } | |
394 | ||
395 | static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame, | |
396 | int tx_buf_idx) | |
397 | { | |
fce5c293 | 398 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
399 | u32 sid, eid, exide, rtr; |
400 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
401 | ||
402 | exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */ | |
403 | if (exide) | |
404 | sid = (frame->can_id & CAN_EFF_MASK) >> 18; | |
405 | else | |
406 | sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */ | |
407 | eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */ | |
408 | rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */ | |
409 | ||
410 | buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx); | |
411 | buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT; | |
412 | buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) | | |
413 | (exide << SIDL_EXIDE_SHIFT) | | |
414 | ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK); | |
415 | buf[TXBEID8_OFF] = GET_BYTE(eid, 1); | |
416 | buf[TXBEID0_OFF] = GET_BYTE(eid, 0); | |
417 | buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc; | |
418 | memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc); | |
419 | mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx); | |
cab32f39 BL |
420 | |
421 | /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */ | |
422 | priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx); | |
423 | mcp251x_spi_trans(priv->spi, 1); | |
e0000163 CP |
424 | } |
425 | ||
426 | static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf, | |
427 | int buf_idx) | |
428 | { | |
fce5c293 | 429 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 | 430 | |
beab675c | 431 | if (mcp251x_is_2510(spi)) { |
e0000163 CP |
432 | int i, len; |
433 | ||
434 | for (i = 1; i < RXBDAT_OFF; i++) | |
435 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
c7cd606f OH |
436 | |
437 | len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); | |
e0000163 CP |
438 | for (; i < (RXBDAT_OFF + len); i++) |
439 | buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i); | |
440 | } else { | |
e0000163 CP |
441 | priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx); |
442 | mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN); | |
443 | memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN); | |
e0000163 CP |
444 | } |
445 | } | |
446 | ||
447 | static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx) | |
448 | { | |
fce5c293 | 449 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
450 | struct sk_buff *skb; |
451 | struct can_frame *frame; | |
452 | u8 buf[SPI_TRANSFER_BUF_LEN]; | |
453 | ||
454 | skb = alloc_can_skb(priv->net, &frame); | |
455 | if (!skb) { | |
456 | dev_err(&spi->dev, "cannot allocate RX skb\n"); | |
457 | priv->net->stats.rx_dropped++; | |
458 | return; | |
459 | } | |
460 | ||
461 | mcp251x_hw_rx_frame(spi, buf, buf_idx); | |
462 | if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) { | |
463 | /* Extended ID format */ | |
464 | frame->can_id = CAN_EFF_FLAG; | |
465 | frame->can_id |= | |
466 | /* Extended ID part */ | |
467 | SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) | | |
468 | SET_BYTE(buf[RXBEID8_OFF], 1) | | |
469 | SET_BYTE(buf[RXBEID0_OFF], 0) | | |
470 | /* Standard ID part */ | |
471 | (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
472 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18); | |
473 | /* Remote transmission request */ | |
474 | if (buf[RXBDLC_OFF] & RXBDLC_RTR) | |
475 | frame->can_id |= CAN_RTR_FLAG; | |
476 | } else { | |
477 | /* Standard ID format */ | |
478 | frame->can_id = | |
479 | (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) | | |
480 | (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT); | |
b9958a95 MKB |
481 | if (buf[RXBSIDL_OFF] & RXBSIDL_SRR) |
482 | frame->can_id |= CAN_RTR_FLAG; | |
e0000163 CP |
483 | } |
484 | /* Data length */ | |
c7cd606f | 485 | frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK); |
e0000163 CP |
486 | memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc); |
487 | ||
488 | priv->net->stats.rx_packets++; | |
489 | priv->net->stats.rx_bytes += frame->can_dlc; | |
eb072a9b FB |
490 | |
491 | can_led_event(priv->net, CAN_LED_EVENT_RX); | |
492 | ||
57d3c7b0 | 493 | netif_rx_ni(skb); |
e0000163 CP |
494 | } |
495 | ||
496 | static void mcp251x_hw_sleep(struct spi_device *spi) | |
497 | { | |
498 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP); | |
499 | } | |
500 | ||
e0000163 CP |
501 | static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb, |
502 | struct net_device *net) | |
503 | { | |
504 | struct mcp251x_priv *priv = netdev_priv(net); | |
505 | struct spi_device *spi = priv->spi; | |
506 | ||
507 | if (priv->tx_skb || priv->tx_len) { | |
508 | dev_warn(&spi->dev, "hard_xmit called while tx busy\n"); | |
e0000163 CP |
509 | return NETDEV_TX_BUSY; |
510 | } | |
511 | ||
3ccd4c61 | 512 | if (can_dropped_invalid_skb(net, skb)) |
e0000163 | 513 | return NETDEV_TX_OK; |
e0000163 CP |
514 | |
515 | netif_stop_queue(net); | |
516 | priv->tx_skb = skb; | |
e0000163 CP |
517 | queue_work(priv->wq, &priv->tx_work); |
518 | ||
519 | return NETDEV_TX_OK; | |
520 | } | |
521 | ||
522 | static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode) | |
523 | { | |
524 | struct mcp251x_priv *priv = netdev_priv(net); | |
525 | ||
526 | switch (mode) { | |
527 | case CAN_MODE_START: | |
bf66f373 | 528 | mcp251x_clean(net); |
e0000163 CP |
529 | /* We have to delay work since SPI I/O may sleep */ |
530 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
531 | priv->restart_tx = 1; | |
532 | if (priv->can.restart_ms == 0) | |
533 | priv->after_suspend = AFTER_SUSPEND_RESTART; | |
bf66f373 | 534 | queue_work(priv->wq, &priv->restart_work); |
e0000163 CP |
535 | break; |
536 | default: | |
537 | return -EOPNOTSUPP; | |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
bf66f373 | 543 | static int mcp251x_set_normal_mode(struct spi_device *spi) |
e0000163 | 544 | { |
fce5c293 | 545 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
546 | unsigned long timeout; |
547 | ||
548 | /* Enable interrupts */ | |
549 | mcp251x_write_reg(spi, CANINTE, | |
550 | CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE | | |
bf66f373 | 551 | CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE); |
e0000163 CP |
552 | |
553 | if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { | |
554 | /* Put device into loopback mode */ | |
555 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK); | |
ad72c347 CP |
556 | } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { |
557 | /* Put device into listen-only mode */ | |
558 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY); | |
e0000163 CP |
559 | } else { |
560 | /* Put device into normal mode */ | |
bf66f373 | 561 | mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL); |
e0000163 CP |
562 | |
563 | /* Wait for the device to enter normal mode */ | |
564 | timeout = jiffies + HZ; | |
565 | while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) { | |
566 | schedule(); | |
567 | if (time_after(jiffies, timeout)) { | |
568 | dev_err(&spi->dev, "MCP251x didn't" | |
569 | " enter in normal mode\n"); | |
bf66f373 | 570 | return -EBUSY; |
e0000163 CP |
571 | } |
572 | } | |
573 | } | |
574 | priv->can.state = CAN_STATE_ERROR_ACTIVE; | |
bf66f373 | 575 | return 0; |
e0000163 CP |
576 | } |
577 | ||
578 | static int mcp251x_do_set_bittiming(struct net_device *net) | |
579 | { | |
580 | struct mcp251x_priv *priv = netdev_priv(net); | |
581 | struct can_bittiming *bt = &priv->can.bittiming; | |
582 | struct spi_device *spi = priv->spi; | |
583 | ||
584 | mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) | | |
585 | (bt->brp - 1)); | |
586 | mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE | | |
587 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ? | |
588 | CNF2_SAM : 0) | | |
589 | ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) | | |
590 | (bt->prop_seg - 1)); | |
591 | mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK, | |
592 | (bt->phase_seg2 - 1)); | |
1e6cacdb AS |
593 | dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n", |
594 | mcp251x_read_reg(spi, CNF1), | |
595 | mcp251x_read_reg(spi, CNF2), | |
596 | mcp251x_read_reg(spi, CNF3)); | |
e0000163 CP |
597 | |
598 | return 0; | |
599 | } | |
600 | ||
aa681722 | 601 | static int mcp251x_setup(struct net_device *net, struct spi_device *spi) |
e0000163 | 602 | { |
615534bc | 603 | mcp251x_do_set_bittiming(net); |
e0000163 | 604 | |
bf66f373 CP |
605 | mcp251x_write_reg(spi, RXBCTRL(0), |
606 | RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
607 | mcp251x_write_reg(spi, RXBCTRL(1), | |
608 | RXBCTRL_RXM0 | RXBCTRL_RXM1); | |
e0000163 CP |
609 | return 0; |
610 | } | |
611 | ||
bf66f373 | 612 | static int mcp251x_hw_reset(struct spi_device *spi) |
e0000163 | 613 | { |
fce5c293 | 614 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
ff06d611 | 615 | u8 reg; |
e0000163 | 616 | int ret; |
ff06d611 AS |
617 | |
618 | /* Wait for oscillator startup timer after power up */ | |
619 | mdelay(MCP251X_OST_DELAY_MS); | |
e0000163 CP |
620 | |
621 | priv->spi_tx_buf[0] = INSTRUCTION_RESET; | |
ff06d611 AS |
622 | ret = mcp251x_spi_trans(spi, 1); |
623 | if (ret) | |
624 | return ret; | |
625 | ||
626 | /* Wait for oscillator startup timer after reset */ | |
627 | mdelay(MCP251X_OST_DELAY_MS); | |
35b7fa4d | 628 | |
ff06d611 AS |
629 | reg = mcp251x_read_reg(spi, CANSTAT); |
630 | if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF) | |
631 | return -ENODEV; | |
bf66f373 | 632 | |
bf66f373 | 633 | return 0; |
e0000163 CP |
634 | } |
635 | ||
636 | static int mcp251x_hw_probe(struct spi_device *spi) | |
637 | { | |
ee967fff AS |
638 | u8 ctrl; |
639 | int ret; | |
640 | ||
641 | ret = mcp251x_hw_reset(spi); | |
642 | if (ret) | |
643 | return ret; | |
e0000163 | 644 | |
ee967fff | 645 | ctrl = mcp251x_read_reg(spi, CANCTRL); |
e0000163 | 646 | |
ee967fff | 647 | dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl); |
e0000163 | 648 | |
ee967fff AS |
649 | /* Check for power up default value */ |
650 | if ((ctrl & 0x17) != 0x07) | |
651 | return -ENODEV; | |
e0000163 | 652 | |
ee967fff | 653 | return 0; |
e0000163 CP |
654 | } |
655 | ||
1ddff7da AS |
656 | static int mcp251x_power_enable(struct regulator *reg, int enable) |
657 | { | |
76aeec83 | 658 | if (IS_ERR_OR_NULL(reg)) |
1ddff7da AS |
659 | return 0; |
660 | ||
661 | if (enable) | |
662 | return regulator_enable(reg); | |
663 | else | |
664 | return regulator_disable(reg); | |
665 | } | |
666 | ||
e0000163 CP |
667 | static int mcp251x_stop(struct net_device *net) |
668 | { | |
669 | struct mcp251x_priv *priv = netdev_priv(net); | |
670 | struct spi_device *spi = priv->spi; | |
e0000163 CP |
671 | |
672 | close_candev(net); | |
673 | ||
bf66f373 CP |
674 | priv->force_quit = 1; |
675 | free_irq(spi->irq, priv); | |
676 | destroy_workqueue(priv->wq); | |
677 | priv->wq = NULL; | |
678 | ||
679 | mutex_lock(&priv->mcp_lock); | |
680 | ||
e0000163 CP |
681 | /* Disable and clear pending interrupts */ |
682 | mcp251x_write_reg(spi, CANINTE, 0x00); | |
683 | mcp251x_write_reg(spi, CANINTF, 0x00); | |
684 | ||
e0000163 | 685 | mcp251x_write_reg(spi, TXBCTRL(0), 0); |
bf66f373 | 686 | mcp251x_clean(net); |
e0000163 CP |
687 | |
688 | mcp251x_hw_sleep(spi); | |
689 | ||
1ddff7da | 690 | mcp251x_power_enable(priv->transceiver, 0); |
e0000163 CP |
691 | |
692 | priv->can.state = CAN_STATE_STOPPED; | |
693 | ||
bf66f373 CP |
694 | mutex_unlock(&priv->mcp_lock); |
695 | ||
eb072a9b FB |
696 | can_led_event(net, CAN_LED_EVENT_STOP); |
697 | ||
e0000163 CP |
698 | return 0; |
699 | } | |
700 | ||
bf66f373 CP |
701 | static void mcp251x_error_skb(struct net_device *net, int can_id, int data1) |
702 | { | |
703 | struct sk_buff *skb; | |
704 | struct can_frame *frame; | |
705 | ||
706 | skb = alloc_can_err_skb(net, &frame); | |
707 | if (skb) { | |
612eef4f | 708 | frame->can_id |= can_id; |
bf66f373 | 709 | frame->data[1] = data1; |
57d3c7b0 | 710 | netif_rx_ni(skb); |
bf66f373 | 711 | } else { |
aabdfd6a | 712 | netdev_err(net, "cannot allocate error skb\n"); |
bf66f373 CP |
713 | } |
714 | } | |
715 | ||
e0000163 CP |
716 | static void mcp251x_tx_work_handler(struct work_struct *ws) |
717 | { | |
718 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
719 | tx_work); | |
720 | struct spi_device *spi = priv->spi; | |
721 | struct net_device *net = priv->net; | |
722 | struct can_frame *frame; | |
723 | ||
bf66f373 | 724 | mutex_lock(&priv->mcp_lock); |
e0000163 | 725 | if (priv->tx_skb) { |
e0000163 CP |
726 | if (priv->can.state == CAN_STATE_BUS_OFF) { |
727 | mcp251x_clean(net); | |
bf66f373 CP |
728 | } else { |
729 | frame = (struct can_frame *)priv->tx_skb->data; | |
730 | ||
731 | if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN) | |
732 | frame->can_dlc = CAN_FRAME_MAX_DATA_LEN; | |
733 | mcp251x_hw_tx(spi, frame, 0); | |
734 | priv->tx_len = 1 + frame->can_dlc; | |
735 | can_put_echo_skb(priv->tx_skb, net, 0); | |
736 | priv->tx_skb = NULL; | |
e0000163 | 737 | } |
e0000163 | 738 | } |
bf66f373 | 739 | mutex_unlock(&priv->mcp_lock); |
e0000163 CP |
740 | } |
741 | ||
bf66f373 | 742 | static void mcp251x_restart_work_handler(struct work_struct *ws) |
e0000163 CP |
743 | { |
744 | struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv, | |
bf66f373 | 745 | restart_work); |
e0000163 CP |
746 | struct spi_device *spi = priv->spi; |
747 | struct net_device *net = priv->net; | |
e0000163 | 748 | |
bf66f373 | 749 | mutex_lock(&priv->mcp_lock); |
e0000163 | 750 | if (priv->after_suspend) { |
e0000163 | 751 | mcp251x_hw_reset(spi); |
aa681722 | 752 | mcp251x_setup(net, spi); |
e0000163 CP |
753 | if (priv->after_suspend & AFTER_SUSPEND_RESTART) { |
754 | mcp251x_set_normal_mode(spi); | |
755 | } else if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
756 | netif_device_attach(net); | |
bf66f373 | 757 | mcp251x_clean(net); |
e0000163 | 758 | mcp251x_set_normal_mode(spi); |
bf66f373 | 759 | netif_wake_queue(net); |
e0000163 CP |
760 | } else { |
761 | mcp251x_hw_sleep(spi); | |
762 | } | |
763 | priv->after_suspend = 0; | |
bf66f373 | 764 | priv->force_quit = 0; |
e0000163 CP |
765 | } |
766 | ||
bf66f373 CP |
767 | if (priv->restart_tx) { |
768 | priv->restart_tx = 0; | |
769 | mcp251x_write_reg(spi, TXBCTRL(0), 0); | |
770 | mcp251x_clean(net); | |
771 | netif_wake_queue(net); | |
772 | mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0); | |
773 | } | |
774 | mutex_unlock(&priv->mcp_lock); | |
775 | } | |
e0000163 | 776 | |
bf66f373 CP |
777 | static irqreturn_t mcp251x_can_ist(int irq, void *dev_id) |
778 | { | |
779 | struct mcp251x_priv *priv = dev_id; | |
780 | struct spi_device *spi = priv->spi; | |
781 | struct net_device *net = priv->net; | |
e0000163 | 782 | |
bf66f373 CP |
783 | mutex_lock(&priv->mcp_lock); |
784 | while (!priv->force_quit) { | |
785 | enum can_state new_state; | |
f3a3ed31 | 786 | u8 intf, eflag; |
d3cd1565 | 787 | u8 clear_intf = 0; |
bf66f373 | 788 | int can_id = 0, data1 = 0; |
e0000163 | 789 | |
f3a3ed31 SH |
790 | mcp251x_read_2regs(spi, CANINTF, &intf, &eflag); |
791 | ||
5601b2df MKB |
792 | /* mask out flags we don't care about */ |
793 | intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR; | |
794 | ||
d3cd1565 | 795 | /* receive buffer 0 */ |
bf66f373 CP |
796 | if (intf & CANINTF_RX0IF) { |
797 | mcp251x_hw_rx(spi, 0); | |
35b7fa4d SN |
798 | /* Free one buffer ASAP |
799 | * (The MCP2515/25625 does this automatically.) | |
9c473fc3 MKB |
800 | */ |
801 | if (mcp251x_is_2510(spi)) | |
802 | mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00); | |
e0000163 CP |
803 | } |
804 | ||
d3cd1565 MKB |
805 | /* receive buffer 1 */ |
806 | if (intf & CANINTF_RX1IF) { | |
bf66f373 | 807 | mcp251x_hw_rx(spi, 1); |
35b7fa4d | 808 | /* The MCP2515/25625 does this automatically. */ |
9c473fc3 MKB |
809 | if (mcp251x_is_2510(spi)) |
810 | clear_intf |= CANINTF_RX1IF; | |
d3cd1565 | 811 | } |
e0000163 | 812 | |
d3cd1565 | 813 | /* any error or tx interrupt we need to clear? */ |
5601b2df MKB |
814 | if (intf & (CANINTF_ERR | CANINTF_TX)) |
815 | clear_intf |= intf & (CANINTF_ERR | CANINTF_TX); | |
d3cd1565 MKB |
816 | if (clear_intf) |
817 | mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00); | |
e0000163 | 818 | |
d694b06c | 819 | if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) |
7e15de3a | 820 | mcp251x_write_bits(spi, EFLG, eflag, 0x00); |
bf66f373 | 821 | |
e0000163 CP |
822 | /* Update can state */ |
823 | if (eflag & EFLG_TXBO) { | |
824 | new_state = CAN_STATE_BUS_OFF; | |
825 | can_id |= CAN_ERR_BUSOFF; | |
826 | } else if (eflag & EFLG_TXEP) { | |
827 | new_state = CAN_STATE_ERROR_PASSIVE; | |
828 | can_id |= CAN_ERR_CRTL; | |
829 | data1 |= CAN_ERR_CRTL_TX_PASSIVE; | |
830 | } else if (eflag & EFLG_RXEP) { | |
831 | new_state = CAN_STATE_ERROR_PASSIVE; | |
832 | can_id |= CAN_ERR_CRTL; | |
833 | data1 |= CAN_ERR_CRTL_RX_PASSIVE; | |
834 | } else if (eflag & EFLG_TXWAR) { | |
835 | new_state = CAN_STATE_ERROR_WARNING; | |
836 | can_id |= CAN_ERR_CRTL; | |
837 | data1 |= CAN_ERR_CRTL_TX_WARNING; | |
838 | } else if (eflag & EFLG_RXWAR) { | |
839 | new_state = CAN_STATE_ERROR_WARNING; | |
840 | can_id |= CAN_ERR_CRTL; | |
841 | data1 |= CAN_ERR_CRTL_RX_WARNING; | |
842 | } else { | |
843 | new_state = CAN_STATE_ERROR_ACTIVE; | |
844 | } | |
845 | ||
846 | /* Update can state statistics */ | |
847 | switch (priv->can.state) { | |
848 | case CAN_STATE_ERROR_ACTIVE: | |
849 | if (new_state >= CAN_STATE_ERROR_WARNING && | |
850 | new_state <= CAN_STATE_BUS_OFF) | |
851 | priv->can.can_stats.error_warning++; | |
5a8dadbc GS |
852 | /* fall through */ |
853 | case CAN_STATE_ERROR_WARNING: | |
e0000163 CP |
854 | if (new_state >= CAN_STATE_ERROR_PASSIVE && |
855 | new_state <= CAN_STATE_BUS_OFF) | |
856 | priv->can.can_stats.error_passive++; | |
857 | break; | |
858 | default: | |
859 | break; | |
860 | } | |
861 | priv->can.state = new_state; | |
862 | ||
bf66f373 CP |
863 | if (intf & CANINTF_ERRIF) { |
864 | /* Handle overflow counters */ | |
865 | if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) { | |
711e4d6e | 866 | if (eflag & EFLG_RX0OVR) { |
bf66f373 | 867 | net->stats.rx_over_errors++; |
711e4d6e SH |
868 | net->stats.rx_errors++; |
869 | } | |
870 | if (eflag & EFLG_RX1OVR) { | |
bf66f373 | 871 | net->stats.rx_over_errors++; |
711e4d6e SH |
872 | net->stats.rx_errors++; |
873 | } | |
bf66f373 CP |
874 | can_id |= CAN_ERR_CRTL; |
875 | data1 |= CAN_ERR_CRTL_RX_OVERFLOW; | |
e0000163 | 876 | } |
bf66f373 | 877 | mcp251x_error_skb(net, can_id, data1); |
e0000163 CP |
878 | } |
879 | ||
880 | if (priv->can.state == CAN_STATE_BUS_OFF) { | |
881 | if (priv->can.restart_ms == 0) { | |
bf66f373 | 882 | priv->force_quit = 1; |
be38a6f9 | 883 | priv->can.can_stats.bus_off++; |
e0000163 CP |
884 | can_bus_off(net); |
885 | mcp251x_hw_sleep(spi); | |
bf66f373 | 886 | break; |
e0000163 CP |
887 | } |
888 | } | |
889 | ||
890 | if (intf == 0) | |
891 | break; | |
892 | ||
5601b2df | 893 | if (intf & CANINTF_TX) { |
e0000163 CP |
894 | net->stats.tx_packets++; |
895 | net->stats.tx_bytes += priv->tx_len - 1; | |
eb072a9b | 896 | can_led_event(net, CAN_LED_EVENT_TX); |
e0000163 CP |
897 | if (priv->tx_len) { |
898 | can_get_echo_skb(net, 0); | |
899 | priv->tx_len = 0; | |
900 | } | |
901 | netif_wake_queue(net); | |
902 | } | |
903 | ||
bf66f373 CP |
904 | } |
905 | mutex_unlock(&priv->mcp_lock); | |
906 | return IRQ_HANDLED; | |
907 | } | |
e0000163 | 908 | |
bf66f373 CP |
909 | static int mcp251x_open(struct net_device *net) |
910 | { | |
911 | struct mcp251x_priv *priv = netdev_priv(net); | |
912 | struct spi_device *spi = priv->spi; | |
ae5d589e | 913 | unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING; |
bf66f373 CP |
914 | int ret; |
915 | ||
916 | ret = open_candev(net); | |
917 | if (ret) { | |
918 | dev_err(&spi->dev, "unable to set initial baudrate!\n"); | |
919 | return ret; | |
920 | } | |
921 | ||
922 | mutex_lock(&priv->mcp_lock); | |
1ddff7da | 923 | mcp251x_power_enable(priv->transceiver, 1); |
bf66f373 CP |
924 | |
925 | priv->force_quit = 0; | |
926 | priv->tx_skb = NULL; | |
927 | priv->tx_len = 0; | |
928 | ||
929 | ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist, | |
e1dfefeb | 930 | flags | IRQF_ONESHOT, DEVICE_NAME, priv); |
bf66f373 CP |
931 | if (ret) { |
932 | dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq); | |
375f7558 | 933 | goto out_close; |
bf66f373 CP |
934 | } |
935 | ||
b6fd3aba AKC |
936 | priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM, |
937 | 0); | |
375f7558 WH |
938 | if (!priv->wq) { |
939 | ret = -ENOMEM; | |
940 | goto out_clean; | |
941 | } | |
bf66f373 CP |
942 | INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler); |
943 | INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler); | |
944 | ||
945 | ret = mcp251x_hw_reset(spi); | |
375f7558 WH |
946 | if (ret) |
947 | goto out_free_wq; | |
aa681722 | 948 | ret = mcp251x_setup(net, spi); |
375f7558 WH |
949 | if (ret) |
950 | goto out_free_wq; | |
bf66f373 | 951 | ret = mcp251x_set_normal_mode(spi); |
375f7558 WH |
952 | if (ret) |
953 | goto out_free_wq; | |
eb072a9b FB |
954 | |
955 | can_led_event(net, CAN_LED_EVENT_OPEN); | |
956 | ||
bf66f373 | 957 | netif_wake_queue(net); |
375f7558 | 958 | mutex_unlock(&priv->mcp_lock); |
bf66f373 | 959 | |
375f7558 WH |
960 | return 0; |
961 | ||
962 | out_free_wq: | |
963 | destroy_workqueue(priv->wq); | |
964 | out_clean: | |
965 | free_irq(spi->irq, priv); | |
966 | mcp251x_hw_sleep(spi); | |
967 | out_close: | |
968 | mcp251x_power_enable(priv->transceiver, 0); | |
969 | close_candev(net); | |
bf66f373 CP |
970 | mutex_unlock(&priv->mcp_lock); |
971 | return ret; | |
e0000163 CP |
972 | } |
973 | ||
974 | static const struct net_device_ops mcp251x_netdev_ops = { | |
975 | .ndo_open = mcp251x_open, | |
976 | .ndo_stop = mcp251x_stop, | |
977 | .ndo_start_xmit = mcp251x_hard_start_xmit, | |
c971fa2a | 978 | .ndo_change_mtu = can_change_mtu, |
e0000163 CP |
979 | }; |
980 | ||
66606aaf AS |
981 | static const struct of_device_id mcp251x_of_match[] = { |
982 | { | |
983 | .compatible = "microchip,mcp2510", | |
984 | .data = (void *)CAN_MCP251X_MCP2510, | |
985 | }, | |
986 | { | |
987 | .compatible = "microchip,mcp2515", | |
988 | .data = (void *)CAN_MCP251X_MCP2515, | |
989 | }, | |
35b7fa4d SN |
990 | { |
991 | .compatible = "microchip,mcp25625", | |
992 | .data = (void *)CAN_MCP251X_MCP25625, | |
993 | }, | |
66606aaf AS |
994 | { } |
995 | }; | |
996 | MODULE_DEVICE_TABLE(of, mcp251x_of_match); | |
997 | ||
998 | static const struct spi_device_id mcp251x_id_table[] = { | |
999 | { | |
1000 | .name = "mcp2510", | |
1001 | .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510, | |
1002 | }, | |
1003 | { | |
1004 | .name = "mcp2515", | |
1005 | .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515, | |
1006 | }, | |
35b7fa4d SN |
1007 | { |
1008 | .name = "mcp25625", | |
1009 | .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625, | |
1010 | }, | |
66606aaf AS |
1011 | { } |
1012 | }; | |
1013 | MODULE_DEVICE_TABLE(spi, mcp251x_id_table); | |
1014 | ||
3c8ac0f2 | 1015 | static int mcp251x_can_probe(struct spi_device *spi) |
e0000163 | 1016 | { |
66606aaf AS |
1017 | const struct of_device_id *of_id = of_match_device(mcp251x_of_match, |
1018 | &spi->dev); | |
1019 | struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev); | |
e0000163 CP |
1020 | struct net_device *net; |
1021 | struct mcp251x_priv *priv; | |
66606aaf | 1022 | struct clk *clk; |
31473c28 | 1023 | int freq, ret; |
66606aaf AS |
1024 | |
1025 | clk = devm_clk_get(&spi->dev, NULL); | |
1026 | if (IS_ERR(clk)) { | |
1027 | if (pdata) | |
1028 | freq = pdata->oscillator_frequency; | |
1029 | else | |
1030 | return PTR_ERR(clk); | |
1031 | } else { | |
1032 | freq = clk_get_rate(clk); | |
1033 | } | |
e0000163 | 1034 | |
66606aaf AS |
1035 | /* Sanity check */ |
1036 | if (freq < 1000000 || freq > 25000000) | |
1037 | return -ERANGE; | |
e0000163 CP |
1038 | |
1039 | /* Allocate can/net device */ | |
1040 | net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX); | |
66606aaf AS |
1041 | if (!net) |
1042 | return -ENOMEM; | |
1043 | ||
1044 | if (!IS_ERR(clk)) { | |
1045 | ret = clk_prepare_enable(clk); | |
1046 | if (ret) | |
1047 | goto out_free; | |
e0000163 CP |
1048 | } |
1049 | ||
1050 | net->netdev_ops = &mcp251x_netdev_ops; | |
1051 | net->flags |= IFF_ECHO; | |
1052 | ||
1053 | priv = netdev_priv(net); | |
1054 | priv->can.bittiming_const = &mcp251x_bittiming_const; | |
1055 | priv->can.do_set_mode = mcp251x_do_set_mode; | |
66606aaf | 1056 | priv->can.clock.freq = freq / 2; |
ad72c347 CP |
1057 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | |
1058 | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; | |
66606aaf AS |
1059 | if (of_id) |
1060 | priv->model = (enum mcp251x_model)of_id->data; | |
1061 | else | |
1062 | priv->model = spi_get_device_id(spi)->driver_data; | |
e0000163 | 1063 | priv->net = net; |
66606aaf | 1064 | priv->clk = clk; |
1ddff7da | 1065 | |
31473c28 AS |
1066 | spi_set_drvdata(spi, priv); |
1067 | ||
1068 | /* Configure the SPI bus */ | |
1069 | spi->bits_per_word = 8; | |
1070 | if (mcp251x_is_2510(spi)) | |
1071 | spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000; | |
1072 | else | |
1073 | spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000; | |
1074 | ret = spi_setup(spi); | |
1075 | if (ret) | |
1076 | goto out_clk; | |
1077 | ||
69da3f2a SA |
1078 | priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); |
1079 | priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); | |
1ddff7da AS |
1080 | if ((PTR_ERR(priv->power) == -EPROBE_DEFER) || |
1081 | (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) { | |
1082 | ret = -EPROBE_DEFER; | |
66606aaf | 1083 | goto out_clk; |
1ddff7da AS |
1084 | } |
1085 | ||
1086 | ret = mcp251x_power_enable(priv->power, 1); | |
1087 | if (ret) | |
66606aaf | 1088 | goto out_clk; |
1ddff7da | 1089 | |
e0000163 | 1090 | priv->spi = spi; |
bf66f373 | 1091 | mutex_init(&priv->mcp_lock); |
e0000163 CP |
1092 | |
1093 | /* If requested, allocate DMA buffers */ | |
1094 | if (mcp251x_enable_dma) { | |
1095 | spi->dev.coherent_dma_mask = ~0; | |
1096 | ||
1097 | /* | |
1098 | * Minimum coherent DMA allocation is PAGE_SIZE, so allocate | |
1099 | * that much and share it between Tx and Rx DMA buffers. | |
1100 | */ | |
3a73aeff HS |
1101 | priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev, |
1102 | PAGE_SIZE, | |
1103 | &priv->spi_tx_dma, | |
1104 | GFP_DMA); | |
e0000163 CP |
1105 | |
1106 | if (priv->spi_tx_buf) { | |
c2fd03a0 | 1107 | priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2)); |
e0000163 CP |
1108 | priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma + |
1109 | (PAGE_SIZE / 2)); | |
1110 | } else { | |
1111 | /* Fall back to non-DMA */ | |
1112 | mcp251x_enable_dma = 0; | |
1113 | } | |
1114 | } | |
1115 | ||
1116 | /* Allocate non-DMA buffers */ | |
1117 | if (!mcp251x_enable_dma) { | |
21629e1a AS |
1118 | priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, |
1119 | GFP_KERNEL); | |
e0000163 CP |
1120 | if (!priv->spi_tx_buf) { |
1121 | ret = -ENOMEM; | |
21629e1a | 1122 | goto error_probe; |
e0000163 | 1123 | } |
21629e1a AS |
1124 | priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN, |
1125 | GFP_KERNEL); | |
ce739b47 | 1126 | if (!priv->spi_rx_buf) { |
e0000163 | 1127 | ret = -ENOMEM; |
21629e1a | 1128 | goto error_probe; |
e0000163 CP |
1129 | } |
1130 | } | |
1131 | ||
e0000163 CP |
1132 | SET_NETDEV_DEV(net, &spi->dev); |
1133 | ||
bf66f373 | 1134 | /* Here is OK to not lock the MCP, no one knows about it yet */ |
ee967fff | 1135 | ret = mcp251x_hw_probe(spi); |
b63f69d0 ES |
1136 | if (ret) { |
1137 | if (ret == -ENODEV) | |
1138 | dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n", priv->model); | |
e0000163 | 1139 | goto error_probe; |
b63f69d0 | 1140 | } |
ee967fff | 1141 | |
e0000163 CP |
1142 | mcp251x_hw_sleep(spi); |
1143 | ||
e0000163 | 1144 | ret = register_candev(net); |
eb072a9b FB |
1145 | if (ret) |
1146 | goto error_probe; | |
1147 | ||
1148 | devm_can_led_init(net); | |
1149 | ||
b63f69d0 | 1150 | netdev_info(net, "MCP%x successfully initialized.\n", priv->model); |
ee967fff | 1151 | return 0; |
eb072a9b | 1152 | |
e0000163 | 1153 | error_probe: |
1ddff7da | 1154 | mcp251x_power_enable(priv->power, 0); |
66606aaf AS |
1155 | |
1156 | out_clk: | |
1157 | if (!IS_ERR(clk)) | |
1158 | clk_disable_unprepare(clk); | |
1159 | ||
1160 | out_free: | |
1ddff7da | 1161 | free_candev(net); |
66606aaf | 1162 | |
b63f69d0 | 1163 | dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); |
e0000163 CP |
1164 | return ret; |
1165 | } | |
1166 | ||
3c8ac0f2 | 1167 | static int mcp251x_can_remove(struct spi_device *spi) |
e0000163 | 1168 | { |
fce5c293 | 1169 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
1170 | struct net_device *net = priv->net; |
1171 | ||
1172 | unregister_candev(net); | |
e0000163 | 1173 | |
1ddff7da AS |
1174 | mcp251x_power_enable(priv->power, 0); |
1175 | ||
66606aaf AS |
1176 | if (!IS_ERR(priv->clk)) |
1177 | clk_disable_unprepare(priv->clk); | |
1178 | ||
1ddff7da | 1179 | free_candev(net); |
e0000163 CP |
1180 | |
1181 | return 0; | |
1182 | } | |
1183 | ||
f16a4210 | 1184 | static int __maybe_unused mcp251x_can_suspend(struct device *dev) |
e0000163 | 1185 | { |
612b2a97 | 1186 | struct spi_device *spi = to_spi_device(dev); |
fce5c293 | 1187 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 CP |
1188 | struct net_device *net = priv->net; |
1189 | ||
bf66f373 CP |
1190 | priv->force_quit = 1; |
1191 | disable_irq(spi->irq); | |
1192 | /* | |
1193 | * Note: at this point neither IST nor workqueues are running. | |
1194 | * open/stop cannot be called anyway so locking is not needed | |
1195 | */ | |
e0000163 CP |
1196 | if (netif_running(net)) { |
1197 | netif_device_detach(net); | |
1198 | ||
1199 | mcp251x_hw_sleep(spi); | |
1ddff7da | 1200 | mcp251x_power_enable(priv->transceiver, 0); |
e0000163 CP |
1201 | priv->after_suspend = AFTER_SUSPEND_UP; |
1202 | } else { | |
1203 | priv->after_suspend = AFTER_SUSPEND_DOWN; | |
1204 | } | |
1205 | ||
76aeec83 | 1206 | if (!IS_ERR_OR_NULL(priv->power)) { |
1ddff7da | 1207 | regulator_disable(priv->power); |
e0000163 CP |
1208 | priv->after_suspend |= AFTER_SUSPEND_POWER; |
1209 | } | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
f16a4210 | 1214 | static int __maybe_unused mcp251x_can_resume(struct device *dev) |
e0000163 | 1215 | { |
612b2a97 | 1216 | struct spi_device *spi = to_spi_device(dev); |
fce5c293 | 1217 | struct mcp251x_priv *priv = spi_get_drvdata(spi); |
e0000163 | 1218 | |
25b401c1 | 1219 | if (priv->after_suspend & AFTER_SUSPEND_POWER) |
1ddff7da | 1220 | mcp251x_power_enable(priv->power, 1); |
25b401c1 SA |
1221 | |
1222 | if (priv->after_suspend & AFTER_SUSPEND_UP) { | |
1223 | mcp251x_power_enable(priv->transceiver, 1); | |
bf66f373 | 1224 | queue_work(priv->wq, &priv->restart_work); |
e0000163 | 1225 | } else { |
25b401c1 | 1226 | priv->after_suspend = 0; |
e0000163 | 1227 | } |
25b401c1 | 1228 | |
bf66f373 CP |
1229 | priv->force_quit = 0; |
1230 | enable_irq(spi->irq); | |
e0000163 CP |
1231 | return 0; |
1232 | } | |
612b2a97 LPC |
1233 | |
1234 | static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend, | |
1235 | mcp251x_can_resume); | |
e0000163 CP |
1236 | |
1237 | static struct spi_driver mcp251x_can_driver = { | |
1238 | .driver = { | |
1239 | .name = DEVICE_NAME, | |
66606aaf | 1240 | .of_match_table = mcp251x_of_match, |
4fcc999e | 1241 | .pm = &mcp251x_can_pm_ops, |
e0000163 | 1242 | }, |
e446630c | 1243 | .id_table = mcp251x_id_table, |
e0000163 | 1244 | .probe = mcp251x_can_probe, |
3c8ac0f2 | 1245 | .remove = mcp251x_can_remove, |
e0000163 | 1246 | }; |
01b88070 | 1247 | module_spi_driver(mcp251x_can_driver); |
e0000163 CP |
1248 | |
1249 | MODULE_AUTHOR("Chris Elston <celston@katalix.com>, " | |
1250 | "Christian Pellegrin <chripell@evolware.org>"); | |
35b7fa4d | 1251 | MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver"); |
e0000163 | 1252 | MODULE_LICENSE("GPL v2"); |