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bnx2x: Remove configured vlans as part of unload sequence.
[thirdparty/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
CommitLineData
4ad79e13 1/* bnx2x_main.c: QLogic Everest network driver.
a2fbb9ea 2 *
247fa82b 3 * Copyright (c) 2007-2013 Broadcom Corporation
4ad79e13
YM		 4 * Copyright (c) 2014 QLogic Corporation
5 * All rights reserved
a2fbb9ea
ET		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
10 *
08f6dd89 11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
24e3fcef 12 * Written by: Eliezer Tamir
a2fbb9ea
ET		 13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
ca00392c 15 * Slowpath and fastpath rework by Vladislav Zolotarov
c14423fe 16 * Statistics and Link management by Yitchak Gertner
a2fbb9ea
ET		 17 *
18 */
19
f1deab50
JP		 20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
a2fbb9ea
ET		 22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/kernel.h>
25#include <linux/device.h> /* for dev_info() */
26#include <linux/timer.h>
27#include <linux/errno.h>
28#include <linux/ioport.h>
29#include <linux/slab.h>
a2fbb9ea
ET		 30#include <linux/interrupt.h>
31#include <linux/pci.h>
33d8e6a5 32#include <linux/aer.h>
a2fbb9ea
ET		 33#include <linux/init.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/dma-mapping.h>
38#include <linux/bitops.h>
39#include <linux/irq.h>
40#include <linux/delay.h>
41#include <asm/byteorder.h>
42#include <linux/time.h>
43#include <linux/ethtool.h>
44#include <linux/mii.h>
0c6671b0 45#include <linux/if_vlan.h>
c9931896 46#include <linux/crash_dump.h>
a2fbb9ea 47#include <net/ip.h>
619c5cb6 48#include <net/ipv6.h>
a2fbb9ea 49#include <net/tcp.h>
51de7bb9 50#include <net/vxlan.h>
a2fbb9ea 51#include <net/checksum.h>
34f80b04 52#include <net/ip6_checksum.h>
a2fbb9ea
ET		 53#include <linux/workqueue.h>
54#include <linux/crc32.h>
34f80b04 55#include <linux/crc32c.h>
a2fbb9ea
ET		 56#include <linux/prefetch.h>
57#include <linux/zlib.h>
a2fbb9ea 58#include <linux/io.h>
452427b0 59#include <linux/semaphore.h>
45229b42 60#include <linux/stringify.h>
7ab24bfd 61#include <linux/vmalloc.h>
a2fbb9ea
ET		 62#include "bnx2x.h"
63#include "bnx2x_init.h"
94a78b79 64#include "bnx2x_init_ops.h"
9f6c9258 65#include "bnx2x_cmn.h"
1ab4434c 66#include "bnx2x_vfpf.h"
e4901dde 67#include "bnx2x_dcb.h"
042181f5 68#include "bnx2x_sp.h"
94a78b79
VZ		 69#include <linux/firmware.h>
70#include "bnx2x_fw_file_hdr.h"
71/* FW files */
45229b42
BH		 72#define FW_FILE_VERSION \
73 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
74 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
75 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
76 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
560131f3
DK		 77#define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
78#define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
f2e0899f 79#define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
94a78b79 80
34f80b04
EG		 81/* Time in jiffies before concluding the transmitter is hung */
82#define TX_TIMEOUT (5*HZ)
a2fbb9ea 83
0329aba1 84static char version[] =
4ad79e13 85 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
a2fbb9ea
ET		 86 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
87
24e3fcef 88MODULE_AUTHOR("Eliezer Tamir");
4ad79e13 89MODULE_DESCRIPTION("QLogic "
619c5cb6
VZ		 90 "BCM57710/57711/57711E/"
91 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
92 "57840/57840_MF Driver");
a2fbb9ea
ET		 93MODULE_LICENSE("GPL");
94MODULE_VERSION(DRV_MODULE_VERSION);
45229b42
BH		 95MODULE_FIRMWARE(FW_FILE_NAME_E1);
96MODULE_FIRMWARE(FW_FILE_NAME_E1H);
f2e0899f 97MODULE_FIRMWARE(FW_FILE_NAME_E2);
a2fbb9ea 98
a8f47eb7 99int bnx2x_num_queues;
d3757ba4 100module_param_named(num_queues, bnx2x_num_queues, int, 0444);
96305234
DK		 101MODULE_PARM_DESC(num_queues,
102 " Set number of queues (default is as a number of CPUs)");
555f6c78 103
19680c48 104static int disable_tpa;
d3757ba4 105module_param(disable_tpa, int, 0444);
9898f86d 106MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
8badd27a 107
a8f47eb7 108static int int_mode;
d3757ba4 109module_param(int_mode, int, 0444);
619c5cb6 110MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
cdaa7cb8 111 "(1 INT#x; 2 MSI)");
8badd27a 112
a18f5128 113static int dropless_fc;
d3757ba4 114module_param(dropless_fc, int, 0444);
a18f5128
EG		 115MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
8d5726c4 117static int mrrs = -1;
d3757ba4 118module_param(mrrs, int, 0444);
8d5726c4
EG		 119MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120
9898f86d 121static int debug;
d3757ba4 122module_param(debug, int, 0444);
9898f86d
EG		 123MODULE_PARM_DESC(debug, " Default debug msglevel");
124
370d4a26
YM		 125static struct workqueue_struct *bnx2x_wq;
126struct workqueue_struct *bnx2x_iov_wq;
ec6ba945 127
1ef1d45a
BW		 128struct bnx2x_mac_vals {
129 u32 xmac_addr;
130 u32 xmac_val;
131 u32 emac_addr;
132 u32 emac_val;
3d6b7253
YM		 133 u32 umac_addr[2];
134 u32 umac_val[2];
1ef1d45a
BW		 135 u32 bmac_addr;
136 u32 bmac_val[2];
137};
138
a2fbb9ea
ET		 139enum bnx2x_board_type {
140 BCM57710 = 0,
619c5cb6
VZ		 141 BCM57711,
142 BCM57711E,
143 BCM57712,
144 BCM57712_MF,
1ab4434c 145 BCM57712_VF,
619c5cb6
VZ		 146 BCM57800,
147 BCM57800_MF,
1ab4434c 148 BCM57800_VF,
619c5cb6
VZ		 149 BCM57810,
150 BCM57810_MF,
1ab4434c 151 BCM57810_VF,
c3def943
YM		 152 BCM57840_4_10,
153 BCM57840_2_20,
7e8e02df 154 BCM57840_MF,
1ab4434c 155 BCM57840_VF,
7e8e02df 156 BCM57811,
1ab4434c
AE		 157 BCM57811_MF,
158 BCM57840_O,
159 BCM57840_MFO,
160 BCM57811_VF
a2fbb9ea
ET		 161};
162
34f80b04 163/* indexed by board_type, above */
53a10565 164static struct {
a2fbb9ea 165 char *name;
0329aba1 166} board_info[] = {
4ad79e13
YM		 167 [BCM57710] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
168 [BCM57711] = { "QLogic BCM57711 10 Gigabit PCIe" },
169 [BCM57711E] = { "QLogic BCM57711E 10 Gigabit PCIe" },
170 [BCM57712] = { "QLogic BCM57712 10 Gigabit Ethernet" },
171 [BCM57712_MF] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
172 [BCM57712_VF] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
173 [BCM57800] = { "QLogic BCM57800 10 Gigabit Ethernet" },
174 [BCM57800_MF] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
175 [BCM57800_VF] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
176 [BCM57810] = { "QLogic BCM57810 10 Gigabit Ethernet" },
177 [BCM57810_MF] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
178 [BCM57810_VF] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
179 [BCM57840_4_10] = { "QLogic BCM57840 10 Gigabit Ethernet" },
180 [BCM57840_2_20] = { "QLogic BCM57840 20 Gigabit Ethernet" },
181 [BCM57840_MF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
182 [BCM57840_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
183 [BCM57811] = { "QLogic BCM57811 10 Gigabit Ethernet" },
184 [BCM57811_MF] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
185 [BCM57840_O] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
186 [BCM57840_MFO] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
187 [BCM57811_VF] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
a2fbb9ea
ET		 188};
189
619c5cb6
VZ		 190#ifndef PCI_DEVICE_ID_NX2_57710
191#define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
192#endif
193#ifndef PCI_DEVICE_ID_NX2_57711
194#define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
195#endif
196#ifndef PCI_DEVICE_ID_NX2_57711E
197#define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
198#endif
199#ifndef PCI_DEVICE_ID_NX2_57712
200#define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
201#endif
202#ifndef PCI_DEVICE_ID_NX2_57712_MF
203#define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
204#endif
8395be5e
AE		 205#ifndef PCI_DEVICE_ID_NX2_57712_VF
206#define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
207#endif
619c5cb6
VZ		 208#ifndef PCI_DEVICE_ID_NX2_57800
209#define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
210#endif
211#ifndef PCI_DEVICE_ID_NX2_57800_MF
212#define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
213#endif
8395be5e
AE		 214#ifndef PCI_DEVICE_ID_NX2_57800_VF
215#define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
216#endif
619c5cb6
VZ		 217#ifndef PCI_DEVICE_ID_NX2_57810
218#define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
219#endif
220#ifndef PCI_DEVICE_ID_NX2_57810_MF
221#define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
222#endif
c3def943
YM		 223#ifndef PCI_DEVICE_ID_NX2_57840_O
224#define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
225#endif
8395be5e
AE		 226#ifndef PCI_DEVICE_ID_NX2_57810_VF
227#define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
228#endif
c3def943
YM		 229#ifndef PCI_DEVICE_ID_NX2_57840_4_10
230#define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
231#endif
232#ifndef PCI_DEVICE_ID_NX2_57840_2_20
233#define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
234#endif
235#ifndef PCI_DEVICE_ID_NX2_57840_MFO
236#define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
619c5cb6
VZ		 237#endif
238#ifndef PCI_DEVICE_ID_NX2_57840_MF
239#define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
240#endif
8395be5e
AE		 241#ifndef PCI_DEVICE_ID_NX2_57840_VF
242#define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
243#endif
7e8e02df
BW		 244#ifndef PCI_DEVICE_ID_NX2_57811
245#define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
246#endif
247#ifndef PCI_DEVICE_ID_NX2_57811_MF
248#define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
249#endif
8395be5e
AE		 250#ifndef PCI_DEVICE_ID_NX2_57811_VF
251#define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
252#endif
253
9baa3c34 254static const struct pci_device_id bnx2x_pci_tbl[] = {
e4ed7113
EG		 255 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
f2e0899f 258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
619c5cb6 259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
8395be5e 260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
619c5cb6
VZ		 261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
8395be5e 263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
619c5cb6
VZ		 264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
c3def943
YM		 266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
9c9a6524 268 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
c3def943 269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
8395be5e 270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
c3def943 271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
619c5cb6 272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
9c9a6524 273 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
8395be5e 274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
9c9a6524 275 { PCI_VDEVICE(QLOGIC, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
7e8e02df
BW		 276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
8395be5e 278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
a2fbb9ea
ET		 279 { 0 }
280};
281
282MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
283
452427b0
YM		 284/* Global resources for unloading a previously loaded device */
285#define BNX2X_PREV_WAIT_NEEDED 1
286static DEFINE_SEMAPHORE(bnx2x_prev_sem);
287static LIST_HEAD(bnx2x_prev_list);
a8f47eb7 288
289/* Forward declaration */
290static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
291static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
292static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
293
a2fbb9ea
ET		 294/****************************************************************************
295* General service functions
296****************************************************************************/
297
eeed018c
MK		 298static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
299
1191cb83 300static void __storm_memset_dma_mapping(struct bnx2x *bp,
619c5cb6
VZ		 301 u32 addr, dma_addr_t mapping)
302{
303 REG_WR(bp, addr, U64_LO(mapping));
304 REG_WR(bp, addr + 4, U64_HI(mapping));
305}
306
1191cb83
ED		 307static void storm_memset_spq_addr(struct bnx2x *bp,
308 dma_addr_t mapping, u16 abs_fid)
619c5cb6
VZ		 309{
310 u32 addr = XSEM_REG_FAST_MEMORY +
311 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
312
313 __storm_memset_dma_mapping(bp, addr, mapping);
314}
315
1191cb83
ED		 316static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
317 u16 pf_id)
523224a3 318{
619c5cb6
VZ		 319 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
320 pf_id);
321 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
322 pf_id);
323 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
324 pf_id);
325 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
326 pf_id);
523224a3
DK		 327}
328
1191cb83
ED		 329static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
330 u8 enable)
619c5cb6
VZ		 331{
332 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
333 enable);
334 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
335 enable);
336 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
337 enable);
338 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
339 enable);
340}
523224a3 341
1191cb83
ED		 342static void storm_memset_eq_data(struct bnx2x *bp,
343 struct event_ring_data *eq_data,
523224a3
DK		 344 u16 pfid)
345{
346 size_t size = sizeof(struct event_ring_data);
347
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
349
350 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
351}
352
1191cb83
ED		 353static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
354 u16 pfid)
523224a3
DK		 355{
356 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
357 REG_WR16(bp, addr, eq_prod);
358}
359
a2fbb9ea
ET		 360/* used only at init
361 * locking is done by mcp
362 */
8d96286a 363static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
a2fbb9ea
ET		 364{
365 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
366 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
368 PCICFG_VENDOR_ID_OFFSET);
369}
370
a2fbb9ea
ET		 371static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
372{
373 u32 val;
374
375 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
376 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
377 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
378 PCICFG_VENDOR_ID_OFFSET);
379
380 return val;
381}
a2fbb9ea 382
f2e0899f
DK		 383#define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
384#define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
385#define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
386#define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
387#define DMAE_DP_DST_NONE "dst_addr [none]"
388
6bf07b8e
YM		 389static void bnx2x_dp_dmae(struct bnx2x *bp,
390 struct dmae_command *dmae, int msglvl)
fd1fc79d
AE		 391{
392 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
6bf07b8e 393 int i;
fd1fc79d
AE		 394
395 switch (dmae->opcode & DMAE_COMMAND_DST) {
396 case DMAE_CMD_DST_PCI:
397 if (src_type == DMAE_CMD_SRC_PCI)
398 DP(msglvl, "DMAE: opcode 0x%08x\n"
399 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
400 "comp_addr [%x:%08x], comp_val 0x%08x\n",
401 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
402 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
403 dmae->comp_addr_hi, dmae->comp_addr_lo,
404 dmae->comp_val);
405 else
406 DP(msglvl, "DMAE: opcode 0x%08x\n"
407 "src [%08x], len [%d*4], dst [%x:%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae->opcode, dmae->src_addr_lo >> 2,
410 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
411 dmae->comp_addr_hi, dmae->comp_addr_lo,
412 dmae->comp_val);
413 break;
414 case DMAE_CMD_DST_GRC:
415 if (src_type == DMAE_CMD_SRC_PCI)
416 DP(msglvl, "DMAE: opcode 0x%08x\n"
417 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
418 "comp_addr [%x:%08x], comp_val 0x%08x\n",
419 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
420 dmae->len, dmae->dst_addr_lo >> 2,
421 dmae->comp_addr_hi, dmae->comp_addr_lo,
422 dmae->comp_val);
423 else
424 DP(msglvl, "DMAE: opcode 0x%08x\n"
425 "src [%08x], len [%d*4], dst [%08x]\n"
426 "comp_addr [%x:%08x], comp_val 0x%08x\n",
427 dmae->opcode, dmae->src_addr_lo >> 2,
428 dmae->len, dmae->dst_addr_lo >> 2,
429 dmae->comp_addr_hi, dmae->comp_addr_lo,
430 dmae->comp_val);
431 break;
432 default:
433 if (src_type == DMAE_CMD_SRC_PCI)
434 DP(msglvl, "DMAE: opcode 0x%08x\n"
435 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
436 "comp_addr [%x:%08x] comp_val 0x%08x\n",
437 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
438 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
439 dmae->comp_val);
440 else
441 DP(msglvl, "DMAE: opcode 0x%08x\n"
442 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
443 "comp_addr [%x:%08x] comp_val 0x%08x\n",
444 dmae->opcode, dmae->src_addr_lo >> 2,
445 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
446 dmae->comp_val);
447 break;
448 }
6bf07b8e
YM		 449
450 for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
451 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
452 i, *(((u32 *)dmae) + i));
fd1fc79d 453}
f2e0899f 454
a2fbb9ea 455/* copy command into DMAE command memory and set DMAE command go */
6c719d00 456void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
a2fbb9ea
ET		 457{
458 u32 cmd_offset;
459 int i;
460
461 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
462 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
463 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
a2fbb9ea
ET		 464 }
465 REG_WR(bp, dmae_reg_go_c[idx], 1);
466}
467
f2e0899f 468u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
a2fbb9ea 469{
f2e0899f
DK		 470 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
471 DMAE_CMD_C_ENABLE);
472}
ad8d3948 473
f2e0899f
DK		 474u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
475{
476 return opcode & ~DMAE_CMD_SRC_RESET;
477}
ad8d3948 478
f2e0899f
DK		 479u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
480 bool with_comp, u8 comp_type)
481{
482 u32 opcode = 0;
483
484 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
485 (dst_type << DMAE_COMMAND_DST_SHIFT));
ad8d3948 486
f2e0899f
DK		 487 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
488
489 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
3395a033
DK		 490 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
491 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
f2e0899f 492 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
a2fbb9ea 493
a2fbb9ea 494#ifdef __BIG_ENDIAN
f2e0899f 495 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
a2fbb9ea 496#else
f2e0899f 497 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
a2fbb9ea 498#endif
f2e0899f
DK		 499 if (with_comp)
500 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
501 return opcode;
502}
503
fd1fc79d 504void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
8d96286a 505 struct dmae_command *dmae,
506 u8 src_type, u8 dst_type)
f2e0899f
DK		 507{
508 memset(dmae, 0, sizeof(struct dmae_command));
509
510 /* set the opcode */
511 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
512 true, DMAE_COMP_PCI);
513
514 /* fill in the completion parameters */
515 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
516 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
517 dmae->comp_val = DMAE_COMP_VAL;
518}
519
fd1fc79d 520/* issue a dmae command over the init-channel and wait for completion */
32316a46
AE		 521int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
522 u32 *comp)
f2e0899f 523{
5e374b5a 524 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
f2e0899f
DK		 525 int rc = 0;
526
6bf07b8e
YM		 527 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
528
529 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
619c5cb6
VZ		 530 * as long as this code is called both from syscall context and
531 * from ndo_set_rx_mode() flow that may be called from BH.
532 */
eeed018c 533
6e30dd4e 534 spin_lock_bh(&bp->dmae_lock);
5ff7b6d4 535
f2e0899f 536 /* reset completion */
32316a46 537 *comp = 0;
a2fbb9ea 538
f2e0899f
DK		 539 /* post the command on the channel used for initializations */
540 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
a2fbb9ea 541
f2e0899f 542 /* wait for completion */
a2fbb9ea 543 udelay(5);
32316a46 544 while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
ad8d3948 545
95c6c616
AE		 546 if (!cnt ||
547 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
548 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
c3eefaf6 549 BNX2X_ERR("DMAE timeout!\n");
f2e0899f
DK		 550 rc = DMAE_TIMEOUT;
551 goto unlock;
a2fbb9ea 552 }
ad8d3948 553 cnt--;
f2e0899f 554 udelay(50);
a2fbb9ea 555 }
32316a46 556 if (*comp & DMAE_PCI_ERR_FLAG) {
f2e0899f
DK		 557 BNX2X_ERR("DMAE PCI error!\n");
558 rc = DMAE_PCI_ERROR;
559 }
560
f2e0899f 561unlock:
eeed018c 562
6e30dd4e 563 spin_unlock_bh(&bp->dmae_lock);
eeed018c 564
f2e0899f
DK		 565 return rc;
566}
567
568void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
569 u32 len32)
570{
6bf07b8e 571 int rc;
f2e0899f
DK		 572 struct dmae_command dmae;
573
574 if (!bp->dmae_ready) {
575 u32 *data = bnx2x_sp(bp, wb_data[0]);
576
127a425e
AE		 577 if (CHIP_IS_E1(bp))
578 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
579 else
580 bnx2x_init_str_wr(bp, dst_addr, data, len32);
f2e0899f
DK		 581 return;
582 }
583
584 /* set opcode and fixed command fields */
585 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
586
587 /* fill in addresses and len */
588 dmae.src_addr_lo = U64_LO(dma_addr);
589 dmae.src_addr_hi = U64_HI(dma_addr);
590 dmae.dst_addr_lo = dst_addr >> 2;
591 dmae.dst_addr_hi = 0;
592 dmae.len = len32;
593
f2e0899f 594 /* issue the command and wait for completion */
32316a46 595 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 596 if (rc) {
597 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 598#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 599 bnx2x_panic();
9dcd9acd 600#endif
6bf07b8e 601 }
a2fbb9ea
ET		 602}
603
c18487ee 604void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
a2fbb9ea 605{
6bf07b8e 606 int rc;
5ff7b6d4 607 struct dmae_command dmae;
ad8d3948
EG		 608
609 if (!bp->dmae_ready) {
610 u32 *data = bnx2x_sp(bp, wb_data[0]);
611 int i;
612
51c1a580 613 if (CHIP_IS_E1(bp))
127a425e
AE		 614 for (i = 0; i < len32; i++)
615 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
51c1a580 616 else
127a425e
AE		 617 for (i = 0; i < len32; i++)
618 data[i] = REG_RD(bp, src_addr + i*4);
619
ad8d3948
EG		 620 return;
621 }
622
f2e0899f
DK		 623 /* set opcode and fixed command fields */
624 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
a2fbb9ea 625
f2e0899f 626 /* fill in addresses and len */
5ff7b6d4
EG		 627 dmae.src_addr_lo = src_addr >> 2;
628 dmae.src_addr_hi = 0;
629 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
630 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
631 dmae.len = len32;
ad8d3948 632
f2e0899f 633 /* issue the command and wait for completion */
32316a46 634 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
6bf07b8e
YM		 635 if (rc) {
636 BNX2X_ERR("DMAE returned failure %d\n", rc);
9dcd9acd 637#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e 638 bnx2x_panic();
9dcd9acd 639#endif
c957d09f 640 }
ad8d3948
EG		 641}
642
8d96286a 643static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
644 u32 addr, u32 len)
573f2035 645{
02e3c6cb 646 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
573f2035
EG		 647 int offset = 0;
648
02e3c6cb 649 while (len > dmae_wr_max) {
573f2035 650 bnx2x_write_dmae(bp, phys_addr + offset,
02e3c6cb
VZ		 651 addr + offset, dmae_wr_max);
652 offset += dmae_wr_max * 4;
653 len -= dmae_wr_max;
573f2035
EG		 654 }
655
656 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
657}
658
97539f1e
AE		 659enum storms {
660 XSTORM,
661 TSTORM,
662 CSTORM,
663 USTORM,
664 MAX_STORMS
665};
34f80b04 666
97539f1e
AE		 667#define STORMS_NUM 4
668#define REGS_IN_ENTRY 4
34f80b04 669
97539f1e
AE		 670static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
671 enum storms storm,
672 int entry)
673{
674 switch (storm) {
675 case XSTORM:
676 return XSTORM_ASSERT_LIST_OFFSET(entry);
677 case TSTORM:
678 return TSTORM_ASSERT_LIST_OFFSET(entry);
679 case CSTORM:
680 return CSTORM_ASSERT_LIST_OFFSET(entry);
681 case USTORM:
682 return USTORM_ASSERT_LIST_OFFSET(entry);
683 case MAX_STORMS:
684 default:
685 BNX2X_ERR("unknown storm\n");
34f80b04 686 }
97539f1e
AE		 687 return -EINVAL;
688}
34f80b04 689
97539f1e
AE		 690static int bnx2x_mc_assert(struct bnx2x *bp)
691{
692 char last_idx;
693 int i, j, rc = 0;
694 enum storms storm;
695 u32 regs[REGS_IN_ENTRY];
696 u32 bar_storm_intmem[STORMS_NUM] = {
697 BAR_XSTRORM_INTMEM,
698 BAR_TSTRORM_INTMEM,
699 BAR_CSTRORM_INTMEM,
700 BAR_USTRORM_INTMEM
701 };
702 u32 storm_assert_list_index[STORMS_NUM] = {
703 XSTORM_ASSERT_LIST_INDEX_OFFSET,
704 TSTORM_ASSERT_LIST_INDEX_OFFSET,
705 CSTORM_ASSERT_LIST_INDEX_OFFSET,
706 USTORM_ASSERT_LIST_INDEX_OFFSET
707 };
708 char *storms_string[STORMS_NUM] = {
709 "XSTORM",
710 "TSTORM",
711 "CSTORM",
712 "USTORM"
713 };
714
715 for (storm = XSTORM; storm < MAX_STORMS; storm++) {
716 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
717 storm_assert_list_index[storm]);
718 if (last_idx)
719 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
720 storms_string[storm], last_idx);
721
722 /* print the asserts */
723 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
724 /* read a single assert entry */
725 for (j = 0; j < REGS_IN_ENTRY; j++)
726 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
727 bnx2x_get_assert_list_entry(bp,
728 storm,
729 i) +
730 sizeof(u32) * j);
731
732 /* log entry if it contains a valid assert */
733 if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
734 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
735 storms_string[storm], i, regs[3],
736 regs[2], regs[1], regs[0]);
737 rc++;
738 } else {
739 break;
740 }
a2fbb9ea
ET		 741 }
742 }
34f80b04 743
97539f1e
AE		 744 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
745 CHIP_IS_E1(bp) ? "everest1" :
746 CHIP_IS_E1H(bp) ? "everest1h" :
747 CHIP_IS_E2(bp) ? "everest2" : "everest3",
748 BCM_5710_FW_MAJOR_VERSION,
749 BCM_5710_FW_MINOR_VERSION,
750 BCM_5710_FW_REVISION_VERSION);
751
a2fbb9ea
ET		 752 return rc;
753}
c14423fe 754
1a6974b2
YM		 755#define MCPR_TRACE_BUFFER_SIZE (0x800)
756#define SCRATCH_BUFFER_SIZE(bp) \
757 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
758
7a25cc73 759void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
a2fbb9ea 760{
7a25cc73 761 u32 addr, val;
a2fbb9ea 762 u32 mark, offset;
4781bfad 763 __be32 data[9];
a2fbb9ea 764 int word;
f2e0899f 765 u32 trace_shmem_base;
2145a920
VZ		 766 if (BP_NOMCP(bp)) {
767 BNX2X_ERR("NO MCP - can not dump\n");
768 return;
769 }
7a25cc73
DK		 770 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
771 (bp->common.bc_ver & 0xff0000) >> 16,
772 (bp->common.bc_ver & 0xff00) >> 8,
773 (bp->common.bc_ver & 0xff));
774
b44e108b
GP		 775 if (pci_channel_offline(bp->pdev)) {
776 BNX2X_ERR("Cannot dump MCP info while in PCI error\n");
777 return;
778 }
779
7a25cc73
DK		 780 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
781 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
51c1a580 782 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
cdaa7cb8 783
f2e0899f
DK		 784 if (BP_PATH(bp) == 0)
785 trace_shmem_base = bp->common.shmem_base;
786 else
787 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
1a6974b2
YM		 788
789 /* sanity */
790 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
791 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
792 SCRATCH_BUFFER_SIZE(bp)) {
793 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
794 trace_shmem_base);
795 return;
796 }
797
798 addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
de128804
DK		 799
800 /* validate TRCB signature */
801 mark = REG_RD(bp, addr);
802 if (mark != MFW_TRACE_SIGNATURE) {
803 BNX2X_ERR("Trace buffer signature is missing.");
804 return ;
805 }
806
807 /* read cyclic buffer pointer */
808 addr += 4;
cdaa7cb8 809 mark = REG_RD(bp, addr);
1a6974b2
YM		 810 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
811 if (mark >= trace_shmem_base || mark < addr + 4) {
812 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
813 return;
814 }
7a25cc73 815 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
a2fbb9ea 816
7a25cc73 817 printk("%s", lvl);
2de67439
YM		 818
819 /* dump buffer after the mark */
1a6974b2 820 for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
a2fbb9ea 821 for (word = 0; word < 8; word++)
cdaa7cb8 822 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 823 data[8] = 0x0;
7995c64e 824 pr_cont("%s", (char *)data);
a2fbb9ea 825 }
2de67439
YM		 826
827 /* dump buffer before the mark */
cdaa7cb8 828 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
a2fbb9ea 829 for (word = 0; word < 8; word++)
cdaa7cb8 830 data[word] = htonl(REG_RD(bp, offset + 4*word));
a2fbb9ea 831 data[8] = 0x0;
7995c64e 832 pr_cont("%s", (char *)data);
a2fbb9ea 833 }
7a25cc73
DK		 834 printk("%s" "end of fw dump\n", lvl);
835}
836
1191cb83 837static void bnx2x_fw_dump(struct bnx2x *bp)
7a25cc73
DK		 838{
839 bnx2x_fw_dump_lvl(bp, KERN_ERR);
a2fbb9ea
ET		 840}
841
823e1d90
YM		 842static void bnx2x_hc_int_disable(struct bnx2x *bp)
843{
844 int port = BP_PORT(bp);
845 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
846 u32 val = REG_RD(bp, addr);
847
848 /* in E1 we must use only PCI configuration space to disable
16a5fd92
YM		 849 * MSI/MSIX capability
850 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
823e1d90
YM		 851 */
852 if (CHIP_IS_E1(bp)) {
853 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
854 * Use mask register to prevent from HC sending interrupts
855 * after we exit the function
856 */
857 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
858
859 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
860 HC_CONFIG_0_REG_INT_LINE_EN_0 |
861 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
862 } else
863 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
864 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
865 HC_CONFIG_0_REG_INT_LINE_EN_0 |
866 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
867
868 DP(NETIF_MSG_IFDOWN,
869 "write %x to HC %d (addr 0x%x)\n",
870 val, port, addr);
871
872 /* flush all outstanding writes */
873 mmiowb();
874
875 REG_WR(bp, addr, val);
876 if (REG_RD(bp, addr) != val)
6bf07b8e 877 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 878}
879
880static void bnx2x_igu_int_disable(struct bnx2x *bp)
881{
882 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
883
884 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
885 IGU_PF_CONF_INT_LINE_EN |
886 IGU_PF_CONF_ATTN_BIT_EN);
887
888 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
889
890 /* flush all outstanding writes */
891 mmiowb();
892
893 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
894 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
6bf07b8e 895 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
823e1d90
YM		 896}
897
898static void bnx2x_int_disable(struct bnx2x *bp)
899{
900 if (bp->common.int_block == INT_BLOCK_HC)
901 bnx2x_hc_int_disable(bp);
902 else
903 bnx2x_igu_int_disable(bp);
904}
905
906void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
a2fbb9ea
ET		 907{
908 int i;
523224a3
DK		 909 u16 j;
910 struct hc_sp_status_block_data sp_sb_data;
911 int func = BP_FUNC(bp);
912#ifdef BNX2X_STOP_ON_ERROR
913 u16 start = 0, end = 0;
6383c0b3 914 u8 cos;
523224a3 915#endif
0155a27c 916 if (IS_PF(bp) && disable_int)
823e1d90 917 bnx2x_int_disable(bp);
a2fbb9ea 918
66e855f3 919 bp->stats_state = STATS_STATE_DISABLED;
7a752993 920 bp->eth_stats.unrecoverable_error++;
66e855f3
YG		 921 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
922
a2fbb9ea
ET		 923 BNX2X_ERR("begin crash dump -----------------\n");
924
8440d2b6
EG		 925 /* Indices */
926 /* Common */
0155a27c
YM		 927 if (IS_PF(bp)) {
928 struct host_sp_status_block *def_sb = bp->def_status_blk;
929 int data_size, cstorm_offset;
930
931 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
932 bp->def_idx, bp->def_att_idx, bp->attn_state,
933 bp->spq_prod_idx, bp->stats_counter);
934 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
935 def_sb->atten_status_block.attn_bits,
936 def_sb->atten_status_block.attn_bits_ack,
937 def_sb->atten_status_block.status_block_id,
938 def_sb->atten_status_block.attn_bits_index);
939 BNX2X_ERR(" def (");
940 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
941 pr_cont("0x%x%s",
942 def_sb->sp_sb.index_values[i],
943 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
944
945 data_size = sizeof(struct hc_sp_status_block_data) /
946 sizeof(u32);
947 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
948 for (i = 0; i < data_size; i++)
949 *((u32 *)&sp_sb_data + i) =
950 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
951 i * sizeof(u32));
952
953 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
954 sp_sb_data.igu_sb_id,
955 sp_sb_data.igu_seg_id,
956 sp_sb_data.p_func.pf_id,
957 sp_sb_data.p_func.vnic_id,
958 sp_sb_data.p_func.vf_id,
959 sp_sb_data.p_func.vf_valid,
960 sp_sb_data.state);
961 }
523224a3 962
ec6ba945 963 for_each_eth_queue(bp, i) {
a2fbb9ea 964 struct bnx2x_fastpath *fp = &bp->fp[i];
523224a3 965 int loop;
f2e0899f 966 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 967 struct hc_status_block_data_e1x sb_data_e1x;
968 struct hc_status_block_sm *hc_sm_p =
619c5cb6
VZ		 969 CHIP_IS_E1x(bp) ?
970 sb_data_e1x.common.state_machine :
971 sb_data_e2.common.state_machine;
523224a3 972 struct hc_index_data *hc_index_p =
619c5cb6
VZ		 973 CHIP_IS_E1x(bp) ?
974 sb_data_e1x.index_data :
975 sb_data_e2.index_data;
6383c0b3 976 u8 data_size, cos;
523224a3 977 u32 *sb_data_p;
6383c0b3 978 struct bnx2x_fp_txdata txdata;
523224a3 979
e2611998
YM		 980 if (!bp->fp)
981 break;
982
983 if (!fp->rx_cons_sb)
984 continue;
985
523224a3 986 /* Rx */
51c1a580 987 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
8440d2b6 988 i, fp->rx_bd_prod, fp->rx_bd_cons,
523224a3 989 fp->rx_comp_prod,
66e855f3 990 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
51c1a580 991 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
8440d2b6 992 fp->rx_sge_prod, fp->last_max_sge,
523224a3 993 le16_to_cpu(fp->fp_hc_idx));
a2fbb9ea 994
523224a3 995 /* Tx */
6383c0b3
AE		 996 for_each_cos_in_tx_queue(fp, cos)
997 {
1fc3de94 998 if (!fp->txdata_ptr[cos])
e2611998
YM		 999 break;
1000
65565884 1001 txdata = *fp->txdata_ptr[cos];
e2611998
YM		 1002
1003 if (!txdata.tx_cons_sb)
1004 continue;
1005
51c1a580 1006 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
6383c0b3
AE		 1007 i, txdata.tx_pkt_prod,
1008 txdata.tx_pkt_cons, txdata.tx_bd_prod,
1009 txdata.tx_bd_cons,
1010 le16_to_cpu(*txdata.tx_cons_sb));
1011 }
523224a3 1012
619c5cb6
VZ		 1013 loop = CHIP_IS_E1x(bp) ?
1014 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
523224a3
DK		 1015
1016 /* host sb data */
1017
ec6ba945
VZ		 1018 if (IS_FCOE_FP(fp))
1019 continue;
55c11941 1020
523224a3
DK		 1021 BNX2X_ERR(" run indexes (");
1022 for (j = 0; j < HC_SB_MAX_SM; j++)
1023 pr_cont("0x%x%s",
1024 fp->sb_running_index[j],
1025 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1026
1027 BNX2X_ERR(" indexes (");
1028 for (j = 0; j < loop; j++)
1029 pr_cont("0x%x%s",
1030 fp->sb_index_values[j],
1031 (j == loop - 1) ? ")" : " ");
0155a27c
YM		 1032
1033 /* VF cannot access FW refelection for status block */
1034 if (IS_VF(bp))
1035 continue;
1036
523224a3 1037 /* fw sb data */
619c5cb6
VZ		 1038 data_size = CHIP_IS_E1x(bp) ?
1039 sizeof(struct hc_status_block_data_e1x) :
1040 sizeof(struct hc_status_block_data_e2);
523224a3 1041 data_size /= sizeof(u32);
619c5cb6
VZ		 1042 sb_data_p = CHIP_IS_E1x(bp) ?
1043 (u32 *)&sb_data_e1x :
1044 (u32 *)&sb_data_e2;
523224a3
DK		 1045 /* copy sb data in here */
1046 for (j = 0; j < data_size; j++)
1047 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1048 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1049 j * sizeof(u32));
1050
619c5cb6 1051 if (!CHIP_IS_E1x(bp)) {
51c1a580 1052 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1053 sb_data_e2.common.p_func.pf_id,
1054 sb_data_e2.common.p_func.vf_id,
1055 sb_data_e2.common.p_func.vf_valid,
1056 sb_data_e2.common.p_func.vnic_id,
619c5cb6
VZ		 1057 sb_data_e2.common.same_igu_sb_1b,
1058 sb_data_e2.common.state);
f2e0899f 1059 } else {
51c1a580 1060 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
f2e0899f
DK		 1061 sb_data_e1x.common.p_func.pf_id,
1062 sb_data_e1x.common.p_func.vf_id,
1063 sb_data_e1x.common.p_func.vf_valid,
1064 sb_data_e1x.common.p_func.vnic_id,
619c5cb6
VZ		 1065 sb_data_e1x.common.same_igu_sb_1b,
1066 sb_data_e1x.common.state);
f2e0899f 1067 }
523224a3
DK		 1068
1069 /* SB_SMs data */
1070 for (j = 0; j < HC_SB_MAX_SM; j++) {
51c1a580
MS		 1071 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1072 j, hc_sm_p[j].__flags,
1073 hc_sm_p[j].igu_sb_id,
1074 hc_sm_p[j].igu_seg_id,
1075 hc_sm_p[j].time_to_expire,
1076 hc_sm_p[j].timer_value);
523224a3
DK		 1077 }
1078
16a5fd92 1079 /* Indices data */
523224a3 1080 for (j = 0; j < loop; j++) {
51c1a580 1081 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
523224a3
DK		 1082 hc_index_p[j].flags,
1083 hc_index_p[j].timeout);
1084 }
8440d2b6 1085 }
a2fbb9ea 1086
523224a3 1087#ifdef BNX2X_STOP_ON_ERROR
0155a27c
YM		 1088 if (IS_PF(bp)) {
1089 /* event queue */
1090 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1091 for (i = 0; i < NUM_EQ_DESC; i++) {
1092 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1093
1094 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1095 i, bp->eq_ring[i].message.opcode,
1096 bp->eq_ring[i].message.error);
1097 BNX2X_ERR("data: %x %x %x\n",
1098 data[0], data[1], data[2]);
1099 }
04c46736
YM		 1100 }
1101
8440d2b6
EG		 1102 /* Rings */
1103 /* Rx */
55c11941 1104 for_each_valid_rx_queue(bp, i) {
8440d2b6 1105 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1106
e2611998
YM		 1107 if (!bp->fp)
1108 break;
1109
1110 if (!fp->rx_cons_sb)
1111 continue;
1112
a2fbb9ea
ET		 1113 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1114 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
8440d2b6 1115 for (j = start; j != end; j = RX_BD(j + 1)) {
a2fbb9ea
ET		 1116 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1117 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1118
c3eefaf6 1119 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
44151acb 1120 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
a2fbb9ea
ET		 1121 }
1122
3196a88a
EG		 1123 start = RX_SGE(fp->rx_sge_prod);
1124 end = RX_SGE(fp->last_max_sge);
8440d2b6 1125 for (j = start; j != end; j = RX_SGE(j + 1)) {
7a9b2557
VZ		 1126 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1127 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1128
c3eefaf6
EG		 1129 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1130 i, j, rx_sge[1], rx_sge[0], sw_page->page);
7a9b2557
VZ		 1131 }
1132
a2fbb9ea
ET		 1133 start = RCQ_BD(fp->rx_comp_cons - 10);
1134 end = RCQ_BD(fp->rx_comp_cons + 503);
8440d2b6 1135 for (j = start; j != end; j = RCQ_BD(j + 1)) {
a2fbb9ea
ET		 1136 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1137
c3eefaf6
EG		 1138 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1139 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
a2fbb9ea
ET		 1140 }
1141 }
1142
8440d2b6 1143 /* Tx */
55c11941 1144 for_each_valid_tx_queue(bp, i) {
8440d2b6 1145 struct bnx2x_fastpath *fp = &bp->fp[i];
e2611998
YM		 1146
1147 if (!bp->fp)
1148 break;
1149
6383c0b3 1150 for_each_cos_in_tx_queue(fp, cos) {
65565884 1151 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
6383c0b3 1152
1fc3de94 1153 if (!fp->txdata_ptr[cos])
e2611998
YM		 1154 break;
1155
ea36475a 1156 if (!txdata->tx_cons_sb)
e2611998
YM		 1157 continue;
1158
6383c0b3
AE		 1159 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1160 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1161 for (j = start; j != end; j = TX_BD(j + 1)) {
1162 struct sw_tx_bd *sw_bd =
1163 &txdata->tx_buf_ring[j];
1164
51c1a580 1165 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
6383c0b3
AE		 1166 i, cos, j, sw_bd->skb,
1167 sw_bd->first_bd);
1168 }
8440d2b6 1169
6383c0b3
AE		 1170 start = TX_BD(txdata->tx_bd_cons - 10);
1171 end = TX_BD(txdata->tx_bd_cons + 254);
1172 for (j = start; j != end; j = TX_BD(j + 1)) {
1173 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
8440d2b6 1174
51c1a580 1175 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
6383c0b3
AE		 1176 i, cos, j, tx_bd[0], tx_bd[1],
1177 tx_bd[2], tx_bd[3]);
1178 }
8440d2b6
EG		 1179 }
1180 }
523224a3 1181#endif
0155a27c
YM		 1182 if (IS_PF(bp)) {
1183 bnx2x_fw_dump(bp);
1184 bnx2x_mc_assert(bp);
1185 }
a2fbb9ea 1186 BNX2X_ERR("end crash dump -----------------\n");
a2fbb9ea
ET		 1187}
1188
619c5cb6
VZ		 1189/*
1190 * FLR Support for E2
1191 *
1192 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1193 * initialization.
1194 */
16a5fd92 1195#define FLR_WAIT_USEC 10000 /* 10 milliseconds */
89db4ad8
AE		 1196#define FLR_WAIT_INTERVAL 50 /* usec */
1197#define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
619c5cb6
VZ		 1198
1199struct pbf_pN_buf_regs {
1200 int pN;
1201 u32 init_crd;
1202 u32 crd;
1203 u32 crd_freed;
1204};
1205
1206struct pbf_pN_cmd_regs {
1207 int pN;
1208 u32 lines_occup;
1209 u32 lines_freed;
1210};
1211
1212static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1213 struct pbf_pN_buf_regs *regs,
1214 u32 poll_count)
1215{
1216 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1217 u32 cur_cnt = poll_count;
1218
1219 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1220 crd = crd_start = REG_RD(bp, regs->crd);
1221 init_crd = REG_RD(bp, regs->init_crd);
1222
1223 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1224 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1225 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1226
1227 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1228 (init_crd - crd_start))) {
1229 if (cur_cnt--) {
89db4ad8 1230 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1231 crd = REG_RD(bp, regs->crd);
1232 crd_freed = REG_RD(bp, regs->crd_freed);
1233 } else {
1234 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1235 regs->pN);
1236 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1237 regs->pN, crd);
1238 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1239 regs->pN, crd_freed);
1240 break;
1241 }
1242 }
1243 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
89db4ad8 1244 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1245}
1246
1247static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1248 struct pbf_pN_cmd_regs *regs,
1249 u32 poll_count)
1250{
1251 u32 occup, to_free, freed, freed_start;
1252 u32 cur_cnt = poll_count;
1253
1254 occup = to_free = REG_RD(bp, regs->lines_occup);
1255 freed = freed_start = REG_RD(bp, regs->lines_freed);
1256
1257 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1258 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1259
1260 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1261 if (cur_cnt--) {
89db4ad8 1262 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1263 occup = REG_RD(bp, regs->lines_occup);
1264 freed = REG_RD(bp, regs->lines_freed);
1265 } else {
1266 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1267 regs->pN);
1268 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1269 regs->pN, occup);
1270 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1271 regs->pN, freed);
1272 break;
1273 }
1274 }
1275 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
89db4ad8 1276 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
619c5cb6
VZ		 1277}
1278
1191cb83
ED		 1279static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1280 u32 expected, u32 poll_count)
619c5cb6
VZ		 1281{
1282 u32 cur_cnt = poll_count;
1283 u32 val;
1284
1285 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
89db4ad8 1286 udelay(FLR_WAIT_INTERVAL);
619c5cb6
VZ		 1287
1288 return val;
1289}
1290
d16132ce
AE		 1291int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1292 char *msg, u32 poll_cnt)
619c5cb6
VZ		 1293{
1294 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1295 if (val != 0) {
1296 BNX2X_ERR("%s usage count=%d\n", msg, val);
1297 return 1;
1298 }
1299 return 0;
1300}
1301
d16132ce
AE		 1302/* Common routines with VF FLR cleanup */
1303u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
619c5cb6
VZ		 1304{
1305 /* adjust polling timeout */
1306 if (CHIP_REV_IS_EMUL(bp))
1307 return FLR_POLL_CNT * 2000;
1308
1309 if (CHIP_REV_IS_FPGA(bp))
1310 return FLR_POLL_CNT * 120;
1311
1312 return FLR_POLL_CNT;
1313}
1314
d16132ce 1315void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
619c5cb6
VZ		 1316{
1317 struct pbf_pN_cmd_regs cmd_regs[] = {
1318 {0, (CHIP_IS_E3B0(bp)) ?
1319 PBF_REG_TQ_OCCUPANCY_Q0 :
1320 PBF_REG_P0_TQ_OCCUPANCY,
1321 (CHIP_IS_E3B0(bp)) ?
1322 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1323 PBF_REG_P0_TQ_LINES_FREED_CNT},
1324 {1, (CHIP_IS_E3B0(bp)) ?
1325 PBF_REG_TQ_OCCUPANCY_Q1 :
1326 PBF_REG_P1_TQ_OCCUPANCY,
1327 (CHIP_IS_E3B0(bp)) ?
1328 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1329 PBF_REG_P1_TQ_LINES_FREED_CNT},
1330 {4, (CHIP_IS_E3B0(bp)) ?
1331 PBF_REG_TQ_OCCUPANCY_LB_Q :
1332 PBF_REG_P4_TQ_OCCUPANCY,
1333 (CHIP_IS_E3B0(bp)) ?
1334 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1335 PBF_REG_P4_TQ_LINES_FREED_CNT}
1336 };
1337
1338 struct pbf_pN_buf_regs buf_regs[] = {
1339 {0, (CHIP_IS_E3B0(bp)) ?
1340 PBF_REG_INIT_CRD_Q0 :
1341 PBF_REG_P0_INIT_CRD ,
1342 (CHIP_IS_E3B0(bp)) ?
1343 PBF_REG_CREDIT_Q0 :
1344 PBF_REG_P0_CREDIT,
1345 (CHIP_IS_E3B0(bp)) ?
1346 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1347 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1348 {1, (CHIP_IS_E3B0(bp)) ?
1349 PBF_REG_INIT_CRD_Q1 :
1350 PBF_REG_P1_INIT_CRD,
1351 (CHIP_IS_E3B0(bp)) ?
1352 PBF_REG_CREDIT_Q1 :
1353 PBF_REG_P1_CREDIT,
1354 (CHIP_IS_E3B0(bp)) ?
1355 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1356 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1357 {4, (CHIP_IS_E3B0(bp)) ?
1358 PBF_REG_INIT_CRD_LB_Q :
1359 PBF_REG_P4_INIT_CRD,
1360 (CHIP_IS_E3B0(bp)) ?
1361 PBF_REG_CREDIT_LB_Q :
1362 PBF_REG_P4_CREDIT,
1363 (CHIP_IS_E3B0(bp)) ?
1364 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1365 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1366 };
1367
1368 int i;
1369
1370 /* Verify the command queues are flushed P0, P1, P4 */
1371 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1372 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1373
619c5cb6
VZ		 1374 /* Verify the transmission buffers are flushed P0, P1, P4 */
1375 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1376 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1377}
1378
1379#define OP_GEN_PARAM(param) \
1380 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1381
1382#define OP_GEN_TYPE(type) \
1383 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1384
1385#define OP_GEN_AGG_VECT(index) \
1386 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1387
d16132ce 1388int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
619c5cb6 1389{
86564c3f 1390 u32 op_gen_command = 0;
619c5cb6
VZ		 1391 u32 comp_addr = BAR_CSTRORM_INTMEM +
1392 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1393 int ret = 0;
1394
1395 if (REG_RD(bp, comp_addr)) {
89db4ad8 1396 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
619c5cb6
VZ		 1397 return 1;
1398 }
1399
86564c3f
YM		 1400 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1401 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1402 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1403 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
619c5cb6 1404
89db4ad8 1405 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
86564c3f 1406 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
619c5cb6
VZ		 1407
1408 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1409 BNX2X_ERR("FW final cleanup did not succeed\n");
51c1a580
MS		 1410 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1411 (REG_RD(bp, comp_addr)));
d16132ce
AE		 1412 bnx2x_panic();
1413 return 1;
619c5cb6 1414 }
16a5fd92 1415 /* Zero completion for next FLR */
619c5cb6
VZ		 1416 REG_WR(bp, comp_addr, 0);
1417
1418 return ret;
1419}
1420
b56e9670 1421u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
619c5cb6 1422{
619c5cb6
VZ		 1423 u16 status;
1424
2a80eebc 1425 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
619c5cb6
VZ		 1426 return status & PCI_EXP_DEVSTA_TRPND;
1427}
1428
1429/* PF FLR specific routines
1430*/
1431static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1432{
619c5cb6
VZ		 1433 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1434 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1435 CFC_REG_NUM_LCIDS_INSIDE_PF,
1436 "CFC PF usage counter timed out",
1437 poll_cnt))
1438 return 1;
1439
619c5cb6
VZ		 1440 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1441 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1442 DORQ_REG_PF_USAGE_CNT,
1443 "DQ PF usage counter timed out",
1444 poll_cnt))
1445 return 1;
1446
1447 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1448 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1449 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1450 "QM PF usage counter timed out",
1451 poll_cnt))
1452 return 1;
1453
1454 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1455 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1456 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1457 "Timers VNIC usage counter timed out",
1458 poll_cnt))
1459 return 1;
1460 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1461 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1462 "Timers NUM_SCANS usage counter timed out",
1463 poll_cnt))
1464 return 1;
1465
1466 /* Wait DMAE PF usage counter to zero */
1467 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1468 dmae_reg_go_c[INIT_DMAE_C(bp)],
6bf07b8e 1469 "DMAE command register timed out",
619c5cb6
VZ		 1470 poll_cnt))
1471 return 1;
1472
1473 return 0;
1474}
1475
1476static void bnx2x_hw_enable_status(struct bnx2x *bp)
1477{
1478 u32 val;
1479
1480 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1481 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1482
1483 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1484 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1485
1486 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1487 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1488
1489 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1490 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1491
1492 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1493 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1494
1495 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1496 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1497
1498 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1499 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1500
1501 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1502 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1503 val);
1504}
1505
1506static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1507{
1508 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1509
1510 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1511
1512 /* Re-enable PF target read access */
1513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1514
1515 /* Poll HW usage counters */
89db4ad8 1516 DP(BNX2X_MSG_SP, "Polling usage counters\n");
619c5cb6
VZ		 1517 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1518 return -EBUSY;
1519
1520 /* Zero the igu 'trailing edge' and 'leading edge' */
1521
1522 /* Send the FW cleanup command */
1523 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1524 return -EBUSY;
1525
1526 /* ATC cleanup */
1527
1528 /* Verify TX hw is flushed */
1529 bnx2x_tx_hw_flushed(bp, poll_cnt);
1530
1531 /* Wait 100ms (not adjusted according to platform) */
1532 msleep(100);
1533
1534 /* Verify no pending pci transactions */
1535 if (bnx2x_is_pcie_pending(bp->pdev))
1536 BNX2X_ERR("PCIE Transactions still pending\n");
1537
1538 /* Debug */
1539 bnx2x_hw_enable_status(bp);
1540
1541 /*
1542 * Master enable - Due to WB DMAE writes performed before this
1543 * register is re-initialized as part of the regular function init
1544 */
1545 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1546
1547 return 0;
1548}
1549
f2e0899f 1550static void bnx2x_hc_int_enable(struct bnx2x *bp)
a2fbb9ea 1551{
34f80b04 1552 int port = BP_PORT(bp);
a2fbb9ea
ET		 1553 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1554 u32 val = REG_RD(bp, addr);
69c326b3
DK		 1555 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1556 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1557 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
a2fbb9ea
ET		 1558
1559 if (msix) {
8badd27a
EG		 1560 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1561 HC_CONFIG_0_REG_INT_LINE_EN_0);
a2fbb9ea
ET		 1562 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
69c326b3
DK		 1564 if (single_msix)
1565 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
8badd27a
EG		 1566 } else if (msi) {
1567 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1568 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1569 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1570 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
a2fbb9ea
ET		 1571 } else {
1572 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
615f8fd9 1573 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
a2fbb9ea
ET		 1574 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1575 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
615f8fd9 1576
a0fd065c 1577 if (!CHIP_IS_E1(bp)) {
51c1a580
MS		 1578 DP(NETIF_MSG_IFUP,
1579 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
615f8fd9 1580
a0fd065c 1581 REG_WR(bp, addr, val);
615f8fd9 1582
a0fd065c
DK		 1583 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1584 }
a2fbb9ea
ET		 1585 }
1586
a0fd065c
DK		 1587 if (CHIP_IS_E1(bp))
1588 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1589
51c1a580
MS		 1590 DP(NETIF_MSG_IFUP,
1591 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1592 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
a2fbb9ea
ET		 1593
1594 REG_WR(bp, addr, val);
37dbbf32
EG		 1595 /*
1596 * Ensure that HC_CONFIG is written before leading/trailing edge config
1597 */
1598 mmiowb();
1599 barrier();
34f80b04 1600
f2e0899f 1601 if (!CHIP_IS_E1(bp)) {
34f80b04 1602 /* init leading/trailing edge */
fb3bff17 1603 if (IS_MF(bp)) {
3395a033 1604 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
34f80b04 1605 if (bp->port.pmf)
4acac6a5
EG		 1606 /* enable nig and gpio3 attention */
1607 val |= 0x1100;
34f80b04
EG		 1608 } else
1609 val = 0xffff;
1610
1611 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1612 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1613 }
37dbbf32
EG		 1614
1615 /* Make sure that interrupts are indeed enabled from here on */
1616 mmiowb();
a2fbb9ea
ET		 1617}
1618
f2e0899f
DK		 1619static void bnx2x_igu_int_enable(struct bnx2x *bp)
1620{
1621 u32 val;
30a5de77
DK		 1622 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1623 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1624 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
f2e0899f
DK		 1625
1626 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1627
1628 if (msix) {
1629 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1630 IGU_PF_CONF_SINGLE_ISR_EN);
ebe61d80 1631 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f 1632 IGU_PF_CONF_ATTN_BIT_EN);
30a5de77
DK		 1633
1634 if (single_msix)
1635 val |= IGU_PF_CONF_SINGLE_ISR_EN;
f2e0899f
DK		 1636 } else if (msi) {
1637 val &= ~IGU_PF_CONF_INT_LINE_EN;
ebe61d80 1638 val |= (IGU_PF_CONF_MSI_MSIX_EN |
f2e0899f
DK		 1639 IGU_PF_CONF_ATTN_BIT_EN |
1640 IGU_PF_CONF_SINGLE_ISR_EN);
1641 } else {
1642 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
ebe61d80 1643 val |= (IGU_PF_CONF_INT_LINE_EN |
f2e0899f
DK		 1644 IGU_PF_CONF_ATTN_BIT_EN |
1645 IGU_PF_CONF_SINGLE_ISR_EN);
1646 }
1647
ebe61d80
YM		 1648 /* Clean previous status - need to configure igu prior to ack*/
1649 if ((!msix) || single_msix) {
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651 bnx2x_ack_int(bp);
1652 }
1653
1654 val |= IGU_PF_CONF_FUNC_EN;
1655
51c1a580 1656 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
f2e0899f
DK		 1657 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1658
1659 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1660
79a8557a
YM		 1661 if (val & IGU_PF_CONF_INT_LINE_EN)
1662 pci_intx(bp->pdev, true);
1663
f2e0899f
DK		 1664 barrier();
1665
1666 /* init leading/trailing edge */
1667 if (IS_MF(bp)) {
3395a033 1668 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 1669 if (bp->port.pmf)
1670 /* enable nig and gpio3 attention */
1671 val |= 0x1100;
1672 } else
1673 val = 0xffff;
1674
1675 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1676 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1677
1678 /* Make sure that interrupts are indeed enabled from here on */
1679 mmiowb();
1680}
1681
1682void bnx2x_int_enable(struct bnx2x *bp)
1683{
1684 if (bp->common.int_block == INT_BLOCK_HC)
1685 bnx2x_hc_int_enable(bp);
1686 else
1687 bnx2x_igu_int_enable(bp);
1688}
1689
9f6c9258 1690void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
a2fbb9ea 1691{
a2fbb9ea 1692 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8badd27a 1693 int i, offset;
a2fbb9ea 1694
f8ef6e44
YG		 1695 if (disable_hw)
1696 /* prevent the HW from sending interrupts */
1697 bnx2x_int_disable(bp);
a2fbb9ea
ET		 1698
1699 /* make sure all ISRs are done */
1700 if (msix) {
8badd27a
EG		 1701 synchronize_irq(bp->msix_table[0].vector);
1702 offset = 1;
55c11941
MS		 1703 if (CNIC_SUPPORT(bp))
1704 offset++;
ec6ba945 1705 for_each_eth_queue(bp, i)
754a2f52 1706 synchronize_irq(bp->msix_table[offset++].vector);
a2fbb9ea
ET		 1707 } else
1708 synchronize_irq(bp->pdev->irq);
1709
1710 /* make sure sp_task is not running */
1cf167f2 1711 cancel_delayed_work(&bp->sp_task);
3deb8167 1712 cancel_delayed_work(&bp->period_task);
1cf167f2 1713 flush_workqueue(bnx2x_wq);
a2fbb9ea
ET		 1714}
1715
34f80b04 1716/* fast path */
a2fbb9ea
ET		 1717
1718/*
34f80b04 1719 * General service functions
a2fbb9ea
ET		 1720 */
1721
72fd0718
VZ		 1722/* Return true if succeeded to acquire the lock */
1723static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1724{
1725 u32 lock_status;
1726 u32 resource_bit = (1 << resource);
1727 int func = BP_FUNC(bp);
1728 u32 hw_lock_control_reg;
1729
51c1a580
MS		 1730 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1731 "Trying to take a lock on resource %d\n", resource);
72fd0718
VZ		 1732
1733 /* Validating that the resource is within range */
1734 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 1735 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
72fd0718
VZ		 1736 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1737 resource, HW_LOCK_MAX_RESOURCE_VALUE);
0fdf4d09 1738 return false;
72fd0718
VZ		 1739 }
1740
1741 if (func <= 5)
1742 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1743 else
1744 hw_lock_control_reg =
1745 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1746
1747 /* Try to acquire the lock */
1748 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1749 lock_status = REG_RD(bp, hw_lock_control_reg);
1750 if (lock_status & resource_bit)
1751 return true;
1752
51c1a580
MS		 1753 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1754 "Failed to get a lock on resource %d\n", resource);
72fd0718
VZ		 1755 return false;
1756}
1757
c9ee9206
VZ		 1758/**
1759 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1760 *
1761 * @bp: driver handle
1762 *
1763 * Returns the recovery leader resource id according to the engine this function
1764 * belongs to. Currently only only 2 engines is supported.
1765 */
1191cb83 1766static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
c9ee9206
VZ		 1767{
1768 if (BP_PATH(bp))
1769 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1770 else
1771 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1772}
1773
1774/**
2de67439 1775 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
c9ee9206
VZ		 1776 *
1777 * @bp: driver handle
1778 *
2de67439 1779 * Tries to acquire a leader lock for current engine.
c9ee9206 1780 */
1191cb83 1781static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
c9ee9206
VZ		 1782{
1783 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1784}
1785
619c5cb6 1786static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
55c11941 1787
fd1fc79d
AE		 1788/* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1789static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1790{
1791 /* Set the interrupt occurred bit for the sp-task to recognize it
1792 * must ack the interrupt and transition according to the IGU
1793 * state machine.
1794 */
1795 atomic_set(&bp->interrupt_occurred, 1);
1796
1797 /* The sp_task must execute only after this bit
1798 * is set, otherwise we will get out of sync and miss all
1799 * further interrupts. Hence, the barrier.
1800 */
1801 smp_wmb();
1802
1803 /* schedule sp_task to workqueue */
1804 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1805}
3196a88a 1806
619c5cb6 1807void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
a2fbb9ea
ET		 1808{
1809 struct bnx2x *bp = fp->bp;
1810 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1811 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
619c5cb6 1812 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
15192a8c 1813 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a2fbb9ea 1814
34f80b04 1815 DP(BNX2X_MSG_SP,
a2fbb9ea 1816 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
0626b899 1817 fp->index, cid, command, bp->state,
34f80b04 1818 rr_cqe->ramrod_cqe.ramrod_type);
a2fbb9ea 1819
fd1fc79d
AE		 1820 /* If cid is within VF range, replace the slowpath object with the
1821 * one corresponding to this VF
1822 */
1823 if (cid >= BNX2X_FIRST_VF_CID &&
1824 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1825 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1826
619c5cb6
VZ		 1827 switch (command) {
1828 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
d6cae238 1829 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
619c5cb6
VZ		 1830 drv_cmd = BNX2X_Q_CMD_UPDATE;
1831 break;
d6cae238 1832
619c5cb6 1833 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
d6cae238 1834 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
619c5cb6 1835 drv_cmd = BNX2X_Q_CMD_SETUP;
a2fbb9ea
ET		 1836 break;
1837
6383c0b3 1838 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
51c1a580 1839 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
6383c0b3
AE		 1840 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1841 break;
1842
619c5cb6 1843 case (RAMROD_CMD_ID_ETH_HALT):
d6cae238 1844 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
619c5cb6 1845 drv_cmd = BNX2X_Q_CMD_HALT;
a2fbb9ea
ET		 1846 break;
1847
619c5cb6 1848 case (RAMROD_CMD_ID_ETH_TERMINATE):
6bf07b8e 1849 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
619c5cb6 1850 drv_cmd = BNX2X_Q_CMD_TERMINATE;
a2fbb9ea
ET		 1851 break;
1852
619c5cb6 1853 case (RAMROD_CMD_ID_ETH_EMPTY):
d6cae238 1854 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
619c5cb6 1855 drv_cmd = BNX2X_Q_CMD_EMPTY;
993ac7b5 1856 break;
619c5cb6 1857
14a94ebd
MK		 1858 case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1859 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1860 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1861 break;
1862
619c5cb6
VZ		 1863 default:
1864 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1865 command, fp->index);
1866 return;
523224a3 1867 }
3196a88a 1868
619c5cb6
VZ		 1869 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1870 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1871 /* q_obj->complete_cmd() failure means that this was
1872 * an unexpected completion.
1873 *
1874 * In this case we don't want to increase the bp->spq_left
1875 * because apparently we haven't sent this command the first
1876 * place.
1877 */
1878#ifdef BNX2X_STOP_ON_ERROR
1879 bnx2x_panic();
1880#else
1881 return;
1882#endif
1883
4e857c58 1884 smp_mb__before_atomic();
6e30dd4e 1885 atomic_inc(&bp->cq_spq_left);
619c5cb6 1886 /* push the change in bp->spq_left and towards the memory */
4e857c58 1887 smp_mb__after_atomic();
49d66772 1888
d6cae238
VZ		 1889 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1890
a3348722
BW		 1891 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1892 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1893 /* if Q update ramrod is completed for last Q in AFEX vif set
1894 * flow, then ACK MCP at the end
1895 *
1896 * mark pending ACK to MCP bit.
1897 * prevent case that both bits are cleared.
1898 * At the end of load/unload driver checks that
2de67439 1899 * sp_state is cleared, and this order prevents
a3348722
BW		 1900 * races
1901 */
4e857c58 1902 smp_mb__before_atomic();
a3348722
BW		 1903 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1904 wmb();
1905 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 1906 smp_mb__after_atomic();
a3348722 1907
fd1fc79d
AE		 1908 /* schedule the sp task as mcp ack is required */
1909 bnx2x_schedule_sp_task(bp);
a3348722
BW		 1910 }
1911
523224a3 1912 return;
a2fbb9ea
ET		 1913}
1914
9f6c9258 1915irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
a2fbb9ea 1916{
555f6c78 1917 struct bnx2x *bp = netdev_priv(dev_instance);
a2fbb9ea 1918 u16 status = bnx2x_ack_int(bp);
34f80b04 1919 u16 mask;
ca00392c 1920 int i;
6383c0b3 1921 u8 cos;
a2fbb9ea 1922
34f80b04 1923 /* Return here if interrupt is shared and it's not for us */
a2fbb9ea
ET		 1924 if (unlikely(status == 0)) {
1925 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1926 return IRQ_NONE;
1927 }
f5372251 1928 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
a2fbb9ea 1929
3196a88a
EG		 1930#ifdef BNX2X_STOP_ON_ERROR
1931 if (unlikely(bp->panic))
1932 return IRQ_HANDLED;
1933#endif
1934
ec6ba945 1935 for_each_eth_queue(bp, i) {
ca00392c 1936 struct bnx2x_fastpath *fp = &bp->fp[i];
a2fbb9ea 1937
55c11941 1938 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
ca00392c 1939 if (status & mask) {
619c5cb6 1940 /* Handle Rx or Tx according to SB id */
6383c0b3 1941 for_each_cos_in_tx_queue(fp, cos)
65565884 1942 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
523224a3 1943 prefetch(&fp->sb_running_index[SM_RX_ID]);
f5fbf115 1944 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi));
ca00392c
EG		 1945 status &= ~mask;
1946 }
a2fbb9ea
ET		 1947 }
1948
55c11941
MS		 1949 if (CNIC_SUPPORT(bp)) {
1950 mask = 0x2;
1951 if (status & (mask | 0x1)) {
1952 struct cnic_ops *c_ops = NULL;
993ac7b5 1953
ad9b4359
MC		 1954 rcu_read_lock();
1955 c_ops = rcu_dereference(bp->cnic_ops);
1956 if (c_ops && (bp->cnic_eth_dev.drv_state &
1957 CNIC_DRV_STATE_HANDLES_IRQ))
1958 c_ops->cnic_handler(bp->cnic_data, NULL);
1959 rcu_read_unlock();
993ac7b5 1960
55c11941
MS		 1961 status &= ~mask;
1962 }
993ac7b5 1963 }
a2fbb9ea 1964
34f80b04 1965 if (unlikely(status & 0x1)) {
fd1fc79d
AE		 1966
1967 /* schedule sp task to perform default status block work, ack
1968 * attentions and enable interrupts.
1969 */
1970 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 1971
1972 status &= ~0x1;
1973 if (!status)
1974 return IRQ_HANDLED;
1975 }
1976
cdaa7cb8
VZ		 1977 if (unlikely(status))
1978 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
34f80b04 1979 status);
a2fbb9ea 1980
c18487ee 1981 return IRQ_HANDLED;
a2fbb9ea
ET		 1982}
1983
c18487ee
YR		 1984/* Link */
1985
1986/*
1987 * General service functions
1988 */
a2fbb9ea 1989
9f6c9258 1990int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 1991{
1992 u32 lock_status;
1993 u32 resource_bit = (1 << resource);
4a37fb66
YG		 1994 int func = BP_FUNC(bp);
1995 u32 hw_lock_control_reg;
c18487ee 1996 int cnt;
a2fbb9ea 1997
c18487ee
YR		 1998 /* Validating that the resource is within range */
1999 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2000 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2001 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2002 return -EINVAL;
2003 }
a2fbb9ea 2004
4a37fb66
YG		 2005 if (func <= 5) {
2006 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2007 } else {
2008 hw_lock_control_reg =
2009 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2010 }
2011
c18487ee 2012 /* Validating that the resource is not already taken */
4a37fb66 2013 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2014 if (lock_status & resource_bit) {
51c1a580 2015 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
c18487ee
YR		 2016 lock_status, resource_bit);
2017 return -EEXIST;
2018 }
a2fbb9ea 2019
46230476
EG		 2020 /* Try for 5 second every 5ms */
2021 for (cnt = 0; cnt < 1000; cnt++) {
c18487ee 2022 /* Try to acquire the lock */
4a37fb66
YG		 2023 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2024 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee
YR		 2025 if (lock_status & resource_bit)
2026 return 0;
a2fbb9ea 2027
639d65b8 2028 usleep_range(5000, 10000);
a2fbb9ea 2029 }
51c1a580 2030 BNX2X_ERR("Timeout\n");
c18487ee
YR		 2031 return -EAGAIN;
2032}
a2fbb9ea 2033
c9ee9206
VZ		 2034int bnx2x_release_leader_lock(struct bnx2x *bp)
2035{
2036 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2037}
2038
9f6c9258 2039int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
c18487ee
YR		 2040{
2041 u32 lock_status;
2042 u32 resource_bit = (1 << resource);
4a37fb66
YG		 2043 int func = BP_FUNC(bp);
2044 u32 hw_lock_control_reg;
a2fbb9ea 2045
c18487ee
YR		 2046 /* Validating that the resource is within range */
2047 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
51c1a580 2048 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
c18487ee
YR		 2049 resource, HW_LOCK_MAX_RESOURCE_VALUE);
2050 return -EINVAL;
2051 }
2052
4a37fb66
YG		 2053 if (func <= 5) {
2054 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2055 } else {
2056 hw_lock_control_reg =
2057 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2058 }
2059
c18487ee 2060 /* Validating that the resource is currently taken */
4a37fb66 2061 lock_status = REG_RD(bp, hw_lock_control_reg);
c18487ee 2062 if (!(lock_status & resource_bit)) {
6bf07b8e
YM		 2063 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2064 lock_status, resource_bit);
c18487ee 2065 return -EFAULT;
a2fbb9ea
ET		 2066 }
2067
9f6c9258
DK		 2068 REG_WR(bp, hw_lock_control_reg, resource_bit);
2069 return 0;
c18487ee 2070}
a2fbb9ea 2071
4acac6a5
EG		 2072int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2073{
2074 /* The GPIO should be swapped if swap register is set and active */
2075 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2076 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2077 int gpio_shift = gpio_num +
2078 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2079 u32 gpio_mask = (1 << gpio_shift);
2080 u32 gpio_reg;
2081 int value;
2082
2083 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2084 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2085 return -EINVAL;
2086 }
2087
2088 /* read GPIO value */
2089 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2090
2091 /* get the requested pin value */
2092 if ((gpio_reg & gpio_mask) == gpio_mask)
2093 value = 1;
2094 else
2095 value = 0;
2096
4acac6a5
EG		 2097 return value;
2098}
2099
17de50b7 2100int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
c18487ee
YR		 2101{
2102 /* The GPIO should be swapped if swap register is set and active */
2103 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
17de50b7 2104 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
c18487ee
YR		 2105 int gpio_shift = gpio_num +
2106 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2107 u32 gpio_mask = (1 << gpio_shift);
2108 u32 gpio_reg;
a2fbb9ea 2109
c18487ee
YR		 2110 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2111 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2112 return -EINVAL;
2113 }
a2fbb9ea 2114
4a37fb66 2115 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
c18487ee
YR		 2116 /* read GPIO and mask except the float bits */
2117 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
a2fbb9ea 2118
c18487ee
YR		 2119 switch (mode) {
2120 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
51c1a580
MS		 2121 DP(NETIF_MSG_LINK,
2122 "Set GPIO %d (shift %d) -> output low\n",
c18487ee
YR		 2123 gpio_num, gpio_shift);
2124 /* clear FLOAT and set CLR */
2125 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2127 break;
a2fbb9ea 2128
c18487ee 2129 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
51c1a580
MS		 2130 DP(NETIF_MSG_LINK,
2131 "Set GPIO %d (shift %d) -> output high\n",
c18487ee
YR		 2132 gpio_num, gpio_shift);
2133 /* clear FLOAT and set SET */
2134 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2136 break;
a2fbb9ea 2137
17de50b7 2138 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
51c1a580
MS		 2139 DP(NETIF_MSG_LINK,
2140 "Set GPIO %d (shift %d) -> input\n",
c18487ee
YR		 2141 gpio_num, gpio_shift);
2142 /* set FLOAT */
2143 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2144 break;
a2fbb9ea 2145
c18487ee
YR		 2146 default:
2147 break;
a2fbb9ea
ET		 2148 }
2149
c18487ee 2150 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
4a37fb66 2151 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
f1410647 2152
c18487ee 2153 return 0;
a2fbb9ea
ET		 2154}
2155
0d40f0d4
YR		 2156int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2157{
2158 u32 gpio_reg = 0;
2159 int rc = 0;
2160
2161 /* Any port swapping should be handled by caller. */
2162
2163 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2164 /* read GPIO and mask except the float bits */
2165 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2166 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2167 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2168 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2169
2170 switch (mode) {
2171 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2172 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2173 /* set CLR */
2174 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2175 break;
2176
2177 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2178 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2179 /* set SET */
2180 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2181 break;
2182
2183 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2184 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2185 /* set FLOAT */
2186 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2187 break;
2188
2189 default:
2190 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2191 rc = -EINVAL;
2192 break;
2193 }
2194
2195 if (rc == 0)
2196 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2197
2198 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199
2200 return rc;
2201}
2202
4acac6a5
EG		 2203int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2204{
2205 /* The GPIO should be swapped if swap register is set and active */
2206 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2207 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2208 int gpio_shift = gpio_num +
2209 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2210 u32 gpio_mask = (1 << gpio_shift);
2211 u32 gpio_reg;
2212
2213 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2214 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2215 return -EINVAL;
2216 }
2217
2218 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2219 /* read GPIO int */
2220 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2221
2222 switch (mode) {
2223 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
51c1a580
MS		 2224 DP(NETIF_MSG_LINK,
2225 "Clear GPIO INT %d (shift %d) -> output low\n",
2226 gpio_num, gpio_shift);
4acac6a5
EG		 2227 /* clear SET and set CLR */
2228 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2229 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2230 break;
2231
2232 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
51c1a580
MS		 2233 DP(NETIF_MSG_LINK,
2234 "Set GPIO INT %d (shift %d) -> output high\n",
2235 gpio_num, gpio_shift);
4acac6a5
EG		 2236 /* clear CLR and set SET */
2237 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2238 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2239 break;
2240
2241 default:
2242 break;
2243 }
2244
2245 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2246 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2247
2248 return 0;
2249}
2250
d6d99a3f 2251static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
a2fbb9ea 2252{
c18487ee 2253 u32 spio_reg;
a2fbb9ea 2254
d6d99a3f
YM		 2255 /* Only 2 SPIOs are configurable */
2256 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2257 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
c18487ee 2258 return -EINVAL;
a2fbb9ea
ET		 2259 }
2260
4a37fb66 2261 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2262 /* read SPIO and mask except the float bits */
d6d99a3f 2263 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
a2fbb9ea 2264
c18487ee 2265 switch (mode) {
d6d99a3f
YM		 2266 case MISC_SPIO_OUTPUT_LOW:
2267 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
c18487ee 2268 /* clear FLOAT and set CLR */
d6d99a3f
YM		 2269 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2270 spio_reg |= (spio << MISC_SPIO_CLR_POS);
c18487ee 2271 break;
a2fbb9ea 2272
d6d99a3f
YM		 2273 case MISC_SPIO_OUTPUT_HIGH:
2274 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
c18487ee 2275 /* clear FLOAT and set SET */
d6d99a3f
YM		 2276 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2277 spio_reg |= (spio << MISC_SPIO_SET_POS);
c18487ee 2278 break;
a2fbb9ea 2279
d6d99a3f
YM		 2280 case MISC_SPIO_INPUT_HI_Z:
2281 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
c18487ee 2282 /* set FLOAT */
d6d99a3f 2283 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
c18487ee 2284 break;
a2fbb9ea 2285
c18487ee
YR		 2286 default:
2287 break;
a2fbb9ea
ET		 2288 }
2289
c18487ee 2290 REG_WR(bp, MISC_REG_SPIO, spio_reg);
4a37fb66 2291 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
c18487ee 2292
a2fbb9ea
ET		 2293 return 0;
2294}
2295
9f6c9258 2296void bnx2x_calc_fc_adv(struct bnx2x *bp)
a2fbb9ea 2297{
a22f0788 2298 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1359d73c
YM		 2299
2300 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2301 ADVERTISED_Pause);
ad33ea3a
EG		 2302 switch (bp->link_vars.ieee_fc &
2303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
c18487ee 2304 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
a22f0788 2305 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
f85582f8 2306 ADVERTISED_Pause);
c18487ee 2307 break;
356e2385 2308
c18487ee 2309 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
a22f0788 2310 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
c18487ee 2311 break;
356e2385 2312
c18487ee 2313 default:
c18487ee
YR		 2314 break;
2315 }
2316}
f1410647 2317
cd1dfce2 2318static void bnx2x_set_requested_fc(struct bnx2x *bp)
c18487ee 2319{
cd1dfce2
YM		 2320 /* Initialize link parameters structure variables
2321 * It is recommended to turn off RX FC for jumbo frames
2322 * for better performance
2323 */
2324 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2325 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2326 else
2327 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2328}
a2fbb9ea 2329
9156b30b
DK		 2330static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2331{
2332 u32 pause_enabled = 0;
2333
2334 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2335 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2336 pause_enabled = 1;
2337
2338 REG_WR(bp, BAR_USTRORM_INTMEM +
2339 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2340 pause_enabled);
2341 }
2342
2343 DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2344 pause_enabled ? "enabled" : "disabled");
2345}
2346
cd1dfce2
YM		 2347int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2348{
2349 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2350 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2351
2352 if (!BP_NOMCP(bp)) {
2353 bnx2x_set_requested_fc(bp);
4a37fb66 2354 bnx2x_acquire_phy_lock(bp);
b5bf9068 2355
a22f0788 2356 if (load_mode == LOAD_DIAG) {
1cb0c788
YR		 2357 struct link_params *lp = &bp->link_params;
2358 lp->loopback_mode = LOOPBACK_XGXS;
2f43b821
YM		 2359 /* Prefer doing PHY loopback at highest speed */
2360 if (lp->req_line_speed[cfx_idx] < SPEED_20000) {
1cb0c788 2361 if (lp->speed_cap_mask[cfx_idx] &
2f43b821 2362 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
1cb0c788 2363 lp->req_line_speed[cfx_idx] =
2f43b821
YM		 2364 SPEED_20000;
2365 else if (lp->speed_cap_mask[cfx_idx] &
2366 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2367 lp->req_line_speed[cfx_idx] =
2368 SPEED_10000;
1cb0c788
YR		 2369 else
2370 lp->req_line_speed[cfx_idx] =
2371 SPEED_1000;
2372 }
a22f0788 2373 }
b5bf9068 2374
8970b2e4
MS		 2375 if (load_mode == LOAD_LOOPBACK_EXT) {
2376 struct link_params *lp = &bp->link_params;
2377 lp->loopback_mode = LOOPBACK_EXT;
2378 }
2379
19680c48 2380 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
b5bf9068 2381
4a37fb66 2382 bnx2x_release_phy_lock(bp);
a2fbb9ea 2383
9156b30b
DK		 2384 bnx2x_init_dropless_fc(bp);
2385
3c96c68b
EG		 2386 bnx2x_calc_fc_adv(bp);
2387
cd1dfce2 2388 if (bp->link_vars.link_up) {
b5bf9068 2389 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
19680c48 2390 bnx2x_link_report(bp);
cd1dfce2
YM		 2391 }
2392 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
a22f0788 2393 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
19680c48
EG		 2394 return rc;
2395 }
f5372251 2396 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
19680c48 2397 return -EINVAL;
a2fbb9ea
ET		 2398}
2399
9f6c9258 2400void bnx2x_link_set(struct bnx2x *bp)
a2fbb9ea 2401{
19680c48 2402 if (!BP_NOMCP(bp)) {
4a37fb66 2403 bnx2x_acquire_phy_lock(bp);
19680c48 2404 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
4a37fb66 2405 bnx2x_release_phy_lock(bp);
a2fbb9ea 2406
9156b30b
DK		 2407 bnx2x_init_dropless_fc(bp);
2408
19680c48
EG		 2409 bnx2x_calc_fc_adv(bp);
2410 } else
f5372251 2411 BNX2X_ERR("Bootcode is missing - can not set link\n");
c18487ee 2412}
a2fbb9ea 2413
c18487ee
YR		 2414static void bnx2x__link_reset(struct bnx2x *bp)
2415{
19680c48 2416 if (!BP_NOMCP(bp)) {
4a37fb66 2417 bnx2x_acquire_phy_lock(bp);
5d07d868 2418 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
4a37fb66 2419 bnx2x_release_phy_lock(bp);
19680c48 2420 } else
f5372251 2421 BNX2X_ERR("Bootcode is missing - can not reset link\n");
c18487ee 2422}
a2fbb9ea 2423
5d07d868
YM		 2424void bnx2x_force_link_reset(struct bnx2x *bp)
2425{
2426 bnx2x_acquire_phy_lock(bp);
2427 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2428 bnx2x_release_phy_lock(bp);
2429}
2430
a22f0788 2431u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
c18487ee 2432{
2145a920 2433 u8 rc = 0;
a2fbb9ea 2434
2145a920
VZ		 2435 if (!BP_NOMCP(bp)) {
2436 bnx2x_acquire_phy_lock(bp);
a22f0788
YR		 2437 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2438 is_serdes);
2145a920
VZ		 2439 bnx2x_release_phy_lock(bp);
2440 } else
2441 BNX2X_ERR("Bootcode is missing - can not test link\n");
a2fbb9ea 2442
c18487ee
YR		 2443 return rc;
2444}
a2fbb9ea 2445
2691d51d
EG		 2446/* Calculates the sum of vn_min_rates.
2447 It's needed for further normalizing of the min_rates.
2448 Returns:
2449 sum of vn_min_rates.
2450 or
2451 0 - if all the min_rates are 0.
16a5fd92 2452 In the later case fairness algorithm should be deactivated.
2691d51d
EG		 2453 If not all min_rates are zero then those that are zeroes will be set to 1.
2454 */
b475d78f
YM		 2455static void bnx2x_calc_vn_min(struct bnx2x *bp,
2456 struct cmng_init_input *input)
2691d51d
EG		 2457{
2458 int all_zero = 1;
2691d51d
EG		 2459 int vn;
2460
3395a033 2461 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
f2e0899f 2462 u32 vn_cfg = bp->mf_config[vn];
2691d51d
EG		 2463 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2464 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2465
2466 /* Skip hidden vns */
2467 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
b475d78f 2468 vn_min_rate = 0;
2691d51d 2469 /* If min rate is zero - set it to 1 */
b475d78f 2470 else if (!vn_min_rate)
2691d51d
EG		 2471 vn_min_rate = DEF_MIN_RATE;
2472 else
2473 all_zero = 0;
2474
b475d78f 2475 input->vnic_min_rate[vn] = vn_min_rate;
2691d51d
EG		 2476 }
2477
30ae438b
DK		 2478 /* if ETS or all min rates are zeros - disable fairness */
2479 if (BNX2X_IS_ETS_ENABLED(bp)) {
b475d78f 2480 input->flags.cmng_enables &=
30ae438b
DK		 2481 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2483 } else if (all_zero) {
b475d78f 2484 input->flags.cmng_enables &=
b015e3d1 2485 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
b475d78f
YM		 2486 DP(NETIF_MSG_IFUP,
2487 "All MIN values are zeroes fairness will be disabled\n");
b015e3d1 2488 } else
b475d78f 2489 input->flags.cmng_enables |=
b015e3d1 2490 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2691d51d
EG		 2491}
2492
b475d78f
YM		 2493static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2494 struct cmng_init_input *input)
34f80b04 2495{
b475d78f 2496 u16 vn_max_rate;
f2e0899f 2497 u32 vn_cfg = bp->mf_config[vn];
34f80b04 2498
b475d78f 2499 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
34f80b04 2500 vn_max_rate = 0;
b475d78f 2501 else {
faa6fcbb
DK		 2502 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2503
da3cc2da 2504 if (IS_MF_PERCENT_BW(bp)) {
faa6fcbb
DK		 2505 /* maxCfg in percents of linkspeed */
2506 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
b475d78f 2507 } else /* SD modes */
faa6fcbb
DK		 2508 /* maxCfg is absolute in 100Mb units */
2509 vn_max_rate = maxCfg * 100;
34f80b04 2510 }
f85582f8 2511
b475d78f 2512 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
34f80b04 2513
b475d78f 2514 input->vnic_max_rate[vn] = vn_max_rate;
34f80b04 2515}
f85582f8 2516
523224a3
DK		 2517static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2518{
2519 if (CHIP_REV_IS_SLOW(bp))
2520 return CMNG_FNS_NONE;
fb3bff17 2521 if (IS_MF(bp))
523224a3
DK		 2522 return CMNG_FNS_MINMAX;
2523
2524 return CMNG_FNS_NONE;
2525}
2526
2ae17f66 2527void bnx2x_read_mf_cfg(struct bnx2x *bp)
523224a3 2528{
0793f83f 2529 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
523224a3
DK		 2530
2531 if (BP_NOMCP(bp))
16a5fd92 2532 return; /* what should be the default value in this case */
523224a3 2533
0793f83f
DK		 2534 /* For 2 port configuration the absolute function number formula
2535 * is:
2536 * abs_func = 2 * vn + BP_PORT + BP_PATH
2537 *
2538 * and there are 4 functions per port
2539 *
2540 * For 4 port configuration it is
2541 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2542 *
2543 * and there are 2 functions per port
2544 */
3395a033 2545 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
0793f83f
DK		 2546 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2547
2548 if (func >= E1H_FUNC_MAX)
2549 break;
2550
f2e0899f 2551 bp->mf_config[vn] =
523224a3
DK		 2552 MF_CFG_RD(bp, func_mf_config[func].config);
2553 }
a3348722
BW		 2554 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2555 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2556 bp->flags |= MF_FUNC_DIS;
2557 } else {
2558 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2559 bp->flags &= ~MF_FUNC_DIS;
2560 }
523224a3
DK		 2561}
2562
2563static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2564{
b475d78f
YM		 2565 struct cmng_init_input input;
2566 memset(&input, 0, sizeof(struct cmng_init_input));
2567
2568 input.port_rate = bp->link_vars.line_speed;
523224a3 2569
568e2426 2570 if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
523224a3
DK		 2571 int vn;
2572
523224a3
DK		 2573 /* read mf conf from shmem */
2574 if (read_cfg)
2575 bnx2x_read_mf_cfg(bp);
2576
523224a3 2577 /* vn_weight_sum and enable fairness if not 0 */
b475d78f 2578 bnx2x_calc_vn_min(bp, &input);
523224a3
DK		 2579
2580 /* calculate and set min-max rate for each vn */
c4154f25 2581 if (bp->port.pmf)
3395a033 2582 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
b475d78f 2583 bnx2x_calc_vn_max(bp, vn, &input);
523224a3
DK		 2584
2585 /* always enable rate shaping and fairness */
b475d78f 2586 input.flags.cmng_enables |=
523224a3 2587 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
b475d78f
YM		 2588
2589 bnx2x_init_cmng(&input, &bp->cmng);
523224a3
DK		 2590 return;
2591 }
2592
2593 /* rate shaping and fairness are disabled */
2594 DP(NETIF_MSG_IFUP,
2595 "rate shaping and fairness are disabled\n");
2596}
34f80b04 2597
1191cb83
ED		 2598static void storm_memset_cmng(struct bnx2x *bp,
2599 struct cmng_init *cmng,
2600 u8 port)
2601{
2602 int vn;
2603 size_t size = sizeof(struct cmng_struct_per_port);
2604
2605 u32 addr = BAR_XSTRORM_INTMEM +
2606 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2607
2608 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2609
2610 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2611 int func = func_by_vn(bp, vn);
2612
2613 addr = BAR_XSTRORM_INTMEM +
2614 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2615 size = sizeof(struct rate_shaping_vars_per_vn);
2616 __storm_memset_struct(bp, addr, size,
2617 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2618
2619 addr = BAR_XSTRORM_INTMEM +
2620 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2621 size = sizeof(struct fairness_vars_per_vn);
2622 __storm_memset_struct(bp, addr, size,
2623 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2624 }
2625}
2626
568e2426
DK		 2627/* init cmng mode in HW according to local configuration */
2628void bnx2x_set_local_cmng(struct bnx2x *bp)
2629{
2630 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2631
2632 if (cmng_fns != CMNG_FNS_NONE) {
2633 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2634 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2635 } else {
2636 /* rate shaping and fairness are disabled */
2637 DP(NETIF_MSG_IFUP,
2638 "single function mode without fairness\n");
2639 }
2640}
2641
c18487ee
YR		 2642/* This function is called upon link interrupt */
2643static void bnx2x_link_attn(struct bnx2x *bp)
2644{
bb2a0f7a
YG		 2645 /* Make sure that we are synced with the current statistics */
2646 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2647
c18487ee 2648 bnx2x_link_update(&bp->link_params, &bp->link_vars);
a2fbb9ea 2649
9156b30b 2650 bnx2x_init_dropless_fc(bp);
1c06328c 2651
9156b30b 2652 if (bp->link_vars.link_up) {
1c06328c 2653
619c5cb6 2654 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
bb2a0f7a
YG		 2655 struct host_port_stats *pstats;
2656
2657 pstats = bnx2x_sp(bp, port_stats);
619c5cb6 2658 /* reset old mac stats */
bb2a0f7a
YG		 2659 memset(&(pstats->mac_stx[0]), 0,
2660 sizeof(struct mac_stx));
2661 }
f34d28ea 2662 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a
YG		 2663 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2664 }
2665
568e2426
DK		 2666 if (bp->link_vars.link_up && bp->link_vars.line_speed)
2667 bnx2x_set_local_cmng(bp);
9fdc3e95 2668
2ae17f66
VZ		 2669 __bnx2x_link_report(bp);
2670
9fdc3e95
DK		 2671 if (IS_MF(bp))
2672 bnx2x_link_sync_notify(bp);
c18487ee 2673}
a2fbb9ea 2674
9f6c9258 2675void bnx2x__link_status_update(struct bnx2x *bp)
c18487ee 2676{
2ae17f66 2677 if (bp->state != BNX2X_STATE_OPEN)
c18487ee 2678 return;
a2fbb9ea 2679
00253a8c 2680 /* read updated dcb configuration */
ad5afc89
AE		 2681 if (IS_PF(bp)) {
2682 bnx2x_dcbx_pmf_update(bp);
2683 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2684 if (bp->link_vars.link_up)
2685 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2686 else
2687 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2688 /* indicate link status */
2689 bnx2x_link_report(bp);
a2fbb9ea 2690
ad5afc89
AE		 2691 } else { /* VF */
2692 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2693 SUPPORTED_10baseT_Full |
2694 SUPPORTED_100baseT_Half |
2695 SUPPORTED_100baseT_Full |
2696 SUPPORTED_1000baseT_Full |
2697 SUPPORTED_2500baseX_Full |
2698 SUPPORTED_10000baseT_Full |
2699 SUPPORTED_TP |
2700 SUPPORTED_FIBRE |
2701 SUPPORTED_Autoneg |
2702 SUPPORTED_Pause |
2703 SUPPORTED_Asym_Pause);
2704 bp->port.advertising[0] = bp->port.supported[0];
2705
2706 bp->link_params.bp = bp;
2707 bp->link_params.port = BP_PORT(bp);
2708 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2709 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2710 bp->link_params.req_line_speed[0] = SPEED_10000;
2711 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2712 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2713 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2714 bp->link_vars.line_speed = SPEED_10000;
2715 bp->link_vars.link_status =
2716 (LINK_STATUS_LINK_UP |
2717 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2718 bp->link_vars.link_up = 1;
2719 bp->link_vars.duplex = DUPLEX_FULL;
2720 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2721 __bnx2x_link_report(bp);
6495d15a
DK		 2722
2723 bnx2x_sample_bulletin(bp);
2724
2725 /* if bulletin board did not have an update for link status
2726 * __bnx2x_link_report will report current status
2727 * but it will NOT duplicate report in case of already reported
2728 * during sampling bulletin board.
2729 */
bb2a0f7a 2730 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
ad5afc89 2731 }
a2fbb9ea 2732}
a2fbb9ea 2733
a3348722
BW		 2734static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2735 u16 vlan_val, u8 allowed_prio)
2736{
86564c3f 2737 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2738 struct bnx2x_func_afex_update_params *f_update_params =
2739 &func_params.params.afex_update;
2740
2741 func_params.f_obj = &bp->func_obj;
2742 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2743
2744 /* no need to wait for RAMROD completion, so don't
2745 * set RAMROD_COMP_WAIT flag
2746 */
2747
2748 f_update_params->vif_id = vifid;
2749 f_update_params->afex_default_vlan = vlan_val;
2750 f_update_params->allowed_priorities = allowed_prio;
2751
2752 /* if ramrod can not be sent, response to MCP immediately */
2753 if (bnx2x_func_state_change(bp, &func_params) < 0)
2754 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2755
2756 return 0;
2757}
2758
2759static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2760 u16 vif_index, u8 func_bit_map)
2761{
86564c3f 2762 struct bnx2x_func_state_params func_params = {NULL};
a3348722
BW		 2763 struct bnx2x_func_afex_viflists_params *update_params =
2764 &func_params.params.afex_viflists;
2765 int rc;
2766 u32 drv_msg_code;
2767
2768 /* validate only LIST_SET and LIST_GET are received from switch */
2769 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2770 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2771 cmd_type);
2772
2773 func_params.f_obj = &bp->func_obj;
2774 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2775
2776 /* set parameters according to cmd_type */
2777 update_params->afex_vif_list_command = cmd_type;
86564c3f 2778 update_params->vif_list_index = vif_index;
a3348722
BW		 2779 update_params->func_bit_map =
2780 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2781 update_params->func_to_clear = 0;
2782 drv_msg_code =
2783 (cmd_type == VIF_LIST_RULE_GET) ?
2784 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2785 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2786
2787 /* if ramrod can not be sent, respond to MCP immediately for
2788 * SET and GET requests (other are not triggered from MCP)
2789 */
2790 rc = bnx2x_func_state_change(bp, &func_params);
2791 if (rc < 0)
2792 bnx2x_fw_command(bp, drv_msg_code, 0);
2793
2794 return 0;
2795}
2796
2797static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2798{
2799 struct afex_stats afex_stats;
2800 u32 func = BP_ABS_FUNC(bp);
2801 u32 mf_config;
2802 u16 vlan_val;
2803 u32 vlan_prio;
2804 u16 vif_id;
2805 u8 allowed_prio;
2806 u8 vlan_mode;
2807 u32 addr_to_write, vifid, addrs, stats_type, i;
2808
2809 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2810 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2811 DP(BNX2X_MSG_MCP,
2812 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2813 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2814 }
2815
2816 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2817 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2818 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2819 DP(BNX2X_MSG_MCP,
2820 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2821 vifid, addrs);
2822 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2823 addrs);
2824 }
2825
2826 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2827 addr_to_write = SHMEM2_RD(bp,
2828 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2829 stats_type = SHMEM2_RD(bp,
2830 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2831
2832 DP(BNX2X_MSG_MCP,
2833 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2834 addr_to_write);
2835
2836 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2837
2838 /* write response to scratchpad, for MCP */
2839 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2840 REG_WR(bp, addr_to_write + i*sizeof(u32),
2841 *(((u32 *)(&afex_stats))+i));
2842
2843 /* send ack message to MCP */
2844 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2845 }
2846
2847 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2848 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2849 bp->mf_config[BP_VN(bp)] = mf_config;
2850 DP(BNX2X_MSG_MCP,
2851 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2852 mf_config);
2853
2854 /* if VIF_SET is "enabled" */
2855 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2856 /* set rate limit directly to internal RAM */
2857 struct cmng_init_input cmng_input;
2858 struct rate_shaping_vars_per_vn m_rs_vn;
2859 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2860 u32 addr = BAR_XSTRORM_INTMEM +
2861 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2862
2863 bp->mf_config[BP_VN(bp)] = mf_config;
2864
2865 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2866 m_rs_vn.vn_counter.rate =
2867 cmng_input.vnic_max_rate[BP_VN(bp)];
2868 m_rs_vn.vn_counter.quota =
2869 (m_rs_vn.vn_counter.rate *
2870 RS_PERIODIC_TIMEOUT_USEC) / 8;
2871
2872 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2873
2874 /* read relevant values from mf_cfg struct in shmem */
2875 vif_id =
2876 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2877 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2878 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2879 vlan_val =
2880 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2881 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2882 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2883 vlan_prio = (mf_config &
2884 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2885 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2886 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2887 vlan_mode =
2888 (MF_CFG_RD(bp,
2889 func_mf_config[func].afex_config) &
2890 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2891 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2892 allowed_prio =
2893 (MF_CFG_RD(bp,
2894 func_mf_config[func].afex_config) &
2895 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2896 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2897
2898 /* send ramrod to FW, return in case of failure */
2899 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2900 allowed_prio))
2901 return;
2902
2903 bp->afex_def_vlan_tag = vlan_val;
2904 bp->afex_vlan_mode = vlan_mode;
2905 } else {
2906 /* notify link down because BP->flags is disabled */
2907 bnx2x_link_report(bp);
2908
2909 /* send INVALID VIF ramrod to FW */
2910 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2911
2912 /* Reset the default afex VLAN */
2913 bp->afex_def_vlan_tag = -1;
2914 }
2915 }
2916}
2917
7609647e
YM		 2918static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2919{
2920 struct bnx2x_func_switch_update_params *switch_update_params;
2921 struct bnx2x_func_state_params func_params;
2922
2923 memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2924 switch_update_params = &func_params.params.switch_update;
2925 func_params.f_obj = &bp->func_obj;
2926 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2927
230d00eb 2928 if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
7609647e
YM		 2929 int func = BP_ABS_FUNC(bp);
2930 u32 val;
2931
2932 /* Re-learn the S-tag from shmem */
2933 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2934 FUNC_MF_CFG_E1HOV_TAG_MASK;
2935 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2936 bp->mf_ov = val;
2937 } else {
2938 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2939 goto fail;
2940 }
2941
2942 /* Configure new S-tag in LLH */
2943 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2944 bp->mf_ov);
2945
2946 /* Send Ramrod to update FW of change */
2947 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2948 &switch_update_params->changes);
2949 switch_update_params->vlan = bp->mf_ov;
2950
2951 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2952 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2953 bp->mf_ov);
2954 goto fail;
230d00eb
YM		 2955 } else {
2956 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
2957 bp->mf_ov);
7609647e 2958 }
230d00eb
YM		 2959 } else {
2960 goto fail;
7609647e
YM		 2961 }
2962
230d00eb
YM		 2963 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2964 return;
7609647e
YM		 2965fail:
2966 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2967}
2968
34f80b04
EG		 2969static void bnx2x_pmf_update(struct bnx2x *bp)
2970{
2971 int port = BP_PORT(bp);
2972 u32 val;
2973
2974 bp->port.pmf = 1;
51c1a580 2975 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
34f80b04 2976
3deb8167
YR		 2977 /*
2978 * We need the mb() to ensure the ordering between the writing to
2979 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2980 */
2981 smp_mb();
2982
2983 /* queue a periodic task */
2984 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2985
ef01854e
DK		 2986 bnx2x_dcbx_pmf_update(bp);
2987
34f80b04 2988 /* enable nig attention */
3395a033 2989 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
f2e0899f
DK		 2990 if (bp->common.int_block == INT_BLOCK_HC) {
2991 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2992 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
619c5cb6 2993 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 2994 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2995 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2996 }
bb2a0f7a
YG		 2997
2998 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
34f80b04
EG		 2999}
3000
c18487ee 3001/* end of Link */
a2fbb9ea
ET		 3002
3003/* slow path */
3004
3005/*
3006 * General service functions
3007 */
3008
2691d51d 3009/* send the MCP a request, block until there is a reply */
a22f0788 3010u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2691d51d 3011{
f2e0899f 3012 int mb_idx = BP_FW_MB_IDX(bp);
a5971d43 3013 u32 seq;
2691d51d
EG		 3014 u32 rc = 0;
3015 u32 cnt = 1;
3016 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3017
c4ff7cbf 3018 mutex_lock(&bp->fw_mb_mutex);
a5971d43 3019 seq = ++bp->fw_seq;
f2e0899f
DK		 3020 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3021 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3022
754a2f52
DK		 3023 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3024 (command | seq), param);
2691d51d
EG		 3025
3026 do {
3027 /* let the FW do it's magic ... */
3028 msleep(delay);
3029
f2e0899f 3030 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2691d51d 3031
c4ff7cbf
EG		 3032 /* Give the FW up to 5 second (500*10ms) */
3033 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2691d51d
EG		 3034
3035 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3036 cnt*delay, rc, seq);
3037
3038 /* is this a reply to our command? */
3039 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3040 rc &= FW_MSG_CODE_MASK;
3041 else {
3042 /* FW BUG! */
3043 BNX2X_ERR("FW failed to respond!\n");
3044 bnx2x_fw_dump(bp);
3045 rc = 0;
3046 }
c4ff7cbf 3047 mutex_unlock(&bp->fw_mb_mutex);
2691d51d
EG		 3048
3049 return rc;
3050}
3051
1191cb83
ED		 3052static void storm_memset_func_cfg(struct bnx2x *bp,
3053 struct tstorm_eth_function_common_config *tcfg,
3054 u16 abs_fid)
3055{
3056 size_t size = sizeof(struct tstorm_eth_function_common_config);
3057
3058 u32 addr = BAR_TSTRORM_INTMEM +
3059 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3060
3061 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3062}
3063
619c5cb6
VZ		 3064void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3065{
3066 if (CHIP_IS_E1x(bp)) {
3067 struct tstorm_eth_function_common_config tcfg = {0};
3068
3069 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3070 }
3071
3072 /* Enable the function in the FW */
3073 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3074 storm_memset_func_en(bp, p->func_id, 1);
3075
3076 /* spq */
05cc5a39 3077 if (p->spq_active) {
619c5cb6
VZ		 3078 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3079 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3080 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3081 }
3082}
3083
6383c0b3 3084/**
16a5fd92 3085 * bnx2x_get_common_flags - Return common flags
6383c0b3
AE		 3086 *
3087 * @bp device handle
3088 * @fp queue handle
3089 * @zero_stats TRUE if statistics zeroing is needed
3090 *
3091 * Return the flags that are common for the Tx-only and not normal connections.
3092 */
1191cb83
ED		 3093static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3094 struct bnx2x_fastpath *fp,
3095 bool zero_stats)
28912902 3096{
619c5cb6
VZ		 3097 unsigned long flags = 0;
3098
3099 /* PF driver will always initialize the Queue to an ACTIVE state */
3100 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
28912902 3101
6383c0b3 3102 /* tx only connections collect statistics (on the same index as the
91226790
DK		 3103 * parent connection). The statistics are zeroed when the parent
3104 * connection is initialized.
6383c0b3 3105 */
50f0a562
BW		 3106
3107 __set_bit(BNX2X_Q_FLG_STATS, &flags);
3108 if (zero_stats)
3109 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3110
c14db202
YM		 3111 if (bp->flags & TX_SWITCHING)
3112 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3113
91226790 3114 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
e287a75c 3115 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
6383c0b3 3116
823e1d90
YM		 3117#ifdef BNX2X_STOP_ON_ERROR
3118 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3119#endif
3120
6383c0b3
AE		 3121 return flags;
3122}
3123
1191cb83
ED		 3124static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3125 struct bnx2x_fastpath *fp,
3126 bool leading)
6383c0b3
AE		 3127{
3128 unsigned long flags = 0;
3129
619c5cb6
VZ		 3130 /* calculate other queue flags */
3131 if (IS_MF_SD(bp))
3132 __set_bit(BNX2X_Q_FLG_OV, &flags);
28912902 3133
a3348722 3134 if (IS_FCOE_FP(fp)) {
619c5cb6 3135 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
a3348722
BW		 3136 /* For FCoE - force usage of default priority (for afex) */
3137 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3138 }
523224a3 3139
7e6b4d44 3140 if (fp->mode != TPA_MODE_DISABLED) {
619c5cb6 3141 __set_bit(BNX2X_Q_FLG_TPA, &flags);
f5219d8e 3142 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
621b4d66
DK		 3143 if (fp->mode == TPA_MODE_GRO)
3144 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
f5219d8e 3145 }
619c5cb6 3146
619c5cb6
VZ		 3147 if (leading) {
3148 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3149 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3150 }
523224a3 3151
619c5cb6
VZ		 3152 /* Always set HW VLAN stripping */
3153 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
523224a3 3154
a3348722
BW		 3155 /* configure silent vlan removal */
3156 if (IS_MF_AFEX(bp))
3157 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3158
6383c0b3 3159 return flags | bnx2x_get_common_flags(bp, fp, true);
523224a3
DK		 3160}
3161
619c5cb6 3162static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
6383c0b3
AE		 3163 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3164 u8 cos)
619c5cb6
VZ		 3165{
3166 gen_init->stat_id = bnx2x_stats_id(fp);
3167 gen_init->spcl_id = fp->cl_id;
3168
3169 /* Always use mini-jumbo MTU for FCoE L2 ring */
3170 if (IS_FCOE_FP(fp))
3171 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3172 else
3173 gen_init->mtu = bp->dev->mtu;
6383c0b3
AE		 3174
3175 gen_init->cos = cos;
02dc4025
YM		 3176
3177 gen_init->fp_hsi = ETH_FP_HSI_VERSION;
619c5cb6
VZ		 3178}
3179
3180static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
523224a3 3181 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
619c5cb6 3182 struct bnx2x_rxq_setup_params *rxq_init)
523224a3 3183{
619c5cb6 3184 u8 max_sge = 0;
523224a3
DK		 3185 u16 sge_sz = 0;
3186 u16 tpa_agg_size = 0;
3187
7e6b4d44 3188 if (fp->mode != TPA_MODE_DISABLED) {
dfacf138
DK		 3189 pause->sge_th_lo = SGE_TH_LO(bp);
3190 pause->sge_th_hi = SGE_TH_HI(bp);
3191
3192 /* validate SGE ring has enough to cross high threshold */
3193 WARN_ON(bp->dropless_fc &&
3194 pause->sge_th_hi + FW_PREFETCH_CNT >
3195 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3196
924d75ab 3197 tpa_agg_size = TPA_AGG_SIZE;
523224a3
DK		 3198 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3199 SGE_PAGE_SHIFT;
3200 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3201 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
924d75ab 3202 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
523224a3
DK		 3203 }
3204
3205 /* pause - not for e1 */
3206 if (!CHIP_IS_E1(bp)) {
dfacf138
DK		 3207 pause->bd_th_lo = BD_TH_LO(bp);
3208 pause->bd_th_hi = BD_TH_HI(bp);
3209
3210 pause->rcq_th_lo = RCQ_TH_LO(bp);
3211 pause->rcq_th_hi = RCQ_TH_HI(bp);
3212 /*
3213 * validate that rings have enough entries to cross
3214 * high thresholds
3215 */
3216 WARN_ON(bp->dropless_fc &&
3217 pause->bd_th_hi + FW_PREFETCH_CNT >
3218 bp->rx_ring_size);
3219 WARN_ON(bp->dropless_fc &&
3220 pause->rcq_th_hi + FW_PREFETCH_CNT >
3221 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
619c5cb6 3222
523224a3
DK		 3223 pause->pri_map = 1;
3224 }
3225
3226 /* rxq setup */
523224a3
DK		 3227 rxq_init->dscr_map = fp->rx_desc_mapping;
3228 rxq_init->sge_map = fp->rx_sge_mapping;
3229 rxq_init->rcq_map = fp->rx_comp_mapping;
3230 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
a8c94b91 3231
619c5cb6
VZ		 3232 /* This should be a maximum number of data bytes that may be
3233 * placed on the BD (not including paddings).
3234 */
e52fcb24 3235 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3cdeec22 3236 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
a8c94b91 3237
523224a3 3238 rxq_init->cl_qzone_id = fp->cl_qzone_id;
523224a3
DK		 3239 rxq_init->tpa_agg_sz = tpa_agg_size;
3240 rxq_init->sge_buf_sz = sge_sz;
3241 rxq_init->max_sges_pkt = max_sge;
619c5cb6 3242 rxq_init->rss_engine_id = BP_FUNC(bp);
259afa1f 3243 rxq_init->mcast_engine_id = BP_FUNC(bp);
619c5cb6
VZ		 3244
3245 /* Maximum number or simultaneous TPA aggregation for this Queue.
3246 *
2de67439 3247 * For PF Clients it should be the maximum available number.
619c5cb6
VZ		 3248 * VF driver(s) may want to define it to a smaller value.
3249 */
dfacf138 3250 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
619c5cb6 3251
523224a3
DK		 3252 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3253 rxq_init->fw_sb_id = fp->fw_sb_id;
3254
ec6ba945
VZ		 3255 if (IS_FCOE_FP(fp))
3256 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3257 else
6383c0b3 3258 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
a3348722
BW		 3259 /* configure silent vlan removal
3260 * if multi function mode is afex, then mask default vlan
3261 */
3262 if (IS_MF_AFEX(bp)) {
3263 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3264 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3265 }
523224a3
DK		 3266}
3267
619c5cb6 3268static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
6383c0b3
AE		 3269 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3270 u8 cos)
523224a3 3271{
65565884 3272 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
6383c0b3 3273 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
523224a3
DK		 3274 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3275 txq_init->fw_sb_id = fp->fw_sb_id;
ec6ba945 3276
619c5cb6 3277 /*
16a5fd92 3278 * set the tss leading client id for TX classification ==
619c5cb6
VZ		 3279 * leading RSS client id
3280 */
3281 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3282
ec6ba945
VZ		 3283 if (IS_FCOE_FP(fp)) {
3284 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3285 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3286 }
523224a3
DK		 3287}
3288
8d96286a 3289static void bnx2x_pf_init(struct bnx2x *bp)
523224a3
DK		 3290{
3291 struct bnx2x_func_init_params func_init = {0};
523224a3 3292 struct event_ring_data eq_data = { {0} };
523224a3 3293
619c5cb6 3294 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 3295 /* reset IGU PF statistics: MSIX + ATTN */
3296 /* PF */
3297 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3298 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3299 (CHIP_MODE_IS_4_PORT(bp) ?
3300 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3301 /* ATTN */
3302 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3303 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3304 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3305 (CHIP_MODE_IS_4_PORT(bp) ?
3306 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3307 }
3308
05cc5a39 3309 func_init.spq_active = true;
523224a3
DK		 3310 func_init.pf_id = BP_FUNC(bp);
3311 func_init.func_id = BP_FUNC(bp);
523224a3
DK		 3312 func_init.spq_map = bp->spq_mapping;
3313 func_init.spq_prod = bp->spq_prod_idx;
3314
3315 bnx2x_func_init(bp, &func_init);
3316
3317 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3318
3319 /*
619c5cb6
VZ		 3320 * Congestion management values depend on the link rate
3321 * There is no active link so initial link rate is set to 10 Gbps.
3322 * When the link comes up The congestion management values are
3323 * re-calculated according to the actual link rate.
3324 */
523224a3
DK		 3325 bp->link_vars.line_speed = SPEED_10000;
3326 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3327
3328 /* Only the PMF sets the HW */
3329 if (bp->port.pmf)
3330 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3331
86564c3f 3332 /* init Event Queue - PCI bus guarantees correct endianity*/
523224a3
DK		 3333 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3334 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3335 eq_data.producer = bp->eq_prod;
3336 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3337 eq_data.sb_id = DEF_SB_ID;
3338 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3339}
3340
523224a3
DK		 3341static void bnx2x_e1h_disable(struct bnx2x *bp)
3342{
3343 int port = BP_PORT(bp);
3344
619c5cb6 3345 bnx2x_tx_disable(bp);
523224a3
DK		 3346
3347 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
523224a3
DK		 3348}
3349
3350static void bnx2x_e1h_enable(struct bnx2x *bp)
3351{
3352 int port = BP_PORT(bp);
3353
7609647e
YM		 3354 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3355 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
523224a3 3356
16a5fd92 3357 /* Tx queue should be only re-enabled */
523224a3
DK		 3358 netif_tx_wake_all_queues(bp->dev);
3359
3360 /*
3361 * Should not call netif_carrier_on since it will be called if the link
3362 * is up when checking for link state
3363 */
3364}
3365
1d187b34
BW		 3366#define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3367
3368static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3369{
3370 struct eth_stats_info *ether_stat =
3371 &bp->slowpath->drv_info_to_mcp.ether_stat;
3ec9f9ca
AE		 3372 struct bnx2x_vlan_mac_obj *mac_obj =
3373 &bp->sp_objs->mac_obj;
3374 int i;
1d187b34 3375
786fdf0b
DC		 3376 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3377 ETH_STAT_INFO_VERSION_LEN);
1d187b34 3378
3ec9f9ca
AE		 3379 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3380 * mac_local field in ether_stat struct. The base address is offset by 2
3381 * bytes to account for the field being 8 bytes but a mac address is
3382 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3383 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3384 * allocated by the ether_stat struct, so the macs will land in their
3385 * proper positions.
3386 */
3387 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3388 memset(ether_stat->mac_local + i, 0,
3389 sizeof(ether_stat->mac_local[0]));
3390 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3391 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3392 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3393 ETH_ALEN);
1d187b34 3394 ether_stat->mtu_size = bp->dev->mtu;
1d187b34
BW		 3395 if (bp->dev->features & NETIF_F_RXCSUM)
3396 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3397 if (bp->dev->features & NETIF_F_TSO)
3398 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3399 ether_stat->feature_flags |= bp->common.boot_mode;
3400
3401 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3402
3403 ether_stat->txq_size = bp->tx_ring_size;
3404 ether_stat->rxq_size = bp->rx_ring_size;
0c757dee 3405
fcf93a0a 3406#ifdef CONFIG_BNX2X_SRIOV
0c757dee 3407 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
fcf93a0a 3408#endif
1d187b34
BW		 3409}
3410
3411static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3412{
3413 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3414 struct fcoe_stats_info *fcoe_stat =
3415 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3416
55c11941
MS		 3417 if (!CNIC_LOADED(bp))
3418 return;
3419
3ec9f9ca 3420 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
1d187b34
BW		 3421
3422 fcoe_stat->qos_priority =
3423 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3424
3425 /* insert FCoE stats from ramrod response */
3426 if (!NO_FCOE(bp)) {
3427 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
65565884 3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3429 tstorm_queue_statistics;
3430
3431 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
65565884 3432 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
1d187b34
BW		 3433 xstorm_queue_statistics;
3434
3435 struct fcoe_statistics_params *fw_fcoe_stat =
3436 &bp->fw_stats_data->fcoe;
3437
86564c3f
YM		 3438 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3439 fcoe_stat->rx_bytes_lo,
3440 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
1d187b34 3441
86564c3f
YM		 3442 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3443 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3444 fcoe_stat->rx_bytes_lo,
3445 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
1d187b34 3446
86564c3f
YM		 3447 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3448 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3449 fcoe_stat->rx_bytes_lo,
3450 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
1d187b34 3451
86564c3f
YM		 3452 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3453 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3454 fcoe_stat->rx_bytes_lo,
3455 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
1d187b34 3456
86564c3f
YM		 3457 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3458 fcoe_stat->rx_frames_lo,
3459 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
1d187b34 3460
86564c3f
YM		 3461 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3462 fcoe_stat->rx_frames_lo,
3463 fcoe_q_tstorm_stats->rcv_ucast_pkts);
1d187b34 3464
86564c3f
YM		 3465 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3466 fcoe_stat->rx_frames_lo,
3467 fcoe_q_tstorm_stats->rcv_bcast_pkts);
1d187b34 3468
86564c3f
YM		 3469 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3470 fcoe_stat->rx_frames_lo,
3471 fcoe_q_tstorm_stats->rcv_mcast_pkts);
1d187b34 3472
86564c3f
YM		 3473 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3474 fcoe_stat->tx_bytes_lo,
3475 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
1d187b34 3476
86564c3f
YM		 3477 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3478 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3479 fcoe_stat->tx_bytes_lo,
3480 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
1d187b34 3481
86564c3f
YM		 3482 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3483 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3484 fcoe_stat->tx_bytes_lo,
3485 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
1d187b34 3486
86564c3f
YM		 3487 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3488 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3489 fcoe_stat->tx_bytes_lo,
3490 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
1d187b34 3491
86564c3f
YM		 3492 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3493 fcoe_stat->tx_frames_lo,
3494 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
1d187b34 3495
86564c3f
YM		 3496 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3497 fcoe_stat->tx_frames_lo,
3498 fcoe_q_xstorm_stats->ucast_pkts_sent);
1d187b34 3499
86564c3f
YM		 3500 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3501 fcoe_stat->tx_frames_lo,
3502 fcoe_q_xstorm_stats->bcast_pkts_sent);
1d187b34 3503
86564c3f
YM		 3504 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3505 fcoe_stat->tx_frames_lo,
3506 fcoe_q_xstorm_stats->mcast_pkts_sent);
1d187b34
BW		 3507 }
3508
1d187b34
BW		 3509 /* ask L5 driver to add data to the struct */
3510 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
1d187b34
BW		 3511}
3512
3513static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3514{
3515 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3516 struct iscsi_stats_info *iscsi_stat =
3517 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3518
55c11941
MS		 3519 if (!CNIC_LOADED(bp))
3520 return;
3521
3ec9f9ca
AE		 3522 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3523 ETH_ALEN);
1d187b34
BW		 3524
3525 iscsi_stat->qos_priority =
3526 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3527
1d187b34
BW		 3528 /* ask L5 driver to add data to the struct */
3529 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
1d187b34
BW		 3530}
3531
0793f83f
DK		 3532/* called due to MCP event (on pmf):
3533 * reread new bandwidth configuration
3534 * configure FW
3535 * notify others function about the change
3536 */
1191cb83 3537static void bnx2x_config_mf_bw(struct bnx2x *bp)
0793f83f 3538{
75a110a1
SS		 3539 /* Workaround for MFW bug.
3540 * MFW is not supposed to generate BW attention in
3541 * single function mode.
3542 */
3543 if (!IS_MF(bp)) {
3544 DP(BNX2X_MSG_MCP,
3545 "Ignoring MF BW config in single function mode\n");
3546 return;
3547 }
3548
0793f83f
DK		 3549 if (bp->link_vars.link_up) {
3550 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3551 bnx2x_link_sync_notify(bp);
3552 }
3553 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3554}
3555
1191cb83 3556static void bnx2x_set_mf_bw(struct bnx2x *bp)
0793f83f
DK		 3557{
3558 bnx2x_config_mf_bw(bp);
3559 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3560}
3561
c8c60d88
YM		 3562static void bnx2x_handle_eee_event(struct bnx2x *bp)
3563{
3564 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3565 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3566}
3567
42f8277f
YM		 3568#define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3569#define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3570
1d187b34
BW		 3571static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3572{
3573 enum drv_info_opcode op_code;
3574 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
42f8277f
YM		 3575 bool release = false;
3576 int wait;
1d187b34
BW		 3577
3578 /* if drv_info version supported by MFW doesn't match - send NACK */
3579 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3580 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3581 return;
3582 }
3583
3584 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3585 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3586
42f8277f
YM		 3587 /* Must prevent other flows from accessing drv_info_to_mcp */
3588 mutex_lock(&bp->drv_info_mutex);
3589
1d187b34
BW		 3590 memset(&bp->slowpath->drv_info_to_mcp, 0,
3591 sizeof(union drv_info_to_mcp));
3592
3593 switch (op_code) {
3594 case ETH_STATS_OPCODE:
3595 bnx2x_drv_info_ether_stat(bp);
3596 break;
3597 case FCOE_STATS_OPCODE:
3598 bnx2x_drv_info_fcoe_stat(bp);
3599 break;
3600 case ISCSI_STATS_OPCODE:
3601 bnx2x_drv_info_iscsi_stat(bp);
3602 break;
3603 default:
3604 /* if op code isn't supported - send NACK */
3605 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
42f8277f 3606 goto out;
1d187b34
BW		 3607 }
3608
3609 /* if we got drv_info attn from MFW then these fields are defined in
3610 * shmem2 for sure
3611 */
3612 SHMEM2_WR(bp, drv_info_host_addr_lo,
3613 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3614 SHMEM2_WR(bp, drv_info_host_addr_hi,
3615 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3616
3617 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
42f8277f
YM		 3618
3619 /* Since possible management wants both this and get_driver_version
3620 * need to wait until management notifies us it finished utilizing
3621 * the buffer.
3622 */
3623 if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3624 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3625 } else if (!bp->drv_info_mng_owner) {
3626 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3627
3628 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3629 u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3630
3631 /* Management is done; need to clear indication */
3632 if (indication & bit) {
3633 SHMEM2_WR(bp, mfw_drv_indication,
3634 indication & ~bit);
3635 release = true;
3636 break;
3637 }
3638
3639 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3640 }
3641 }
3642 if (!release) {
3643 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3644 bp->drv_info_mng_owner = true;
3645 }
3646
3647out:
3648 mutex_unlock(&bp->drv_info_mutex);
3649}
3650
3651static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3652{
3653 u8 vals[4];
3654 int i = 0;
3655
3656 if (bnx2x_format) {
3657 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3658 &vals[0], &vals[1], &vals[2], &vals[3]);
3659 if (i > 0)
3660 vals[0] -= '0';
3661 } else {
3662 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3663 &vals[0], &vals[1], &vals[2], &vals[3]);
3664 }
3665
3666 while (i < 4)
3667 vals[i++] = 0;
3668
3669 return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3670}
3671
3672void bnx2x_update_mng_version(struct bnx2x *bp)
3673{
3674 u32 iscsiver = DRV_VER_NOT_LOADED;
3675 u32 fcoever = DRV_VER_NOT_LOADED;
3676 u32 ethver = DRV_VER_NOT_LOADED;
3677 int idx = BP_FW_MB_IDX(bp);
3678 u8 *version;
3679
3680 if (!SHMEM2_HAS(bp, func_os_drv_ver))
3681 return;
3682
3683 mutex_lock(&bp->drv_info_mutex);
3684 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3685 if (bp->drv_info_mng_owner)
3686 goto out;
3687
3688 if (bp->state != BNX2X_STATE_OPEN)
3689 goto out;
3690
3691 /* Parse ethernet driver version */
3692 ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3693 if (!CNIC_LOADED(bp))
3694 goto out;
3695
3696 /* Try getting storage driver version via cnic */
3697 memset(&bp->slowpath->drv_info_to_mcp, 0,
3698 sizeof(union drv_info_to_mcp));
3699 bnx2x_drv_info_iscsi_stat(bp);
3700 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3701 iscsiver = bnx2x_update_mng_version_utility(version, false);
3702
3703 memset(&bp->slowpath->drv_info_to_mcp, 0,
3704 sizeof(union drv_info_to_mcp));
3705 bnx2x_drv_info_fcoe_stat(bp);
3706 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3707 fcoever = bnx2x_update_mng_version_utility(version, false);
3708
3709out:
3710 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3711 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3712 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3713
3714 mutex_unlock(&bp->drv_info_mutex);
3715
3716 DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3717 ethver, iscsiver, fcoever);
1d187b34
BW		 3718}
3719
c48f350f
YM		 3720void bnx2x_update_mfw_dump(struct bnx2x *bp)
3721{
c48f350f
YM		 3722 u32 drv_ver;
3723 u32 valid_dump;
3724
3725 if (!SHMEM2_HAS(bp, drv_info))
3726 return;
3727
a19a19de
AB		 3728 /* Update Driver load time, possibly broken in y2038 */
3729 SHMEM2_WR(bp, drv_info.epoc, (u32)ktime_get_real_seconds());
c48f350f
YM		 3730
3731 drv_ver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3732 SHMEM2_WR(bp, drv_info.drv_ver, drv_ver);
3733
3734 SHMEM2_WR(bp, drv_info.fw_ver, REG_RD(bp, XSEM_REG_PRAM));
3735
3736 /* Check & notify On-Chip dump. */
3737 valid_dump = SHMEM2_RD(bp, drv_info.valid_dump);
3738
3739 if (valid_dump & FIRST_DUMP_VALID)
3740 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 1st partition\n");
3741
3742 if (valid_dump & SECOND_DUMP_VALID)
3743 DP(NETIF_MSG_IFUP, "A valid On-Chip MFW dump found on 2nd partition\n");
3744}
3745
7609647e 3746static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
523224a3 3747{
7609647e
YM		 3748 u32 cmd_ok, cmd_fail;
3749
3750 /* sanity */
3751 if (event & DRV_STATUS_DCC_EVENT_MASK &&
3752 event & DRV_STATUS_OEM_EVENT_MASK) {
3753 BNX2X_ERR("Received simultaneous events %08x\n", event);
3754 return;
3755 }
523224a3 3756
7609647e
YM		 3757 if (event & DRV_STATUS_DCC_EVENT_MASK) {
3758 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3759 cmd_ok = DRV_MSG_CODE_DCC_OK;
3760 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3761 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3762 cmd_ok = DRV_MSG_CODE_OEM_OK;
3763 }
523224a3 3764
7609647e
YM		 3765 DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3766
3767 if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3768 DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3769 /* This is the only place besides the function initialization
523224a3
DK		 3770 * where the bp->flags can change so it is done without any
3771 * locks
3772 */
f2e0899f 3773 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
51c1a580 3774 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
523224a3
DK		 3775 bp->flags |= MF_FUNC_DIS;
3776
3777 bnx2x_e1h_disable(bp);
3778 } else {
51c1a580 3779 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
523224a3
DK		 3780 bp->flags &= ~MF_FUNC_DIS;
3781
3782 bnx2x_e1h_enable(bp);
3783 }
7609647e
YM		 3784 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3785 DRV_STATUS_OEM_DISABLE_ENABLE_PF);
523224a3 3786 }
7609647e
YM		 3787
3788 if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3789 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
0793f83f 3790 bnx2x_config_mf_bw(bp);
7609647e
YM		 3791 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3792 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
523224a3
DK		 3793 }
3794
3795 /* Report results to MCP */
7609647e
YM		 3796 if (event)
3797 bnx2x_fw_command(bp, cmd_fail, 0);
523224a3 3798 else
7609647e 3799 bnx2x_fw_command(bp, cmd_ok, 0);
523224a3
DK		 3800}
3801
3802/* must be called under the spq lock */
1191cb83 3803static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
523224a3
DK		 3804{
3805 struct eth_spe *next_spe = bp->spq_prod_bd;
3806
3807 if (bp->spq_prod_bd == bp->spq_last_bd) {
3808 bp->spq_prod_bd = bp->spq;
3809 bp->spq_prod_idx = 0;
51c1a580 3810 DP(BNX2X_MSG_SP, "end of spq\n");
523224a3
DK		 3811 } else {
3812 bp->spq_prod_bd++;
3813 bp->spq_prod_idx++;
3814 }
3815 return next_spe;
3816}
3817
3818/* must be called under the spq lock */
1191cb83 3819static void bnx2x_sp_prod_update(struct bnx2x *bp)
28912902
MC		 3820{
3821 int func = BP_FUNC(bp);
3822
53e51e2f
VZ		 3823 /*
3824 * Make sure that BD data is updated before writing the producer:
3825 * BD data is written to the memory, the producer is read from the
3826 * memory, thus we need a full memory barrier to ensure the ordering.
3827 */
3828 mb();
28912902 3829
7f883c77
SK		 3830 REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3831 bp->spq_prod_idx);
28912902
MC		 3832 mmiowb();
3833}
3834
619c5cb6
VZ		 3835/**
3836 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3837 *
3838 * @cmd: command to check
3839 * @cmd_type: command type
3840 */
1191cb83 3841static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
619c5cb6
VZ		 3842{
3843 if ((cmd_type == NONE_CONNECTION_TYPE) ||
6383c0b3 3844 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
619c5cb6
VZ		 3845 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3846 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3847 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3848 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3849 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3850 return true;
3851 else
3852 return false;
619c5cb6
VZ		 3853}
3854
619c5cb6
VZ		 3855/**
3856 * bnx2x_sp_post - place a single command on an SP ring
3857 *
3858 * @bp: driver handle
3859 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3860 * @cid: SW CID the command is related to
3861 * @data_hi: command private data address (high 32 bits)
3862 * @data_lo: command private data address (low 32 bits)
3863 * @cmd_type: command type (e.g. NONE, ETH)
3864 *
3865 * SP data is handled as if it's always an address pair, thus data fields are
3866 * not swapped to little endian in upper functions. Instead this function swaps
3867 * data as if it's two u32 fields.
3868 */
9f6c9258 3869int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
619c5cb6 3870 u32 data_hi, u32 data_lo, int cmd_type)
a2fbb9ea 3871{
28912902 3872 struct eth_spe *spe;
523224a3 3873 u16 type;
619c5cb6 3874 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
a2fbb9ea 3875
a2fbb9ea 3876#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 3877 if (unlikely(bp->panic)) {
3878 BNX2X_ERR("Can't post SP when there is panic\n");
a2fbb9ea 3879 return -EIO;
51c1a580 3880 }
a2fbb9ea
ET		 3881#endif
3882
34f80b04 3883 spin_lock_bh(&bp->spq_lock);
a2fbb9ea 3884
6e30dd4e
VZ		 3885 if (common) {
3886 if (!atomic_read(&bp->eq_spq_left)) {
3887 BNX2X_ERR("BUG! EQ ring full!\n");
3888 spin_unlock_bh(&bp->spq_lock);
3889 bnx2x_panic();
3890 return -EBUSY;
3891 }
3892 } else if (!atomic_read(&bp->cq_spq_left)) {
3893 BNX2X_ERR("BUG! SPQ ring full!\n");
3894 spin_unlock_bh(&bp->spq_lock);
3895 bnx2x_panic();
3896 return -EBUSY;
a2fbb9ea 3897 }
f1410647 3898
28912902
MC		 3899 spe = bnx2x_sp_get_next(bp);
3900
a2fbb9ea 3901 /* CID needs port number to be encoded int it */
28912902 3902 spe->hdr.conn_and_cmd_data =
cdaa7cb8
VZ		 3903 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3904 HW_CID(bp, cid));
523224a3 3905
14a94ebd
MK		 3906 /* In some cases, type may already contain the func-id
3907 * mainly in SRIOV related use cases, so we add it here only
3908 * if it's not already set.
3909 */
3910 if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3911 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3912 SPE_HDR_CONN_TYPE;
3913 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3914 SPE_HDR_FUNCTION_ID);
3915 } else {
3916 type = cmd_type;
3917 }
a2fbb9ea 3918
523224a3
DK		 3919 spe->hdr.type = cpu_to_le16(type);
3920
3921 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3922 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3923
d6cae238
VZ		 3924 /*
3925 * It's ok if the actual decrement is issued towards the memory
3926 * somewhere between the spin_lock and spin_unlock. Thus no
16a5fd92 3927 * more explicit memory barrier is needed.
d6cae238
VZ		 3928 */
3929 if (common)
3930 atomic_dec(&bp->eq_spq_left);
3931 else
3932 atomic_dec(&bp->cq_spq_left);
6e30dd4e 3933
51c1a580
MS		 3934 DP(BNX2X_MSG_SP,
3935 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
cdaa7cb8
VZ		 3936 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3937 (u32)(U64_LO(bp->spq_mapping) +
d6cae238 3938 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
6e30dd4e
VZ		 3939 HW_CID(bp, cid), data_hi, data_lo, type,
3940 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
cdaa7cb8 3941
28912902 3942 bnx2x_sp_prod_update(bp);
34f80b04 3943 spin_unlock_bh(&bp->spq_lock);
a2fbb9ea
ET		 3944 return 0;
3945}
3946
3947/* acquire split MCP access lock register */
4a37fb66 3948static int bnx2x_acquire_alr(struct bnx2x *bp)
a2fbb9ea 3949{
72fd0718 3950 u32 j, val;
34f80b04 3951 int rc = 0;
a2fbb9ea
ET		 3952
3953 might_sleep();
72fd0718 3954 for (j = 0; j < 1000; j++) {
3cdeec22
YM		 3955 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3956 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3957 if (val & MCPR_ACCESS_LOCK_LOCK)
a2fbb9ea
ET		 3958 break;
3959
639d65b8 3960 usleep_range(5000, 10000);
a2fbb9ea 3961 }
3cdeec22 3962 if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
19680c48 3963 BNX2X_ERR("Cannot acquire MCP access lock register\n");
a2fbb9ea
ET		 3964 rc = -EBUSY;
3965 }
3966
3967 return rc;
3968}
3969
4a37fb66
YG		 3970/* release split MCP access lock register */
3971static void bnx2x_release_alr(struct bnx2x *bp)
a2fbb9ea 3972{
3cdeec22 3973 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
a2fbb9ea
ET		 3974}
3975
523224a3
DK		 3976#define BNX2X_DEF_SB_ATT_IDX 0x0001
3977#define BNX2X_DEF_SB_IDX 0x0002
3978
1191cb83 3979static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
a2fbb9ea 3980{
523224a3 3981 struct host_sp_status_block *def_sb = bp->def_status_blk;
a2fbb9ea
ET		 3982 u16 rc = 0;
3983
3984 barrier(); /* status block is written to by the chip */
a2fbb9ea
ET		 3985 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3986 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
523224a3 3987 rc |= BNX2X_DEF_SB_ATT_IDX;
a2fbb9ea 3988 }
523224a3
DK		 3989
3990 if (bp->def_idx != def_sb->sp_sb.running_index) {
3991 bp->def_idx = def_sb->sp_sb.running_index;
3992 rc |= BNX2X_DEF_SB_IDX;
a2fbb9ea 3993 }
523224a3 3994
16a5fd92 3995 /* Do not reorder: indices reading should complete before handling */
523224a3 3996 barrier();
a2fbb9ea
ET		 3997 return rc;
3998}
3999
4000/*
4001 * slow path service functions
4002 */
4003
4004static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
4005{
34f80b04 4006 int port = BP_PORT(bp);
a2fbb9ea
ET		 4007 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4008 MISC_REG_AEU_MASK_ATTN_FUNC_0;
877e9aa4
ET		 4009 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
4010 NIG_REG_MASK_INTERRUPT_PORT0;
3fcaf2e5 4011 u32 aeu_mask;
87942b46 4012 u32 nig_mask = 0;
f2e0899f 4013 u32 reg_addr;
a2fbb9ea 4014
a2fbb9ea
ET		 4015 if (bp->attn_state & asserted)
4016 BNX2X_ERR("IGU ERROR\n");
4017
3fcaf2e5
EG		 4018 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4019 aeu_mask = REG_RD(bp, aeu_addr);
4020
a2fbb9ea 4021 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3fcaf2e5 4022 aeu_mask, asserted);
72fd0718 4023 aeu_mask &= ~(asserted & 0x3ff);
3fcaf2e5 4024 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 4025
3fcaf2e5
EG		 4026 REG_WR(bp, aeu_addr, aeu_mask);
4027 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea 4028
3fcaf2e5 4029 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
a2fbb9ea 4030 bp->attn_state |= asserted;
3fcaf2e5 4031 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
a2fbb9ea
ET		 4032
4033 if (asserted & ATTN_HARD_WIRED_MASK) {
4034 if (asserted & ATTN_NIG_FOR_FUNC) {
a2fbb9ea 4035
a5e9a7cf
EG		 4036 bnx2x_acquire_phy_lock(bp);
4037
877e9aa4 4038 /* save nig interrupt mask */
87942b46 4039 nig_mask = REG_RD(bp, nig_int_mask_addr);
a2fbb9ea 4040
361c391e
YR		 4041 /* If nig_mask is not set, no need to call the update
4042 * function.
4043 */
4044 if (nig_mask) {
4045 REG_WR(bp, nig_int_mask_addr, 0);
4046
4047 bnx2x_link_attn(bp);
4048 }
a2fbb9ea
ET		 4049
4050 /* handle unicore attn? */
4051 }
4052 if (asserted & ATTN_SW_TIMER_4_FUNC)
4053 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4054
4055 if (asserted & GPIO_2_FUNC)
4056 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4057
4058 if (asserted & GPIO_3_FUNC)
4059 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4060
4061 if (asserted & GPIO_4_FUNC)
4062 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4063
4064 if (port == 0) {
4065 if (asserted & ATTN_GENERAL_ATTN_1) {
4066 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4067 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4068 }
4069 if (asserted & ATTN_GENERAL_ATTN_2) {
4070 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4071 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4072 }
4073 if (asserted & ATTN_GENERAL_ATTN_3) {
4074 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4075 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4076 }
4077 } else {
4078 if (asserted & ATTN_GENERAL_ATTN_4) {
4079 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4080 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4081 }
4082 if (asserted & ATTN_GENERAL_ATTN_5) {
4083 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4084 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4085 }
4086 if (asserted & ATTN_GENERAL_ATTN_6) {
4087 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4088 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4089 }
4090 }
4091
4092 } /* if hardwired */
4093
f2e0899f
DK		 4094 if (bp->common.int_block == INT_BLOCK_HC)
4095 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4096 COMMAND_REG_ATTN_BITS_SET);
4097 else
4098 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4099
4100 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4101 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4102 REG_WR(bp, reg_addr, asserted);
a2fbb9ea
ET		 4103
4104 /* now set back the mask */
a5e9a7cf 4105 if (asserted & ATTN_NIG_FOR_FUNC) {
27c1151c
YR		 4106 /* Verify that IGU ack through BAR was written before restoring
4107 * NIG mask. This loop should exit after 2-3 iterations max.
4108 */
4109 if (bp->common.int_block != INT_BLOCK_HC) {
4110 u32 cnt = 0, igu_acked;
4111 do {
4112 igu_acked = REG_RD(bp,
4113 IGU_REG_ATTENTION_ACK_BITS);
4114 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4115 (++cnt < MAX_IGU_ATTN_ACK_TO));
4116 if (!igu_acked)
4117 DP(NETIF_MSG_HW,
4118 "Failed to verify IGU ack on time\n");
4119 barrier();
4120 }
87942b46 4121 REG_WR(bp, nig_int_mask_addr, nig_mask);
a5e9a7cf
EG		 4122 bnx2x_release_phy_lock(bp);
4123 }
a2fbb9ea
ET		 4124}
4125
1191cb83 4126static void bnx2x_fan_failure(struct bnx2x *bp)
fd4ef40d
EG		 4127{
4128 int port = BP_PORT(bp);
b7737c9b 4129 u32 ext_phy_config;
fd4ef40d 4130 /* mark the failure */
b7737c9b
YR		 4131 ext_phy_config =
4132 SHMEM_RD(bp,
4133 dev_info.port_hw_config[port].external_phy_config);
4134
4135 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4136 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
fd4ef40d 4137 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
b7737c9b 4138 ext_phy_config);
fd4ef40d
EG		 4139
4140 /* log the failure */
51c1a580
MS		 4141 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4142 "Please contact OEM Support for assistance\n");
8304859a 4143
16a5fd92 4144 /* Schedule device reset (unload)
8304859a
AE		 4145 * This is due to some boards consuming sufficient power when driver is
4146 * up to overheat if fan fails.
4147 */
230bb0f3 4148 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
fd4ef40d 4149}
ab6ad5a4 4150
1191cb83 4151static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
a2fbb9ea 4152{
34f80b04 4153 int port = BP_PORT(bp);
877e9aa4 4154 int reg_offset;
d90d96ba 4155 u32 val;
877e9aa4 4156
34f80b04
EG		 4157 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4158 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
877e9aa4 4159
34f80b04 4160 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
877e9aa4
ET		 4161
4162 val = REG_RD(bp, reg_offset);
4163 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4164 REG_WR(bp, reg_offset, val);
4165
4166 BNX2X_ERR("SPIO5 hw attention\n");
4167
fd4ef40d 4168 /* Fan failure attention */
d90d96ba 4169 bnx2x_hw_reset_phy(&bp->link_params);
fd4ef40d 4170 bnx2x_fan_failure(bp);
877e9aa4 4171 }
34f80b04 4172
3deb8167 4173 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
589abe3a
EG		 4174 bnx2x_acquire_phy_lock(bp);
4175 bnx2x_handle_module_detect_int(&bp->link_params);
4176 bnx2x_release_phy_lock(bp);
4177 }
4178
a8919661 4179 if (attn & HW_INTERRUPT_ASSERT_SET_0) {
34f80b04
EG		 4180
4181 val = REG_RD(bp, reg_offset);
a8919661 4182 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_0);
34f80b04
EG		 4183 REG_WR(bp, reg_offset, val);
4184
4185 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
a8919661 4186 (u32)(attn & HW_INTERRUPT_ASSERT_SET_0));
34f80b04
EG		 4187 bnx2x_panic();
4188 }
877e9aa4
ET		 4189}
4190
1191cb83 4191static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4192{
4193 u32 val;
4194
0626b899 4195 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
877e9aa4
ET		 4196
4197 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4198 BNX2X_ERR("DB hw attention 0x%x\n", val);
4199 /* DORQ discard attention */
4200 if (val & 0x2)
4201 BNX2X_ERR("FATAL error from DORQ\n");
4202 }
34f80b04 4203
a8919661 4204 if (attn & HW_INTERRUPT_ASSERT_SET_1) {
34f80b04
EG		 4205
4206 int port = BP_PORT(bp);
4207 int reg_offset;
4208
4209 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4210 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4211
4212 val = REG_RD(bp, reg_offset);
a8919661 4213 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_1);
34f80b04
EG		 4214 REG_WR(bp, reg_offset, val);
4215
4216 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
a8919661 4217 (u32)(attn & HW_INTERRUPT_ASSERT_SET_1));
34f80b04
EG		 4218 bnx2x_panic();
4219 }
877e9aa4
ET		 4220}
4221
1191cb83 4222static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
877e9aa4
ET		 4223{
4224 u32 val;
4225
4226 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4227
4228 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4229 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4230 /* CFC error attention */
4231 if (val & 0x2)
4232 BNX2X_ERR("FATAL error from CFC\n");
4233 }
4234
4235 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
877e9aa4 4236 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
619c5cb6 4237 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
877e9aa4
ET		 4238 /* RQ_USDMDP_FIFO_OVERFLOW */
4239 if (val & 0x18000)
4240 BNX2X_ERR("FATAL error from PXP\n");
619c5cb6
VZ		 4241
4242 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 4243 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4244 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4245 }
877e9aa4 4246 }
34f80b04 4247
a8919661 4248 if (attn & HW_INTERRUPT_ASSERT_SET_2) {
34f80b04
EG		 4249
4250 int port = BP_PORT(bp);
4251 int reg_offset;
4252
4253 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4254 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4255
4256 val = REG_RD(bp, reg_offset);
a8919661 4257 val &= ~(attn & HW_INTERRUPT_ASSERT_SET_2);
34f80b04
EG		 4258 REG_WR(bp, reg_offset, val);
4259
4260 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
a8919661 4261 (u32)(attn & HW_INTERRUPT_ASSERT_SET_2));
34f80b04
EG		 4262 bnx2x_panic();
4263 }
877e9aa4
ET		 4264}
4265
1191cb83 4266static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
877e9aa4 4267{
34f80b04
EG		 4268 u32 val;
4269
877e9aa4
ET		 4270 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4271
34f80b04
EG		 4272 if (attn & BNX2X_PMF_LINK_ASSERT) {
4273 int func = BP_FUNC(bp);
4274
4275 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
a3348722 4276 bnx2x_read_mf_cfg(bp);
f2e0899f
DK		 4277 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4278 func_mf_config[BP_ABS_FUNC(bp)].config);
4279 val = SHMEM_RD(bp,
4280 func_mb[BP_FW_MB_IDX(bp)].drv_status);
7609647e
YM		 4281
4282 if (val & (DRV_STATUS_DCC_EVENT_MASK |
4283 DRV_STATUS_OEM_EVENT_MASK))
4284 bnx2x_oem_event(bp,
4285 (val & (DRV_STATUS_DCC_EVENT_MASK |
4286 DRV_STATUS_OEM_EVENT_MASK)));
0793f83f
DK		 4287
4288 if (val & DRV_STATUS_SET_MF_BW)
4289 bnx2x_set_mf_bw(bp);
4290
1d187b34
BW		 4291 if (val & DRV_STATUS_DRV_INFO_REQ)
4292 bnx2x_handle_drv_info_req(bp);
d16132ce
AE		 4293
4294 if (val & DRV_STATUS_VF_DISABLED)
370d4a26
YM		 4295 bnx2x_schedule_iov_task(bp,
4296 BNX2X_IOV_HANDLE_FLR);
d16132ce 4297
2691d51d 4298 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
34f80b04
EG		 4299 bnx2x_pmf_update(bp);
4300
e4901dde 4301 if (bp->port.pmf &&
785b9b1a
SR		 4302 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4303 bp->dcbx_enabled > 0)
e4901dde
VZ		 4304 /* start dcbx state machine */
4305 bnx2x_dcbx_set_params(bp,
4306 BNX2X_DCBX_STATE_NEG_RECEIVED);
a3348722
BW		 4307 if (val & DRV_STATUS_AFEX_EVENT_MASK)
4308 bnx2x_handle_afex_cmd(bp,
4309 val & DRV_STATUS_AFEX_EVENT_MASK);
c8c60d88
YM		 4310 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4311 bnx2x_handle_eee_event(bp);
7609647e
YM		 4312
4313 if (val & DRV_STATUS_OEM_UPDATE_SVID)
4314 bnx2x_handle_update_svid_cmd(bp);
4315
3deb8167
YR		 4316 if (bp->link_vars.periodic_flags &
4317 PERIODIC_FLAGS_LINK_EVENT) {
4318 /* sync with link */
4319 bnx2x_acquire_phy_lock(bp);
4320 bp->link_vars.periodic_flags &=
4321 ~PERIODIC_FLAGS_LINK_EVENT;
4322 bnx2x_release_phy_lock(bp);
4323 if (IS_MF(bp))
4324 bnx2x_link_sync_notify(bp);
4325 bnx2x_link_report(bp);
4326 }
4327 /* Always call it here: bnx2x_link_report() will
4328 * prevent the link indication duplication.
4329 */
4330 bnx2x__link_status_update(bp);
34f80b04 4331 } else if (attn & BNX2X_MC_ASSERT_BITS) {
877e9aa4
ET		 4332
4333 BNX2X_ERR("MC assert!\n");
d6cae238 4334 bnx2x_mc_assert(bp);
877e9aa4
ET		 4335 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4336 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4337 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4338 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4339 bnx2x_panic();
4340
4341 } else if (attn & BNX2X_MCP_ASSERT) {
4342
4343 BNX2X_ERR("MCP assert!\n");
4344 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
34f80b04 4345 bnx2x_fw_dump(bp);
877e9aa4
ET		 4346
4347 } else
4348 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4349 }
4350
4351 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
34f80b04
EG		 4352 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4353 if (attn & BNX2X_GRC_TIMEOUT) {
f2e0899f
DK		 4354 val = CHIP_IS_E1(bp) ? 0 :
4355 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
34f80b04
EG		 4356 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4357 }
4358 if (attn & BNX2X_GRC_RSV) {
f2e0899f
DK		 4359 val = CHIP_IS_E1(bp) ? 0 :
4360 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
34f80b04
EG		 4361 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4362 }
877e9aa4 4363 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
877e9aa4
ET		 4364 }
4365}
4366
c9ee9206
VZ		 4367/*
4368 * Bits map:
4369 * 0-7 - Engine0 load counter.
4370 * 8-15 - Engine1 load counter.
4371 * 16 - Engine0 RESET_IN_PROGRESS bit.
4372 * 17 - Engine1 RESET_IN_PROGRESS bit.
4373 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4374 * on the engine
4375 * 19 - Engine1 ONE_IS_LOADED.
4376 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4377 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4378 * just the one belonging to its engine).
4379 *
4380 */
4381#define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4382
4383#define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4384#define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4385#define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4386#define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4387#define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4388#define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4389#define BNX2X_GLOBAL_RESET_BIT 0x00040000
4390
4391/*
4392 * Set the GLOBAL_RESET bit.
4393 *
4394 * Should be run under rtnl lock
4395 */
4396void bnx2x_set_reset_global(struct bnx2x *bp)
4397{
f16da43b
AE		 4398 u32 val;
4399 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4400 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4401 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
f16da43b 4402 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206
VZ		 4403}
4404
4405/*
4406 * Clear the GLOBAL_RESET bit.
4407 *
4408 * Should be run under rtnl lock
4409 */
1191cb83 4410static void bnx2x_clear_reset_global(struct bnx2x *bp)
c9ee9206 4411{
f16da43b
AE		 4412 u32 val;
4413 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4414 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206 4415 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
f16da43b 4416 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
c9ee9206 4417}
f85582f8 4418
72fd0718 4419/*
c9ee9206
VZ		 4420 * Checks the GLOBAL_RESET bit.
4421 *
72fd0718
VZ		 4422 * should be run under rtnl lock
4423 */
1191cb83 4424static bool bnx2x_reset_is_global(struct bnx2x *bp)
c9ee9206 4425{
3cdeec22 4426 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4427
4428 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4429 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4430}
4431
4432/*
4433 * Clear RESET_IN_PROGRESS bit for the current engine.
4434 *
4435 * Should be run under rtnl lock
4436 */
1191cb83 4437static void bnx2x_set_reset_done(struct bnx2x *bp)
72fd0718 4438{
f16da43b 4439 u32 val;
c9ee9206
VZ		 4440 u32 bit = BP_PATH(bp) ?
4441 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4442 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4443 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4444
4445 /* Clear the bit */
4446 val &= ~bit;
4447 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4448
4449 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4450}
4451
4452/*
c9ee9206
VZ		 4453 * Set RESET_IN_PROGRESS for the current engine.
4454 *
72fd0718
VZ		 4455 * should be run under rtnl lock
4456 */
c9ee9206 4457void bnx2x_set_reset_in_progress(struct bnx2x *bp)
72fd0718 4458{
f16da43b 4459 u32 val;
c9ee9206
VZ		 4460 u32 bit = BP_PATH(bp) ?
4461 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
f16da43b
AE		 4462 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4463 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4464
4465 /* Set the bit */
4466 val |= bit;
4467 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4468 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4469}
4470
4471/*
c9ee9206 4472 * Checks the RESET_IN_PROGRESS bit for the given engine.
72fd0718
VZ		 4473 * should be run under rtnl lock
4474 */
c9ee9206 4475bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
72fd0718 4476{
3cdeec22 4477 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
c9ee9206
VZ		 4478 u32 bit = engine ?
4479 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4480
4481 /* return false if bit is set */
4482 return (val & bit) ? false : true;
72fd0718
VZ		 4483}
4484
4485/*
889b9af3 4486 * set pf load for the current pf.
c9ee9206 4487 *
72fd0718
VZ		 4488 * should be run under rtnl lock
4489 */
889b9af3 4490void bnx2x_set_pf_load(struct bnx2x *bp)
72fd0718 4491{
f16da43b 4492 u32 val1, val;
c9ee9206
VZ		 4493 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4494 BNX2X_PATH0_LOAD_CNT_MASK;
4495 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4496 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4497
f16da43b
AE		 4498 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4499 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4500
51c1a580 4501 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4502
c9ee9206
VZ		 4503 /* get the current counter value */
4504 val1 = (val & mask) >> shift;
4505
889b9af3
AE		 4506 /* set bit of that PF */
4507 val1 |= (1 << bp->pf_num);
c9ee9206
VZ		 4508
4509 /* clear the old value */
4510 val &= ~mask;
4511
4512 /* set the new one */
4513 val |= ((val1 << shift) & mask);
4514
4515 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b 4516 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
72fd0718
VZ		 4517}
4518
c9ee9206 4519/**
889b9af3 4520 * bnx2x_clear_pf_load - clear pf load mark
c9ee9206
VZ		 4521 *
4522 * @bp: driver handle
4523 *
4524 * Should be run under rtnl lock.
4525 * Decrements the load counter for the current engine. Returns
889b9af3 4526 * whether other functions are still loaded
72fd0718 4527 */
889b9af3 4528bool bnx2x_clear_pf_load(struct bnx2x *bp)
72fd0718 4529{
f16da43b 4530 u32 val1, val;
c9ee9206
VZ		 4531 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4532 BNX2X_PATH0_LOAD_CNT_MASK;
4533 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4534 BNX2X_PATH0_LOAD_CNT_SHIFT;
72fd0718 4535
f16da43b
AE		 4536 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4537 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
51c1a580 4538 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
72fd0718 4539
c9ee9206
VZ		 4540 /* get the current counter value */
4541 val1 = (val & mask) >> shift;
4542
889b9af3
AE		 4543 /* clear bit of that PF */
4544 val1 &= ~(1 << bp->pf_num);
c9ee9206
VZ		 4545
4546 /* clear the old value */
4547 val &= ~mask;
4548
4549 /* set the new one */
4550 val |= ((val1 << shift) & mask);
4551
4552 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
f16da43b
AE		 4553 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4554 return val1 != 0;
72fd0718
VZ		 4555}
4556
4557/*
889b9af3 4558 * Read the load status for the current engine.
c9ee9206 4559 *
72fd0718
VZ		 4560 * should be run under rtnl lock
4561 */
1191cb83 4562static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
72fd0718 4563{
c9ee9206
VZ		 4564 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4565 BNX2X_PATH0_LOAD_CNT_MASK);
4566 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4567 BNX2X_PATH0_LOAD_CNT_SHIFT);
4568 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4569
51c1a580 4570 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
c9ee9206
VZ		 4571
4572 val = (val & mask) >> shift;
4573
51c1a580
MS		 4574 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4575 engine, val);
c9ee9206 4576
889b9af3 4577 return val != 0;
72fd0718
VZ		 4578}
4579
6bf07b8e
YM		 4580static void _print_parity(struct bnx2x *bp, u32 reg)
4581{
4582 pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4583}
4584
1191cb83 4585static void _print_next_block(int idx, const char *blk)
72fd0718 4586{
f1deab50 4587 pr_cont("%s%s", idx ? ", " : "", blk);
72fd0718
VZ		 4588}
4589
4293b9f5
DK		 4590static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4591 int *par_num, bool print)
72fd0718 4592{
4293b9f5
DK		 4593 u32 cur_bit;
4594 bool res;
4595 int i;
4596
4597 res = false;
4598
72fd0718 4599 for (i = 0; sig; i++) {
4293b9f5 4600 cur_bit = (0x1UL << i);
72fd0718 4601 if (sig & cur_bit) {
4293b9f5
DK		 4602 res |= true; /* Each bit is real error! */
4603
4604 if (print) {
4605 switch (cur_bit) {
4606 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4607 _print_next_block((*par_num)++, "BRB");
6bf07b8e
YM		 4608 _print_parity(bp,
4609 BRB1_REG_BRB1_PRTY_STS);
4293b9f5
DK		 4610 break;
4611 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4612 _print_next_block((*par_num)++,
4613 "PARSER");
6bf07b8e 4614 _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4293b9f5
DK		 4615 break;
4616 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4617 _print_next_block((*par_num)++, "TSDM");
6bf07b8e
YM		 4618 _print_parity(bp,
4619 TSDM_REG_TSDM_PRTY_STS);
4293b9f5
DK		 4620 break;
4621 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4622 _print_next_block((*par_num)++,
c9ee9206 4623 "SEARCHER");
6bf07b8e 4624 _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4293b9f5
DK		 4625 break;
4626 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4627 _print_next_block((*par_num)++, "TCM");
4628 _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4629 break;
4630 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4631 _print_next_block((*par_num)++,
4632 "TSEMI");
6bf07b8e
YM		 4633 _print_parity(bp,
4634 TSEM_REG_TSEM_PRTY_STS_0);
4635 _print_parity(bp,
4636 TSEM_REG_TSEM_PRTY_STS_1);
4293b9f5
DK		 4637 break;
4638 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4639 _print_next_block((*par_num)++, "XPB");
6bf07b8e
YM		 4640 _print_parity(bp, GRCBASE_XPB +
4641 PB_REG_PB_PRTY_STS);
4293b9f5 4642 break;
6bf07b8e 4643 }
72fd0718
VZ		 4644 }
4645
4646 /* Clear the bit */
4647 sig &= ~cur_bit;
4648 }
4649 }
4650
4293b9f5 4651 return res;
72fd0718
VZ		 4652}
4653
4293b9f5
DK		 4654static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4655 int *par_num, bool *global,
6bf07b8e 4656 bool print)
72fd0718 4657{
4293b9f5
DK		 4658 u32 cur_bit;
4659 bool res;
4660 int i;
4661
4662 res = false;
4663
72fd0718 4664 for (i = 0; sig; i++) {
4293b9f5 4665 cur_bit = (0x1UL << i);
72fd0718 4666 if (sig & cur_bit) {
4293b9f5 4667 res |= true; /* Each bit is real error! */
72fd0718 4668 switch (cur_bit) {
c9ee9206 4669 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
6bf07b8e 4670 if (print) {
4293b9f5 4671 _print_next_block((*par_num)++, "PBF");
6bf07b8e
YM		 4672 _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4673 }
72fd0718
VZ		 4674 break;
4675 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
6bf07b8e 4676 if (print) {
4293b9f5 4677 _print_next_block((*par_num)++, "QM");
6bf07b8e
YM		 4678 _print_parity(bp, QM_REG_QM_PRTY_STS);
4679 }
c9ee9206
VZ		 4680 break;
4681 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
6bf07b8e 4682 if (print) {
4293b9f5 4683 _print_next_block((*par_num)++, "TM");
6bf07b8e
YM		 4684 _print_parity(bp, TM_REG_TM_PRTY_STS);
4685 }
72fd0718
VZ		 4686 break;
4687 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
6bf07b8e 4688 if (print) {
4293b9f5 4689 _print_next_block((*par_num)++, "XSDM");
6bf07b8e
YM		 4690 _print_parity(bp,
4691 XSDM_REG_XSDM_PRTY_STS);
4692 }
c9ee9206
VZ		 4693 break;
4694 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
6bf07b8e 4695 if (print) {
4293b9f5 4696 _print_next_block((*par_num)++, "XCM");
6bf07b8e
YM		 4697 _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4698 }
72fd0718
VZ		 4699 break;
4700 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
6bf07b8e 4701 if (print) {
4293b9f5
DK		 4702 _print_next_block((*par_num)++,
4703 "XSEMI");
6bf07b8e
YM		 4704 _print_parity(bp,
4705 XSEM_REG_XSEM_PRTY_STS_0);
4706 _print_parity(bp,
4707 XSEM_REG_XSEM_PRTY_STS_1);
4708 }
72fd0718
VZ		 4709 break;
4710 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
6bf07b8e 4711 if (print) {
4293b9f5 4712 _print_next_block((*par_num)++,
c9ee9206 4713 "DOORBELLQ");
6bf07b8e
YM		 4714 _print_parity(bp,
4715 DORQ_REG_DORQ_PRTY_STS);
4716 }
c9ee9206
VZ		 4717 break;
4718 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
6bf07b8e 4719 if (print) {
4293b9f5 4720 _print_next_block((*par_num)++, "NIG");
6bf07b8e
YM		 4721 if (CHIP_IS_E1x(bp)) {
4722 _print_parity(bp,
4723 NIG_REG_NIG_PRTY_STS);
4724 } else {
4725 _print_parity(bp,
4726 NIG_REG_NIG_PRTY_STS_0);
4727 _print_parity(bp,
4728 NIG_REG_NIG_PRTY_STS_1);
4729 }
4730 }
72fd0718
VZ		 4731 break;
4732 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
c9ee9206 4733 if (print)
4293b9f5 4734 _print_next_block((*par_num)++,
c9ee9206
VZ		 4735 "VAUX PCI CORE");
4736 *global = true;
72fd0718
VZ		 4737 break;
4738 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
6bf07b8e 4739 if (print) {
4293b9f5
DK		 4740 _print_next_block((*par_num)++,
4741 "DEBUG");
6bf07b8e
YM		 4742 _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4743 }
72fd0718
VZ		 4744 break;
4745 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
6bf07b8e 4746 if (print) {
4293b9f5 4747 _print_next_block((*par_num)++, "USDM");
6bf07b8e
YM		 4748 _print_parity(bp,
4749 USDM_REG_USDM_PRTY_STS);
4750 }
72fd0718 4751 break;
8736c826 4752 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
6bf07b8e 4753 if (print) {
4293b9f5 4754 _print_next_block((*par_num)++, "UCM");
6bf07b8e
YM		 4755 _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4756 }
8736c826 4757 break;
72fd0718 4758 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
6bf07b8e 4759 if (print) {
4293b9f5
DK		 4760 _print_next_block((*par_num)++,
4761 "USEMI");
6bf07b8e
YM		 4762 _print_parity(bp,
4763 USEM_REG_USEM_PRTY_STS_0);
4764 _print_parity(bp,
4765 USEM_REG_USEM_PRTY_STS_1);
4766 }
72fd0718
VZ		 4767 break;
4768 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
6bf07b8e 4769 if (print) {
4293b9f5 4770 _print_next_block((*par_num)++, "UPB");
6bf07b8e
YM		 4771 _print_parity(bp, GRCBASE_UPB +
4772 PB_REG_PB_PRTY_STS);
4773 }
72fd0718
VZ		 4774 break;
4775 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
6bf07b8e 4776 if (print) {
4293b9f5 4777 _print_next_block((*par_num)++, "CSDM");
6bf07b8e
YM		 4778 _print_parity(bp,
4779 CSDM_REG_CSDM_PRTY_STS);
4780 }
72fd0718 4781 break;
8736c826 4782 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
6bf07b8e 4783 if (print) {
4293b9f5 4784 _print_next_block((*par_num)++, "CCM");
6bf07b8e
YM		 4785 _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4786 }
8736c826 4787 break;
72fd0718
VZ		 4788 }
4789
4790 /* Clear the bit */
4791 sig &= ~cur_bit;
4792 }
4793 }
4794
4293b9f5 4795 return res;
72fd0718
VZ		 4796}
4797
4293b9f5
DK		 4798static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4799 int *par_num, bool print)
72fd0718 4800{
4293b9f5
DK		 4801 u32 cur_bit;
4802 bool res;
4803 int i;
4804
4805 res = false;
4806
72fd0718 4807 for (i = 0; sig; i++) {
4293b9f5 4808 cur_bit = (0x1UL << i);
72fd0718 4809 if (sig & cur_bit) {
0c23ad37 4810 res = true; /* Each bit is real error! */
4293b9f5
DK		 4811 if (print) {
4812 switch (cur_bit) {
4813 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4814 _print_next_block((*par_num)++,
4815 "CSEMI");
6bf07b8e
YM		 4816 _print_parity(bp,
4817 CSEM_REG_CSEM_PRTY_STS_0);
4818 _print_parity(bp,
4819 CSEM_REG_CSEM_PRTY_STS_1);
4293b9f5
DK		 4820 break;
4821 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4822 _print_next_block((*par_num)++, "PXP");
6bf07b8e
YM		 4823 _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4824 _print_parity(bp,
4825 PXP2_REG_PXP2_PRTY_STS_0);
4826 _print_parity(bp,
4827 PXP2_REG_PXP2_PRTY_STS_1);
4293b9f5
DK		 4828 break;
4829 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4830 _print_next_block((*par_num)++,
4831 "PXPPCICLOCKCLIENT");
4832 break;
4833 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4834 _print_next_block((*par_num)++, "CFC");
6bf07b8e
YM		 4835 _print_parity(bp,
4836 CFC_REG_CFC_PRTY_STS);
4293b9f5
DK		 4837 break;
4838 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4839 _print_next_block((*par_num)++, "CDU");
6bf07b8e 4840 _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4293b9f5
DK		 4841 break;
4842 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4843 _print_next_block((*par_num)++, "DMAE");
6bf07b8e
YM		 4844 _print_parity(bp,
4845 DMAE_REG_DMAE_PRTY_STS);
4293b9f5
DK		 4846 break;
4847 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4848 _print_next_block((*par_num)++, "IGU");
6bf07b8e
YM		 4849 if (CHIP_IS_E1x(bp))
4850 _print_parity(bp,
4851 HC_REG_HC_PRTY_STS);
4852 else
4853 _print_parity(bp,
4854 IGU_REG_IGU_PRTY_STS);
4293b9f5
DK		 4855 break;
4856 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4857 _print_next_block((*par_num)++, "MISC");
6bf07b8e
YM		 4858 _print_parity(bp,
4859 MISC_REG_MISC_PRTY_STS);
4293b9f5 4860 break;
6bf07b8e 4861 }
72fd0718
VZ		 4862 }
4863
4864 /* Clear the bit */
4865 sig &= ~cur_bit;
4866 }
4867 }
4868
4293b9f5 4869 return res;
72fd0718
VZ		 4870}
4871
4293b9f5
DK		 4872static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4873 int *par_num, bool *global,
4874 bool print)
72fd0718 4875{
4293b9f5
DK		 4876 bool res = false;
4877 u32 cur_bit;
4878 int i;
4879
72fd0718 4880 for (i = 0; sig; i++) {
4293b9f5 4881 cur_bit = (0x1UL << i);
72fd0718
VZ		 4882 if (sig & cur_bit) {
4883 switch (cur_bit) {
4884 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
c9ee9206 4885 if (print)
4293b9f5
DK		 4886 _print_next_block((*par_num)++,
4887 "MCP ROM");
c9ee9206 4888 *global = true;
0c23ad37 4889 res = true;
72fd0718
VZ		 4890 break;
4891 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
c9ee9206 4892 if (print)
4293b9f5 4893 _print_next_block((*par_num)++,
c9ee9206
VZ		 4894 "MCP UMP RX");
4895 *global = true;
0c23ad37 4896 res = true;
72fd0718
VZ		 4897 break;
4898 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
c9ee9206 4899 if (print)
4293b9f5 4900 _print_next_block((*par_num)++,
c9ee9206
VZ		 4901 "MCP UMP TX");
4902 *global = true;
0c23ad37 4903 res = true;
72fd0718
VZ		 4904 break;
4905 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
ad6afbe9 4906 (*par_num)++;
4293b9f5
DK		 4907 /* clear latched SCPAD PATIRY from MCP */
4908 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4909 1UL << 10);
72fd0718
VZ		 4910 break;
4911 }
4912
4913 /* Clear the bit */
4914 sig &= ~cur_bit;
4915 }
4916 }
4917
4293b9f5 4918 return res;
72fd0718
VZ		 4919}
4920
4293b9f5
DK		 4921static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4922 int *par_num, bool print)
8736c826 4923{
4293b9f5
DK		 4924 u32 cur_bit;
4925 bool res;
4926 int i;
4927
4928 res = false;
4929
8736c826 4930 for (i = 0; sig; i++) {
4293b9f5 4931 cur_bit = (0x1UL << i);
8736c826 4932 if (sig & cur_bit) {
0c23ad37 4933 res = true; /* Each bit is real error! */
4293b9f5
DK		 4934 if (print) {
4935 switch (cur_bit) {
4936 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4937 _print_next_block((*par_num)++,
4938 "PGLUE_B");
6bf07b8e 4939 _print_parity(bp,
4293b9f5
DK		 4940 PGLUE_B_REG_PGLUE_B_PRTY_STS);
4941 break;
4942 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4943 _print_next_block((*par_num)++, "ATC");
6bf07b8e
YM		 4944 _print_parity(bp,
4945 ATC_REG_ATC_PRTY_STS);
4293b9f5 4946 break;
6bf07b8e 4947 }
8736c826 4948 }
8736c826
VZ		 4949 /* Clear the bit */
4950 sig &= ~cur_bit;
4951 }
4952 }
4953
4293b9f5 4954 return res;
8736c826
VZ		 4955}
4956
1191cb83
ED		 4957static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4958 u32 *sig)
72fd0718 4959{
4293b9f5
DK		 4960 bool res = false;
4961
8736c826
VZ		 4962 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4963 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4964 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4965 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4966 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
72fd0718 4967 int par_num = 0;
ad6afbe9 4968
51c1a580
MS		 4969 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4970 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
8736c826
VZ		 4971 sig[0] & HW_PRTY_ASSERT_SET_0,
4972 sig[1] & HW_PRTY_ASSERT_SET_1,
4973 sig[2] & HW_PRTY_ASSERT_SET_2,
4974 sig[3] & HW_PRTY_ASSERT_SET_3,
4975 sig[4] & HW_PRTY_ASSERT_SET_4);
ad6afbe9
MC		 4976 if (print) {
4977 if (((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4978 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4979 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4980 (sig[4] & HW_PRTY_ASSERT_SET_4)) ||
4981 (sig[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD)) {
4982 netdev_err(bp->dev,
4983 "Parity errors detected in blocks: ");
4984 } else {
4985 print = false;
4986 }
4987 }
4293b9f5
DK		 4988 res |= bnx2x_check_blocks_with_parity0(bp,
4989 sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4990 res |= bnx2x_check_blocks_with_parity1(bp,
4991 sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4992 res |= bnx2x_check_blocks_with_parity2(bp,
4993 sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4994 res |= bnx2x_check_blocks_with_parity3(bp,
4995 sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4996 res |= bnx2x_check_blocks_with_parity4(bp,
4997 sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
8736c826 4998
c9ee9206
VZ		 4999 if (print)
5000 pr_cont("\n");
4293b9f5 5001 }
8736c826 5002
4293b9f5 5003 return res;
72fd0718
VZ		 5004}
5005
c9ee9206
VZ		 5006/**
5007 * bnx2x_chk_parity_attn - checks for parity attentions.
5008 *
5009 * @bp: driver handle
5010 * @global: true if there was a global attention
5011 * @print: show parity attention in syslog
5012 */
5013bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
877e9aa4 5014{
8736c826 5015 struct attn_route attn = { {0} };
72fd0718
VZ		 5016 int port = BP_PORT(bp);
5017
5018 attn.sig[0] = REG_RD(bp,
5019 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
5020 port*4);
5021 attn.sig[1] = REG_RD(bp,
5022 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
5023 port*4);
5024 attn.sig[2] = REG_RD(bp,
5025 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
5026 port*4);
5027 attn.sig[3] = REG_RD(bp,
5028 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
5029 port*4);
0a5ccb75
YM		 5030 /* Since MCP attentions can't be disabled inside the block, we need to
5031 * read AEU registers to see whether they're currently disabled
5032 */
5033 attn.sig[3] &= ((REG_RD(bp,
5034 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5035 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
5036 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
5037 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
72fd0718 5038
8736c826
VZ		 5039 if (!CHIP_IS_E1x(bp))
5040 attn.sig[4] = REG_RD(bp,
5041 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
5042 port*4);
5043
5044 return bnx2x_parity_attn(bp, global, print, attn.sig);
72fd0718
VZ		 5045}
5046
1191cb83 5047static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
f2e0899f
DK		 5048{
5049 u32 val;
5050 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5051
5052 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5053 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5054 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
51c1a580 5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
f2e0899f 5056 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
51c1a580 5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
f2e0899f 5058 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
51c1a580 5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
f2e0899f 5060 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
51c1a580 5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
f2e0899f
DK		 5062 if (val &
5063 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
51c1a580 5064 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
f2e0899f
DK		 5065 if (val &
5066 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
51c1a580 5067 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
f2e0899f 5068 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
51c1a580 5069 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
f2e0899f 5070 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
51c1a580 5071 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
f2e0899f 5072 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
51c1a580 5073 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
f2e0899f
DK		 5074 }
5075 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5076 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5077 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5078 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5079 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5080 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
51c1a580 5081 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
f2e0899f 5082 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
51c1a580 5083 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
f2e0899f 5084 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
51c1a580 5085 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
f2e0899f
DK		 5086 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5087 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5088 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
51c1a580 5089 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
f2e0899f
DK		 5090 }
5091
5092 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5093 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5094 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5095 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5096 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5097 }
f2e0899f
DK		 5098}
5099
72fd0718
VZ		 5100static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5101{
5102 struct attn_route attn, *group_mask;
34f80b04 5103 int port = BP_PORT(bp);
877e9aa4 5104 int index;
a2fbb9ea
ET		 5105 u32 reg_addr;
5106 u32 val;
3fcaf2e5 5107 u32 aeu_mask;
c9ee9206 5108 bool global = false;
a2fbb9ea
ET		 5109
5110 /* need to take HW lock because MCP or other port might also
5111 try to handle this event */
4a37fb66 5112 bnx2x_acquire_alr(bp);
a2fbb9ea 5113
c9ee9206
VZ		 5114 if (bnx2x_chk_parity_attn(bp, &global, true)) {
5115#ifndef BNX2X_STOP_ON_ERROR
72fd0718 5116 bp->recovery_state = BNX2X_RECOVERY_INIT;
7be08a72 5117 schedule_delayed_work(&bp->sp_rtnl_task, 0);
72fd0718
VZ		 5118 /* Disable HW interrupts */
5119 bnx2x_int_disable(bp);
72fd0718
VZ		 5120 /* In case of parity errors don't handle attentions so that
5121 * other function would "see" parity errors.
5122 */
c9ee9206
VZ		 5123#else
5124 bnx2x_panic();
5125#endif
5126 bnx2x_release_alr(bp);
72fd0718
VZ		 5127 return;
5128 }
5129
a2fbb9ea
ET		 5130 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5131 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5132 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5133 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
619c5cb6 5134 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 5135 attn.sig[4] =
5136 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5137 else
5138 attn.sig[4] = 0;
5139
5140 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5141 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
a2fbb9ea
ET		 5142
5143 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5144 if (deasserted & (1 << index)) {
72fd0718 5145 group_mask = &bp->attn_group[index];
a2fbb9ea 5146
51c1a580 5147 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
f2e0899f
DK		 5148 index,
5149 group_mask->sig[0], group_mask->sig[1],
5150 group_mask->sig[2], group_mask->sig[3],
5151 group_mask->sig[4]);
a2fbb9ea 5152
f2e0899f
DK		 5153 bnx2x_attn_int_deasserted4(bp,
5154 attn.sig[4] & group_mask->sig[4]);
877e9aa4 5155 bnx2x_attn_int_deasserted3(bp,
72fd0718 5156 attn.sig[3] & group_mask->sig[3]);
877e9aa4 5157 bnx2x_attn_int_deasserted1(bp,
72fd0718 5158 attn.sig[1] & group_mask->sig[1]);
877e9aa4 5159 bnx2x_attn_int_deasserted2(bp,
72fd0718 5160 attn.sig[2] & group_mask->sig[2]);
877e9aa4 5161 bnx2x_attn_int_deasserted0(bp,
72fd0718 5162 attn.sig[0] & group_mask->sig[0]);
a2fbb9ea
ET		 5163 }
5164 }
5165
4a37fb66 5166 bnx2x_release_alr(bp);
a2fbb9ea 5167
f2e0899f
DK		 5168 if (bp->common.int_block == INT_BLOCK_HC)
5169 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5170 COMMAND_REG_ATTN_BITS_CLR);
5171 else
5172 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
a2fbb9ea
ET		 5173
5174 val = ~deasserted;
f2e0899f
DK		 5175 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5176 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5c862848 5177 REG_WR(bp, reg_addr, val);
a2fbb9ea 5178
a2fbb9ea 5179 if (~bp->attn_state & deasserted)
3fcaf2e5 5180 BNX2X_ERR("IGU ERROR\n");
a2fbb9ea
ET		 5181
5182 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5183 MISC_REG_AEU_MASK_ATTN_FUNC_0;
5184
3fcaf2e5
EG		 5185 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5186 aeu_mask = REG_RD(bp, reg_addr);
5187
5188 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
5189 aeu_mask, deasserted);
72fd0718 5190 aeu_mask |= (deasserted & 0x3ff);
3fcaf2e5 5191 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
a2fbb9ea 5192
3fcaf2e5
EG		 5193 REG_WR(bp, reg_addr, aeu_mask);
5194 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
a2fbb9ea
ET		 5195
5196 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5197 bp->attn_state &= ~deasserted;
5198 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5199}
5200
5201static void bnx2x_attn_int(struct bnx2x *bp)
5202{
5203 /* read local copy of bits */
68d59484
EG		 5204 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5205 attn_bits);
5206 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5207 attn_bits_ack);
a2fbb9ea
ET		 5208 u32 attn_state = bp->attn_state;
5209
5210 /* look for changed bits */
5211 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
5212 u32 deasserted = ~attn_bits & attn_ack & attn_state;
5213
5214 DP(NETIF_MSG_HW,
5215 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5216 attn_bits, attn_ack, asserted, deasserted);
5217
5218 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
34f80b04 5219 BNX2X_ERR("BAD attention state\n");
a2fbb9ea
ET		 5220
5221 /* handle bits that were raised */
5222 if (asserted)
5223 bnx2x_attn_int_asserted(bp, asserted);
5224
5225 if (deasserted)
5226 bnx2x_attn_int_deasserted(bp, deasserted);
5227}
5228
619c5cb6
VZ		 5229void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5230 u16 index, u8 op, u8 update)
5231{
dc1ba591
AE		 5232 u32 igu_addr = bp->igu_base_addr;
5233 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
619c5cb6
VZ		 5234 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5235 igu_addr);
5236}
5237
1191cb83 5238static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
523224a3
DK		 5239{
5240 /* No memory barriers */
5241 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5242 mmiowb(); /* keep prod updates ordered */
5243}
5244
523224a3
DK		 5245static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5246 union event_ring_elem *elem)
5247{
619c5cb6
VZ		 5248 u8 err = elem->message.error;
5249
523224a3 5250 if (!bp->cnic_eth_dev.starting_cid ||
c3a8ce61
VZ		 5251 (cid < bp->cnic_eth_dev.starting_cid &&
5252 cid != bp->cnic_eth_dev.iscsi_l2_cid))
523224a3
DK		 5253 return 1;
5254
5255 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5256
619c5cb6
VZ		 5257 if (unlikely(err)) {
5258
523224a3
DK		 5259 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5260 cid);
823e1d90 5261 bnx2x_panic_dump(bp, false);
523224a3 5262 }
619c5cb6 5263 bnx2x_cnic_cfc_comp(bp, cid, err);
523224a3
DK		 5264 return 0;
5265}
523224a3 5266
1191cb83 5267static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5268{
5269 struct bnx2x_mcast_ramrod_params rparam;
5270 int rc;
5271
5272 memset(&rparam, 0, sizeof(rparam));
5273
5274 rparam.mcast_obj = &bp->mcast_obj;
5275
5276 netif_addr_lock_bh(bp->dev);
5277
5278 /* Clear pending state for the last command */
5279 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5280
5281 /* If there are pending mcast commands - send them */
5282 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5283 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5284 if (rc < 0)
5285 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5286 rc);
5287 }
5288
5289 netif_addr_unlock_bh(bp->dev);
5290}
5291
1191cb83
ED		 5292static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5293 union event_ring_elem *elem)
619c5cb6
VZ		 5294{
5295 unsigned long ramrod_flags = 0;
5296 int rc = 0;
9cd753a1
MS		 5297 u32 echo = le32_to_cpu(elem->message.data.eth_event.echo);
5298 u32 cid = echo & BNX2X_SWCID_MASK;
619c5cb6
VZ		 5299 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5300
5301 /* Always push next commands out, don't wait here */
5302 __set_bit(RAMROD_CONT, &ramrod_flags);
5303
9cd753a1 5304 switch (echo >> BNX2X_SWCID_SHIFT) {
619c5cb6 5305 case BNX2X_FILTER_MAC_PENDING:
51c1a580 5306 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
55c11941 5307 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
619c5cb6
VZ		 5308 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5309 else
15192a8c 5310 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
619c5cb6 5311
05cc5a39
YM		 5312 break;
5313 case BNX2X_FILTER_VLAN_PENDING:
5314 DP(BNX2X_MSG_SP, "Got SETUP_VLAN completions\n");
5315 vlan_mac_obj = &bp->sp_objs[cid].vlan_obj;
619c5cb6 5316 break;
619c5cb6 5317 case BNX2X_FILTER_MCAST_PENDING:
51c1a580 5318 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
619c5cb6
VZ		 5319 /* This is only relevant for 57710 where multicast MACs are
5320 * configured as unicast MACs using the same ramrod.
5321 */
5322 bnx2x_handle_mcast_eqe(bp);
5323 return;
5324 default:
9cd753a1 5325 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo);
619c5cb6
VZ		 5326 return;
5327 }
5328
5329 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5330
5331 if (rc < 0)
5332 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5333 else if (rc > 0)
5334 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
619c5cb6
VZ		 5335}
5336
619c5cb6 5337static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
619c5cb6 5338
1191cb83 5339static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
619c5cb6
VZ		 5340{
5341 netif_addr_lock_bh(bp->dev);
5342
5343 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5344
5345 /* Send rx_mode command again if was requested */
5346 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5347 bnx2x_set_storm_rx_mode(bp);
619c5cb6
VZ		 5348 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5349 &bp->sp_state))
5350 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5351 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5352 &bp->sp_state))
5353 bnx2x_set_iscsi_eth_rx_mode(bp, false);
619c5cb6
VZ		 5354
5355 netif_addr_unlock_bh(bp->dev);
5356}
5357
1191cb83 5358static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
a3348722
BW		 5359 union event_ring_elem *elem)
5360{
5361 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5362 DP(BNX2X_MSG_SP,
5363 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5364 elem->message.data.vif_list_event.func_bit_map);
5365 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5366 elem->message.data.vif_list_event.func_bit_map);
5367 } else if (elem->message.data.vif_list_event.echo ==
5368 VIF_LIST_RULE_SET) {
5369 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5370 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5371 }
5372}
5373
5374/* called with rtnl_lock */
1191cb83 5375static void bnx2x_after_function_update(struct bnx2x *bp)
a3348722
BW		 5376{
5377 int q, rc;
5378 struct bnx2x_fastpath *fp;
5379 struct bnx2x_queue_state_params queue_params = {NULL};
5380 struct bnx2x_queue_update_params *q_update_params =
5381 &queue_params.params.update;
5382
2de67439 5383 /* Send Q update command with afex vlan removal values for all Qs */
a3348722
BW		 5384 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5385
5386 /* set silent vlan removal values according to vlan mode */
5387 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5388 &q_update_params->update_flags);
5389 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5390 &q_update_params->update_flags);
5391 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5392
5393 /* in access mode mark mask and value are 0 to strip all vlans */
5394 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5395 q_update_params->silent_removal_value = 0;
5396 q_update_params->silent_removal_mask = 0;
5397 } else {
5398 q_update_params->silent_removal_value =
5399 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5400 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5401 }
5402
5403 for_each_eth_queue(bp, q) {
5404 /* Set the appropriate Queue object */
5405 fp = &bp->fp[q];
15192a8c 5406 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5407
5408 /* send the ramrod */
5409 rc = bnx2x_queue_state_change(bp, &queue_params);
5410 if (rc < 0)
5411 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5412 q);
5413 }
5414
fea75645 5415 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
65565884 5416 fp = &bp->fp[FCOE_IDX(bp)];
15192a8c 5417 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
a3348722
BW		 5418
5419 /* clear pending completion bit */
5420 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5421
5422 /* mark latest Q bit */
4e857c58 5423 smp_mb__before_atomic();
a3348722 5424 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4e857c58 5425 smp_mb__after_atomic();
a3348722
BW		 5426
5427 /* send Q update ramrod for FCoE Q */
5428 rc = bnx2x_queue_state_change(bp, &queue_params);
5429 if (rc < 0)
5430 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5431 q);
5432 } else {
5433 /* If no FCoE ring - ACK MCP now */
5434 bnx2x_link_report(bp);
5435 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5436 }
a3348722
BW		 5437}
5438
1191cb83 5439static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
619c5cb6
VZ		 5440 struct bnx2x *bp, u32 cid)
5441{
94f05b0f 5442 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
55c11941
MS		 5443
5444 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
15192a8c 5445 return &bnx2x_fcoe_sp_obj(bp, q_obj);
619c5cb6 5446 else
15192a8c 5447 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
619c5cb6
VZ		 5448}
5449
523224a3
DK		 5450static void bnx2x_eq_int(struct bnx2x *bp)
5451{
5452 u16 hw_cons, sw_cons, sw_prod;
5453 union event_ring_elem *elem;
55c11941 5454 u8 echo;
523224a3
DK		 5455 u32 cid;
5456 u8 opcode;
fd1fc79d 5457 int rc, spqe_cnt = 0;
619c5cb6
VZ		 5458 struct bnx2x_queue_sp_obj *q_obj;
5459 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5460 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
523224a3
DK		 5461
5462 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5463
5464 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
16a5fd92 5465 * when we get the next-page we need to adjust so the loop
523224a3
DK		 5466 * condition below will be met. The next element is the size of a
5467 * regular element and hence incrementing by 1
5468 */
5469 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5470 hw_cons++;
5471
25985edc 5472 /* This function may never run in parallel with itself for a
523224a3
DK		 5473 * specific bp, thus there is no need in "paired" read memory
5474 * barrier here.
5475 */
5476 sw_cons = bp->eq_cons;
5477 sw_prod = bp->eq_prod;
5478
d6cae238 5479 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
6e30dd4e 5480 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
523224a3
DK		 5481
5482 for (; sw_cons != hw_cons;
5483 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5484
523224a3
DK		 5485 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5486
fd1fc79d
AE		 5487 rc = bnx2x_iov_eq_sp_event(bp, elem);
5488 if (!rc) {
5489 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5490 rc);
5491 goto next_spqe;
5492 }
523224a3 5493
86564c3f 5494 opcode = elem->message.opcode;
523224a3
DK		 5495
5496 /* handle eq element */
5497 switch (opcode) {
fd1fc79d 5498 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
370d4a26
YM		 5499 bnx2x_vf_mbx_schedule(bp,
5500 &elem->message.data.vf_pf_event);
fd1fc79d
AE		 5501 continue;
5502
523224a3 5503 case EVENT_RING_OPCODE_STAT_QUERY:
76ca70fa
YM		 5504 DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5505 "got statistics comp event %d\n",
5506 bp->stats_comp++);
523224a3 5507 /* nothing to do with stats comp */
d6cae238 5508 goto next_spqe;
523224a3
DK		 5509
5510 case EVENT_RING_OPCODE_CFC_DEL:
5511 /* handle according to cid range */
5512 /*
5513 * we may want to verify here that the bp state is
5514 * HALTING
5515 */
ca4f2d50
MS		 5516
5517 /* elem CID originates from FW; actually LE */
da472731 5518 cid = SW_CID(elem->message.data.cfc_del_event.cid);
ca4f2d50 5519
d6cae238 5520 DP(BNX2X_MSG_SP,
523224a3 5521 "got delete ramrod for MULTI[%d]\n", cid);
55c11941
MS		 5522
5523 if (CNIC_LOADED(bp) &&
5524 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
523224a3 5525 goto next_spqe;
55c11941 5526
619c5cb6
VZ		 5527 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5528
5529 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5530 break;
5531
523224a3 5532 goto next_spqe;
e4901dde
VZ		 5533
5534 case EVENT_RING_OPCODE_STOP_TRAFFIC:
51c1a580 5535 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
6ffa39f2 5536 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
6debea87
DK		 5537 if (f_obj->complete_cmd(bp, f_obj,
5538 BNX2X_F_CMD_TX_STOP))
5539 break;
e4901dde 5540 goto next_spqe;
619c5cb6 5541
e4901dde 5542 case EVENT_RING_OPCODE_START_TRAFFIC:
51c1a580 5543 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
6ffa39f2 5544 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
6debea87
DK		 5545 if (f_obj->complete_cmd(bp, f_obj,
5546 BNX2X_F_CMD_TX_START))
5547 break;
e4901dde 5548 goto next_spqe;
55c11941 5549
a3348722 5550 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
55c11941
MS		 5551 echo = elem->message.data.function_update_event.echo;
5552 if (echo == SWITCH_UPDATE) {
5553 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5554 "got FUNC_SWITCH_UPDATE ramrod\n");
5555 if (f_obj->complete_cmd(
5556 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5557 break;
a3348722 5558
55c11941 5559 } else {
230bb0f3
YM		 5560 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5561
55c11941
MS		 5562 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5563 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5564 f_obj->complete_cmd(bp, f_obj,
5565 BNX2X_F_CMD_AFEX_UPDATE);
5566
5567 /* We will perform the Queues update from
5568 * sp_rtnl task as all Queue SP operations
5569 * should run under rtnl_lock.
5570 */
230bb0f3 5571 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
55c11941 5572 }
a3348722 5573
a3348722
BW		 5574 goto next_spqe;
5575
5576 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5577 f_obj->complete_cmd(bp, f_obj,
5578 BNX2X_F_CMD_AFEX_VIFLISTS);
5579 bnx2x_after_afex_vif_lists(bp, elem);
5580 goto next_spqe;
619c5cb6 5581 case EVENT_RING_OPCODE_FUNCTION_START:
51c1a580
MS		 5582 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5583 "got FUNC_START ramrod\n");
619c5cb6
VZ		 5584 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5585 break;
5586
5587 goto next_spqe;
5588
5589 case EVENT_RING_OPCODE_FUNCTION_STOP:
51c1a580
MS		 5590 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5591 "got FUNC_STOP ramrod\n");
619c5cb6
VZ		 5592 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5593 break;
5594
5595 goto next_spqe;
eeed018c
MK		 5596
5597 case EVENT_RING_OPCODE_SET_TIMESYNC:
5598 DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5599 "got set_timesync ramrod completion\n");
5600 if (f_obj->complete_cmd(bp, f_obj,
5601 BNX2X_F_CMD_SET_TIMESYNC))
5602 break;
5603 goto next_spqe;
523224a3
DK		 5604 }
5605
5606 switch (opcode | bp->state) {
619c5cb6
VZ		 5607 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5608 BNX2X_STATE_OPEN):
5609 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
523224a3 5610 BNX2X_STATE_OPENING_WAIT4_PORT):
28311f8e
YM		 5611 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5612 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5613 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
9cd753a1 5614 SW_CID(elem->message.data.eth_event.echo));
619c5cb6 5615 rss_raw->clear_pending(rss_raw);
523224a3
DK		 5616 break;
5617
619c5cb6
VZ		 5618 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5619 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5620 case (EVENT_RING_OPCODE_SET_MAC |
523224a3 5621 BNX2X_STATE_CLOSING_WAIT4_HALT):
619c5cb6
VZ		 5622 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5623 BNX2X_STATE_OPEN):
5624 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5625 BNX2X_STATE_DIAG):
5626 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5627 BNX2X_STATE_CLOSING_WAIT4_HALT):
05cc5a39 5628 DP(BNX2X_MSG_SP, "got (un)set vlan/mac ramrod\n");
619c5cb6 5629 bnx2x_handle_classification_eqe(bp, elem);
523224a3
DK		 5630 break;
5631
619c5cb6
VZ		 5632 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5633 BNX2X_STATE_OPEN):
5634 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5635 BNX2X_STATE_DIAG):
5636 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5637 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5638 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
619c5cb6 5639 bnx2x_handle_mcast_eqe(bp);
523224a3
DK		 5640 break;
5641
619c5cb6
VZ		 5642 case (EVENT_RING_OPCODE_FILTERS_RULES |
5643 BNX2X_STATE_OPEN):
5644 case (EVENT_RING_OPCODE_FILTERS_RULES |
5645 BNX2X_STATE_DIAG):
5646 case (EVENT_RING_OPCODE_FILTERS_RULES |
523224a3 5647 BNX2X_STATE_CLOSING_WAIT4_HALT):
d6cae238 5648 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
619c5cb6 5649 bnx2x_handle_rx_mode_eqe(bp);
523224a3
DK		 5650 break;
5651 default:
5652 /* unknown event log error and continue */
619c5cb6
VZ		 5653 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5654 elem->message.opcode, bp->state);
523224a3
DK		 5655 }
5656next_spqe:
5657 spqe_cnt++;
5658 } /* for */
5659
4e857c58 5660 smp_mb__before_atomic();
6e30dd4e 5661 atomic_add(spqe_cnt, &bp->eq_spq_left);
523224a3
DK		 5662
5663 bp->eq_cons = sw_cons;
5664 bp->eq_prod = sw_prod;
5665 /* Make sure that above mem writes were issued towards the memory */
5666 smp_wmb();
5667
5668 /* update producer */
5669 bnx2x_update_eq_prod(bp, bp->eq_prod);
5670}
5671
a2fbb9ea
ET		 5672static void bnx2x_sp_task(struct work_struct *work)
5673{
1cf167f2 5674 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
a2fbb9ea 5675
fd1fc79d 5676 DP(BNX2X_MSG_SP, "sp task invoked\n");
a2fbb9ea 5677
16a5fd92 5678 /* make sure the atomic interrupt_occurred has been written */
fd1fc79d
AE		 5679 smp_rmb();
5680 if (atomic_read(&bp->interrupt_occurred)) {
a2fbb9ea 5681
fd1fc79d
AE		 5682 /* what work needs to be performed? */
5683 u16 status = bnx2x_update_dsb_idx(bp);
cdaa7cb8 5684
fd1fc79d
AE		 5685 DP(BNX2X_MSG_SP, "status %x\n", status);
5686 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5687 atomic_set(&bp->interrupt_occurred, 0);
5688
5689 /* HW attentions */
5690 if (status & BNX2X_DEF_SB_ATT_IDX) {
5691 bnx2x_attn_int(bp);
5692 status &= ~BNX2X_DEF_SB_ATT_IDX;
5693 }
5694
5695 /* SP events: STAT_QUERY and others */
5696 if (status & BNX2X_DEF_SB_IDX) {
5697 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
523224a3 5698
7e88009b 5699 if (FCOE_INIT(bp) &&
fd1fc79d
AE		 5700 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5701 /* Prevent local bottom-halves from running as
5702 * we are going to change the local NAPI list.
5703 */
5704 local_bh_disable();
5705 napi_schedule(&bnx2x_fcoe(bp, napi));
5706 local_bh_enable();
5707 }
5708
5709 /* Handle EQ completions */
5710 bnx2x_eq_int(bp);
5711 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5712 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5713
5714 status &= ~BNX2X_DEF_SB_IDX;
019dbb4c 5715 }
55c11941 5716
fd1fc79d
AE		 5717 /* if status is non zero then perhaps something went wrong */
5718 if (unlikely(status))
5719 DP(BNX2X_MSG_SP,
5720 "got an unknown interrupt! (status 0x%x)\n", status);
523224a3 5721
fd1fc79d
AE		 5722 /* ack status block only if something was actually handled */
5723 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5724 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
cdaa7cb8
VZ		 5725 }
5726
a3348722
BW		 5727 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5728 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5729 &bp->sp_state)) {
5730 bnx2x_link_report(bp);
5731 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5732 }
a2fbb9ea
ET		 5733}
5734
9f6c9258 5735irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
a2fbb9ea
ET		 5736{
5737 struct net_device *dev = dev_instance;
5738 struct bnx2x *bp = netdev_priv(dev);
5739
523224a3
DK		 5740 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5741 IGU_INT_DISABLE, 0);
a2fbb9ea
ET		 5742
5743#ifdef BNX2X_STOP_ON_ERROR
5744 if (unlikely(bp->panic))
5745 return IRQ_HANDLED;
5746#endif
5747
55c11941 5748 if (CNIC_LOADED(bp)) {
993ac7b5
MC		 5749 struct cnic_ops *c_ops;
5750
5751 rcu_read_lock();
5752 c_ops = rcu_dereference(bp->cnic_ops);
5753 if (c_ops)
5754 c_ops->cnic_handler(bp->cnic_data, NULL);
5755 rcu_read_unlock();
5756 }
55c11941 5757
fd1fc79d
AE		 5758 /* schedule sp task to perform default status block work, ack
5759 * attentions and enable interrupts.
5760 */
5761 bnx2x_schedule_sp_task(bp);
a2fbb9ea
ET		 5762
5763 return IRQ_HANDLED;
5764}
5765
5766/* end of slow path */
5767
619c5cb6
VZ		 5768void bnx2x_drv_pulse(struct bnx2x *bp)
5769{
5770 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5771 bp->fw_drv_pulse_wr_seq);
5772}
5773
e99e88a9 5774static void bnx2x_timer(struct timer_list *t)
a2fbb9ea 5775{
e99e88a9 5776 struct bnx2x *bp = from_timer(bp, t, timer);
a2fbb9ea
ET		 5777
5778 if (!netif_running(bp->dev))
5779 return;
5780
67c431a5
AE		 5781 if (IS_PF(bp) &&
5782 !BP_NOMCP(bp)) {
f2e0899f 5783 int mb_idx = BP_FW_MB_IDX(bp);
4c868664
EG		 5784 u16 drv_pulse;
5785 u16 mcp_pulse;
a2fbb9ea
ET		 5786
5787 ++bp->fw_drv_pulse_wr_seq;
5788 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
a2fbb9ea 5789 drv_pulse = bp->fw_drv_pulse_wr_seq;
619c5cb6 5790 bnx2x_drv_pulse(bp);
a2fbb9ea 5791
f2e0899f 5792 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
a2fbb9ea
ET		 5793 MCP_PULSE_SEQ_MASK);
5794 /* The delta between driver pulse and mcp response
4c868664
EG		 5795 * should not get too big. If the MFW is more than 5 pulses
5796 * behind, we should worry about it enough to generate an error
5797 * log.
a2fbb9ea 5798 */
4c868664
EG		 5799 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5800 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
a2fbb9ea 5801 drv_pulse, mcp_pulse);
a2fbb9ea
ET		 5802 }
5803
f34d28ea 5804 if (bp->state == BNX2X_STATE_OPEN)
bb2a0f7a 5805 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
a2fbb9ea 5806
abc5a021 5807 /* sample pf vf bulletin board for new posts from pf */
37173488
YM		 5808 if (IS_VF(bp))
5809 bnx2x_timer_sriov(bp);
78c3bcc5 5810
a2fbb9ea
ET		 5811 mod_timer(&bp->timer, jiffies + bp->current_interval);
5812}
5813
5814/* end of Statistics */
5815
5816/* nic init */
5817
5818/*
5819 * nic init service functions
5820 */
5821
1191cb83 5822static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
a2fbb9ea 5823{
523224a3
DK		 5824 u32 i;
5825 if (!(len%4) && !(addr%4))
5826 for (i = 0; i < len; i += 4)
5827 REG_WR(bp, addr + i, fill);
5828 else
5829 for (i = 0; i < len; i++)
5830 REG_WR8(bp, addr + i, fill);
34f80b04
EG		 5831}
5832
523224a3 5833/* helper: writes FP SP data to FW - data_size in dwords */
1191cb83
ED		 5834static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5835 int fw_sb_id,
5836 u32 *sb_data_p,
5837 u32 data_size)
34f80b04 5838{
a2fbb9ea 5839 int index;
523224a3
DK		 5840 for (index = 0; index < data_size; index++)
5841 REG_WR(bp, BAR_CSTRORM_INTMEM +
5842 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5843 sizeof(u32)*index,
5844 *(sb_data_p + index));
5845}
a2fbb9ea 5846
1191cb83 5847static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
523224a3
DK		 5848{
5849 u32 *sb_data_p;
5850 u32 data_size = 0;
f2e0899f 5851 struct hc_status_block_data_e2 sb_data_e2;
523224a3 5852 struct hc_status_block_data_e1x sb_data_e1x;
a2fbb9ea 5853
523224a3 5854 /* disable the function first */
619c5cb6 5855 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5856 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5857 sb_data_e2.common.state = SB_DISABLED;
f2e0899f
DK		 5858 sb_data_e2.common.p_func.vf_valid = false;
5859 sb_data_p = (u32 *)&sb_data_e2;
5860 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5861 } else {
5862 memset(&sb_data_e1x, 0,
5863 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5864 sb_data_e1x.common.state = SB_DISABLED;
f2e0899f
DK		 5865 sb_data_e1x.common.p_func.vf_valid = false;
5866 sb_data_p = (u32 *)&sb_data_e1x;
5867 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5868 }
523224a3 5869 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
a2fbb9ea 5870
523224a3
DK		 5871 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5872 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5873 CSTORM_STATUS_BLOCK_SIZE);
5874 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5875 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5876 CSTORM_SYNC_BLOCK_SIZE);
5877}
34f80b04 5878
523224a3 5879/* helper: writes SP SB data to FW */
1191cb83 5880static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
523224a3
DK		 5881 struct hc_sp_status_block_data *sp_sb_data)
5882{
5883 int func = BP_FUNC(bp);
5884 int i;
5885 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5886 REG_WR(bp, BAR_CSTRORM_INTMEM +
5887 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5888 i*sizeof(u32),
5889 *((u32 *)sp_sb_data + i));
34f80b04
EG		 5890}
5891
1191cb83 5892static void bnx2x_zero_sp_sb(struct bnx2x *bp)
34f80b04
EG		 5893{
5894 int func = BP_FUNC(bp);
523224a3
DK		 5895 struct hc_sp_status_block_data sp_sb_data;
5896 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
a2fbb9ea 5897
619c5cb6 5898 sp_sb_data.state = SB_DISABLED;
523224a3
DK		 5899 sp_sb_data.p_func.vf_valid = false;
5900
5901 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5902
5903 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5904 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5905 CSTORM_SP_STATUS_BLOCK_SIZE);
5906 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5907 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5908 CSTORM_SP_SYNC_BLOCK_SIZE);
523224a3
DK		 5909}
5910
1191cb83 5911static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
523224a3
DK		 5912 int igu_sb_id, int igu_seg_id)
5913{
5914 hc_sm->igu_sb_id = igu_sb_id;
5915 hc_sm->igu_seg_id = igu_seg_id;
5916 hc_sm->timer_value = 0xFF;
5917 hc_sm->time_to_expire = 0xFFFFFFFF;
a2fbb9ea
ET		 5918}
5919
150966ad 5920/* allocates state machine ids. */
1191cb83 5921static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
150966ad
AE		 5922{
5923 /* zero out state machine indices */
5924 /* rx indices */
5925 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5926
5927 /* tx indices */
5928 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5929 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5930 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5931 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5932
5933 /* map indices */
5934 /* rx indices */
5935 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5936 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5937
5938 /* tx indices */
5939 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5940 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5941 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5942 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5943 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5944 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5945 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5946 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5947}
5948
b93288d5 5949void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
523224a3 5950 u8 vf_valid, int fw_sb_id, int igu_sb_id)
a2fbb9ea 5951{
523224a3
DK		 5952 int igu_seg_id;
5953
f2e0899f 5954 struct hc_status_block_data_e2 sb_data_e2;
523224a3
DK		 5955 struct hc_status_block_data_e1x sb_data_e1x;
5956 struct hc_status_block_sm *hc_sm_p;
523224a3
DK		 5957 int data_size;
5958 u32 *sb_data_p;
5959
f2e0899f
DK		 5960 if (CHIP_INT_MODE_IS_BC(bp))
5961 igu_seg_id = HC_SEG_ACCESS_NORM;
5962 else
5963 igu_seg_id = IGU_SEG_ACCESS_NORM;
523224a3
DK		 5964
5965 bnx2x_zero_fp_sb(bp, fw_sb_id);
5966
619c5cb6 5967 if (!CHIP_IS_E1x(bp)) {
f2e0899f 5968 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
619c5cb6 5969 sb_data_e2.common.state = SB_ENABLED;
f2e0899f
DK		 5970 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5971 sb_data_e2.common.p_func.vf_id = vfid;
5972 sb_data_e2.common.p_func.vf_valid = vf_valid;
5973 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5974 sb_data_e2.common.same_igu_sb_1b = true;
5975 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5976 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5977 hc_sm_p = sb_data_e2.common.state_machine;
f2e0899f
DK		 5978 sb_data_p = (u32 *)&sb_data_e2;
5979 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
150966ad 5980 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
f2e0899f
DK		 5981 } else {
5982 memset(&sb_data_e1x, 0,
5983 sizeof(struct hc_status_block_data_e1x));
619c5cb6 5984 sb_data_e1x.common.state = SB_ENABLED;
f2e0899f
DK		 5985 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5986 sb_data_e1x.common.p_func.vf_id = 0xff;
5987 sb_data_e1x.common.p_func.vf_valid = false;
5988 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5989 sb_data_e1x.common.same_igu_sb_1b = true;
5990 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5991 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5992 hc_sm_p = sb_data_e1x.common.state_machine;
f2e0899f
DK		 5993 sb_data_p = (u32 *)&sb_data_e1x;
5994 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
150966ad 5995 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
f2e0899f 5996 }
523224a3
DK		 5997
5998 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5999 igu_sb_id, igu_seg_id);
6000 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
6001 igu_sb_id, igu_seg_id);
6002
51c1a580 6003 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
523224a3 6004
86564c3f 6005 /* write indices to HW - PCI guarantees endianity of regpairs */
523224a3
DK		 6006 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
6007}
6008
619c5cb6 6009static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
523224a3
DK		 6010 u16 tx_usec, u16 rx_usec)
6011{
6383c0b3 6012 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
523224a3 6013 false, rx_usec);
6383c0b3
AE		 6014 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6015 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
6016 tx_usec);
6017 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6018 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
6019 tx_usec);
6020 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
6021 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
6022 tx_usec);
523224a3 6023}
f2e0899f 6024
523224a3
DK		 6025static void bnx2x_init_def_sb(struct bnx2x *bp)
6026{
6027 struct host_sp_status_block *def_sb = bp->def_status_blk;
6028 dma_addr_t mapping = bp->def_status_blk_mapping;
6029 int igu_sp_sb_index;
6030 int igu_seg_id;
34f80b04
EG		 6031 int port = BP_PORT(bp);
6032 int func = BP_FUNC(bp);
f2eaeb58 6033 int reg_offset, reg_offset_en5;
a2fbb9ea 6034 u64 section;
523224a3
DK		 6035 int index;
6036 struct hc_sp_status_block_data sp_sb_data;
6037 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
6038
f2e0899f
DK		 6039 if (CHIP_INT_MODE_IS_BC(bp)) {
6040 igu_sp_sb_index = DEF_SB_IGU_ID;
6041 igu_seg_id = HC_SEG_ACCESS_DEF;
6042 } else {
6043 igu_sp_sb_index = bp->igu_dsb_id;
6044 igu_seg_id = IGU_SEG_ACCESS_DEF;
6045 }
a2fbb9ea
ET		 6046
6047 /* ATTN */
523224a3 6048 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
a2fbb9ea 6049 atten_status_block);
523224a3 6050 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
a2fbb9ea 6051
49d66772
ET		 6052 bp->attn_state = 0;
6053
a2fbb9ea
ET		 6054 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6055 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
f2eaeb58
DK		 6056 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6057 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
34f80b04 6058 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
523224a3
DK		 6059 int sindex;
6060 /* take care of sig[0]..sig[4] */
6061 for (sindex = 0; sindex < 4; sindex++)
6062 bp->attn_group[index].sig[sindex] =
6063 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
f2e0899f 6064
619c5cb6 6065 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6066 /*
6067 * enable5 is separate from the rest of the registers,
6068 * and therefore the address skip is 4
6069 * and not 16 between the different groups
6070 */
6071 bp->attn_group[index].sig[4] = REG_RD(bp,
f2eaeb58 6072 reg_offset_en5 + 0x4*index);
f2e0899f
DK		 6073 else
6074 bp->attn_group[index].sig[4] = 0;
a2fbb9ea
ET		 6075 }
6076
f2e0899f
DK		 6077 if (bp->common.int_block == INT_BLOCK_HC) {
6078 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6079 HC_REG_ATTN_MSG0_ADDR_L);
6080
6081 REG_WR(bp, reg_offset, U64_LO(section));
6082 REG_WR(bp, reg_offset + 4, U64_HI(section));
619c5cb6 6083 } else if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6084 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6085 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6086 }
a2fbb9ea 6087
523224a3
DK		 6088 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6089 sp_sb);
a2fbb9ea 6090
523224a3 6091 bnx2x_zero_sp_sb(bp);
a2fbb9ea 6092
86564c3f 6093 /* PCI guarantees endianity of regpairs */
619c5cb6 6094 sp_sb_data.state = SB_ENABLED;
523224a3
DK		 6095 sp_sb_data.host_sb_addr.lo = U64_LO(section);
6096 sp_sb_data.host_sb_addr.hi = U64_HI(section);
6097 sp_sb_data.igu_sb_id = igu_sp_sb_index;
6098 sp_sb_data.igu_seg_id = igu_seg_id;
6099 sp_sb_data.p_func.pf_id = func;
f2e0899f 6100 sp_sb_data.p_func.vnic_id = BP_VN(bp);
523224a3 6101 sp_sb_data.p_func.vf_id = 0xff;
a2fbb9ea 6102
523224a3 6103 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
49d66772 6104
523224a3 6105 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
a2fbb9ea
ET		 6106}
6107
9f6c9258 6108void bnx2x_update_coalesce(struct bnx2x *bp)
a2fbb9ea 6109{
a2fbb9ea
ET		 6110 int i;
6111
ec6ba945 6112 for_each_eth_queue(bp, i)
523224a3 6113 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
423cfa7e 6114 bp->tx_ticks, bp->rx_ticks);
a2fbb9ea
ET		 6115}
6116
a2fbb9ea
ET		 6117static void bnx2x_init_sp_ring(struct bnx2x *bp)
6118{
a2fbb9ea 6119 spin_lock_init(&bp->spq_lock);
6e30dd4e 6120 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
a2fbb9ea 6121
a2fbb9ea 6122 bp->spq_prod_idx = 0;
a2fbb9ea
ET		 6123 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6124 bp->spq_prod_bd = bp->spq;
6125 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
a2fbb9ea
ET		 6126}
6127
523224a3 6128static void bnx2x_init_eq_ring(struct bnx2x *bp)
a2fbb9ea
ET		 6129{
6130 int i;
523224a3
DK		 6131 for (i = 1; i <= NUM_EQ_PAGES; i++) {
6132 union event_ring_elem *elem =
6133 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
a2fbb9ea 6134
523224a3
DK		 6135 elem->next_page.addr.hi =
6136 cpu_to_le32(U64_HI(bp->eq_mapping +
6137 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6138 elem->next_page.addr.lo =
6139 cpu_to_le32(U64_LO(bp->eq_mapping +
6140 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
a2fbb9ea 6141 }
523224a3
DK		 6142 bp->eq_cons = 0;
6143 bp->eq_prod = NUM_EQ_DESC;
6144 bp->eq_cons_sb = BNX2X_EQ_INDEX;
16a5fd92 6145 /* we want a warning message before it gets wrought... */
6e30dd4e
VZ		 6146 atomic_set(&bp->eq_spq_left,
6147 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
a2fbb9ea
ET		 6148}
6149
619c5cb6 6150/* called with netif_addr_lock_bh() */
a8f47eb7 6151static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6152 unsigned long rx_mode_flags,
6153 unsigned long rx_accept_flags,
6154 unsigned long tx_accept_flags,
6155 unsigned long ramrod_flags)
ab532cf3 6156{
619c5cb6
VZ		 6157 struct bnx2x_rx_mode_ramrod_params ramrod_param;
6158 int rc;
6159
6160 memset(&ramrod_param, 0, sizeof(ramrod_param));
6161
6162 /* Prepare ramrod parameters */
6163 ramrod_param.cid = 0;
6164 ramrod_param.cl_id = cl_id;
6165 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6166 ramrod_param.func_id = BP_FUNC(bp);
ab532cf3 6167
619c5cb6
VZ		 6168 ramrod_param.pstate = &bp->sp_state;
6169 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
ab532cf3 6170
619c5cb6
VZ		 6171 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6172 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6173
6174 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6175
6176 ramrod_param.ramrod_flags = ramrod_flags;
6177 ramrod_param.rx_mode_flags = rx_mode_flags;
6178
6179 ramrod_param.rx_accept_flags = rx_accept_flags;
6180 ramrod_param.tx_accept_flags = tx_accept_flags;
6181
6182 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6183 if (rc < 0) {
6184 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
924d75ab 6185 return rc;
619c5cb6 6186 }
924d75ab
YM		 6187
6188 return 0;
a2fbb9ea
ET		 6189}
6190
86564c3f
YM		 6191static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6192 unsigned long *rx_accept_flags,
6193 unsigned long *tx_accept_flags)
471de716 6194{
924d75ab
YM		 6195 /* Clear the flags first */
6196 *rx_accept_flags = 0;
6197 *tx_accept_flags = 0;
619c5cb6 6198
924d75ab 6199 switch (rx_mode) {
619c5cb6
VZ		 6200 case BNX2X_RX_MODE_NONE:
6201 /*
6202 * 'drop all' supersedes any accept flags that may have been
6203 * passed to the function.
6204 */
6205 break;
6206 case BNX2X_RX_MODE_NORMAL:
924d75ab
YM		 6207 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6208 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6209 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6210
6211 /* internal switching mode */
924d75ab
YM		 6212 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6213 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6214 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6215
05cc5a39
YM		 6216 if (bp->accept_any_vlan) {
6217 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6218 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6219 }
6220
619c5cb6
VZ		 6221 break;
6222 case BNX2X_RX_MODE_ALLMULTI:
924d75ab
YM		 6223 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6224 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6225 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6226
6227 /* internal switching mode */
924d75ab
YM		 6228 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6229 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6230 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6 6231
05cc5a39
YM		 6232 if (bp->accept_any_vlan) {
6233 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6234 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6235 }
6236
619c5cb6
VZ		 6237 break;
6238 case BNX2X_RX_MODE_PROMISC:
16a5fd92 6239 /* According to definition of SI mode, iface in promisc mode
619c5cb6
VZ		 6240 * should receive matched and unmatched (in resolution of port)
6241 * unicast packets.
6242 */
924d75ab
YM		 6243 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6244 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6245 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6246 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
619c5cb6
VZ		 6247
6248 /* internal switching mode */
924d75ab
YM		 6249 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6250 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
619c5cb6
VZ		 6251
6252 if (IS_MF_SI(bp))
924d75ab 6253 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
619c5cb6 6254 else
924d75ab 6255 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
619c5cb6 6256
05cc5a39
YM		 6257 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6258 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6259
619c5cb6
VZ		 6260 break;
6261 default:
924d75ab
YM		 6262 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6263 return -EINVAL;
619c5cb6 6264 }
de832a55 6265
924d75ab
YM		 6266 return 0;
6267}
6268
6269/* called with netif_addr_lock_bh() */
a8f47eb7 6270static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
924d75ab
YM		 6271{
6272 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6273 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6274 int rc;
6275
6276 if (!NO_FCOE(bp))
6277 /* Configure rx_mode of FCoE Queue */
6278 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6279
6280 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6281 &tx_accept_flags);
6282 if (rc)
6283 return rc;
6284
619c5cb6
VZ		 6285 __set_bit(RAMROD_RX, &ramrod_flags);
6286 __set_bit(RAMROD_TX, &ramrod_flags);
6287
924d75ab
YM		 6288 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6289 rx_accept_flags, tx_accept_flags,
6290 ramrod_flags);
619c5cb6
VZ		 6291}
6292
6293static void bnx2x_init_internal_common(struct bnx2x *bp)
6294{
6295 int i;
6296
523224a3
DK		 6297 /* Zero this manually as its initialization is
6298 currently missing in the initTool */
6299 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
ca00392c 6300 REG_WR(bp, BAR_USTRORM_INTMEM +
523224a3 6301 USTORM_AGG_DATA_OFFSET + i * 4, 0);
619c5cb6 6302 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 6303 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6304 CHIP_INT_MODE_IS_BC(bp) ?
6305 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6306 }
523224a3 6307}
8a1c38d1 6308
471de716
EG		 6309static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6310{
6311 switch (load_code) {
6312 case FW_MSG_CODE_DRV_LOAD_COMMON:
f2e0899f 6313 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
471de716
EG		 6314 bnx2x_init_internal_common(bp);
6315 /* no break */
6316
6317 case FW_MSG_CODE_DRV_LOAD_PORT:
619c5cb6 6318 /* nothing to do */
471de716
EG		 6319 /* no break */
6320
6321 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
523224a3
DK		 6322 /* internal memory per function is
6323 initialized inside bnx2x_pf_init */
471de716
EG		 6324 break;
6325
6326 default:
6327 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6328 break;
6329 }
6330}
6331
619c5cb6 6332static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
523224a3 6333{
55c11941 6334 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6 6335}
523224a3 6336
619c5cb6
VZ		 6337static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6338{
55c11941 6339 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
619c5cb6
VZ		 6340}
6341
1191cb83 6342static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
619c5cb6
VZ		 6343{
6344 if (CHIP_IS_E1x(fp->bp))
6345 return BP_L_ID(fp->bp) + fp->index;
6346 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6347 return bnx2x_fp_igu_sb_id(fp);
6348}
6349
6383c0b3 6350static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
619c5cb6
VZ		 6351{
6352 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6383c0b3 6353 u8 cos;
619c5cb6 6354 unsigned long q_type = 0;
6383c0b3 6355 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
f233cafe 6356 fp->rx_queue = fp_idx;
b3b83c3f 6357 fp->cid = fp_idx;
619c5cb6
VZ		 6358 fp->cl_id = bnx2x_fp_cl_id(fp);
6359 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6360 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
523224a3 6361 /* qZone id equals to FW (per path) client id */
619c5cb6
VZ		 6362 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
6363
523224a3 6364 /* init shortcut */
619c5cb6 6365 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
7a752993 6366
16a5fd92 6367 /* Setup SB indices */
523224a3 6368 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
523224a3 6369
619c5cb6
VZ		 6370 /* Configure Queue State object */
6371 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6372 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6383c0b3
AE		 6373
6374 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6375
6376 /* init tx data */
6377 for_each_cos_in_tx_queue(fp, cos) {
65565884
MS		 6378 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6379 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6380 FP_COS_TO_TXQ(fp, cos, bp),
6381 BNX2X_TX_SB_INDEX_BASE + cos, fp);
6382 cids[cos] = fp->txdata_ptr[cos]->cid;
6383c0b3
AE		 6383 }
6384
ad5afc89
AE		 6385 /* nothing more for vf to do here */
6386 if (IS_VF(bp))
6387 return;
6388
6389 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6390 fp->fw_sb_id, fp->igu_sb_id);
6391 bnx2x_update_fpsb_idx(fp);
15192a8c
BW		 6392 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6393 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6383c0b3 6394 bnx2x_sp_mapping(bp, q_rdata), q_type);
619c5cb6
VZ		 6395
6396 /**
6397 * Configure classification DBs: Always enable Tx switching
6398 */
6399 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6400
ad5afc89
AE		 6401 DP(NETIF_MSG_IFUP,
6402 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6403 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6404 fp->igu_sb_id);
523224a3
DK		 6405}
6406
1191cb83
ED		 6407static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6408{
6409 int i;
6410
6411 for (i = 1; i <= NUM_TX_RINGS; i++) {
6412 struct eth_tx_next_bd *tx_next_bd =
6413 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6414
6415 tx_next_bd->addr_hi =
6416 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6417 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6418 tx_next_bd->addr_lo =
6419 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6420 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6421 }
6422
639d65b8
YM		 6423 *txdata->tx_cons_sb = cpu_to_le16(0);
6424
1191cb83
ED		 6425 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6426 txdata->tx_db.data.zero_fill1 = 0;
6427 txdata->tx_db.data.prod = 0;
6428
6429 txdata->tx_pkt_prod = 0;
6430 txdata->tx_pkt_cons = 0;
6431 txdata->tx_bd_prod = 0;
6432 txdata->tx_bd_cons = 0;
6433 txdata->tx_pkt = 0;
6434}
6435
55c11941
MS		 6436static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6437{
6438 int i;
6439
6440 for_each_tx_queue_cnic(bp, i)
6441 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6442}
d76a6111 6443
1191cb83
ED		 6444static void bnx2x_init_tx_rings(struct bnx2x *bp)
6445{
6446 int i;
6447 u8 cos;
6448
55c11941 6449 for_each_eth_queue(bp, i)
1191cb83 6450 for_each_cos_in_tx_queue(&bp->fp[i], cos)
65565884 6451 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
1191cb83
ED		 6452}
6453
a8f47eb7 6454static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6455{
6456 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6457 unsigned long q_type = 0;
6458
6459 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6460 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6461 BNX2X_FCOE_ETH_CL_ID_IDX);
6462 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6463 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6464 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6465 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6466 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6467 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6468 fp);
6469
6470 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6471
6472 /* qZone id equals to FW (per path) client id */
6473 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6474 /* init shortcut */
6475 bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6476 bnx2x_rx_ustorm_prods_offset(fp);
6477
6478 /* Configure Queue State object */
6479 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6480 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6481
6482 /* No multi-CoS for FCoE L2 client */
6483 BUG_ON(fp->max_cos != 1);
6484
6485 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6486 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6487 bnx2x_sp_mapping(bp, q_rdata), q_type);
6488
6489 DP(NETIF_MSG_IFUP,
6490 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6491 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6492 fp->igu_sb_id);
6493}
6494
55c11941 6495void bnx2x_nic_init_cnic(struct bnx2x *bp)
a2fbb9ea 6496{
ec6ba945
VZ		 6497 if (!NO_FCOE(bp))
6498 bnx2x_init_fcoe_fp(bp);
523224a3
DK		 6499
6500 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6501 BNX2X_VF_ID_INVALID, false,
619c5cb6 6502 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
523224a3 6503
55c11941
MS		 6504 /* ensure status block indices were read */
6505 rmb();
6506 bnx2x_init_rx_rings_cnic(bp);
6507 bnx2x_init_tx_rings_cnic(bp);
6508
6509 /* flush all */
6510 mb();
6511 mmiowb();
6512}
a2fbb9ea 6513
ecf01c22 6514void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
55c11941
MS		 6515{
6516 int i;
6517
ecf01c22 6518 /* Setup NIC internals and enable interrupts */
55c11941
MS		 6519 for_each_eth_queue(bp, i)
6520 bnx2x_init_eth_fp(bp, i);
ad5afc89
AE		 6521
6522 /* ensure status block indices were read */
6523 rmb();
6524 bnx2x_init_rx_rings(bp);
6525 bnx2x_init_tx_rings(bp);
6526
ecf01c22
YM		 6527 if (IS_PF(bp)) {
6528 /* Initialize MOD_ABS interrupts */
6529 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6530 bp->common.shmem_base,
6531 bp->common.shmem2_base, BP_PORT(bp));
ad5afc89 6532
ecf01c22
YM		 6533 /* initialize the default status block and sp ring */
6534 bnx2x_init_def_sb(bp);
6535 bnx2x_update_dsb_idx(bp);
6536 bnx2x_init_sp_ring(bp);
3cdeec22
YM		 6537 } else {
6538 bnx2x_memset_stats(bp);
ecf01c22
YM		 6539 }
6540}
16119785 6541
ecf01c22
YM		 6542void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6543{
523224a3 6544 bnx2x_init_eq_ring(bp);
471de716 6545 bnx2x_init_internal(bp, load_code);
523224a3 6546 bnx2x_pf_init(bp);
0ef00459
EG		 6547 bnx2x_stats_init(bp);
6548
0ef00459
EG		 6549 /* flush all before enabling interrupts */
6550 mb();
6551 mmiowb();
6552
615f8fd9 6553 bnx2x_int_enable(bp);
eb8da205
EG		 6554
6555 /* Check for SPIO5 */
6556 bnx2x_attn_int_deasserted0(bp,
6557 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6558 AEU_INPUTS_ATTN_BITS_SPIO5);
a2fbb9ea
ET		 6559}
6560
ecf01c22 6561/* gzip service functions */
a2fbb9ea
ET		 6562static int bnx2x_gunzip_init(struct bnx2x *bp)
6563{
1a983142
FT		 6564 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6565 &bp->gunzip_mapping, GFP_KERNEL);
a2fbb9ea
ET		 6566 if (bp->gunzip_buf == NULL)
6567 goto gunzip_nomem1;
6568
6569 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6570 if (bp->strm == NULL)
6571 goto gunzip_nomem2;
6572
7ab24bfd 6573 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
a2fbb9ea
ET		 6574 if (bp->strm->workspace == NULL)
6575 goto gunzip_nomem3;
6576
6577 return 0;
6578
6579gunzip_nomem3:
6580 kfree(bp->strm);
6581 bp->strm = NULL;
6582
6583gunzip_nomem2:
1a983142
FT		 6584 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6585 bp->gunzip_mapping);
a2fbb9ea
ET		 6586 bp->gunzip_buf = NULL;
6587
6588gunzip_nomem1:
51c1a580 6589 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
a2fbb9ea
ET		 6590 return -ENOMEM;
6591}
6592
6593static void bnx2x_gunzip_end(struct bnx2x *bp)
6594{
b3b83c3f 6595 if (bp->strm) {
7ab24bfd 6596 vfree(bp->strm->workspace);
b3b83c3f
DK		 6597 kfree(bp->strm);
6598 bp->strm = NULL;
6599 }
a2fbb9ea
ET		 6600
6601 if (bp->gunzip_buf) {
1a983142
FT		 6602 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6603 bp->gunzip_mapping);
a2fbb9ea
ET		 6604 bp->gunzip_buf = NULL;
6605 }
6606}
6607
94a78b79 6608static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
a2fbb9ea
ET		 6609{
6610 int n, rc;
6611
6612 /* check gzip header */
94a78b79
VZ		 6613 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6614 BNX2X_ERR("Bad gzip header\n");
a2fbb9ea 6615 return -EINVAL;
94a78b79 6616 }
a2fbb9ea
ET		 6617
6618 n = 10;
6619
34f80b04 6620#define FNAME 0x8
a2fbb9ea
ET		 6621
6622 if (zbuf[3] & FNAME)
6623 while ((zbuf[n++] != 0) && (n < len));
6624
94a78b79 6625 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
a2fbb9ea
ET		 6626 bp->strm->avail_in = len - n;
6627 bp->strm->next_out = bp->gunzip_buf;
6628 bp->strm->avail_out = FW_BUF_SIZE;
6629
6630 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6631 if (rc != Z_OK)
6632 return rc;
6633
6634 rc = zlib_inflate(bp->strm, Z_FINISH);
6635 if ((rc != Z_OK) && (rc != Z_STREAM_END))
7995c64e
JP		 6636 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6637 bp->strm->msg);
a2fbb9ea
ET		 6638
6639 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6640 if (bp->gunzip_outlen & 0x3)
51c1a580
MS		 6641 netdev_err(bp->dev,
6642 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
cdaa7cb8 6643 bp->gunzip_outlen);
a2fbb9ea
ET		 6644 bp->gunzip_outlen >>= 2;
6645
6646 zlib_inflateEnd(bp->strm);
6647
6648 if (rc == Z_STREAM_END)
6649 return 0;
6650
6651 return rc;
6652}
6653
6654/* nic load/unload */
6655
6656/*
34f80b04 6657 * General service functions
a2fbb9ea
ET		 6658 */
6659
6660/* send a NIG loopback debug packet */
6661static void bnx2x_lb_pckt(struct bnx2x *bp)
6662{
a2fbb9ea 6663 u32 wb_write[3];
a2fbb9ea
ET		 6664
6665 /* Ethernet source and destination addresses */
a2fbb9ea
ET		 6666 wb_write[0] = 0x55555555;
6667 wb_write[1] = 0x55555555;
34f80b04 6668 wb_write[2] = 0x20; /* SOP */
a2fbb9ea 6669 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6670
6671 /* NON-IP protocol */
a2fbb9ea
ET		 6672 wb_write[0] = 0x09000000;
6673 wb_write[1] = 0x55555555;
34f80b04 6674 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
a2fbb9ea 6675 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
a2fbb9ea
ET		 6676}
6677
6678/* some of the internal memories
6679 * are not directly readable from the driver
6680 * to test them we send debug packets
6681 */
6682static int bnx2x_int_mem_test(struct bnx2x *bp)
6683{
6684 int factor;
6685 int count, i;
6686 u32 val = 0;
6687
ad8d3948 6688 if (CHIP_REV_IS_FPGA(bp))
a2fbb9ea 6689 factor = 120;
ad8d3948
EG		 6690 else if (CHIP_REV_IS_EMUL(bp))
6691 factor = 200;
6692 else
a2fbb9ea 6693 factor = 1;
a2fbb9ea 6694
a2fbb9ea
ET		 6695 /* Disable inputs of parser neighbor blocks */
6696 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6697 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6698 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6699 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6700
6701 /* Write 0 to parser credits for CFC search request */
6702 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6703
6704 /* send Ethernet packet */
6705 bnx2x_lb_pckt(bp);
6706
6707 /* TODO do i reset NIG statistic? */
6708 /* Wait until NIG register shows 1 packet of size 0x10 */
6709 count = 1000 * factor;
6710 while (count) {
34f80b04 6711
a2fbb9ea
ET		 6712 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6713 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6714 if (val == 0x10)
6715 break;
6716
639d65b8 6717 usleep_range(10000, 20000);
a2fbb9ea
ET		 6718 count--;
6719 }
6720 if (val != 0x10) {
6721 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6722 return -1;
6723 }
6724
6725 /* Wait until PRS register shows 1 packet */
6726 count = 1000 * factor;
6727 while (count) {
6728 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
a2fbb9ea
ET		 6729 if (val == 1)
6730 break;
6731
639d65b8 6732 usleep_range(10000, 20000);
a2fbb9ea
ET		 6733 count--;
6734 }
6735 if (val != 0x1) {
6736 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6737 return -2;
6738 }
6739
6740 /* Reset and init BRB, PRS */
34f80b04 6741 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
a2fbb9ea 6742 msleep(50);
34f80b04 6743 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
a2fbb9ea 6744 msleep(50);
619c5cb6
VZ		 6745 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6746 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
a2fbb9ea
ET		 6747
6748 DP(NETIF_MSG_HW, "part2\n");
6749
6750 /* Disable inputs of parser neighbor blocks */
6751 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6752 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6753 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
3196a88a 6754 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
a2fbb9ea
ET		 6755
6756 /* Write 0 to parser credits for CFC search request */
6757 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6758
6759 /* send 10 Ethernet packets */
6760 for (i = 0; i < 10; i++)
6761 bnx2x_lb_pckt(bp);
6762
6763 /* Wait until NIG register shows 10 + 1
6764 packets of size 11*0x10 = 0xb0 */
6765 count = 1000 * factor;
6766 while (count) {
34f80b04 6767
a2fbb9ea
ET		 6768 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6769 val = *bnx2x_sp(bp, wb_data[0]);
a2fbb9ea
ET		 6770 if (val == 0xb0)
6771 break;
6772
639d65b8 6773 usleep_range(10000, 20000);
a2fbb9ea
ET		 6774 count--;
6775 }
6776 if (val != 0xb0) {
6777 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6778 return -3;
6779 }
6780
6781 /* Wait until PRS register shows 2 packets */
6782 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6783 if (val != 2)
6784 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6785
6786 /* Write 1 to parser credits for CFC search request */
6787 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6788
6789 /* Wait until PRS register shows 3 packets */
6790 msleep(10 * factor);
6791 /* Wait until NIG register shows 1 packet of size 0x10 */
6792 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6793 if (val != 3)
6794 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6795
6796 /* clear NIG EOP FIFO */
6797 for (i = 0; i < 11; i++)
6798 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6799 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6800 if (val != 1) {
6801 BNX2X_ERR("clear of NIG failed\n");
6802 return -4;
6803 }
6804
6805 /* Reset and init BRB, PRS, NIG */
6806 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6807 msleep(50);
6808 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6809 msleep(50);
619c5cb6
VZ		 6810 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6811 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
55c11941
MS		 6812 if (!CNIC_SUPPORT(bp))
6813 /* set NIC mode */
6814 REG_WR(bp, PRS_REG_NIC_MODE, 1);
a2fbb9ea
ET		 6815
6816 /* Enable inputs of parser neighbor blocks */
6817 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6818 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6819 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
3196a88a 6820 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
a2fbb9ea
ET		 6821
6822 DP(NETIF_MSG_HW, "done\n");
6823
6824 return 0; /* OK */
6825}
6826
4a33bc03 6827static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
a2fbb9ea 6828{
b343d002
YM		 6829 u32 val;
6830
a2fbb9ea 6831 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
619c5cb6 6832 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 6833 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6834 else
6835 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
a2fbb9ea
ET		 6836 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6837 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
f2e0899f
DK		 6838 /*
6839 * mask read length error interrupts in brb for parser
6840 * (parsing unit and 'checksum and crc' unit)
6841 * these errors are legal (PU reads fixed length and CAC can cause
6842 * read length error on truncated packets)
6843 */
6844 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
a2fbb9ea
ET		 6845 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6846 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6847 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6848 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6849 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
34f80b04
EG		 6850/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6851/* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6852 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6853 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6854 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
34f80b04
EG		 6855/* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6856/* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
a2fbb9ea
ET		 6857 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6858 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6859 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6860 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
34f80b04
EG		 6861/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6862/* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
f85582f8 6863
b343d002
YM		 6864 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6865 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6866 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6867 if (!CHIP_IS_E1x(bp))
6868 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6869 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6870 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6871
a2fbb9ea
ET		 6872 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6873 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6874 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
34f80b04 6875/* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
619c5cb6
VZ		 6876
6877 if (!CHIP_IS_E1x(bp))
6878 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6879 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6880
a2fbb9ea
ET		 6881 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6882 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
34f80b04 6883/* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4a33bc03 6884 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
a2fbb9ea
ET		 6885}
6886
81f75bbf
EG		 6887static void bnx2x_reset_common(struct bnx2x *bp)
6888{
619c5cb6
VZ		 6889 u32 val = 0x1400;
6890
81f75bbf
EG		 6891 /* reset_common */
6892 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6893 0xd3ffff7f);
619c5cb6
VZ		 6894
6895 if (CHIP_IS_E3(bp)) {
6896 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6897 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6898 }
6899
6900 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6901}
6902
6903static void bnx2x_setup_dmae(struct bnx2x *bp)
6904{
6905 bp->dmae_ready = 0;
6906 spin_lock_init(&bp->dmae_lock);
81f75bbf
EG		 6907}
6908
573f2035
EG		 6909static void bnx2x_init_pxp(struct bnx2x *bp)
6910{
6911 u16 devctl;
6912 int r_order, w_order;
6913
2a80eebc 6914 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
573f2035
EG		 6915 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6916 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6917 if (bp->mrrs == -1)
6918 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6919 else {
6920 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6921 r_order = bp->mrrs;
6922 }
6923
6924 bnx2x_init_pxp_arb(bp, r_order, w_order);
6925}
fd4ef40d
EG		 6926
6927static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6928{
2145a920 6929 int is_required;
fd4ef40d 6930 u32 val;
2145a920 6931 int port;
fd4ef40d 6932
2145a920
VZ		 6933 if (BP_NOMCP(bp))
6934 return;
6935
6936 is_required = 0;
fd4ef40d
EG		 6937 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6938 SHARED_HW_CFG_FAN_FAILURE_MASK;
6939
6940 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6941 is_required = 1;
6942
6943 /*
6944 * The fan failure mechanism is usually related to the PHY type since
6945 * the power consumption of the board is affected by the PHY. Currently,
6946 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6947 */
6948 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6949 for (port = PORT_0; port < PORT_MAX; port++) {
fd4ef40d 6950 is_required |=
d90d96ba
YR		 6951 bnx2x_fan_failure_det_req(
6952 bp,
6953 bp->common.shmem_base,
a22f0788 6954 bp->common.shmem2_base,
d90d96ba 6955 port);
fd4ef40d
EG		 6956 }
6957
6958 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6959
6960 if (is_required == 0)
6961 return;
6962
6963 /* Fan failure is indicated by SPIO 5 */
d6d99a3f 6964 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
fd4ef40d
EG		 6965
6966 /* set to active low mode */
6967 val = REG_RD(bp, MISC_REG_SPIO_INT);
d6d99a3f 6968 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
fd4ef40d
EG		 6969 REG_WR(bp, MISC_REG_SPIO_INT, val);
6970
6971 /* enable interrupt to signal the IGU */
6972 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 6973 val |= MISC_SPIO_SPIO5;
fd4ef40d
EG		 6974 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6975}
6976
c9ee9206 6977void bnx2x_pf_disable(struct bnx2x *bp)
f2e0899f
DK		 6978{
6979 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6980 val &= ~IGU_PF_CONF_FUNC_EN;
6981
6982 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6983 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6984 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6985}
6986
1191cb83 6987static void bnx2x__common_init_phy(struct bnx2x *bp)
619c5cb6
VZ		 6988{
6989 u32 shmem_base[2], shmem2_base[2];
b884d95b
YR		 6990 /* Avoid common init in case MFW supports LFA */
6991 if (SHMEM2_RD(bp, size) >
6992 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6993 return;
619c5cb6
VZ		 6994 shmem_base[0] = bp->common.shmem_base;
6995 shmem2_base[0] = bp->common.shmem2_base;
6996 if (!CHIP_IS_E1x(bp)) {
6997 shmem_base[1] =
6998 SHMEM2_RD(bp, other_shmem_base_addr);
6999 shmem2_base[1] =
7000 SHMEM2_RD(bp, other_shmem2_base_addr);
7001 }
7002 bnx2x_acquire_phy_lock(bp);
7003 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
7004 bp->common.chip_id);
7005 bnx2x_release_phy_lock(bp);
7006}
7007
04860eb7
MC		 7008static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
7009{
7010 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
7011 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
7012 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
7013 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
7014 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
7015
7016 /* make sure this value is 0 */
7017 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
7018
7019 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
7020 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
7021 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
7022 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
7023}
7024
7025static void bnx2x_set_endianity(struct bnx2x *bp)
7026{
7027#ifdef __BIG_ENDIAN
7028 bnx2x_config_endianity(bp, 1);
7029#else
7030 bnx2x_config_endianity(bp, 0);
7031#endif
7032}
7033
7034static void bnx2x_reset_endianity(struct bnx2x *bp)
7035{
7036 bnx2x_config_endianity(bp, 0);
7037}
7038
619c5cb6
VZ		 7039/**
7040 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7041 *
7042 * @bp: driver handle
7043 */
7044static int bnx2x_init_hw_common(struct bnx2x *bp)
a2fbb9ea 7045{
619c5cb6 7046 u32 val;
a2fbb9ea 7047
51c1a580 7048 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
a2fbb9ea 7049
2031bd3a 7050 /*
2de67439 7051 * take the RESET lock to protect undi_unload flow from accessing
2031bd3a
DK		 7052 * registers while we're resetting the chip
7053 */
7a06a122 7054 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7055
81f75bbf 7056 bnx2x_reset_common(bp);
34f80b04 7057 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
a2fbb9ea 7058
619c5cb6
VZ		 7059 val = 0xfffc;
7060 if (CHIP_IS_E3(bp)) {
7061 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7062 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7063 }
7064 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7065
7a06a122 7066 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
2031bd3a 7067
619c5cb6 7068 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
a2fbb9ea 7069
619c5cb6
VZ		 7070 if (!CHIP_IS_E1x(bp)) {
7071 u8 abs_func_id;
f2e0899f
DK		 7072
7073 /**
7074 * 4-port mode or 2-port mode we need to turn of master-enable
7075 * for everyone, after that, turn it back on for self.
7076 * so, we disregard multi-function or not, and always disable
7077 * for all functions on the given path, this means 0,2,4,6 for
7078 * path 0 and 1,3,5,7 for path 1
7079 */
619c5cb6
VZ		 7080 for (abs_func_id = BP_PATH(bp);
7081 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7082 if (abs_func_id == BP_ABS_FUNC(bp)) {
f2e0899f
DK		 7083 REG_WR(bp,
7084 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7085 1);
7086 continue;
7087 }
7088
619c5cb6 7089 bnx2x_pretend_func(bp, abs_func_id);
f2e0899f
DK		 7090 /* clear pf enable */
7091 bnx2x_pf_disable(bp);
7092 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7093 }
7094 }
a2fbb9ea 7095
619c5cb6 7096 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
34f80b04
EG		 7097 if (CHIP_IS_E1(bp)) {
7098 /* enable HW interrupt from PXP on USDM overflow
7099 bit 16 on INT_MASK_0 */
7100 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7101 }
a2fbb9ea 7102
619c5cb6 7103 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
34f80b04 7104 bnx2x_init_pxp(bp);
04860eb7 7105 bnx2x_set_endianity(bp);
523224a3
DK		 7106 bnx2x_ilt_init_page_size(bp, INITOP_SET);
7107
34f80b04
EG		 7108 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7109 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
a2fbb9ea 7110
34f80b04
EG		 7111 /* let the HW do it's magic ... */
7112 msleep(100);
7113 /* finish PXP init */
7114 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7115 if (val != 1) {
7116 BNX2X_ERR("PXP2 CFG failed\n");
7117 return -EBUSY;
7118 }
7119 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7120 if (val != 1) {
7121 BNX2X_ERR("PXP2 RD_INIT failed\n");
7122 return -EBUSY;
7123 }
a2fbb9ea 7124
f2e0899f
DK		 7125 /* Timers bug workaround E2 only. We need to set the entire ILT to
7126 * have entries with value "0" and valid bit on.
7127 * This needs to be done by the first PF that is loaded in a path
7128 * (i.e. common phase)
7129 */
619c5cb6
VZ		 7130 if (!CHIP_IS_E1x(bp)) {
7131/* In E2 there is a bug in the timers block that can cause function 6 / 7
7132 * (i.e. vnic3) to start even if it is marked as "scan-off".
7133 * This occurs when a different function (func2,3) is being marked
7134 * as "scan-off". Real-life scenario for example: if a driver is being
7135 * load-unloaded while func6,7 are down. This will cause the timer to access
7136 * the ilt, translate to a logical address and send a request to read/write.
7137 * Since the ilt for the function that is down is not valid, this will cause
7138 * a translation error which is unrecoverable.
7139 * The Workaround is intended to make sure that when this happens nothing fatal
7140 * will occur. The workaround:
7141 * 1. First PF driver which loads on a path will:
7142 * a. After taking the chip out of reset, by using pretend,
7143 * it will write "0" to the following registers of
7144 * the other vnics.
7145 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7146 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7147 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7148 * And for itself it will write '1' to
7149 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7150 * dmae-operations (writing to pram for example.)
7151 * note: can be done for only function 6,7 but cleaner this
7152 * way.
7153 * b. Write zero+valid to the entire ILT.
7154 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7155 * VNIC3 (of that port). The range allocated will be the
7156 * entire ILT. This is needed to prevent ILT range error.
7157 * 2. Any PF driver load flow:
7158 * a. ILT update with the physical addresses of the allocated
7159 * logical pages.
7160 * b. Wait 20msec. - note that this timeout is needed to make
7161 * sure there are no requests in one of the PXP internal
7162 * queues with "old" ILT addresses.
7163 * c. PF enable in the PGLC.
7164 * d. Clear the was_error of the PF in the PGLC. (could have
2de67439 7165 * occurred while driver was down)
619c5cb6
VZ		 7166 * e. PF enable in the CFC (WEAK + STRONG)
7167 * f. Timers scan enable
7168 * 3. PF driver unload flow:
7169 * a. Clear the Timers scan_en.
7170 * b. Polling for scan_on=0 for that PF.
7171 * c. Clear the PF enable bit in the PXP.
7172 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7173 * e. Write zero+valid to all ILT entries (The valid bit must
7174 * stay set)
7175 * f. If this is VNIC 3 of a port then also init
7176 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16a5fd92 7177 * to the last entry in the ILT.
619c5cb6
VZ		 7178 *
7179 * Notes:
7180 * Currently the PF error in the PGLC is non recoverable.
7181 * In the future the there will be a recovery routine for this error.
7182 * Currently attention is masked.
7183 * Having an MCP lock on the load/unload process does not guarantee that
7184 * there is no Timer disable during Func6/7 enable. This is because the
7185 * Timers scan is currently being cleared by the MCP on FLR.
7186 * Step 2.d can be done only for PF6/7 and the driver can also check if
7187 * there is error before clearing it. But the flow above is simpler and
7188 * more general.
7189 * All ILT entries are written by zero+valid and not just PF6/7
7190 * ILT entries since in the future the ILT entries allocation for
7191 * PF-s might be dynamic.
7192 */
f2e0899f
DK		 7193 struct ilt_client_info ilt_cli;
7194 struct bnx2x_ilt ilt;
7195 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7196 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7197
b595076a 7198 /* initialize dummy TM client */
f2e0899f
DK		 7199 ilt_cli.start = 0;
7200 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7201 ilt_cli.client_num = ILT_CLIENT_TM;
7202
7203 /* Step 1: set zeroes to all ilt page entries with valid bit on
7204 * Step 2: set the timers first/last ilt entry to point
7205 * to the entire range to prevent ILT range error for 3rd/4th
2de67439 7206 * vnic (this code assumes existence of the vnic)
f2e0899f
DK		 7207 *
7208 * both steps performed by call to bnx2x_ilt_client_init_op()
7209 * with dummy TM client
7210 *
7211 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7212 * and his brother are split registers
7213 */
7214 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7215 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7216 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7217
7218 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7219 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7220 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7221 }
7222
34f80b04
EG		 7223 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7224 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
a2fbb9ea 7225
619c5cb6 7226 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7227 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7228 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
619c5cb6 7229 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
f2e0899f 7230
619c5cb6 7231 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
f2e0899f
DK		 7232
7233 /* let the HW do it's magic ... */
7234 do {
7235 msleep(200);
7236 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7237 } while (factor-- && (val != 1));
7238
7239 if (val != 1) {
7240 BNX2X_ERR("ATC_INIT failed\n");
7241 return -EBUSY;
7242 }
7243 }
7244
619c5cb6 7245 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
a2fbb9ea 7246
b56e9670
AE		 7247 bnx2x_iov_init_dmae(bp);
7248
34f80b04
EG		 7249 /* clean the DMAE memory */
7250 bp->dmae_ready = 1;
619c5cb6
VZ		 7251 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7252
7253 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7254
7255 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7256
7257 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
a2fbb9ea 7258
619c5cb6 7259 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
a2fbb9ea 7260
34f80b04
EG		 7261 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7262 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7263 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7264 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7265
619c5cb6 7266 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
37b091ba 7267
523224a3
DK		 7268 /* QM queues pointers table */
7269 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7270
34f80b04
EG		 7271 /* soft reset pulse */
7272 REG_WR(bp, QM_REG_SOFT_RESET, 1);
7273 REG_WR(bp, QM_REG_SOFT_RESET, 0);
a2fbb9ea 7274
55c11941
MS		 7275 if (CNIC_SUPPORT(bp))
7276 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
a2fbb9ea 7277
619c5cb6 7278 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
b9871bcf 7279
619c5cb6 7280 if (!CHIP_REV_IS_SLOW(bp))
34f80b04
EG		 7281 /* enable hw interrupt from doorbell Q */
7282 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
a2fbb9ea 7283
619c5cb6 7284 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
f2e0899f 7285
619c5cb6 7286 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
26c8fa4d 7287 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
619c5cb6 7288
f2e0899f 7289 if (!CHIP_IS_E1(bp))
619c5cb6 7290 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
f85582f8 7291
a3348722
BW		 7292 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7293 if (IS_MF_AFEX(bp)) {
7294 /* configure that VNTag and VLAN headers must be
7295 * received in afex mode
7296 */
7297 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7298 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7299 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7300 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7301 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7302 } else {
7303 /* Bit-map indicating which L2 hdrs may appear
7304 * after the basic Ethernet header
7305 */
7306 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7307 bp->path_has_ovlan ? 7 : 6);
7308 }
7309 }
a2fbb9ea 7310
619c5cb6
VZ		 7311 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7312 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7313 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7314 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
a2fbb9ea 7315
619c5cb6
VZ		 7316 if (!CHIP_IS_E1x(bp)) {
7317 /* reset VFC memories */
7318 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7319 VFC_MEMORIES_RST_REG_CAM_RST |
7320 VFC_MEMORIES_RST_REG_RAM_RST);
7321 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7322 VFC_MEMORIES_RST_REG_CAM_RST |
7323 VFC_MEMORIES_RST_REG_RAM_RST);
a2fbb9ea 7324
619c5cb6
VZ		 7325 msleep(20);
7326 }
a2fbb9ea 7327
619c5cb6
VZ		 7328 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7329 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7330 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7331 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
f2e0899f 7332
34f80b04
EG		 7333 /* sync semi rtc */
7334 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7335 0x80000000);
7336 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7337 0x80000000);
a2fbb9ea 7338
619c5cb6
VZ		 7339 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7340 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7341 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
a2fbb9ea 7342
a3348722
BW		 7343 if (!CHIP_IS_E1x(bp)) {
7344 if (IS_MF_AFEX(bp)) {
7345 /* configure that VNTag and VLAN headers must be
7346 * sent in afex mode
7347 */
7348 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7349 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7350 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7351 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7352 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7353 } else {
7354 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7355 bp->path_has_ovlan ? 7 : 6);
7356 }
7357 }
f2e0899f 7358
34f80b04 7359 REG_WR(bp, SRC_REG_SOFT_RST, 1);
f85582f8 7360
619c5cb6
VZ		 7361 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7362
55c11941
MS		 7363 if (CNIC_SUPPORT(bp)) {
7364 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7365 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7366 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7367 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7368 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7369 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7370 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7371 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7372 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7373 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7374 }
34f80b04 7375 REG_WR(bp, SRC_REG_SOFT_RST, 0);
a2fbb9ea 7376
34f80b04
EG		 7377 if (sizeof(union cdu_context) != 1024)
7378 /* we currently assume that a context is 1024 bytes */
51c1a580
MS		 7379 dev_alert(&bp->pdev->dev,
7380 "please adjust the size of cdu_context(%ld)\n",
7381 (long)sizeof(union cdu_context));
a2fbb9ea 7382
619c5cb6 7383 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
34f80b04
EG		 7384 val = (4 << 24) + (0 << 12) + 1024;
7385 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
a2fbb9ea 7386
619c5cb6 7387 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
34f80b04 7388 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
8d9c5f34
EG		 7389 /* enable context validation interrupt from CFC */
7390 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7391
7392 /* set the thresholds to prevent CFC/CDU race */
7393 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
a2fbb9ea 7394
619c5cb6 7395 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
f2e0899f 7396
619c5cb6 7397 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
f2e0899f
DK		 7398 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7399
619c5cb6
VZ		 7400 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7401 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
a2fbb9ea 7402
34f80b04
EG		 7403 /* Reset PCIE errors for debug */
7404 REG_WR(bp, 0x2814, 0xffffffff);
7405 REG_WR(bp, 0x3820, 0xffffffff);
a2fbb9ea 7406
619c5cb6 7407 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7408 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7409 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7410 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7411 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7412 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7413 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7414 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7415 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7416 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7417 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7418 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7419 }
7420
619c5cb6 7421 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
f2e0899f 7422 if (!CHIP_IS_E1(bp)) {
619c5cb6
VZ		 7423 /* in E3 this done in per-port section */
7424 if (!CHIP_IS_E3(bp))
7425 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
f2e0899f 7426 }
619c5cb6
VZ		 7427 if (CHIP_IS_E1H(bp))
7428 /* not applicable for E2 (and above ...) */
7429 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
34f80b04
EG		 7430
7431 if (CHIP_REV_IS_SLOW(bp))
7432 msleep(200);
7433
7434 /* finish CFC init */
7435 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7436 if (val != 1) {
7437 BNX2X_ERR("CFC LL_INIT failed\n");
7438 return -EBUSY;
7439 }
7440 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7441 if (val != 1) {
7442 BNX2X_ERR("CFC AC_INIT failed\n");
7443 return -EBUSY;
7444 }
7445 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7446 if (val != 1) {
7447 BNX2X_ERR("CFC CAM_INIT failed\n");
7448 return -EBUSY;
7449 }
7450 REG_WR(bp, CFC_REG_DEBUG0, 0);
f1410647 7451
f2e0899f
DK		 7452 if (CHIP_IS_E1(bp)) {
7453 /* read NIG statistic
7454 to see if this is our first up since powerup */
7455 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7456 val = *bnx2x_sp(bp, wb_data[0]);
34f80b04 7457
f2e0899f
DK		 7458 /* do internal memory self test */
7459 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7460 BNX2X_ERR("internal mem self test failed\n");
7461 return -EBUSY;
7462 }
34f80b04
EG		 7463 }
7464
fd4ef40d
EG		 7465 bnx2x_setup_fan_failure_detection(bp);
7466
34f80b04
EG		 7467 /* clear PXP2 attentions */
7468 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
a2fbb9ea 7469
4a33bc03 7470 bnx2x_enable_blocks_attention(bp);
c9ee9206 7471 bnx2x_enable_blocks_parity(bp);
a2fbb9ea 7472
6bbca910 7473 if (!BP_NOMCP(bp)) {
619c5cb6
VZ		 7474 if (CHIP_IS_E1x(bp))
7475 bnx2x__common_init_phy(bp);
6bbca910
YR		 7476 } else
7477 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7478
230d00eb
YM		 7479 if (SHMEM2_HAS(bp, netproc_fw_ver))
7480 SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
7481
34f80b04
EG		 7482 return 0;
7483}
a2fbb9ea 7484
619c5cb6
VZ		 7485/**
7486 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7487 *
7488 * @bp: driver handle
7489 */
7490static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7491{
7492 int rc = bnx2x_init_hw_common(bp);
7493
7494 if (rc)
7495 return rc;
7496
7497 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7498 if (!BP_NOMCP(bp))
7499 bnx2x__common_init_phy(bp);
7500
7501 return 0;
7502}
7503
523224a3 7504static int bnx2x_init_hw_port(struct bnx2x *bp)
34f80b04
EG		 7505{
7506 int port = BP_PORT(bp);
619c5cb6 7507 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
1c06328c 7508 u32 low, high;
4293b9f5 7509 u32 val, reg;
a2fbb9ea 7510
51c1a580 7511 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
34f80b04
EG		 7512
7513 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
a2fbb9ea 7514
619c5cb6
VZ		 7515 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7516 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7517 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
ca00392c 7518
f2e0899f
DK		 7519 /* Timers bug workaround: disables the pf_master bit in pglue at
7520 * common phase, we need to enable it here before any dmae access are
7521 * attempted. Therefore we manually added the enable-master to the
7522 * port phase (it also happens in the function phase)
7523 */
619c5cb6 7524 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 7525 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7526
619c5cb6
VZ		 7527 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7528 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7529 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7530 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7531
7532 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7533 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7534 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7535 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
a2fbb9ea 7536
523224a3
DK		 7537 /* QM cid (connection) count */
7538 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
a2fbb9ea 7539
55c11941
MS		 7540 if (CNIC_SUPPORT(bp)) {
7541 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7542 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7543 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7544 }
cdaa7cb8 7545
619c5cb6 7546 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
f2e0899f 7547
2b674047
DK		 7548 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7549
f2e0899f 7550 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
619c5cb6
VZ		 7551
7552 if (IS_MF(bp))
7553 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7554 else if (bp->dev->mtu > 4096) {
7555 if (bp->flags & ONE_PORT_FLAG)
7556 low = 160;
7557 else {
7558 val = bp->dev->mtu;
7559 /* (24*1024 + val*4)/256 */
7560 low = 96 + (val/64) +
7561 ((val % 64) ? 1 : 0);
7562 }
7563 } else
7564 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7565 high = low + 56; /* 14*1024/256 */
f2e0899f
DK		 7566 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7567 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
1c06328c 7568 }
1c06328c 7569
619c5cb6
VZ		 7570 if (CHIP_MODE_IS_4_PORT(bp))
7571 REG_WR(bp, (BP_PORT(bp) ?
7572 BRB1_REG_MAC_GUARANTIED_1 :
7573 BRB1_REG_MAC_GUARANTIED_0), 40);
1c06328c 7574
619c5cb6 7575 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
a3348722
BW		 7576 if (CHIP_IS_E3B0(bp)) {
7577 if (IS_MF_AFEX(bp)) {
7578 /* configure headers for AFEX mode */
7579 REG_WR(bp, BP_PORT(bp) ?
7580 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7581 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7582 REG_WR(bp, BP_PORT(bp) ?
7583 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7584 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7585 REG_WR(bp, BP_PORT(bp) ?
7586 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7587 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7588 } else {
7589 /* Ovlan exists only if we are in multi-function +
7590 * switch-dependent mode, in switch-independent there
7591 * is no ovlan headers
7592 */
7593 REG_WR(bp, BP_PORT(bp) ?
7594 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7595 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7596 (bp->path_has_ovlan ? 7 : 6));
7597 }
7598 }
356e2385 7599
619c5cb6
VZ		 7600 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7601 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7602 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7603 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
356e2385 7604
619c5cb6
VZ		 7605 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7606 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7607 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7608 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
34f80b04 7609
619c5cb6
VZ		 7610 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7611 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
a2fbb9ea 7612
619c5cb6
VZ		 7613 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7614
7615 if (CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7616 /* configure PBF to work without PAUSE mtu 9000 */
7617 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
a2fbb9ea 7618
f2e0899f
DK		 7619 /* update threshold */
7620 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7621 /* update init credit */
7622 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
a2fbb9ea 7623
f2e0899f
DK		 7624 /* probe changes */
7625 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7626 udelay(50);
7627 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7628 }
a2fbb9ea 7629
55c11941
MS		 7630 if (CNIC_SUPPORT(bp))
7631 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7632
619c5cb6
VZ		 7633 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7634 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04
EG		 7635
7636 if (CHIP_IS_E1(bp)) {
7637 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7638 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7639 }
619c5cb6 7640 bnx2x_init_block(bp, BLOCK_HC, init_phase);
34f80b04 7641
619c5cb6 7642 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 7643
619c5cb6 7644 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
34f80b04 7645 /* init aeu_mask_attn_func_0/1:
16a5fd92
YM		 7646 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7647 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
34f80b04 7648 * bits 4-7 are used for "per vn group attention" */
e4901dde
VZ		 7649 val = IS_MF(bp) ? 0xF7 : 0x7;
7650 /* Enable DCBX attention for all but E1 */
7651 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7652 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
34f80b04 7653
4293b9f5
DK		 7654 /* SCPAD_PARITY should NOT trigger close the gates */
7655 reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7656 REG_WR(bp, reg,
7657 REG_RD(bp, reg) &
7658 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7659
7660 reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7661 REG_WR(bp, reg,
7662 REG_RD(bp, reg) &
7663 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7664
619c5cb6
VZ		 7665 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7666
7667 if (!CHIP_IS_E1x(bp)) {
7668 /* Bit-map indicating which L2 hdrs may appear after the
7669 * basic Ethernet header
7670 */
a3348722
BW		 7671 if (IS_MF_AFEX(bp))
7672 REG_WR(bp, BP_PORT(bp) ?
7673 NIG_REG_P1_HDRS_AFTER_BASIC :
7674 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7675 else
7676 REG_WR(bp, BP_PORT(bp) ?
7677 NIG_REG_P1_HDRS_AFTER_BASIC :
7678 NIG_REG_P0_HDRS_AFTER_BASIC,
7679 IS_MF_SD(bp) ? 7 : 6);
619c5cb6
VZ		 7680
7681 if (CHIP_IS_E3(bp))
7682 REG_WR(bp, BP_PORT(bp) ?
7683 NIG_REG_LLH1_MF_MODE :
7684 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7685 }
7686 if (!CHIP_IS_E3(bp))
7687 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
34f80b04 7688
f2e0899f 7689 if (!CHIP_IS_E1(bp)) {
fb3bff17 7690 /* 0x2 disable mf_ov, 0x1 enable */
34f80b04 7691 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
0793f83f 7692 (IS_MF_SD(bp) ? 0x1 : 0x2));
34f80b04 7693
619c5cb6 7694 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 7695 val = 0;
7696 switch (bp->mf_mode) {
7697 case MULTI_FUNCTION_SD:
7698 val = 1;
7699 break;
7700 case MULTI_FUNCTION_SI:
a3348722 7701 case MULTI_FUNCTION_AFEX:
f2e0899f
DK		 7702 val = 2;
7703 break;
7704 }
7705
7706 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7707 NIG_REG_LLH0_CLS_TYPE), val);
7708 }
1c06328c
EG		 7709 {
7710 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7711 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7712 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7713 }
34f80b04
EG		 7714 }
7715
619c5cb6
VZ		 7716 /* If SPIO5 is set to generate interrupts, enable it for this port */
7717 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
d6d99a3f 7718 if (val & MISC_SPIO_SPIO5) {
4d295db0
EG		 7719 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7720 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7721 val = REG_RD(bp, reg_addr);
f1410647 7722 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
4d295db0 7723 REG_WR(bp, reg_addr, val);
f1410647 7724 }
a2fbb9ea 7725
34f80b04
EG		 7726 return 0;
7727}
7728
34f80b04
EG		 7729static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7730{
7731 int reg;
32d68de1 7732 u32 wb_write[2];
34f80b04 7733
f2e0899f 7734 if (CHIP_IS_E1(bp))
34f80b04 7735 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
f2e0899f
DK		 7736 else
7737 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
34f80b04 7738
32d68de1
YM		 7739 wb_write[0] = ONCHIP_ADDR1(addr);
7740 wb_write[1] = ONCHIP_ADDR2(addr);
7741 REG_WR_DMAE(bp, reg, wb_write, 2);
34f80b04
EG		 7742}
7743
b56e9670 7744void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
1191cb83
ED		 7745{
7746 u32 data, ctl, cnt = 100;
7747 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7748 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7749 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7750 u32 sb_bit = 1 << (idu_sb_id%32);
b56e9670 7751 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
1191cb83
ED		 7752 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7753
7754 /* Not supported in BC mode */
7755 if (CHIP_INT_MODE_IS_BC(bp))
7756 return;
7757
7758 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7759 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7760 IGU_REGULAR_CLEANUP_SET |
7761 IGU_REGULAR_BCLEANUP;
7762
7763 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7764 func_encode << IGU_CTRL_REG_FID_SHIFT |
7765 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7766
7767 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7768 data, igu_addr_data);
7769 REG_WR(bp, igu_addr_data, data);
7770 mmiowb();
7771 barrier();
7772 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7773 ctl, igu_addr_ctl);
7774 REG_WR(bp, igu_addr_ctl, ctl);
7775 mmiowb();
7776 barrier();
7777
7778 /* wait for clean up to finish */
7779 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7780 msleep(20);
7781
1191cb83
ED		 7782 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7783 DP(NETIF_MSG_HW,
7784 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7785 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7786 }
7787}
7788
7789static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
f2e0899f 7790{
619c5cb6 7791 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
f2e0899f
DK		 7792}
7793
1191cb83 7794static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
f2e0899f
DK		 7795{
7796 u32 i, base = FUNC_ILT_BASE(func);
7797 for (i = base; i < base + ILT_PER_FUNC; i++)
7798 bnx2x_ilt_wr(bp, i, 0);
7799}
7800
910cc727 7801static void bnx2x_init_searcher(struct bnx2x *bp)
55c11941
MS		 7802{
7803 int port = BP_PORT(bp);
7804 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7805 /* T1 hash bits value determines the T1 number of entries */
7806 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7807}
7808
7809static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7810{
7811 int rc;
7812 struct bnx2x_func_state_params func_params = {NULL};
7813 struct bnx2x_func_switch_update_params *switch_update_params =
7814 &func_params.params.switch_update;
7815
7816 /* Prepare parameters for function state transitions */
7817 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7818 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7819
7820 func_params.f_obj = &bp->func_obj;
7821 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7822
7823 /* Function parameters */
e42780b6
DK		 7824 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7825 &switch_update_params->changes);
7826 if (suspend)
7827 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7828 &switch_update_params->changes);
55c11941
MS		 7829
7830 rc = bnx2x_func_state_change(bp, &func_params);
7831
7832 return rc;
7833}
7834
910cc727 7835static int bnx2x_reset_nic_mode(struct bnx2x *bp)
55c11941
MS		 7836{
7837 int rc, i, port = BP_PORT(bp);
7838 int vlan_en = 0, mac_en[NUM_MACS];
7839
55c11941
MS		 7840 /* Close input from network */
7841 if (bp->mf_mode == SINGLE_FUNCTION) {
7842 bnx2x_set_rx_filter(&bp->link_params, 0);
7843 } else {
7844 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7845 NIG_REG_LLH0_FUNC_EN);
7846 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7847 NIG_REG_LLH0_FUNC_EN, 0);
7848 for (i = 0; i < NUM_MACS; i++) {
7849 mac_en[i] = REG_RD(bp, port ?
7850 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7851 4 * i) :
7852 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7853 4 * i));
7854 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7855 4 * i) :
7856 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7857 }
7858 }
7859
7860 /* Close BMC to host */
7861 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7862 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7863
7864 /* Suspend Tx switching to the PF. Completion of this ramrod
7865 * further guarantees that all the packets of that PF / child
7866 * VFs in BRB were processed by the Parser, so it is safe to
7867 * change the NIC_MODE register.
7868 */
7869 rc = bnx2x_func_switch_update(bp, 1);
7870 if (rc) {
7871 BNX2X_ERR("Can't suspend tx-switching!\n");
7872 return rc;
7873 }
7874
7875 /* Change NIC_MODE register */
7876 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7877
7878 /* Open input from network */
7879 if (bp->mf_mode == SINGLE_FUNCTION) {
7880 bnx2x_set_rx_filter(&bp->link_params, 1);
7881 } else {
7882 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7883 NIG_REG_LLH0_FUNC_EN, vlan_en);
7884 for (i = 0; i < NUM_MACS; i++) {
7885 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7886 4 * i) :
7887 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7888 mac_en[i]);
7889 }
7890 }
7891
7892 /* Enable BMC to host */
7893 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7894 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7895
7896 /* Resume Tx switching to the PF */
7897 rc = bnx2x_func_switch_update(bp, 0);
7898 if (rc) {
7899 BNX2X_ERR("Can't resume tx-switching!\n");
7900 return rc;
7901 }
7902
7903 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7904 return 0;
7905}
7906
7907int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7908{
7909 int rc;
7910
7911 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7912
7913 if (CONFIGURE_NIC_MODE(bp)) {
16a5fd92 7914 /* Configure searcher as part of function hw init */
55c11941
MS		 7915 bnx2x_init_searcher(bp);
7916
7917 /* Reset NIC mode */
7918 rc = bnx2x_reset_nic_mode(bp);
7919 if (rc)
7920 BNX2X_ERR("Can't change NIC mode!\n");
7921 return rc;
7922 }
7923
7924 return 0;
7925}
7926
da254fbc
YM		 7927/* previous driver DMAE transaction may have occurred when pre-boot stage ended
7928 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7929 * the addresses of the transaction, resulting in was-error bit set in the pci
7930 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7931 * to clear the interrupt which detected this from the pglueb and the was done
7932 * bit
7933 */
7934static void bnx2x_clean_pglue_errors(struct bnx2x *bp)
7935{
7936 if (!CHIP_IS_E1x(bp))
7937 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
7938 1 << BP_ABS_FUNC(bp));
7939}
7940
523224a3 7941static int bnx2x_init_hw_func(struct bnx2x *bp)
34f80b04
EG		 7942{
7943 int port = BP_PORT(bp);
7944 int func = BP_FUNC(bp);
619c5cb6 7945 int init_phase = PHASE_PF0 + func;
523224a3
DK		 7946 struct bnx2x_ilt *ilt = BP_ILT(bp);
7947 u16 cdu_ilt_start;
8badd27a 7948 u32 addr, val;
f4a66897 7949 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
89db4ad8 7950 int i, main_mem_width, rc;
34f80b04 7951
51c1a580 7952 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
34f80b04 7953
619c5cb6 7954 /* FLR cleanup - hmmm */
89db4ad8
AE		 7955 if (!CHIP_IS_E1x(bp)) {
7956 rc = bnx2x_pf_flr_clnup(bp);
04c46736
YM		 7957 if (rc) {
7958 bnx2x_fw_dump(bp);
89db4ad8 7959 return rc;
04c46736 7960 }
89db4ad8 7961 }
619c5cb6 7962
8badd27a 7963 /* set MSI reconfigure capability */
f2e0899f
DK		 7964 if (bp->common.int_block == INT_BLOCK_HC) {
7965 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7966 val = REG_RD(bp, addr);
7967 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7968 REG_WR(bp, addr, val);
7969 }
8badd27a 7970
619c5cb6
VZ		 7971 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7972 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7973
523224a3
DK		 7974 ilt = BP_ILT(bp);
7975 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
37b091ba 7976
290ca2bb
AE		 7977 if (IS_SRIOV(bp))
7978 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7979 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7980
7981 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7982 * those of the VFs, so start line should be reset
7983 */
7984 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
523224a3 7985 for (i = 0; i < L2_ILT_LINES(bp); i++) {
a052997e 7986 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
523224a3 7987 ilt->lines[cdu_ilt_start + i].page_mapping =
a052997e
MS		 7988 bp->context[i].cxt_mapping;
7989 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
37b091ba 7990 }
290ca2bb 7991
523224a3 7992 bnx2x_ilt_init_op(bp, INITOP_SET);
f85582f8 7993
55c11941
MS		 7994 if (!CONFIGURE_NIC_MODE(bp)) {
7995 bnx2x_init_searcher(bp);
7996 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7997 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7998 } else {
7999 /* Set NIC mode */
8000 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6bf07b8e 8001 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
55c11941 8002 }
37b091ba 8003
619c5cb6 8004 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8005 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
8006
8007 /* Turn on a single ISR mode in IGU if driver is going to use
8008 * INT#x or MSI
8009 */
8010 if (!(bp->flags & USING_MSIX_FLAG))
8011 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
8012 /*
8013 * Timers workaround bug: function init part.
8014 * Need to wait 20msec after initializing ILT,
8015 * needed to make sure there are no requests in
8016 * one of the PXP internal queues with "old" ILT addresses
8017 */
8018 msleep(20);
8019 /*
8020 * Master enable - Due to WB DMAE writes performed before this
8021 * register is re-initialized as part of the regular function
8022 * init
8023 */
8024 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
8025 /* Enable the function in IGU */
8026 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
8027 }
8028
523224a3 8029 bp->dmae_ready = 1;
34f80b04 8030
619c5cb6 8031 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
523224a3 8032
da254fbc 8033 bnx2x_clean_pglue_errors(bp);
f2e0899f 8034
619c5cb6
VZ		 8035 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
8036 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
8037 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
8038 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
8039 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
8040 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
8041 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
8042 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
8043 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
8044 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
8045 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
8046 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
8047 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
8048
8049 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8050 REG_WR(bp, QM_REG_PF_EN, 1);
8051
619c5cb6
VZ		 8052 if (!CHIP_IS_E1x(bp)) {
8053 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8054 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8055 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8056 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
8057 }
8058 bnx2x_init_block(bp, BLOCK_QM, init_phase);
8059
8060 bnx2x_init_block(bp, BLOCK_TM, init_phase);
8061 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
c19d65c9 8062 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
b56e9670
AE		 8063
8064 bnx2x_iov_init_dq(bp);
8065
619c5cb6
VZ		 8066 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
8067 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
8068 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
8069 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
8070 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
8071 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
8072 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8073 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8074 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8075 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8076 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8077
619c5cb6 8078 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
523224a3 8079
619c5cb6 8080 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
34f80b04 8081
619c5cb6 8082 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 8083 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8084
fb3bff17 8085 if (IS_MF(bp)) {
7609647e
YM		 8086 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8087 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8088 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8089 bp->mf_ov);
8090 }
34f80b04
EG		 8091 }
8092
619c5cb6 8093 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
523224a3 8094
34f80b04 8095 /* HC init per function */
f2e0899f
DK		 8096 if (bp->common.int_block == INT_BLOCK_HC) {
8097 if (CHIP_IS_E1H(bp)) {
8098 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8099
8100 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8101 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8102 }
619c5cb6 8103 bnx2x_init_block(bp, BLOCK_HC, init_phase);
f2e0899f
DK		 8104
8105 } else {
8106 int num_segs, sb_idx, prod_offset;
8107
34f80b04
EG		 8108 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8109
619c5cb6 8110 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8111 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8112 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8113 }
8114
619c5cb6 8115 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
f2e0899f 8116
619c5cb6 8117 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 8118 int dsb_idx = 0;
8119 /**
8120 * Producer memory:
8121 * E2 mode: address 0-135 match to the mapping memory;
8122 * 136 - PF0 default prod; 137 - PF1 default prod;
8123 * 138 - PF2 default prod; 139 - PF3 default prod;
8124 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8125 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8126 * 144-147 reserved.
8127 *
8128 * E1.5 mode - In backward compatible mode;
8129 * for non default SB; each even line in the memory
8130 * holds the U producer and each odd line hold
8131 * the C producer. The first 128 producers are for
8132 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8133 * producers are for the DSB for each PF.
8134 * Each PF has five segments: (the order inside each
8135 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8136 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8137 * 144-147 attn prods;
8138 */
8139 /* non-default-status-blocks */
8140 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8141 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8142 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8143 prod_offset = (bp->igu_base_sb + sb_idx) *
8144 num_segs;
8145
8146 for (i = 0; i < num_segs; i++) {
8147 addr = IGU_REG_PROD_CONS_MEMORY +
8148 (prod_offset + i) * 4;
8149 REG_WR(bp, addr, 0);
8150 }
8151 /* send consumer update with value 0 */
8152 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8153 USTORM_ID, 0, IGU_INT_NOP, 1);
8154 bnx2x_igu_clear_sb(bp,
8155 bp->igu_base_sb + sb_idx);
8156 }
8157
8158 /* default-status-blocks */
8159 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8160 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8161
8162 if (CHIP_MODE_IS_4_PORT(bp))
8163 dsb_idx = BP_FUNC(bp);
8164 else
3395a033 8165 dsb_idx = BP_VN(bp);
f2e0899f
DK		 8166
8167 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8168 IGU_BC_BASE_DSB_PROD + dsb_idx :
8169 IGU_NORM_BASE_DSB_PROD + dsb_idx);
8170
3395a033
DK		 8171 /*
8172 * igu prods come in chunks of E1HVN_MAX (4) -
8173 * does not matters what is the current chip mode
8174 */
f2e0899f
DK		 8175 for (i = 0; i < (num_segs * E1HVN_MAX);
8176 i += E1HVN_MAX) {
8177 addr = IGU_REG_PROD_CONS_MEMORY +
8178 (prod_offset + i)*4;
8179 REG_WR(bp, addr, 0);
8180 }
8181 /* send consumer update with 0 */
8182 if (CHIP_INT_MODE_IS_BC(bp)) {
8183 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8184 USTORM_ID, 0, IGU_INT_NOP, 1);
8185 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8186 CSTORM_ID, 0, IGU_INT_NOP, 1);
8187 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8188 XSTORM_ID, 0, IGU_INT_NOP, 1);
8189 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8190 TSTORM_ID, 0, IGU_INT_NOP, 1);
8191 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8192 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8193 } else {
8194 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8195 USTORM_ID, 0, IGU_INT_NOP, 1);
8196 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8197 ATTENTION_ID, 0, IGU_INT_NOP, 1);
8198 }
8199 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8200
16a5fd92 8201 /* !!! These should become driver const once
f2e0899f
DK		 8202 rf-tool supports split-68 const */
8203 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8204 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8205 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8206 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8207 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8208 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8209 }
34f80b04 8210 }
34f80b04 8211
c14423fe 8212 /* Reset PCIE errors for debug */
a2fbb9ea
ET		 8213 REG_WR(bp, 0x2114, 0xffffffff);
8214 REG_WR(bp, 0x2120, 0xffffffff);
523224a3 8215
f4a66897
VZ		 8216 if (CHIP_IS_E1x(bp)) {
8217 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8218 main_mem_base = HC_REG_MAIN_MEMORY +
8219 BP_PORT(bp) * (main_mem_size * 4);
8220 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8221 main_mem_width = 8;
8222
8223 val = REG_RD(bp, main_mem_prty_clr);
8224 if (val)
51c1a580
MS		 8225 DP(NETIF_MSG_HW,
8226 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8227 val);
f4a66897
VZ		 8228
8229 /* Clear "false" parity errors in MSI-X table */
8230 for (i = main_mem_base;
8231 i < main_mem_base + main_mem_size * 4;
8232 i += main_mem_width) {
8233 bnx2x_read_dmae(bp, i, main_mem_width / 4);
8234 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8235 i, main_mem_width / 4);
8236 }
8237 /* Clear HC parity attention */
8238 REG_RD(bp, main_mem_prty_clr);
8239 }
8240
619c5cb6
VZ		 8241#ifdef BNX2X_STOP_ON_ERROR
8242 /* Enable STORMs SP logging */
8243 REG_WR8(bp, BAR_USTRORM_INTMEM +
8244 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8245 REG_WR8(bp, BAR_TSTRORM_INTMEM +
8246 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8247 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8248 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8249 REG_WR8(bp, BAR_XSTRORM_INTMEM +
8250 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8251#endif
8252
b7737c9b 8253 bnx2x_phy_probe(&bp->link_params);
f85582f8 8254
34f80b04
EG		 8255 return 0;
8256}
8257
55c11941
MS		 8258void bnx2x_free_mem_cnic(struct bnx2x *bp)
8259{
8260 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8261
8262 if (!CHIP_IS_E1x(bp))
8263 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8264 sizeof(struct host_hc_status_block_e2));
8265 else
8266 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8267 sizeof(struct host_hc_status_block_e1x));
8268
8269 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8270}
8271
9f6c9258 8272void bnx2x_free_mem(struct bnx2x *bp)
a2fbb9ea 8273{
a052997e
MS		 8274 int i;
8275
619c5cb6
VZ		 8276 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8277 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8278
b4cddbd6
AE		 8279 if (IS_VF(bp))
8280 return;
8281
8282 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8283 sizeof(struct host_sp_status_block));
8284
a2fbb9ea 8285 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
34f80b04 8286 sizeof(struct bnx2x_slowpath));
a2fbb9ea 8287
a052997e
MS		 8288 for (i = 0; i < L2_ILT_LINES(bp); i++)
8289 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8290 bp->context[i].size);
523224a3
DK		 8291 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8292
8293 BNX2X_FREE(bp->ilt->lines);
f85582f8 8294
7a9b2557 8295 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
a2fbb9ea 8296
523224a3
DK		 8297 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8298 BCM_PAGE_SIZE * NUM_EQ_PAGES);
580d9d08 8299
05952246
YM		 8300 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8301
580d9d08 8302 bnx2x_iov_free_mem(bp);
619c5cb6
VZ		 8303}
8304
55c11941 8305int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
a2fbb9ea 8306{
cd2b0389 8307 if (!CHIP_IS_E1x(bp)) {
619c5cb6 8308 /* size = the status block + ramrod buffers */
cd2b0389
JP		 8309 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8310 sizeof(struct host_hc_status_block_e2));
8311 if (!bp->cnic_sb.e2_sb)
8312 goto alloc_mem_err;
8313 } else {
8314 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8315 sizeof(struct host_hc_status_block_e1x));
8316 if (!bp->cnic_sb.e1x_sb)
8317 goto alloc_mem_err;
8318 }
8badd27a 8319
cd2b0389 8320 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
16a5fd92 8321 /* allocate searcher T2 table, as it wasn't allocated before */
cd2b0389
JP		 8322 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8323 if (!bp->t2)
8324 goto alloc_mem_err;
8325 }
55c11941
MS		 8326
8327 /* write address to which L5 should insert its values */
8328 bp->cnic_eth_dev.addr_drv_info_to_mcp =
8329 &bp->slowpath->drv_info_to_mcp;
8330
8331 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8332 goto alloc_mem_err;
8333
8334 return 0;
8335
8336alloc_mem_err:
8337 bnx2x_free_mem_cnic(bp);
8338 BNX2X_ERR("Can't allocate memory\n");
8339 return -ENOMEM;
8340}
8341
8342int bnx2x_alloc_mem(struct bnx2x *bp)
8343{
8344 int i, allocated, context_size;
a2fbb9ea 8345
cd2b0389 8346 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
55c11941 8347 /* allocate searcher T2 table */
cd2b0389
JP		 8348 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8349 if (!bp->t2)
8350 goto alloc_mem_err;
8351 }
8badd27a 8352
cd2b0389
JP		 8353 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8354 sizeof(struct host_sp_status_block));
8355 if (!bp->def_status_blk)
8356 goto alloc_mem_err;
a2fbb9ea 8357
cd2b0389
JP		 8358 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8359 sizeof(struct bnx2x_slowpath));
8360 if (!bp->slowpath)
8361 goto alloc_mem_err;
a2fbb9ea 8362
a052997e
MS		 8363 /* Allocate memory for CDU context:
8364 * This memory is allocated separately and not in the generic ILT
8365 * functions because CDU differs in few aspects:
8366 * 1. There are multiple entities allocating memory for context -
8367 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8368 * its own ILT lines.
8369 * 2. Since CDU page-size is not a single 4KB page (which is the case
8370 * for the other ILT clients), to be efficient we want to support
8371 * allocation of sub-page-size in the last entry.
8372 * 3. Context pointers are used by the driver to pass to FW / update
8373 * the context (for the other ILT clients the pointers are used just to
8374 * free the memory during unload).
8375 */
8376 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
65abd74d 8377
a052997e
MS		 8378 for (i = 0, allocated = 0; allocated < context_size; i++) {
8379 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8380 (context_size - allocated));
cd2b0389
JP		 8381 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8382 bp->context[i].size);
8383 if (!bp->context[i].vcxt)
8384 goto alloc_mem_err;
a052997e
MS		 8385 allocated += bp->context[i].size;
8386 }
cd2b0389
JP		 8387 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8388 GFP_KERNEL);
8389 if (!bp->ilt->lines)
8390 goto alloc_mem_err;
65abd74d 8391
523224a3
DK		 8392 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8393 goto alloc_mem_err;
65abd74d 8394
67c431a5
AE		 8395 if (bnx2x_iov_alloc_mem(bp))
8396 goto alloc_mem_err;
8397
9f6c9258 8398 /* Slow path ring */
cd2b0389
JP		 8399 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8400 if (!bp->spq)
8401 goto alloc_mem_err;
65abd74d 8402
523224a3 8403 /* EQ */
cd2b0389
JP		 8404 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8405 BCM_PAGE_SIZE * NUM_EQ_PAGES);
8406 if (!bp->eq_ring)
8407 goto alloc_mem_err;
ab532cf3 8408
9f6c9258 8409 return 0;
e1510706 8410
9f6c9258
DK		 8411alloc_mem_err:
8412 bnx2x_free_mem(bp);
51c1a580 8413 BNX2X_ERR("Can't allocate memory\n");
9f6c9258 8414 return -ENOMEM;
65abd74d
YG		 8415}
8416
a2fbb9ea
ET		 8417/*
8418 * Init service functions
8419 */
a2fbb9ea 8420
619c5cb6
VZ		 8421int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8422 struct bnx2x_vlan_mac_obj *obj, bool set,
8423 int mac_type, unsigned long *ramrod_flags)
a2fbb9ea 8424{
619c5cb6
VZ		 8425 int rc;
8426 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
a2fbb9ea 8427
619c5cb6 8428 memset(&ramrod_param, 0, sizeof(ramrod_param));
a2fbb9ea 8429
619c5cb6
VZ		 8430 /* Fill general parameters */
8431 ramrod_param.vlan_mac_obj = obj;
8432 ramrod_param.ramrod_flags = *ramrod_flags;
a2fbb9ea 8433
619c5cb6
VZ		 8434 /* Fill a user request section if needed */
8435 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8436 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
a2fbb9ea 8437
619c5cb6 8438 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
e3553b29 8439
619c5cb6
VZ		 8440 /* Set the command: ADD or DEL */
8441 if (set)
8442 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8443 else
8444 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
a2fbb9ea
ET		 8445 }
8446
619c5cb6 8447 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7b5342d9
YM		 8448
8449 if (rc == -EEXIST) {
8450 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8451 /* do not treat adding same MAC as error */
8452 rc = 0;
8453 } else if (rc < 0)
619c5cb6 8454 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7b5342d9 8455
619c5cb6 8456 return rc;
a2fbb9ea
ET		 8457}
8458
05cc5a39
YM		 8459int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
8460 struct bnx2x_vlan_mac_obj *obj, bool set,
8461 unsigned long *ramrod_flags)
8462{
8463 int rc;
8464 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8465
8466 memset(&ramrod_param, 0, sizeof(ramrod_param));
8467
8468 /* Fill general parameters */
8469 ramrod_param.vlan_mac_obj = obj;
8470 ramrod_param.ramrod_flags = *ramrod_flags;
8471
8472 /* Fill a user request section if needed */
8473 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8474 ramrod_param.user_req.u.vlan.vlan = vlan;
04f05230 8475 __set_bit(BNX2X_VLAN, &ramrod_param.user_req.vlan_mac_flags);
05cc5a39
YM		 8476 /* Set the command: ADD or DEL */
8477 if (set)
8478 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8479 else
8480 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8481 }
8482
8483 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8484
8485 if (rc == -EEXIST) {
8486 /* Do not treat adding same vlan as error. */
8487 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8488 rc = 0;
8489 } else if (rc < 0) {
8490 BNX2X_ERR("%s VLAN failed\n", (set ? "Set" : "Del"));
8491 }
8492
8493 return rc;
8494}
8495
04f05230
SRK		 8496static int bnx2x_del_all_vlans(struct bnx2x *bp)
8497{
8498 struct bnx2x_vlan_mac_obj *vlan_obj = &bp->sp_objs[0].vlan_obj;
8499 unsigned long ramrod_flags = 0, vlan_flags = 0;
8500 struct bnx2x_vlan_entry *vlan;
8501 int rc;
8502
8503 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8504 __set_bit(BNX2X_VLAN, &vlan_flags);
8505 rc = vlan_obj->delete_all(bp, vlan_obj, &vlan_flags, &ramrod_flags);
8506 if (rc)
8507 return rc;
8508
8509 /* Mark that hw forgot all entries */
8510 list_for_each_entry(vlan, &bp->vlan_reg, link)
8511 vlan->hw = false;
8512 bp->vlan_cnt = 0;
8513
8514 return 0;
8515}
8516
619c5cb6
VZ		 8517int bnx2x_del_all_macs(struct bnx2x *bp,
8518 struct bnx2x_vlan_mac_obj *mac_obj,
8519 int mac_type, bool wait_for_comp)
e665bfda 8520{
619c5cb6
VZ		 8521 int rc;
8522 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
0793f83f 8523
619c5cb6
VZ		 8524 /* Wait for completion of requested */
8525 if (wait_for_comp)
8526 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
0793f83f 8527
619c5cb6
VZ		 8528 /* Set the mac type of addresses we want to clear */
8529 __set_bit(mac_type, &vlan_mac_flags);
0793f83f 8530
619c5cb6
VZ		 8531 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8532 if (rc < 0)
8533 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
0793f83f 8534
619c5cb6 8535 return rc;
0793f83f
DK		 8536}
8537
619c5cb6 8538int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
523224a3 8539{
f8f4f61a
DK		 8540 if (IS_PF(bp)) {
8541 unsigned long ramrod_flags = 0;
0793f83f 8542
f8f4f61a
DK		 8543 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8544 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8545 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8546 &bp->sp_objs->mac_obj, set,
8547 BNX2X_ETH_MAC, &ramrod_flags);
8548 } else { /* vf */
8549 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
bb9e9c1d 8550 bp->fp->index, set);
f8f4f61a 8551 }
e665bfda 8552}
6e30dd4e 8553
619c5cb6 8554int bnx2x_setup_leading(struct bnx2x *bp)
ec6ba945 8555{
60cad4e6
AE		 8556 if (IS_PF(bp))
8557 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8558 else /* VF */
8559 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
993ac7b5 8560}
a2fbb9ea 8561
d6214d7a 8562/**
e8920674 8563 * bnx2x_set_int_mode - configure interrupt mode
d6214d7a 8564 *
e8920674 8565 * @bp: driver handle
d6214d7a 8566 *
e8920674 8567 * In case of MSI-X it will also try to enable MSI-X.
d6214d7a 8568 */
1ab4434c 8569int bnx2x_set_int_mode(struct bnx2x *bp)
ca00392c 8570{
1ab4434c
AE		 8571 int rc = 0;
8572
60cad4e6
AE		 8573 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8574 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
1ab4434c 8575 return -EINVAL;
60cad4e6 8576 }
1ab4434c 8577
9ee3d37b 8578 switch (int_mode) {
1ab4434c
AE		 8579 case BNX2X_INT_MODE_MSIX:
8580 /* attempt to enable msix */
8581 rc = bnx2x_enable_msix(bp);
8582
8583 /* msix attained */
8584 if (!rc)
8585 return 0;
8586
8587 /* vfs use only msix */
8588 if (rc && IS_VF(bp))
8589 return rc;
8590
8591 /* failed to enable multiple MSI-X */
8592 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8593 bp->num_queues,
8594 1 + bp->num_cnic_queues);
8595
83607344 8596 /* fall through */
1ab4434c 8597 case BNX2X_INT_MODE_MSI:
d6214d7a 8598 bnx2x_enable_msi(bp);
1ab4434c 8599
83607344 8600 /* fall through */
1ab4434c 8601 case BNX2X_INT_MODE_INTX:
55c11941
MS		 8602 bp->num_ethernet_queues = 1;
8603 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
51c1a580 8604 BNX2X_DEV_INFO("set number of queues to 1\n");
ca00392c 8605 break;
d6214d7a 8606 default:
1ab4434c
AE		 8607 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8608 return -EINVAL;
9f6c9258 8609 }
1ab4434c 8610 return 0;
a2fbb9ea
ET		 8611}
8612
1ab4434c 8613/* must be called prior to any HW initializations */
c2bff63f
DK		 8614static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8615{
290ca2bb
AE		 8616 if (IS_SRIOV(bp))
8617 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
c2bff63f
DK		 8618 return L2_ILT_LINES(bp);
8619}
8620
523224a3
DK		 8621void bnx2x_ilt_set_info(struct bnx2x *bp)
8622{
8623 struct ilt_client_info *ilt_client;
8624 struct bnx2x_ilt *ilt = BP_ILT(bp);
8625 u16 line = 0;
8626
8627 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8628 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8629
8630 /* CDU */
8631 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8632 ilt_client->client_num = ILT_CLIENT_CDU;
8633 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8634 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8635 ilt_client->start = line;
619c5cb6 8636 line += bnx2x_cid_ilt_lines(bp);
55c11941
MS		 8637
8638 if (CNIC_SUPPORT(bp))
8639 line += CNIC_ILT_LINES;
523224a3
DK		 8640 ilt_client->end = line - 1;
8641
51c1a580 8642 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8643 ilt_client->start,
8644 ilt_client->end,
8645 ilt_client->page_size,
8646 ilt_client->flags,
8647 ilog2(ilt_client->page_size >> 12));
8648
8649 /* QM */
8650 if (QM_INIT(bp->qm_cid_count)) {
8651 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8652 ilt_client->client_num = ILT_CLIENT_QM;
8653 ilt_client->page_size = QM_ILT_PAGE_SZ;
8654 ilt_client->flags = 0;
8655 ilt_client->start = line;
8656
8657 /* 4 bytes for each cid */
8658 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8659 QM_ILT_PAGE_SZ);
8660
8661 ilt_client->end = line - 1;
8662
51c1a580
MS		 8663 DP(NETIF_MSG_IFUP,
8664 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
523224a3
DK		 8665 ilt_client->start,
8666 ilt_client->end,
8667 ilt_client->page_size,
8668 ilt_client->flags,
8669 ilog2(ilt_client->page_size >> 12));
523224a3 8670 }
523224a3 8671
55c11941
MS		 8672 if (CNIC_SUPPORT(bp)) {
8673 /* SRC */
8674 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8675 ilt_client->client_num = ILT_CLIENT_SRC;
8676 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8677 ilt_client->flags = 0;
8678 ilt_client->start = line;
8679 line += SRC_ILT_LINES;
8680 ilt_client->end = line - 1;
523224a3 8681
55c11941
MS		 8682 DP(NETIF_MSG_IFUP,
8683 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8684 ilt_client->start,
8685 ilt_client->end,
8686 ilt_client->page_size,
8687 ilt_client->flags,
8688 ilog2(ilt_client->page_size >> 12));
9f6c9258 8689
55c11941
MS		 8690 /* TM */
8691 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8692 ilt_client->client_num = ILT_CLIENT_TM;
8693 ilt_client->page_size = TM_ILT_PAGE_SZ;
8694 ilt_client->flags = 0;
8695 ilt_client->start = line;
8696 line += TM_ILT_LINES;
8697 ilt_client->end = line - 1;
523224a3 8698
55c11941
MS		 8699 DP(NETIF_MSG_IFUP,
8700 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8701 ilt_client->start,
8702 ilt_client->end,
8703 ilt_client->page_size,
8704 ilt_client->flags,
8705 ilog2(ilt_client->page_size >> 12));
8706 }
9f6c9258 8707
619c5cb6 8708 BUG_ON(line > ILT_MAX_LINES);
523224a3 8709}
f85582f8 8710
619c5cb6
VZ		 8711/**
8712 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8713 *
8714 * @bp: driver handle
8715 * @fp: pointer to fastpath
8716 * @init_params: pointer to parameters structure
8717 *
8718 * parameters configured:
8719 * - HC configuration
8720 * - Queue's CDU context
8721 */
1191cb83 8722static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
619c5cb6 8723 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
a2fbb9ea 8724{
6383c0b3 8725 u8 cos;
a052997e
MS		 8726 int cxt_index, cxt_offset;
8727
619c5cb6
VZ		 8728 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8729 if (!IS_FCOE_FP(fp)) {
8730 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8731 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8732
16a5fd92 8733 /* If HC is supported, enable host coalescing in the transition
619c5cb6
VZ		 8734 * to INIT state.
8735 */
8736 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8737 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8738
8739 /* HC rate */
8740 init_params->rx.hc_rate = bp->rx_ticks ?
8741 (1000000 / bp->rx_ticks) : 0;
8742 init_params->tx.hc_rate = bp->tx_ticks ?
8743 (1000000 / bp->tx_ticks) : 0;
8744
8745 /* FW SB ID */
8746 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8747 fp->fw_sb_id;
8748
8749 /*
8750 * CQ index among the SB indices: FCoE clients uses the default
8751 * SB, therefore it's different.
8752 */
6383c0b3
AE		 8753 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8754 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
619c5cb6
VZ		 8755 }
8756
6383c0b3
AE		 8757 /* set maximum number of COSs supported by this queue */
8758 init_params->max_cos = fp->max_cos;
8759
51c1a580 8760 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
6383c0b3
AE		 8761 fp->index, init_params->max_cos);
8762
8763 /* set the context pointers queue object */
a052997e 8764 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
65565884
MS		 8765 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8766 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
a052997e 8767 ILT_PAGE_CIDS);
6383c0b3 8768 init_params->cxts[cos] =
a052997e
MS		 8769 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8770 }
619c5cb6
VZ		 8771}
8772
910cc727 8773static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6383c0b3
AE		 8774 struct bnx2x_queue_state_params *q_params,
8775 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8776 int tx_index, bool leading)
8777{
8778 memset(tx_only_params, 0, sizeof(*tx_only_params));
8779
8780 /* Set the command */
8781 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8782
8783 /* Set tx-only QUEUE flags: don't zero statistics */
8784 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8785
8786 /* choose the index of the cid to send the slow path on */
8787 tx_only_params->cid_index = tx_index;
8788
8789 /* Set general TX_ONLY_SETUP parameters */
8790 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8791
8792 /* Set Tx TX_ONLY_SETUP parameters */
8793 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8794
51c1a580
MS		 8795 DP(NETIF_MSG_IFUP,
8796 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
6383c0b3
AE		 8797 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8798 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8799 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8800
8801 /* send the ramrod */
8802 return bnx2x_queue_state_change(bp, q_params);
8803}
8804
619c5cb6
VZ		 8805/**
8806 * bnx2x_setup_queue - setup queue
8807 *
8808 * @bp: driver handle
8809 * @fp: pointer to fastpath
8810 * @leading: is leading
8811 *
8812 * This function performs 2 steps in a Queue state machine
8813 * actually: 1) RESET->INIT 2) INIT->SETUP
8814 */
8815
8816int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8817 bool leading)
8818{
3b603066 8819 struct bnx2x_queue_state_params q_params = {NULL};
619c5cb6
VZ		 8820 struct bnx2x_queue_setup_params *setup_params =
8821 &q_params.params.setup;
6383c0b3
AE		 8822 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8823 &q_params.params.tx_only;
a2fbb9ea 8824 int rc;
6383c0b3
AE		 8825 u8 tx_index;
8826
51c1a580 8827 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
a2fbb9ea 8828
ec6ba945
VZ		 8829 /* reset IGU state skip FCoE L2 queue */
8830 if (!IS_FCOE_FP(fp))
8831 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
523224a3 8832 IGU_INT_ENABLE, 0);
a2fbb9ea 8833
15192a8c 8834 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8835 /* We want to wait for completion in this context */
8836 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8837
619c5cb6
VZ		 8838 /* Prepare the INIT parameters */
8839 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
ec6ba945 8840
619c5cb6
VZ		 8841 /* Set the command */
8842 q_params.cmd = BNX2X_Q_CMD_INIT;
8843
8844 /* Change the state to INIT */
8845 rc = bnx2x_queue_state_change(bp, &q_params);
8846 if (rc) {
6383c0b3 8847 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
619c5cb6
VZ		 8848 return rc;
8849 }
ec6ba945 8850
51c1a580 8851 DP(NETIF_MSG_IFUP, "init complete\n");
6383c0b3 8852
619c5cb6
VZ		 8853 /* Now move the Queue to the SETUP state... */
8854 memset(setup_params, 0, sizeof(*setup_params));
a2fbb9ea 8855
619c5cb6
VZ		 8856 /* Set QUEUE flags */
8857 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
523224a3 8858
619c5cb6 8859 /* Set general SETUP parameters */
6383c0b3
AE		 8860 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8861 FIRST_TX_COS_INDEX);
619c5cb6 8862
6383c0b3 8863 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
619c5cb6
VZ		 8864 &setup_params->rxq_params);
8865
6383c0b3
AE		 8866 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8867 FIRST_TX_COS_INDEX);
619c5cb6
VZ		 8868
8869 /* Set the command */
8870 q_params.cmd = BNX2X_Q_CMD_SETUP;
8871
55c11941
MS		 8872 if (IS_FCOE_FP(fp))
8873 bp->fcoe_init = true;
8874
619c5cb6
VZ		 8875 /* Change the state to SETUP */
8876 rc = bnx2x_queue_state_change(bp, &q_params);
6383c0b3
AE		 8877 if (rc) {
8878 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8879 return rc;
8880 }
8881
8882 /* loop through the relevant tx-only indices */
8883 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8884 tx_index < fp->max_cos;
8885 tx_index++) {
8886
8887 /* prepare and send tx-only ramrod*/
8888 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8889 tx_only_params, tx_index, leading);
8890 if (rc) {
8891 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8892 fp->index, tx_index);
8893 return rc;
8894 }
8895 }
523224a3 8896
34f80b04 8897 return rc;
a2fbb9ea
ET		 8898}
8899
619c5cb6 8900static int bnx2x_stop_queue(struct bnx2x *bp, int index)
a2fbb9ea 8901{
619c5cb6 8902 struct bnx2x_fastpath *fp = &bp->fp[index];
6383c0b3 8903 struct bnx2x_fp_txdata *txdata;
3b603066 8904 struct bnx2x_queue_state_params q_params = {NULL};
6383c0b3
AE		 8905 int rc, tx_index;
8906
51c1a580 8907 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
a2fbb9ea 8908
15192a8c 8909 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
619c5cb6
VZ		 8910 /* We want to wait for completion in this context */
8911 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
a2fbb9ea 8912
6383c0b3
AE		 8913 /* close tx-only connections */
8914 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8915 tx_index < fp->max_cos;
8916 tx_index++){
8917
8918 /* ascertain this is a normal queue*/
65565884 8919 txdata = fp->txdata_ptr[tx_index];
6383c0b3 8920
51c1a580 8921 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
6383c0b3
AE		 8922 txdata->txq_index);
8923
8924 /* send halt terminate on tx-only connection */
8925 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8926 memset(&q_params.params.terminate, 0,
8927 sizeof(q_params.params.terminate));
8928 q_params.params.terminate.cid_index = tx_index;
8929
8930 rc = bnx2x_queue_state_change(bp, &q_params);
8931 if (rc)
8932 return rc;
8933
8934 /* send halt terminate on tx-only connection */
8935 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8936 memset(&q_params.params.cfc_del, 0,
8937 sizeof(q_params.params.cfc_del));
8938 q_params.params.cfc_del.cid_index = tx_index;
8939 rc = bnx2x_queue_state_change(bp, &q_params);
8940 if (rc)
8941 return rc;
8942 }
8943 /* Stop the primary connection: */
8944 /* ...halt the connection */
619c5cb6
VZ		 8945 q_params.cmd = BNX2X_Q_CMD_HALT;
8946 rc = bnx2x_queue_state_change(bp, &q_params);
8947 if (rc)
da5a662a 8948 return rc;
a2fbb9ea 8949
6383c0b3 8950 /* ...terminate the connection */
619c5cb6 8951 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
6383c0b3
AE		 8952 memset(&q_params.params.terminate, 0,
8953 sizeof(q_params.params.terminate));
8954 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
619c5cb6
VZ		 8955 rc = bnx2x_queue_state_change(bp, &q_params);
8956 if (rc)
523224a3 8957 return rc;
6383c0b3 8958 /* ...delete cfc entry */
619c5cb6 8959 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
6383c0b3
AE		 8960 memset(&q_params.params.cfc_del, 0,
8961 sizeof(q_params.params.cfc_del));
8962 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
619c5cb6 8963 return bnx2x_queue_state_change(bp, &q_params);
523224a3
DK		 8964}
8965
34f80b04
EG		 8966static void bnx2x_reset_func(struct bnx2x *bp)
8967{
8968 int port = BP_PORT(bp);
8969 int func = BP_FUNC(bp);
f2e0899f 8970 int i;
523224a3
DK		 8971
8972 /* Disable the function in the FW */
8973 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8974 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8975 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8976 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8977
8978 /* FP SBs */
ec6ba945 8979 for_each_eth_queue(bp, i) {
523224a3 8980 struct bnx2x_fastpath *fp = &bp->fp[i];
619c5cb6 8981 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6383c0b3
AE		 8982 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8983 SB_DISABLED);
523224a3
DK		 8984 }
8985
55c11941
MS		 8986 if (CNIC_LOADED(bp))
8987 /* CNIC SB */
8988 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8989 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8990 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8991
523224a3 8992 /* SP SB */
619c5cb6 8993 REG_WR8(bp, BAR_CSTRORM_INTMEM +
2de67439
YM		 8994 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8995 SB_DISABLED);
523224a3
DK		 8996
8997 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8998 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8999 0);
34f80b04
EG		 9000
9001 /* Configure IGU */
f2e0899f
DK		 9002 if (bp->common.int_block == INT_BLOCK_HC) {
9003 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
9004 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
9005 } else {
9006 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
9007 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
9008 }
34f80b04 9009
55c11941
MS		 9010 if (CNIC_LOADED(bp)) {
9011 /* Disable Timer scan */
9012 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
9013 /*
9014 * Wait for at least 10ms and up to 2 second for the timers
9015 * scan to complete
9016 */
9017 for (i = 0; i < 200; i++) {
639d65b8 9018 usleep_range(10000, 20000);
55c11941
MS		 9019 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
9020 break;
9021 }
37b091ba 9022 }
34f80b04 9023 /* Clear ILT */
f2e0899f
DK		 9024 bnx2x_clear_func_ilt(bp, func);
9025
9026 /* Timers workaround bug for E2: if this is vnic-3,
9027 * we need to set the entire ilt range for this timers.
9028 */
619c5cb6 9029 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
f2e0899f
DK		 9030 struct ilt_client_info ilt_cli;
9031 /* use dummy TM client */
9032 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
9033 ilt_cli.start = 0;
9034 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
9035 ilt_cli.client_num = ILT_CLIENT_TM;
9036
9037 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
9038 }
9039
9040 /* this assumes that reset_port() called before reset_func()*/
619c5cb6 9041 if (!CHIP_IS_E1x(bp))
f2e0899f 9042 bnx2x_pf_disable(bp);
523224a3
DK		 9043
9044 bp->dmae_ready = 0;
34f80b04
EG		 9045}
9046
9047static void bnx2x_reset_port(struct bnx2x *bp)
9048{
9049 int port = BP_PORT(bp);
9050 u32 val;
9051
619c5cb6
VZ		 9052 /* Reset physical Link */
9053 bnx2x__link_reset(bp);
9054
34f80b04
EG		 9055 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
9056
9057 /* Do not rcv packets to BRB */
9058 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
9059 /* Do not direct rcv packets that are not for MCP to the BRB */
9060 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
9061 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
9062
9063 /* Configure AEU */
9064 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
9065
9066 msleep(100);
9067 /* Check for BRB port occupancy */
9068 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
9069 if (val)
9070 DP(NETIF_MSG_IFDOWN,
33471629 9071 "BRB1 is not empty %d blocks are occupied\n", val);
34f80b04
EG		 9072
9073 /* TODO: Close Doorbell port? */
9074}
9075
1191cb83 9076static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
34f80b04 9077{
3b603066 9078 struct bnx2x_func_state_params func_params = {NULL};
34f80b04 9079
619c5cb6
VZ		 9080 /* Prepare parameters for function state transitions */
9081 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
34f80b04 9082
619c5cb6
VZ		 9083 func_params.f_obj = &bp->func_obj;
9084 func_params.cmd = BNX2X_F_CMD_HW_RESET;
34f80b04 9085
619c5cb6 9086 func_params.params.hw_init.load_phase = load_code;
49d66772 9087
619c5cb6 9088 return bnx2x_func_state_change(bp, &func_params);
34f80b04
EG		 9089}
9090
1191cb83 9091static int bnx2x_func_stop(struct bnx2x *bp)
ec6ba945 9092{
3b603066 9093 struct bnx2x_func_state_params func_params = {NULL};
619c5cb6 9094 int rc;
228241eb 9095
619c5cb6
VZ		 9096 /* Prepare parameters for function state transitions */
9097 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
9098 func_params.f_obj = &bp->func_obj;
9099 func_params.cmd = BNX2X_F_CMD_STOP;
da5a662a 9100
619c5cb6
VZ		 9101 /*
9102 * Try to stop the function the 'good way'. If fails (in case
9103 * of a parity error during bnx2x_chip_cleanup()) and we are
9104 * not in a debug mode, perform a state transaction in order to
9105 * enable further HW_RESET transaction.
9106 */
9107 rc = bnx2x_func_state_change(bp, &func_params);
9108 if (rc) {
34f80b04 9109#ifdef BNX2X_STOP_ON_ERROR
619c5cb6 9110 return rc;
34f80b04 9111#else
51c1a580 9112 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
619c5cb6
VZ		 9113 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
9114 return bnx2x_func_state_change(bp, &func_params);
34f80b04 9115#endif
228241eb 9116 }
a2fbb9ea 9117
619c5cb6
VZ		 9118 return 0;
9119}
523224a3 9120
619c5cb6
VZ		 9121/**
9122 * bnx2x_send_unload_req - request unload mode from the MCP.
9123 *
9124 * @bp: driver handle
9125 * @unload_mode: requested function's unload mode
9126 *
9127 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9128 */
9129u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
9130{
9131 u32 reset_code = 0;
9132 int port = BP_PORT(bp);
3101c2bc 9133
619c5cb6 9134 /* Select the UNLOAD request mode */
65abd74d
YG		 9135 if (unload_mode == UNLOAD_NORMAL)
9136 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9137
7d0446c2 9138 else if (bp->flags & NO_WOL_FLAG)
65abd74d 9139 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
65abd74d 9140
7d0446c2 9141 else if (bp->wol) {
65abd74d
YG		 9142 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9143 u8 *mac_addr = bp->dev->dev_addr;
29ed74c3 9144 struct pci_dev *pdev = bp->pdev;
65abd74d 9145 u32 val;
f9977903
DK		 9146 u16 pmc;
9147
65abd74d 9148 /* The mac address is written to entries 1-4 to
f9977903
DK		 9149 * preserve entry 0 which is used by the PMF
9150 */
3395a033 9151 u8 entry = (BP_VN(bp) + 1)*8;
65abd74d
YG		 9152
9153 val = (mac_addr[0] << 8) | mac_addr[1];
9154 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9155
9156 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9157 (mac_addr[4] << 8) | mac_addr[5];
9158 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9159
f9977903 9160 /* Enable the PME and clear the status */
29ed74c3 9161 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
f9977903 9162 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
29ed74c3 9163 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
f9977903 9164
65abd74d
YG		 9165 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9166
9167 } else
9168 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
da5a662a 9169
619c5cb6
VZ		 9170 /* Send the request to the MCP */
9171 if (!BP_NOMCP(bp))
9172 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9173 else {
9174 int path = BP_PATH(bp);
9175
51c1a580 9176 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
a8f47eb7 9177 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9178 bnx2x_load_count[path][2]);
9179 bnx2x_load_count[path][0]--;
9180 bnx2x_load_count[path][1 + port]--;
51c1a580 9181 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
a8f47eb7 9182 path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9183 bnx2x_load_count[path][2]);
9184 if (bnx2x_load_count[path][0] == 0)
619c5cb6 9185 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
a8f47eb7 9186 else if (bnx2x_load_count[path][1 + port] == 0)
619c5cb6
VZ		 9187 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9188 else
9189 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9190 }
9191
9192 return reset_code;
9193}
9194
9195/**
9196 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9197 *
9198 * @bp: driver handle
5d07d868 9199 * @keep_link: true iff link should be kept up
619c5cb6 9200 */
5d07d868 9201void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
619c5cb6 9202{
5d07d868
YM		 9203 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9204
619c5cb6
VZ		 9205 /* Report UNLOAD_DONE to MCP */
9206 if (!BP_NOMCP(bp))
5d07d868 9207 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
619c5cb6
VZ		 9208}
9209
1191cb83 9210static int bnx2x_func_wait_started(struct bnx2x *bp)
6debea87
DK		 9211{
9212 int tout = 50;
9213 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9214
9215 if (!bp->port.pmf)
9216 return 0;
9217
9218 /*
9219 * (assumption: No Attention from MCP at this stage)
16a5fd92 9220 * PMF probably in the middle of TX disable/enable transaction
6debea87 9221 * 1. Sync IRS for default SB
16a5fd92
YM		 9222 * 2. Sync SP queue - this guarantees us that attention handling started
9223 * 3. Wait, that TX disable/enable transaction completes
6debea87 9224 *
16a5fd92
YM		 9225 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9226 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9227 * received completion for the transaction the state is TX_STOPPED.
6debea87
DK		 9228 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9229 * transaction.
9230 */
9231
9232 /* make sure default SB ISR is done */
9233 if (msix)
9234 synchronize_irq(bp->msix_table[0].vector);
9235 else
9236 synchronize_irq(bp->pdev->irq);
9237
9238 flush_workqueue(bnx2x_wq);
370d4a26 9239 flush_workqueue(bnx2x_iov_wq);
6debea87
DK		 9240
9241 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9242 BNX2X_F_STATE_STARTED && tout--)
9243 msleep(20);
9244
9245 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9246 BNX2X_F_STATE_STARTED) {
9247#ifdef BNX2X_STOP_ON_ERROR
51c1a580 9248 BNX2X_ERR("Wrong function state\n");
6debea87
DK		 9249 return -EBUSY;
9250#else
9251 /*
9252 * Failed to complete the transaction in a "good way"
9253 * Force both transactions with CLR bit
9254 */
3b603066 9255 struct bnx2x_func_state_params func_params = {NULL};
6debea87 9256
51c1a580 9257 DP(NETIF_MSG_IFDOWN,
0c23ad37 9258 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
6debea87
DK		 9259
9260 func_params.f_obj = &bp->func_obj;
9261 __set_bit(RAMROD_DRV_CLR_ONLY,
9262 &func_params.ramrod_flags);
9263
9264 /* STARTED-->TX_ST0PPED */
9265 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9266 bnx2x_func_state_change(bp, &func_params);
9267
9268 /* TX_ST0PPED-->STARTED */
9269 func_params.cmd = BNX2X_F_CMD_TX_START;
9270 return bnx2x_func_state_change(bp, &func_params);
9271#endif
9272 }
9273
9274 return 0;
9275}
9276
eeed018c
MK		 9277static void bnx2x_disable_ptp(struct bnx2x *bp)
9278{
9279 int port = BP_PORT(bp);
9280
9281 /* Disable sending PTP packets to host */
9282 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9283 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9284
9285 /* Reset PTP event detection rules */
9286 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9287 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9288 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9289 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9290 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9291 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9292 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9293 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9294
9295 /* Disable the PTP feature */
9296 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9297 NIG_REG_P0_PTP_EN, 0x0);
9298}
9299
9300/* Called during unload, to stop PTP-related stuff */
1444c301 9301static void bnx2x_stop_ptp(struct bnx2x *bp)
eeed018c
MK		 9302{
9303 /* Cancel PTP work queue. Should be done after the Tx queues are
9304 * drained to prevent additional scheduling.
9305 */
9306 cancel_work_sync(&bp->ptp_task);
9307
9308 if (bp->ptp_tx_skb) {
9309 dev_kfree_skb_any(bp->ptp_tx_skb);
9310 bp->ptp_tx_skb = NULL;
9311 }
9312
9313 /* Disable PTP in HW */
9314 bnx2x_disable_ptp(bp);
9315
9316 DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9317}
9318
5d07d868 9319void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
619c5cb6
VZ		 9320{
9321 int port = BP_PORT(bp);
6383c0b3
AE		 9322 int i, rc = 0;
9323 u8 cos;
3b603066 9324 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6
VZ		 9325 u32 reset_code;
9326
9327 /* Wait until tx fastpath tasks complete */
9328 for_each_tx_queue(bp, i) {
9329 struct bnx2x_fastpath *fp = &bp->fp[i];
9330
6383c0b3 9331 for_each_cos_in_tx_queue(fp, cos)
65565884 9332 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
619c5cb6
VZ		 9333#ifdef BNX2X_STOP_ON_ERROR
9334 if (rc)
9335 return;
9336#endif
9337 }
9338
9339 /* Give HW time to discard old tx messages */
0926d499 9340 usleep_range(1000, 2000);
619c5cb6
VZ		 9341
9342 /* Clean all ETH MACs */
15192a8c
BW		 9343 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9344 false);
619c5cb6
VZ		 9345 if (rc < 0)
9346 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9347
9348 /* Clean up UC list */
15192a8c 9349 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
619c5cb6
VZ		 9350 true);
9351 if (rc < 0)
51c1a580
MS		 9352 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9353 rc);
619c5cb6 9354
04f05230
SRK		 9355 /* Remove all currently configured VLANs */
9356 rc = bnx2x_del_all_vlans(bp);
9357 if (rc < 0)
9358 BNX2X_ERR("Failed to delete all VLANs\n");
9359
619c5cb6
VZ		 9360 /* Disable LLH */
9361 if (!CHIP_IS_E1(bp))
9362 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9363
9364 /* Set "drop all" (stop Rx).
9365 * We need to take a netif_addr_lock() here in order to prevent
9366 * a race between the completion code and this code.
9367 */
9368 netif_addr_lock_bh(bp->dev);
9369 /* Schedule the rx_mode command */
9370 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9371 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
442866ff 9372 else if (bp->slowpath)
619c5cb6
VZ		 9373 bnx2x_set_storm_rx_mode(bp);
9374
9375 /* Cleanup multicast configuration */
9376 rparam.mcast_obj = &bp->mcast_obj;
9377 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9378 if (rc < 0)
9379 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9380
9381 netif_addr_unlock_bh(bp->dev);
9382
f1929b01 9383 bnx2x_iov_chip_cleanup(bp);
619c5cb6 9384
6debea87
DK		 9385 /*
9386 * Send the UNLOAD_REQUEST to the MCP. This will return if
9387 * this function should perform FUNC, PORT or COMMON HW
9388 * reset.
9389 */
9390 reset_code = bnx2x_send_unload_req(bp, unload_mode);
9391
9392 /*
9393 * (assumption: No Attention from MCP at this stage)
16a5fd92 9394 * PMF probably in the middle of TX disable/enable transaction
6debea87
DK		 9395 */
9396 rc = bnx2x_func_wait_started(bp);
9397 if (rc) {
9398 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9399#ifdef BNX2X_STOP_ON_ERROR
9400 return;
9401#endif
9402 }
9403
34f80b04 9404 /* Close multi and leading connections
619c5cb6
VZ		 9405 * Completions for ramrods are collected in a synchronous way
9406 */
55c11941 9407 for_each_eth_queue(bp, i)
619c5cb6 9408 if (bnx2x_stop_queue(bp, i))
523224a3
DK		 9409#ifdef BNX2X_STOP_ON_ERROR
9410 return;
9411#else
228241eb 9412 goto unload_error;
523224a3 9413#endif
55c11941
MS		 9414
9415 if (CNIC_LOADED(bp)) {
9416 for_each_cnic_queue(bp, i)
9417 if (bnx2x_stop_queue(bp, i))
9418#ifdef BNX2X_STOP_ON_ERROR
9419 return;
9420#else
9421 goto unload_error;
9422#endif
9423 }
9424
619c5cb6
VZ		 9425 /* If SP settings didn't get completed so far - something
9426 * very wrong has happen.
9427 */
9428 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9429 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
a2fbb9ea 9430
619c5cb6
VZ		 9431#ifndef BNX2X_STOP_ON_ERROR
9432unload_error:
9433#endif
523224a3 9434 rc = bnx2x_func_stop(bp);
da5a662a 9435 if (rc) {
523224a3 9436 BNX2X_ERR("Function stop failed!\n");
da5a662a 9437#ifdef BNX2X_STOP_ON_ERROR
523224a3 9438 return;
523224a3 9439#endif
34f80b04 9440 }
a2fbb9ea 9441
eeed018c
MK		 9442 /* stop_ptp should be after the Tx queues are drained to prevent
9443 * scheduling to the cancelled PTP work queue. It should also be after
9444 * function stop ramrod is sent, since as part of this ramrod FW access
9445 * PTP registers.
9446 */
d53c66a5
ED		 9447 if (bp->flags & PTP_SUPPORTED)
9448 bnx2x_stop_ptp(bp);
eeed018c 9449
523224a3
DK		 9450 /* Disable HW interrupts, NAPI */
9451 bnx2x_netif_stop(bp, 1);
26614ba5
MS		 9452 /* Delete all NAPI objects */
9453 bnx2x_del_all_napi(bp);
55c11941
MS		 9454 if (CNIC_LOADED(bp))
9455 bnx2x_del_all_napi_cnic(bp);
523224a3
DK		 9456
9457 /* Release IRQs */
d6214d7a 9458 bnx2x_free_irq(bp);
523224a3 9459
b44e108b
GP		 9460 /* Reset the chip, unless PCI function is offline. If we reach this
9461 * point following a PCI error handling, it means device is really
9462 * in a bad state and we're about to remove it, so reset the chip
9463 * is not a good idea.
9464 */
9465 if (!pci_channel_offline(bp->pdev)) {
9466 rc = bnx2x_reset_hw(bp, reset_code);
9467 if (rc)
9468 BNX2X_ERR("HW_RESET failed\n");
9469 }
a2fbb9ea 9470
619c5cb6 9471 /* Report UNLOAD_DONE to MCP */
5d07d868 9472 bnx2x_send_unload_done(bp, keep_link);
72fd0718
VZ		 9473}
9474
9f6c9258 9475void bnx2x_disable_close_the_gate(struct bnx2x *bp)
72fd0718
VZ		 9476{
9477 u32 val;
9478
51c1a580 9479 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
72fd0718
VZ		 9480
9481 if (CHIP_IS_E1(bp)) {
9482 int port = BP_PORT(bp);
9483 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9484 MISC_REG_AEU_MASK_ATTN_FUNC_0;
9485
9486 val = REG_RD(bp, addr);
9487 val &= ~(0x300);
9488 REG_WR(bp, addr, val);
619c5cb6 9489 } else {
72fd0718
VZ		 9490 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9491 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9492 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9493 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9494 }
9495}
9496
72fd0718
VZ		 9497/* Close gates #2, #3 and #4: */
9498static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9499{
c9ee9206 9500 u32 val;
72fd0718
VZ		 9501
9502 /* Gates #2 and #4a are closed/opened for "not E1" only */
9503 if (!CHIP_IS_E1(bp)) {
9504 /* #4 */
c9ee9206 9505 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
72fd0718 9506 /* #2 */
c9ee9206 9507 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
72fd0718
VZ		 9508 }
9509
9510 /* #3 */
c9ee9206
VZ		 9511 if (CHIP_IS_E1x(bp)) {
9512 /* Prevent interrupts from HC on both ports */
9513 val = REG_RD(bp, HC_REG_CONFIG_1);
9514 REG_WR(bp, HC_REG_CONFIG_1,
9515 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9516 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9517
9518 val = REG_RD(bp, HC_REG_CONFIG_0);
9519 REG_WR(bp, HC_REG_CONFIG_0,
9520 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9521 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9522 } else {
d82603c6 9523 /* Prevent incoming interrupts in IGU */
c9ee9206
VZ		 9524 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9525
9526 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9527 (!close) ?
9528 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9529 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9530 }
72fd0718 9531
51c1a580 9532 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
72fd0718
VZ		 9533 close ? "closing" : "opening");
9534 mmiowb();
9535}
9536
9537#define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9538
9539static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9540{
9541 /* Do some magic... */
9542 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9543 *magic_val = val & SHARED_MF_CLP_MAGIC;
9544 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9545}
9546
e8920674
DK		 9547/**
9548 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
72fd0718 9549 *
e8920674
DK		 9550 * @bp: driver handle
9551 * @magic_val: old value of the `magic' bit.
72fd0718
VZ		 9552 */
9553static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9554{
9555 /* Restore the `magic' bit value... */
72fd0718
VZ		 9556 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9557 MF_CFG_WR(bp, shared_mf_config.clp_mb,
9558 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9559}
9560
f85582f8 9561/**
e8920674 9562 * bnx2x_reset_mcp_prep - prepare for MCP reset.
72fd0718 9563 *
e8920674
DK		 9564 * @bp: driver handle
9565 * @magic_val: old value of 'magic' bit.
9566 *
9567 * Takes care of CLP configurations.
72fd0718
VZ		 9568 */
9569static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9570{
9571 u32 shmem;
9572 u32 validity_offset;
9573
51c1a580 9574 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
72fd0718
VZ		 9575
9576 /* Set `magic' bit in order to save MF config */
9577 if (!CHIP_IS_E1(bp))
9578 bnx2x_clp_reset_prep(bp, magic_val);
9579
9580 /* Get shmem offset */
9581 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
c55e771b
BW		 9582 validity_offset =
9583 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
72fd0718
VZ		 9584
9585 /* Clear validity map flags */
9586 if (shmem > 0)
9587 REG_WR(bp, shmem + validity_offset, 0);
9588}
9589
9590#define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9591#define MCP_ONE_TIMEOUT 100 /* 100 ms */
9592
e8920674
DK		 9593/**
9594 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
72fd0718 9595 *
e8920674 9596 * @bp: driver handle
72fd0718 9597 */
1191cb83 9598static void bnx2x_mcp_wait_one(struct bnx2x *bp)
72fd0718
VZ		 9599{
9600 /* special handling for emulation and FPGA,
9601 wait 10 times longer */
9602 if (CHIP_REV_IS_SLOW(bp))
9603 msleep(MCP_ONE_TIMEOUT*10);
9604 else
9605 msleep(MCP_ONE_TIMEOUT);
9606}
9607
1b6e2ceb
DK		 9608/*
9609 * initializes bp->common.shmem_base and waits for validity signature to appear
9610 */
9611static int bnx2x_init_shmem(struct bnx2x *bp)
72fd0718 9612{
1b6e2ceb
DK		 9613 int cnt = 0;
9614 u32 val = 0;
72fd0718 9615
1b6e2ceb
DK		 9616 do {
9617 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
f7084059
GP		 9618
9619 /* If we read all 0xFFs, means we are in PCI error state and
9620 * should bail out to avoid crashes on adapter's FW reads.
9621 */
9622 if (bp->common.shmem_base == 0xFFFFFFFF) {
9623 bp->flags |= NO_MCP_FLAG;
9624 return -ENODEV;
9625 }
9626
1b6e2ceb
DK		 9627 if (bp->common.shmem_base) {
9628 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9629 if (val & SHR_MEM_VALIDITY_MB)
9630 return 0;
9631 }
72fd0718 9632
1b6e2ceb 9633 bnx2x_mcp_wait_one(bp);
72fd0718 9634
1b6e2ceb 9635 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
72fd0718 9636
1b6e2ceb 9637 BNX2X_ERR("BAD MCP validity signature\n");
72fd0718 9638
1b6e2ceb
DK		 9639 return -ENODEV;
9640}
72fd0718 9641
1b6e2ceb
DK		 9642static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9643{
9644 int rc = bnx2x_init_shmem(bp);
72fd0718 9645
72fd0718
VZ		 9646 /* Restore the `magic' bit value */
9647 if (!CHIP_IS_E1(bp))
9648 bnx2x_clp_reset_done(bp, magic_val);
9649
9650 return rc;
9651}
9652
9653static void bnx2x_pxp_prep(struct bnx2x *bp)
9654{
9655 if (!CHIP_IS_E1(bp)) {
9656 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9657 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
72fd0718
VZ		 9658 mmiowb();
9659 }
9660}
9661
9662/*
9663 * Reset the whole chip except for:
9664 * - PCIE core
9665 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9666 * one reset bit)
9667 * - IGU
9668 * - MISC (including AEU)
9669 * - GRC
9670 * - RBCN, RBCP
9671 */
c9ee9206 9672static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
72fd0718
VZ		 9673{
9674 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8736c826 9675 u32 global_bits2, stay_reset2;
c9ee9206
VZ		 9676
9677 /*
9678 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9679 * (per chip) blocks.
9680 */
9681 global_bits2 =
9682 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9683 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
72fd0718 9684
c55e771b
BW		 9685 /* Don't reset the following blocks.
9686 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9687 * reset, as in 4 port device they might still be owned
9688 * by the MCP (there is only one leader per path).
9689 */
72fd0718
VZ		 9690 not_reset_mask1 =
9691 MISC_REGISTERS_RESET_REG_1_RST_HC |
9692 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9693 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9694
9695 not_reset_mask2 =
c9ee9206 9696 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
72fd0718
VZ		 9697 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9698 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9699 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9700 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9701 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9702 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8736c826
VZ		 9703 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9704 MISC_REGISTERS_RESET_REG_2_RST_ATC |
c55e771b
BW		 9705 MISC_REGISTERS_RESET_REG_2_PGLC |
9706 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9707 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9708 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9709 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9710 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9711 MISC_REGISTERS_RESET_REG_2_UMAC1;
72fd0718 9712
8736c826
VZ		 9713 /*
9714 * Keep the following blocks in reset:
9715 * - all xxMACs are handled by the bnx2x_link code.
9716 */
9717 stay_reset2 =
8736c826
VZ		 9718 MISC_REGISTERS_RESET_REG_2_XMAC |
9719 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9720
9721 /* Full reset masks according to the chip */
72fd0718
VZ		 9722 reset_mask1 = 0xffffffff;
9723
9724 if (CHIP_IS_E1(bp))
9725 reset_mask2 = 0xffff;
8736c826 9726 else if (CHIP_IS_E1H(bp))
72fd0718 9727 reset_mask2 = 0x1ffff;
8736c826
VZ		 9728 else if (CHIP_IS_E2(bp))
9729 reset_mask2 = 0xfffff;
9730 else /* CHIP_IS_E3 */
9731 reset_mask2 = 0x3ffffff;
c9ee9206
VZ		 9732
9733 /* Don't reset global blocks unless we need to */
9734 if (!global)
9735 reset_mask2 &= ~global_bits2;
9736
9737 /*
9738 * In case of attention in the QM, we need to reset PXP
9739 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9740 * because otherwise QM reset would release 'close the gates' shortly
9741 * before resetting the PXP, then the PSWRQ would send a write
9742 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9743 * read the payload data from PSWWR, but PSWWR would not
9744 * respond. The write queue in PGLUE would stuck, dmae commands
9745 * would not return. Therefore it's important to reset the second
9746 * reset register (containing the
9747 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9748 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9749 * bit).
9750 */
72fd0718
VZ		 9751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9752 reset_mask2 & (~not_reset_mask2));
9753
c9ee9206
VZ		 9754 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9755 reset_mask1 & (~not_reset_mask1));
9756
72fd0718
VZ		 9757 barrier();
9758 mmiowb();
9759
8736c826
VZ		 9760 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9761 reset_mask2 & (~stay_reset2));
9762
9763 barrier();
9764 mmiowb();
9765
c9ee9206 9766 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
72fd0718
VZ		 9767 mmiowb();
9768}
9769
c9ee9206
VZ		 9770/**
9771 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9772 * It should get cleared in no more than 1s.
9773 *
9774 * @bp: driver handle
9775 *
9776 * It should get cleared in no more than 1s. Returns 0 if
9777 * pending writes bit gets cleared.
9778 */
9779static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9780{
9781 u32 cnt = 1000;
9782 u32 pend_bits = 0;
9783
9784 do {
9785 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9786
9787 if (pend_bits == 0)
9788 break;
9789
0926d499 9790 usleep_range(1000, 2000);
c9ee9206
VZ		 9791 } while (cnt-- > 0);
9792
9793 if (cnt <= 0) {
9794 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9795 pend_bits);
9796 return -EBUSY;
9797 }
9798
9799 return 0;
9800}
9801
9802static int bnx2x_process_kill(struct bnx2x *bp, bool global)
72fd0718
VZ		 9803{
9804 int cnt = 1000;
9805 u32 val = 0;
9806 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
2de67439 9807 u32 tags_63_32 = 0;
72fd0718
VZ		 9808
9809 /* Empty the Tetris buffer, wait for 1s */
9810 do {
9811 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9812 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9813 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9814 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9815 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
c55e771b
BW		 9816 if (CHIP_IS_E3(bp))
9817 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9818
72fd0718
VZ		 9819 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9820 ((port_is_idle_0 & 0x1) == 0x1) &&
9821 ((port_is_idle_1 & 0x1) == 0x1) &&
c55e771b
BW		 9822 (pgl_exp_rom2 == 0xffffffff) &&
9823 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
72fd0718 9824 break;
0926d499 9825 usleep_range(1000, 2000);
72fd0718
VZ		 9826 } while (cnt-- > 0);
9827
9828 if (cnt <= 0) {
51c1a580
MS		 9829 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9830 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
72fd0718
VZ		 9831 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9832 pgl_exp_rom2);
9833 return -EAGAIN;
9834 }
9835
9836 barrier();
9837
9838 /* Close gates #2, #3 and #4 */
9839 bnx2x_set_234_gates(bp, true);
9840
c9ee9206
VZ		 9841 /* Poll for IGU VQs for 57712 and newer chips */
9842 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9843 return -EAGAIN;
9844
72fd0718
VZ		 9845 /* TBD: Indicate that "process kill" is in progress to MCP */
9846
9847 /* Clear "unprepared" bit */
9848 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9849 barrier();
9850
9851 /* Make sure all is written to the chip before the reset */
9852 mmiowb();
9853
9854 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9855 * PSWHST, GRC and PSWRD Tetris buffer.
9856 */
0926d499 9857 usleep_range(1000, 2000);
72fd0718
VZ		 9858
9859 /* Prepare to chip reset: */
9860 /* MCP */
c9ee9206
VZ		 9861 if (global)
9862 bnx2x_reset_mcp_prep(bp, &val);
72fd0718
VZ		 9863
9864 /* PXP */
9865 bnx2x_pxp_prep(bp);
9866 barrier();
9867
9868 /* reset the chip */
c9ee9206 9869 bnx2x_process_kill_chip_reset(bp, global);
72fd0718
VZ		 9870 barrier();
9871
9dcd9acd
DK		 9872 /* clear errors in PGB */
9873 if (!CHIP_IS_E1x(bp))
9874 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9875
72fd0718
VZ		 9876 /* Recover after reset: */
9877 /* MCP */
c9ee9206 9878 if (global && bnx2x_reset_mcp_comp(bp, val))
72fd0718
VZ		 9879 return -EAGAIN;
9880
c9ee9206
VZ		 9881 /* TBD: Add resetting the NO_MCP mode DB here */
9882
72fd0718
VZ		 9883 /* Open the gates #2, #3 and #4 */
9884 bnx2x_set_234_gates(bp, false);
9885
9886 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9887 * reset state, re-enable attentions. */
9888
a2fbb9ea
ET		 9889 return 0;
9890}
9891
910cc727 9892static int bnx2x_leader_reset(struct bnx2x *bp)
72fd0718
VZ		 9893{
9894 int rc = 0;
c9ee9206 9895 bool global = bnx2x_reset_is_global(bp);
95c6c616
AE		 9896 u32 load_code;
9897
9898 /* if not going to reset MCP - load "fake" driver to reset HW while
9899 * driver is owner of the HW
9900 */
9901 if (!global && !BP_NOMCP(bp)) {
5d07d868
YM		 9902 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9903 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
95c6c616
AE		 9904 if (!load_code) {
9905 BNX2X_ERR("MCP response failure, aborting\n");
9906 rc = -EAGAIN;
9907 goto exit_leader_reset;
9908 }
9909 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9910 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9911 BNX2X_ERR("MCP unexpected resp, aborting\n");
9912 rc = -EAGAIN;
9913 goto exit_leader_reset2;
9914 }
9915 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9916 if (!load_code) {
9917 BNX2X_ERR("MCP response failure, aborting\n");
9918 rc = -EAGAIN;
9919 goto exit_leader_reset2;
9920 }
9921 }
c9ee9206 9922
72fd0718 9923 /* Try to recover after the failure */
c9ee9206 9924 if (bnx2x_process_kill(bp, global)) {
51c1a580
MS		 9925 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9926 BP_PATH(bp));
72fd0718 9927 rc = -EAGAIN;
95c6c616 9928 goto exit_leader_reset2;
72fd0718
VZ		 9929 }
9930
c9ee9206
VZ		 9931 /*
9932 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9933 * state.
9934 */
72fd0718 9935 bnx2x_set_reset_done(bp);
c9ee9206
VZ		 9936 if (global)
9937 bnx2x_clear_reset_global(bp);
72fd0718 9938
95c6c616
AE		 9939exit_leader_reset2:
9940 /* unload "fake driver" if it was loaded */
9941 if (!global && !BP_NOMCP(bp)) {
9942 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9943 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9944 }
72fd0718
VZ		 9945exit_leader_reset:
9946 bp->is_leader = 0;
c9ee9206
VZ		 9947 bnx2x_release_leader_lock(bp);
9948 smp_mb();
72fd0718
VZ		 9949 return rc;
9950}
9951
1191cb83 9952static void bnx2x_recovery_failed(struct bnx2x *bp)
c9ee9206
VZ		 9953{
9954 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9955
9956 /* Disconnect this device */
9957 netif_device_detach(bp->dev);
9958
9959 /*
9960 * Block ifup for all function on this engine until "process kill"
9961 * or power cycle.
9962 */
9963 bnx2x_set_reset_in_progress(bp);
9964
9965 /* Shut down the power */
9966 bnx2x_set_power_state(bp, PCI_D3hot);
9967
9968 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9969
9970 smp_mb();
9971}
9972
9973/*
9974 * Assumption: runs under rtnl lock. This together with the fact
6383c0b3 9975 * that it's called only from bnx2x_sp_rtnl() ensure that it
72fd0718
VZ		 9976 * will never be called when netif_running(bp->dev) is false.
9977 */
9978static void bnx2x_parity_recover(struct bnx2x *bp)
9979{
c9ee9206 9980 bool global = false;
7a752993 9981 u32 error_recovered, error_unrecovered;
95c6c616 9982 bool is_parity;
c9ee9206 9983
72fd0718
VZ		 9984 DP(NETIF_MSG_HW, "Handling parity\n");
9985 while (1) {
9986 switch (bp->recovery_state) {
9987 case BNX2X_RECOVERY_INIT:
9988 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
95c6c616
AE		 9989 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9990 WARN_ON(!is_parity);
c9ee9206 9991
72fd0718 9992 /* Try to get a LEADER_LOCK HW lock */
c9ee9206
VZ		 9993 if (bnx2x_trylock_leader_lock(bp)) {
9994 bnx2x_set_reset_in_progress(bp);
9995 /*
9996 * Check if there is a global attention and if
9997 * there was a global attention, set the global
9998 * reset bit.
9999 */
10000
10001 if (global)
10002 bnx2x_set_reset_global(bp);
10003
72fd0718 10004 bp->is_leader = 1;
c9ee9206 10005 }
72fd0718
VZ		 10006
10007 /* Stop the driver */
10008 /* If interface has been removed - break */
5d07d868 10009 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
72fd0718
VZ		 10010 return;
10011
10012 bp->recovery_state = BNX2X_RECOVERY_WAIT;
c9ee9206 10013
c9ee9206
VZ		 10014 /* Ensure "is_leader", MCP command sequence and
10015 * "recovery_state" update values are seen on other
10016 * CPUs.
72fd0718 10017 */
c9ee9206 10018 smp_mb();
72fd0718
VZ		 10019 break;
10020
10021 case BNX2X_RECOVERY_WAIT:
10022 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
10023 if (bp->is_leader) {
c9ee9206 10024 int other_engine = BP_PATH(bp) ? 0 : 1;
889b9af3
AE		 10025 bool other_load_status =
10026 bnx2x_get_load_status(bp, other_engine);
10027 bool load_status =
10028 bnx2x_get_load_status(bp, BP_PATH(bp));
c9ee9206
VZ		 10029 global = bnx2x_reset_is_global(bp);
10030
10031 /*
10032 * In case of a parity in a global block, let
10033 * the first leader that performs a
10034 * leader_reset() reset the global blocks in
10035 * order to clear global attentions. Otherwise
16a5fd92 10036 * the gates will remain closed for that
c9ee9206
VZ		 10037 * engine.
10038 */
889b9af3
AE		 10039 if (load_status ||
10040 (global && other_load_status)) {
72fd0718
VZ		 10041 /* Wait until all other functions get
10042 * down.
10043 */
7be08a72 10044 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 10045 HZ/10);
10046 return;
10047 } else {
10048 /* If all other functions got down -
10049 * try to bring the chip back to
10050 * normal. In any case it's an exit
10051 * point for a leader.
10052 */
c9ee9206
VZ		 10053 if (bnx2x_leader_reset(bp)) {
10054 bnx2x_recovery_failed(bp);
72fd0718
VZ		 10055 return;
10056 }
10057
c9ee9206
VZ		 10058 /* If we are here, means that the
10059 * leader has succeeded and doesn't
10060 * want to be a leader any more. Try
10061 * to continue as a none-leader.
10062 */
10063 break;
72fd0718
VZ		 10064 }
10065 } else { /* non-leader */
c9ee9206 10066 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
72fd0718
VZ		 10067 /* Try to get a LEADER_LOCK HW lock as
10068 * long as a former leader may have
10069 * been unloaded by the user or
10070 * released a leadership by another
10071 * reason.
10072 */
c9ee9206 10073 if (bnx2x_trylock_leader_lock(bp)) {
72fd0718
VZ		 10074 /* I'm a leader now! Restart a
10075 * switch case.
10076 */
10077 bp->is_leader = 1;
10078 break;
10079 }
10080
7be08a72 10081 schedule_delayed_work(&bp->sp_rtnl_task,
72fd0718
VZ		 10082 HZ/10);
10083 return;
10084
c9ee9206
VZ		 10085 } else {
10086 /*
10087 * If there was a global attention, wait
10088 * for it to be cleared.
10089 */
10090 if (bnx2x_reset_is_global(bp)) {
10091 schedule_delayed_work(
7be08a72
AE		 10092 &bp->sp_rtnl_task,
10093 HZ/10);
c9ee9206
VZ		 10094 return;
10095 }
10096
7a752993
AE		 10097 error_recovered =
10098 bp->eth_stats.recoverable_error;
10099 error_unrecovered =
10100 bp->eth_stats.unrecoverable_error;
95c6c616
AE		 10101 bp->recovery_state =
10102 BNX2X_RECOVERY_NIC_LOADING;
10103 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
7a752993 10104 error_unrecovered++;
95c6c616 10105 netdev_err(bp->dev,
51c1a580 10106 "Recovery failed. Power cycle needed\n");
95c6c616
AE		 10107 /* Disconnect this device */
10108 netif_device_detach(bp->dev);
10109 /* Shut down the power */
10110 bnx2x_set_power_state(
10111 bp, PCI_D3hot);
10112 smp_mb();
10113 } else {
c9ee9206
VZ		 10114 bp->recovery_state =
10115 BNX2X_RECOVERY_DONE;
7a752993 10116 error_recovered++;
c9ee9206
VZ		 10117 smp_mb();
10118 }
7a752993
AE		 10119 bp->eth_stats.recoverable_error =
10120 error_recovered;
10121 bp->eth_stats.unrecoverable_error =
10122 error_unrecovered;
c9ee9206 10123
72fd0718
VZ		 10124 return;
10125 }
10126 }
10127 default:
10128 return;
10129 }
10130 }
10131}
10132
883ce97d 10133static int bnx2x_udp_port_update(struct bnx2x *bp)
f34fa14c
RB		 10134{
10135 struct bnx2x_func_switch_update_params *switch_update_params;
10136 struct bnx2x_func_state_params func_params = {NULL};
883ce97d
YM		 10137 struct bnx2x_udp_tunnel *udp_tunnel;
10138 u16 vxlan_port = 0, geneve_port = 0;
f34fa14c
RB		 10139 int rc;
10140
10141 switch_update_params = &func_params.params.switch_update;
10142
10143 /* Prepare parameters for function state transitions */
10144 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
10145 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
10146
10147 func_params.f_obj = &bp->func_obj;
10148 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
10149
10150 /* Function parameters */
10151 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
10152 &switch_update_params->changes);
883ce97d
YM		 10153
10154 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count) {
10155 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE];
10156 geneve_port = udp_tunnel->dst_port;
10157 switch_update_params->geneve_dst_port = geneve_port;
10158 }
10159
10160 if (bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count) {
10161 udp_tunnel = &bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN];
10162 vxlan_port = udp_tunnel->dst_port;
10163 switch_update_params->vxlan_dst_port = vxlan_port;
10164 }
10165
10166 /* Re-enable inner-rss for the offloaded UDP tunnels */
10167 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
10168 &switch_update_params->changes);
10169
f34fa14c
RB		 10170 rc = bnx2x_func_state_change(bp, &func_params);
10171 if (rc)
883ce97d
YM		 10172 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10173 vxlan_port, geneve_port, rc);
10174 else
10175 DP(BNX2X_MSG_SP,
10176 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10177 vxlan_port, geneve_port);
10178
f34fa14c
RB		 10179 return rc;
10180}
10181
883ce97d
YM		 10182static void __bnx2x_add_udp_port(struct bnx2x *bp, u16 port,
10183 enum bnx2x_udp_port_type type)
f34fa14c 10184{
883ce97d
YM		 10185 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10186
360d9df2 10187 if (!netif_running(bp->dev) || !IS_PF(bp) || CHIP_IS_E1x(bp))
883ce97d
YM		 10188 return;
10189
10190 if (udp_port->count && udp_port->dst_port == port) {
10191 udp_port->count++;
f34fa14c 10192 return;
883ce97d 10193 }
f34fa14c 10194
883ce97d
YM		 10195 if (udp_port->count) {
10196 DP(BNX2X_MSG_SP,
10197 "UDP tunnel [%d] - destination port limit reached\n",
10198 type);
ac7eccd4
JB		 10199 return;
10200 }
10201
883ce97d
YM		 10202 udp_port->dst_port = port;
10203 udp_port->count = 1;
10204 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10205}
10206
10207static void __bnx2x_del_udp_port(struct bnx2x *bp, u16 port,
10208 enum bnx2x_udp_port_type type)
10209{
10210 struct bnx2x_udp_tunnel *udp_port = &bp->udp_tunnel_ports[type];
10211
360d9df2 10212 if (!IS_PF(bp) || CHIP_IS_E1x(bp))
883ce97d
YM		 10213 return;
10214
10215 if (!udp_port->count || udp_port->dst_port != port) {
10216 DP(BNX2X_MSG_SP, "Invalid UDP tunnel [%d] port\n",
10217 type);
f34fa14c
RB		 10218 return;
10219 }
10220
883ce97d
YM		 10221 /* Remove reference, and make certain it's no longer in use */
10222 udp_port->count--;
10223 if (udp_port->count)
10224 return;
10225 udp_port->dst_port = 0;
10226
10227 if (netif_running(bp->dev))
10228 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_CHANGE_UDP_PORT, 0);
10229 else
10230 DP(BNX2X_MSG_SP, "Deleted UDP tunnel [%d] port %d\n",
10231 type, port);
f34fa14c 10232}
883ce97d 10233
6b352912
AD		 10234static void bnx2x_udp_tunnel_add(struct net_device *netdev,
10235 struct udp_tunnel_info *ti)
883ce97d
YM		 10236{
10237 struct bnx2x *bp = netdev_priv(netdev);
6b352912 10238 u16 t_port = ntohs(ti->port);
883ce97d 10239
6b352912
AD		 10240 switch (ti->type) {
10241 case UDP_TUNNEL_TYPE_VXLAN:
10242 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10243 break;
10244 case UDP_TUNNEL_TYPE_GENEVE:
10245 __bnx2x_add_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10246 break;
10247 default:
10248 break;
10249 }
f34fa14c
RB		 10250}
10251
6b352912
AD		 10252static void bnx2x_udp_tunnel_del(struct net_device *netdev,
10253 struct udp_tunnel_info *ti)
f34fa14c
RB		 10254{
10255 struct bnx2x *bp = netdev_priv(netdev);
6b352912 10256 u16 t_port = ntohs(ti->port);
f34fa14c 10257
6b352912
AD		 10258 switch (ti->type) {
10259 case UDP_TUNNEL_TYPE_VXLAN:
10260 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_VXLAN);
10261 break;
10262 case UDP_TUNNEL_TYPE_GENEVE:
10263 __bnx2x_del_udp_port(bp, t_port, BNX2X_UDP_PORT_GENEVE);
10264 break;
10265 default:
10266 break;
10267 }
f34fa14c 10268}
f34fa14c 10269
56ad3152
MS		 10270static int bnx2x_close(struct net_device *dev);
10271
72fd0718
VZ		 10272/* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10273 * scheduled on a general queue in order to prevent a dead lock.
10274 */
7be08a72 10275static void bnx2x_sp_rtnl_task(struct work_struct *work)
34f80b04 10276{
7be08a72 10277 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
34f80b04
EG		 10278
10279 rtnl_lock();
10280
8395be5e
AE		 10281 if (!netif_running(bp->dev)) {
10282 rtnl_unlock();
10283 return;
10284 }
7be08a72 10285
6bf07b8e 10286 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
7be08a72 10287#ifdef BNX2X_STOP_ON_ERROR
6bf07b8e
YM		 10288 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10289 "you will need to reboot when done\n");
10290 goto sp_rtnl_not_reset;
7be08a72 10291#endif
7be08a72 10292 /*
b1fb8740
VZ		 10293 * Clear all pending SP commands as we are going to reset the
10294 * function anyway.
7be08a72 10295 */
b1fb8740
VZ		 10296 bp->sp_rtnl_state = 0;
10297 smp_mb();
10298
72fd0718 10299 bnx2x_parity_recover(bp);
b1fb8740 10300
8395be5e
AE		 10301 rtnl_unlock();
10302 return;
b1fb8740
VZ		 10303 }
10304
10305 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
6bf07b8e
YM		 10306#ifdef BNX2X_STOP_ON_ERROR
10307 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10308 "you will need to reboot when done\n");
10309 goto sp_rtnl_not_reset;
10310#endif
10311
b1fb8740
VZ		 10312 /*
10313 * Clear all pending SP commands as we are going to reset the
10314 * function anyway.
10315 */
10316 bp->sp_rtnl_state = 0;
10317 smp_mb();
10318
484c016d
SRK		 10319 /* Immediately indicate link as down */
10320 bp->link_vars.link_up = 0;
10321 bp->force_link_down = true;
10322 netif_carrier_off(bp->dev);
10323 BNX2X_ERR("Indicating link is down due to Tx-timeout\n");
10324
5d07d868 10325 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
442866ff
ZY		 10326 /* When ret value shows failure of allocation failure,
10327 * the nic is rebooted again. If open still fails, a error
10328 * message to notify the user.
10329 */
10330 if (bnx2x_nic_load(bp, LOAD_NORMAL) == -ENOMEM) {
10331 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10332 if (bnx2x_nic_load(bp, LOAD_NORMAL))
10333 BNX2X_ERR("Open the NIC fails again!\n");
10334 }
8395be5e
AE		 10335 rtnl_unlock();
10336 return;
72fd0718 10337 }
b1fb8740
VZ		 10338#ifdef BNX2X_STOP_ON_ERROR
10339sp_rtnl_not_reset:
10340#endif
10341 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10342 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
a3348722
BW		 10343 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10344 bnx2x_after_function_update(bp);
8304859a
AE		 10345 /*
10346 * in case of fan failure we need to reset id if the "stop on error"
10347 * debug flag is set, since we trying to prevent permanent overheating
10348 * damage
10349 */
10350 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
51c1a580 10351 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8304859a
AE		 10352 netif_device_detach(bp->dev);
10353 bnx2x_close(bp->dev);
8395be5e
AE		 10354 rtnl_unlock();
10355 return;
8304859a
AE		 10356 }
10357
381ac16b
AE		 10358 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10359 DP(BNX2X_MSG_SP,
10360 "sending set mcast vf pf channel message from rtnl sp-task\n");
10361 bnx2x_vfpf_set_mcast(bp->dev);
10362 }
78c3bcc5
AE		 10363 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10364 &bp->sp_rtnl_state)){
3fdd34c1 10365 if (netif_carrier_ok(bp->dev)) {
78c3bcc5
AE		 10366 bnx2x_tx_disable(bp);
10367 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10368 }
10369 }
381ac16b 10370
8b09be5f
YM		 10371 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10372 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10373 bnx2x_set_rx_mode_inner(bp);
381ac16b
AE		 10374 }
10375
3ec9f9ca
AE		 10376 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10377 &bp->sp_rtnl_state))
10378 bnx2x_pf_set_vfs_vlan(bp);
10379
6ffa39f2 10380 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
07b4eb3b 10381 bnx2x_dcbx_stop_hw_tx(bp);
07b4eb3b 10382 bnx2x_dcbx_resume_hw_tx(bp);
6ffa39f2 10383 }
07b4eb3b 10384
42f8277f
YM		 10385 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10386 &bp->sp_rtnl_state))
10387 bnx2x_update_mng_version(bp);
10388
883ce97d 10389 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT,
f34fa14c 10390 &bp->sp_rtnl_state)) {
883ce97d
YM		 10391 if (bnx2x_udp_port_update(bp)) {
10392 /* On error, forget configuration */
10393 memset(bp->udp_tunnel_ports, 0,
10394 sizeof(struct bnx2x_udp_tunnel) *
10395 BNX2X_UDP_PORT_MAX);
10396 } else {
10397 /* Since we don't store additional port information,
6b352912 10398 * if no ports are configured for any feature ask for
883ce97d
YM		 10399 * information about currently configured ports.
10400 */
6b352912
AD		 10401 if (!bp->udp_tunnel_ports[BNX2X_UDP_PORT_VXLAN].count &&
10402 !bp->udp_tunnel_ports[BNX2X_UDP_PORT_GENEVE].count)
10403 udp_tunnel_get_rx_info(bp->dev);
f34fa14c
RB		 10404 }
10405 }
f34fa14c 10406
8395be5e
AE		 10407 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10408 * can be called from other contexts as well)
10409 */
34f80b04 10410 rtnl_unlock();
8395be5e 10411
6411280a 10412 /* enable SR-IOV if applicable */
8395be5e 10413 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
3c76feff
AE		 10414 &bp->sp_rtnl_state)) {
10415 bnx2x_disable_sriov(bp);
6411280a 10416 bnx2x_enable_sriov(bp);
3c76feff 10417 }
34f80b04
EG		 10418}
10419
3deb8167
YR		 10420static void bnx2x_period_task(struct work_struct *work)
10421{
10422 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10423
10424 if (!netif_running(bp->dev))
10425 goto period_task_exit;
10426
10427 if (CHIP_REV_IS_SLOW(bp)) {
10428 BNX2X_ERR("period task called on emulation, ignoring\n");
10429 goto period_task_exit;
10430 }
10431
10432 bnx2x_acquire_phy_lock(bp);
10433 /*
10434 * The barrier is needed to ensure the ordering between the writing to
10435 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10436 * the reading here.
10437 */
10438 smp_mb();
10439 if (bp->port.pmf) {
10440 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10441
10442 /* Re-queue task in 1 sec */
10443 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10444 }
10445
10446 bnx2x_release_phy_lock(bp);
10447period_task_exit:
10448 return;
10449}
10450
a2fbb9ea
ET		 10451/*
10452 * Init service functions
10453 */
10454
a8f47eb7 10455static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
f2e0899f
DK		 10456{
10457 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10458 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10459 return base + (BP_ABS_FUNC(bp)) * stride;
f1ef27ef
EG		 10460}
10461
3d6b7253
YM		 10462static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp,
10463 u8 port, u32 reset_reg,
10464 struct bnx2x_mac_vals *vals)
10465{
10466 u32 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10467 u32 base_addr;
10468
10469 if (!(mask & reset_reg))
10470 return false;
10471
10472 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port);
10473 base_addr = port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10474 vals->umac_addr[port] = base_addr + UMAC_REG_COMMAND_CONFIG;
10475 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]);
10476 REG_WR(bp, vals->umac_addr[port], 0);
10477
10478 return true;
10479}
10480
1ef1d45a
BW		 10481static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10482 struct bnx2x_mac_vals *vals)
34f80b04 10483{
452427b0
YM		 10484 u32 val, base_addr, offset, mask, reset_reg;
10485 bool mac_stopped = false;
10486 u8 port = BP_PORT(bp);
34f80b04 10487
1ef1d45a 10488 /* reset addresses as they also mark which values were changed */
3d6b7253 10489 memset(vals, 0, sizeof(*vals));
1ef1d45a 10490
452427b0 10491 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
f16da43b 10492
452427b0
YM		 10493 if (!CHIP_IS_E3(bp)) {
10494 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10495 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10496 if ((mask & reset_reg) && val) {
10497 u32 wb_data[2];
10498 BNX2X_DEV_INFO("Disable bmac Rx\n");
10499 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10500 : NIG_REG_INGRESS_BMAC0_MEM;
10501 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10502 : BIGMAC_REGISTER_BMAC_CONTROL;
7a06a122 10503
452427b0
YM		 10504 /*
10505 * use rd/wr since we cannot use dmae. This is safe
10506 * since MCP won't access the bus due to the request
10507 * to unload, and no function on the path can be
10508 * loaded at this time.
10509 */
10510 wb_data[0] = REG_RD(bp, base_addr + offset);
10511 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
1ef1d45a
BW		 10512 vals->bmac_addr = base_addr + offset;
10513 vals->bmac_val[0] = wb_data[0];
10514 vals->bmac_val[1] = wb_data[1];
452427b0 10515 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1ef1d45a
BW		 10516 REG_WR(bp, vals->bmac_addr, wb_data[0]);
10517 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
452427b0
YM		 10518 }
10519 BNX2X_DEV_INFO("Disable emac Rx\n");
1ef1d45a
BW		 10520 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10521 vals->emac_val = REG_RD(bp, vals->emac_addr);
10522 REG_WR(bp, vals->emac_addr, 0);
452427b0
YM		 10523 mac_stopped = true;
10524 } else {
10525 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10526 BNX2X_DEV_INFO("Disable xmac Rx\n");
10527 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10528 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10529 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10530 val & ~(1 << 1));
10531 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10532 val | (1 << 1));
1ef1d45a
BW		 10533 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10534 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10535 REG_WR(bp, vals->xmac_addr, 0);
452427b0
YM		 10536 mac_stopped = true;
10537 }
3d6b7253
YM		 10538
10539 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0,
10540 reset_reg, vals);
10541 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1,
10542 reset_reg, vals);
452427b0
YM		 10543 }
10544
10545 if (mac_stopped)
10546 msleep(20);
452427b0
YM		 10547}
10548
10549#define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
7c3afd85
YM		 10550#define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10551 0x1848 + ((f) << 4))
452427b0
YM		 10552#define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10553#define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10554#define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10555
91ebb929
YM		 10556#define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10557#define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10558#define BCM_5710_UNDI_FW_MF_VERS (0x05)
b17b0ca1
YM		 10559
10560static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10561{
10562 /* UNDI marks its presence in DORQ -
10563 * it initializes CID offset for normal bell to 0x7
10564 */
10565 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10566 MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10567 return false;
10568
10569 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10570 BNX2X_DEV_INFO("UNDI previously loaded\n");
10571 return true;
10572 }
10573
10574 return false;
10575}
10576
7c3afd85 10577static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
452427b0
YM		 10578{
10579 u16 rcq, bd;
7c3afd85 10580 u32 addr, tmp_reg;
452427b0 10581
7c3afd85
YM		 10582 if (BP_FUNC(bp) < 2)
10583 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10584 else
10585 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10586
10587 tmp_reg = REG_RD(bp, addr);
452427b0
YM		 10588 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10589 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10590
10591 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
7c3afd85 10592 REG_WR(bp, addr, tmp_reg);
452427b0 10593
7c3afd85
YM		 10594 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10595 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
452427b0
YM		 10596}
10597
0329aba1 10598static int bnx2x_prev_mcp_done(struct bnx2x *bp)
452427b0 10599{
5d07d868
YM		 10600 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10601 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
452427b0
YM		 10602 if (!rc) {
10603 BNX2X_ERR("MCP response failure, aborting\n");
10604 return -EBUSY;
10605 }
10606
10607 return 0;
10608}
10609
c63da990
BW		 10610static struct bnx2x_prev_path_list *
10611 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10612{
10613 struct bnx2x_prev_path_list *tmp_list;
10614
10615 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10616 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10617 bp->pdev->bus->number == tmp_list->bus &&
10618 BP_PATH(bp) == tmp_list->path)
10619 return tmp_list;
10620
10621 return NULL;
10622}
10623
7fa6f340
YM		 10624static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10625{
10626 struct bnx2x_prev_path_list *tmp_list;
10627 int rc;
10628
10629 rc = down_interruptible(&bnx2x_prev_sem);
10630 if (rc) {
10631 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10632 return rc;
10633 }
10634
10635 tmp_list = bnx2x_prev_path_get_entry(bp);
10636 if (tmp_list) {
10637 tmp_list->aer = 1;
10638 rc = 0;
10639 } else {
10640 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10641 BP_PATH(bp));
10642 }
10643
10644 up(&bnx2x_prev_sem);
10645
10646 return rc;
10647}
10648
0329aba1 10649static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
452427b0
YM		 10650{
10651 struct bnx2x_prev_path_list *tmp_list;
b85d717c 10652 bool rc = false;
452427b0
YM		 10653
10654 if (down_trylock(&bnx2x_prev_sem))
10655 return false;
10656
7fa6f340
YM		 10657 tmp_list = bnx2x_prev_path_get_entry(bp);
10658 if (tmp_list) {
10659 if (tmp_list->aer) {
10660 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10661 BP_PATH(bp));
10662 } else {
452427b0
YM		 10663 rc = true;
10664 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10665 BP_PATH(bp));
452427b0
YM		 10666 }
10667 }
10668
10669 up(&bnx2x_prev_sem);
10670
10671 return rc;
10672}
10673
178135c1
DK		 10674bool bnx2x_port_after_undi(struct bnx2x *bp)
10675{
10676 struct bnx2x_prev_path_list *entry;
10677 bool val;
10678
10679 down(&bnx2x_prev_sem);
10680
10681 entry = bnx2x_prev_path_get_entry(bp);
10682 val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10683
10684 up(&bnx2x_prev_sem);
10685
10686 return val;
10687}
10688
c63da990 10689static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
452427b0
YM		 10690{
10691 struct bnx2x_prev_path_list *tmp_list;
10692 int rc;
10693
7fa6f340
YM		 10694 rc = down_interruptible(&bnx2x_prev_sem);
10695 if (rc) {
10696 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10697 return rc;
10698 }
10699
10700 /* Check whether the entry for this path already exists */
10701 tmp_list = bnx2x_prev_path_get_entry(bp);
10702 if (tmp_list) {
10703 if (!tmp_list->aer) {
10704 BNX2X_ERR("Re-Marking the path.\n");
10705 } else {
10706 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10707 BP_PATH(bp));
10708 tmp_list->aer = 0;
10709 }
10710 up(&bnx2x_prev_sem);
10711 return 0;
10712 }
10713 up(&bnx2x_prev_sem);
10714
10715 /* Create an entry for this path and add it */
ea4b3857 10716 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
452427b0
YM		 10717 if (!tmp_list) {
10718 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10719 return -ENOMEM;
10720 }
10721
10722 tmp_list->bus = bp->pdev->bus->number;
10723 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10724 tmp_list->path = BP_PATH(bp);
7fa6f340 10725 tmp_list->aer = 0;
c63da990 10726 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
452427b0
YM		 10727
10728 rc = down_interruptible(&bnx2x_prev_sem);
10729 if (rc) {
10730 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10731 kfree(tmp_list);
10732 } else {
7fa6f340
YM		 10733 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10734 BP_PATH(bp));
452427b0
YM		 10735 list_add(&tmp_list->list, &bnx2x_prev_list);
10736 up(&bnx2x_prev_sem);
10737 }
10738
10739 return rc;
10740}
10741
0329aba1 10742static int bnx2x_do_flr(struct bnx2x *bp)
452427b0 10743{
452427b0
YM		 10744 struct pci_dev *dev = bp->pdev;
10745
8eee694c
YM		 10746 if (CHIP_IS_E1x(bp)) {
10747 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10748 return -EINVAL;
10749 }
10750
10751 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10752 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10753 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10754 bp->common.bc_ver);
10755 return -EINVAL;
10756 }
452427b0 10757
8903b9eb
CL		 10758 if (!pci_wait_for_pending_transaction(dev))
10759 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
452427b0 10760
8eee694c 10761 BNX2X_DEV_INFO("Initiating FLR\n");
452427b0
YM		 10762 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10763
10764 return 0;
10765}
10766
0329aba1 10767static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
452427b0
YM		 10768{
10769 int rc;
10770
10771 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10772
10773 /* Test if previous unload process was already finished for this path */
10774 if (bnx2x_prev_is_path_marked(bp))
10775 return bnx2x_prev_mcp_done(bp);
10776
04c46736
YM		 10777 BNX2X_DEV_INFO("Path is unmarked\n");
10778
b17b0ca1
YM		 10779 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10780 if (bnx2x_prev_is_after_undi(bp))
10781 goto out;
10782
452427b0
YM		 10783 /* If function has FLR capabilities, and existing FW version matches
10784 * the one required, then FLR will be sufficient to clean any residue
10785 * left by previous driver
10786 */
91ebb929 10787 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
8eee694c
YM		 10788
10789 if (!rc) {
10790 /* fw version is good */
10791 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10792 rc = bnx2x_do_flr(bp);
10793 }
10794
10795 if (!rc) {
10796 /* FLR was performed */
10797 BNX2X_DEV_INFO("FLR successful\n");
10798 return 0;
10799 }
10800
10801 BNX2X_DEV_INFO("Could not FLR\n");
452427b0 10802
b17b0ca1 10803out:
452427b0
YM		 10804 /* Close the MCP request, return failure*/
10805 rc = bnx2x_prev_mcp_done(bp);
10806 if (!rc)
10807 rc = BNX2X_PREV_WAIT_NEEDED;
10808
10809 return rc;
10810}
10811
0329aba1 10812static int bnx2x_prev_unload_common(struct bnx2x *bp)
452427b0
YM		 10813{
10814 u32 reset_reg, tmp_reg = 0, rc;
c63da990 10815 bool prev_undi = false;
1ef1d45a
BW		 10816 struct bnx2x_mac_vals mac_vals;
10817
452427b0
YM		 10818 /* It is possible a previous function received 'common' answer,
10819 * but hasn't loaded yet, therefore creating a scenario of
10820 * multiple functions receiving 'common' on the same path.
10821 */
10822 BNX2X_DEV_INFO("Common unload Flow\n");
10823
1ef1d45a
BW		 10824 memset(&mac_vals, 0, sizeof(mac_vals));
10825
452427b0
YM		 10826 if (bnx2x_prev_is_path_marked(bp))
10827 return bnx2x_prev_mcp_done(bp);
10828
10829 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10830
10831 /* Reset should be performed after BRB is emptied */
10832 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10833 u32 timer_count = 1000;
452427b0
YM		 10834
10835 /* Close the MAC Rx to prevent BRB from filling up */
1ef1d45a
BW		 10836 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10837
3d6b7253 10838 /* close LLH filters for both ports towards the BRB */
1ef1d45a 10839 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10840 bp->link_params.port ^= 1;
1ef1d45a 10841 bnx2x_set_rx_filter(&bp->link_params, 0);
3d6b7253 10842 bp->link_params.port ^= 1;
452427b0 10843
b17b0ca1
YM		 10844 /* Check if the UNDI driver was previously loaded */
10845 if (bnx2x_prev_is_after_undi(bp)) {
10846 prev_undi = true;
10847 /* clear the UNDI indication */
10848 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10849 /* clear possible idle check errors */
10850 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
452427b0 10851 }
d46f7c4d
DK		 10852 if (!CHIP_IS_E1x(bp))
10853 /* block FW from writing to host */
10854 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10855
452427b0
YM		 10856 /* wait until BRB is empty */
10857 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10858 while (timer_count) {
10859 u32 prev_brb = tmp_reg;
34f80b04 10860
452427b0
YM		 10861 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10862 if (!tmp_reg)
10863 break;
619c5cb6 10864
452427b0 10865 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
619c5cb6 10866
452427b0
YM		 10867 /* reset timer as long as BRB actually gets emptied */
10868 if (prev_brb > tmp_reg)
10869 timer_count = 1000;
10870 else
10871 timer_count--;
da5a662a 10872
7c3afd85
YM		 10873 /* If UNDI resides in memory, manually increment it */
10874 if (prev_undi)
10875 bnx2x_prev_unload_undi_inc(bp, 1);
10876
452427b0 10877 udelay(10);
7a06a122 10878 }
452427b0
YM		 10879
10880 if (!timer_count)
10881 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
34f80b04 10882 }
f16da43b 10883
452427b0
YM		 10884 /* No packets are in the pipeline, path is ready for reset */
10885 bnx2x_reset_common(bp);
10886
1ef1d45a
BW		 10887 if (mac_vals.xmac_addr)
10888 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
3d6b7253
YM		 10889 if (mac_vals.umac_addr[0])
10890 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]);
10891 if (mac_vals.umac_addr[1])
10892 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]);
1ef1d45a
BW		 10893 if (mac_vals.emac_addr)
10894 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10895 if (mac_vals.bmac_addr) {
10896 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10897 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10898 }
10899
c63da990 10900 rc = bnx2x_prev_mark_path(bp, prev_undi);
452427b0
YM		 10901 if (rc) {
10902 bnx2x_prev_mcp_done(bp);
10903 return rc;
10904 }
10905
10906 return bnx2x_prev_mcp_done(bp);
10907}
10908
0329aba1 10909static int bnx2x_prev_unload(struct bnx2x *bp)
452427b0
YM		 10910{
10911 int time_counter = 10;
10912 u32 rc, fw, hw_lock_reg, hw_lock_val;
10913 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10914
24f06716
AE		 10915 /* clear hw from errors which may have resulted from an interrupted
10916 * dmae transaction.
10917 */
da254fbc 10918 bnx2x_clean_pglue_errors(bp);
24f06716
AE		 10919
10920 /* Release previously held locks */
452427b0
YM		 10921 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10922 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10923 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10924
3cdeec22 10925 hw_lock_val = REG_RD(bp, hw_lock_reg);
452427b0
YM		 10926 if (hw_lock_val) {
10927 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10928 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10929 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10930 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10931 }
10932
10933 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10934 REG_WR(bp, hw_lock_reg, 0xffffffff);
10935 } else
10936 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10937
10938 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10939 BNX2X_DEV_INFO("Release previously held alr\n");
3cdeec22 10940 bnx2x_release_alr(bp);
452427b0
YM		 10941 }
10942
452427b0 10943 do {
7fa6f340 10944 int aer = 0;
452427b0
YM		 10945 /* Lock MCP using an unload request */
10946 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10947 if (!fw) {
10948 BNX2X_ERR("MCP response failure, aborting\n");
10949 rc = -EBUSY;
10950 break;
10951 }
10952
7fa6f340
YM		 10953 rc = down_interruptible(&bnx2x_prev_sem);
10954 if (rc) {
10955 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10956 rc);
10957 } else {
10958 /* If Path is marked by EEH, ignore unload status */
10959 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10960 bnx2x_prev_path_get_entry(bp)->aer);
60cde81f 10961 up(&bnx2x_prev_sem);
7fa6f340 10962 }
7fa6f340
YM		 10963
10964 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
452427b0
YM		 10965 rc = bnx2x_prev_unload_common(bp);
10966 break;
10967 }
10968
16a5fd92 10969 /* non-common reply from MCP might require looping */
452427b0
YM		 10970 rc = bnx2x_prev_unload_uncommon(bp);
10971 if (rc != BNX2X_PREV_WAIT_NEEDED)
10972 break;
10973
10974 msleep(20);
10975 } while (--time_counter);
10976
10977 if (!time_counter || rc) {
91ebb929
YM		 10978 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10979 rc = -EPROBE_DEFER;
452427b0
YM		 10980 }
10981
c63da990 10982 /* Mark function if its port was used to boot from SAN */
178135c1 10983 if (bnx2x_port_after_undi(bp))
c63da990
BW		 10984 bp->link_params.feature_config_flags |=
10985 FEATURE_CONFIG_BOOT_FROM_SAN;
10986
452427b0
YM		 10987 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10988
10989 return rc;
34f80b04
EG		 10990}
10991
0329aba1 10992static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
34f80b04 10993{
1d187b34 10994 u32 val, val2, val3, val4, id, boot_mode;
72ce58c3 10995 u16 pmc;
34f80b04
EG		 10996
10997 /* Get the chip revision id and number. */
10998 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10999 val = REG_RD(bp, MISC_REG_CHIP_NUM);
11000 id = ((val & 0xffff) << 16);
11001 val = REG_RD(bp, MISC_REG_CHIP_REV);
11002 id |= ((val & 0xf) << 12);
f22fdf25
YM		 11003
11004 /* Metal is read from PCI regs, but we can't access >=0x400 from
11005 * the configuration space (so we need to reg_rd)
11006 */
11007 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
11008 id |= (((val >> 24) & 0xf) << 4);
5a40e08e 11009 val = REG_RD(bp, MISC_REG_BOND_ID);
34f80b04
EG		 11010 id |= (val & 0xf);
11011 bp->common.chip_id = id;
523224a3 11012
7e8e02df
BW		 11013 /* force 57811 according to MISC register */
11014 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
11015 if (CHIP_IS_57810(bp))
11016 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
11017 (bp->common.chip_id & 0x0000FFFF);
11018 else if (CHIP_IS_57810_MF(bp))
11019 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
11020 (bp->common.chip_id & 0x0000FFFF);
11021 bp->common.chip_id |= 0x1;
11022 }
11023
523224a3
DK		 11024 /* Set doorbell size */
11025 bp->db_size = (1 << BNX2X_DB_SHIFT);
11026
619c5cb6 11027 if (!CHIP_IS_E1x(bp)) {
f2e0899f
DK		 11028 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
11029 if ((val & 1) == 0)
11030 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
11031 else
11032 val = (val >> 1) & 1;
11033 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
11034 "2_PORT_MODE");
11035 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
11036 CHIP_2_PORT_MODE;
11037
11038 if (CHIP_MODE_IS_4_PORT(bp))
11039 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
11040 else
11041 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
11042 } else {
11043 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
11044 bp->pfid = bp->pf_num; /* 0..7 */
11045 }
11046
51c1a580
MS		 11047 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
11048
f2e0899f
DK		 11049 bp->link_params.chip_id = bp->common.chip_id;
11050 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
523224a3 11051
1c06328c
EG		 11052 val = (REG_RD(bp, 0x2874) & 0x55);
11053 if ((bp->common.chip_id & 0x1) ||
11054 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
11055 bp->flags |= ONE_PORT_FLAG;
11056 BNX2X_DEV_INFO("single port device\n");
11057 }
11058
34f80b04 11059 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
754a2f52 11060 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
34f80b04
EG		 11061 (val & MCPR_NVM_CFG4_FLASH_SIZE));
11062 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11063 bp->common.flash_size, bp->common.flash_size);
11064
1b6e2ceb
DK		 11065 bnx2x_init_shmem(bp);
11066
f2e0899f
DK		 11067 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
11068 MISC_REG_GENERIC_CR_1 :
11069 MISC_REG_GENERIC_CR_0));
1b6e2ceb 11070
34f80b04 11071 bp->link_params.shmem_base = bp->common.shmem_base;
a22f0788 11072 bp->link_params.shmem2_base = bp->common.shmem2_base;
b884d95b
YR		 11073 if (SHMEM2_RD(bp, size) >
11074 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
11075 bp->link_params.lfa_base =
11076 REG_RD(bp, bp->common.shmem2_base +
11077 (u32)offsetof(struct shmem2_region,
11078 lfa_host_addr[BP_PORT(bp)]));
11079 else
11080 bp->link_params.lfa_base = 0;
2691d51d
EG		 11081 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11082 bp->common.shmem_base, bp->common.shmem2_base);
34f80b04 11083
f2e0899f 11084 if (!bp->common.shmem_base) {
34f80b04
EG		 11085 BNX2X_DEV_INFO("MCP not active\n");
11086 bp->flags |= NO_MCP_FLAG;
11087 return;
11088 }
11089
34f80b04 11090 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
35b19ba5 11091 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
34f80b04
EG		 11092
11093 bp->link_params.hw_led_mode = ((bp->common.hw_config &
11094 SHARED_HW_CFG_LED_MODE_MASK) >>
11095 SHARED_HW_CFG_LED_MODE_SHIFT);
11096
c2c8b03e
EG		 11097 bp->link_params.feature_config_flags = 0;
11098 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
11099 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
11100 bp->link_params.feature_config_flags |=
11101 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11102 else
11103 bp->link_params.feature_config_flags &=
11104 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
11105
34f80b04
EG		 11106 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
11107 bp->common.bc_ver = val;
11108 BNX2X_DEV_INFO("bc_ver %X\n", val);
11109 if (val < BNX2X_BC_VER) {
11110 /* for now only warn
11111 * later we might need to enforce this */
51c1a580
MS		 11112 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11113 BNX2X_BC_VER, val);
34f80b04 11114 }
4d295db0 11115 bp->link_params.feature_config_flags |=
a22f0788 11116 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
f85582f8
DK		 11117 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
11118
a22f0788
YR		 11119 bp->link_params.feature_config_flags |=
11120 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
11121 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
a3348722
BW		 11122 bp->link_params.feature_config_flags |=
11123 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
11124 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
85242eea
YR		 11125 bp->link_params.feature_config_flags |=
11126 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
11127 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
55386fe8
YR		 11128
11129 bp->link_params.feature_config_flags |=
11130 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
11131 FEATURE_CONFIG_MT_SUPPORT : 0;
11132
0e898dd7
BW		 11133 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
11134 BC_SUPPORTS_PFC_STATS : 0;
85242eea 11135
2e499d3c
BW		 11136 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
11137 BC_SUPPORTS_FCOE_FEATURES : 0;
11138
9876879f
BW		 11139 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
11140 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
a6d3a5ba
BW		 11141
11142 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
11143 BC_SUPPORTS_RMMOD_CMD : 0;
11144
1d187b34
BW		 11145 boot_mode = SHMEM_RD(bp,
11146 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
11147 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
11148 switch (boot_mode) {
11149 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
11150 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
11151 break;
11152 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
11153 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
11154 break;
11155 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
11156 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
11157 break;
11158 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
11159 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
11160 break;
11161 }
11162
29ed74c3 11163 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
f9a3ebbe
DK		 11164 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
11165
72ce58c3 11166 BNX2X_DEV_INFO("%sWoL capable\n",
f5372251 11167 (bp->flags & NO_WOL_FLAG) ? "not " : "");
34f80b04
EG		 11168
11169 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
11170 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
11171 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
11172 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
11173
cdaa7cb8
VZ		 11174 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
11175 val, val2, val3, val4);
34f80b04
EG		 11176}
11177
f2e0899f
DK		 11178#define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11179#define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11180
0329aba1 11181static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
f2e0899f
DK		 11182{
11183 int pfid = BP_FUNC(bp);
f2e0899f
DK		 11184 int igu_sb_id;
11185 u32 val;
6383c0b3 11186 u8 fid, igu_sb_cnt = 0;
f2e0899f
DK		 11187
11188 bp->igu_base_sb = 0xff;
f2e0899f 11189 if (CHIP_INT_MODE_IS_BC(bp)) {
3395a033 11190 int vn = BP_VN(bp);
6383c0b3 11191 igu_sb_cnt = bp->igu_sb_cnt;
f2e0899f
DK		 11192 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
11193 FP_SB_MAX_E1x;
11194
11195 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
11196 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
11197
9b341bb1 11198 return 0;
f2e0899f
DK		 11199 }
11200
11201 /* IGU in normal mode - read CAM */
11202 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
11203 igu_sb_id++) {
11204 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
11205 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
11206 continue;
11207 fid = IGU_FID(val);
11208 if ((fid & IGU_FID_ENCODE_IS_PF)) {
11209 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
11210 continue;
11211 if (IGU_VEC(val) == 0)
11212 /* default status block */
11213 bp->igu_dsb_id = igu_sb_id;
11214 else {
11215 if (bp->igu_base_sb == 0xff)
11216 bp->igu_base_sb = igu_sb_id;
6383c0b3 11217 igu_sb_cnt++;
f2e0899f
DK		 11218 }
11219 }
11220 }
619c5cb6 11221
6383c0b3 11222#ifdef CONFIG_PCI_MSI
185d4c8b
AE		 11223 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11224 * optional that number of CAM entries will not be equal to the value
11225 * advertised in PCI.
11226 * Driver should use the minimal value of both as the actual status
11227 * block count
619c5cb6 11228 */
185d4c8b 11229 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
6383c0b3 11230#endif
619c5cb6 11231
9b341bb1 11232 if (igu_sb_cnt == 0) {
f2e0899f 11233 BNX2X_ERR("CAM configuration error\n");
9b341bb1
BW		 11234 return -EINVAL;
11235 }
11236
11237 return 0;
f2e0899f
DK		 11238}
11239
1dd06ae8 11240static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
a2fbb9ea 11241{
a22f0788
YR		 11242 int cfg_size = 0, idx, port = BP_PORT(bp);
11243
11244 /* Aggregation of supported attributes of all external phys */
11245 bp->port.supported[0] = 0;
11246 bp->port.supported[1] = 0;
b7737c9b
YR		 11247 switch (bp->link_params.num_phys) {
11248 case 1:
a22f0788
YR		 11249 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
11250 cfg_size = 1;
11251 break;
b7737c9b 11252 case 2:
a22f0788
YR		 11253 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
11254 cfg_size = 1;
11255 break;
11256 case 3:
11257 if (bp->link_params.multi_phy_config &
11258 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11259 bp->port.supported[1] =
11260 bp->link_params.phy[EXT_PHY1].supported;
11261 bp->port.supported[0] =
11262 bp->link_params.phy[EXT_PHY2].supported;
11263 } else {
11264 bp->port.supported[0] =
11265 bp->link_params.phy[EXT_PHY1].supported;
11266 bp->port.supported[1] =
11267 bp->link_params.phy[EXT_PHY2].supported;
11268 }
11269 cfg_size = 2;
11270 break;
b7737c9b 11271 }
a2fbb9ea 11272
a22f0788 11273 if (!(bp->port.supported[0] || bp->port.supported[1])) {
51c1a580 11274 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
b7737c9b 11275 SHMEM_RD(bp,
a22f0788
YR		 11276 dev_info.port_hw_config[port].external_phy_config),
11277 SHMEM_RD(bp,
11278 dev_info.port_hw_config[port].external_phy_config2));
a2fbb9ea 11279 return;
f85582f8 11280 }
a2fbb9ea 11281
619c5cb6
VZ		 11282 if (CHIP_IS_E3(bp))
11283 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
11284 else {
11285 switch (switch_cfg) {
11286 case SWITCH_CFG_1G:
11287 bp->port.phy_addr = REG_RD(
11288 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
11289 break;
11290 case SWITCH_CFG_10G:
11291 bp->port.phy_addr = REG_RD(
11292 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
11293 break;
11294 default:
11295 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11296 bp->port.link_config[0]);
11297 return;
11298 }
a2fbb9ea 11299 }
619c5cb6 11300 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
a22f0788
YR		 11301 /* mask what we support according to speed_cap_mask per configuration */
11302 for (idx = 0; idx < cfg_size; idx++) {
11303 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11304 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
a22f0788 11305 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
a2fbb9ea 11306
a22f0788 11307 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11308 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
a22f0788 11309 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
a2fbb9ea 11310
a22f0788 11311 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11312 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
a22f0788 11313 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
a2fbb9ea 11314
a22f0788 11315 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11316 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
a22f0788 11317 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
a2fbb9ea 11318
a22f0788 11319 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11320 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
a22f0788 11321 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
f85582f8 11322 SUPPORTED_1000baseT_Full);
a2fbb9ea 11323
a22f0788 11324 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11325 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
a22f0788 11326 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
a2fbb9ea 11327
a22f0788 11328 if (!(bp->link_params.speed_cap_mask[idx] &
c18487ee 11329 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
a22f0788 11330 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
b8e0d884
YR		 11331
11332 if (!(bp->link_params.speed_cap_mask[idx] &
11333 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11334 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
a22f0788 11335 }
a2fbb9ea 11336
a22f0788
YR		 11337 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11338 bp->port.supported[1]);
a2fbb9ea
ET		 11339}
11340
0329aba1 11341static void bnx2x_link_settings_requested(struct bnx2x *bp)
a2fbb9ea 11342{
a22f0788
YR		 11343 u32 link_config, idx, cfg_size = 0;
11344 bp->port.advertising[0] = 0;
11345 bp->port.advertising[1] = 0;
11346 switch (bp->link_params.num_phys) {
11347 case 1:
11348 case 2:
11349 cfg_size = 1;
11350 break;
11351 case 3:
11352 cfg_size = 2;
11353 break;
11354 }
11355 for (idx = 0; idx < cfg_size; idx++) {
11356 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11357 link_config = bp->port.link_config[idx];
11358 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
f85582f8 11359 case PORT_FEATURE_LINK_SPEED_AUTO:
a22f0788
YR		 11360 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11361 bp->link_params.req_line_speed[idx] =
11362 SPEED_AUTO_NEG;
11363 bp->port.advertising[idx] |=
11364 bp->port.supported[idx];
10bd1f24
MY		 11365 if (bp->link_params.phy[EXT_PHY1].type ==
11366 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11367 bp->port.advertising[idx] |=
11368 (SUPPORTED_100baseT_Half |
11369 SUPPORTED_100baseT_Full);
f85582f8
DK		 11370 } else {
11371 /* force 10G, no AN */
a22f0788
YR		 11372 bp->link_params.req_line_speed[idx] =
11373 SPEED_10000;
11374 bp->port.advertising[idx] |=
11375 (ADVERTISED_10000baseT_Full |
f85582f8 11376 ADVERTISED_FIBRE);
a22f0788 11377 continue;
f85582f8
DK		 11378 }
11379 break;
a2fbb9ea 11380
f85582f8 11381 case PORT_FEATURE_LINK_SPEED_10M_FULL:
a22f0788
YR		 11382 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11383 bp->link_params.req_line_speed[idx] =
11384 SPEED_10;
11385 bp->port.advertising[idx] |=
11386 (ADVERTISED_10baseT_Full |
f85582f8
DK		 11387 ADVERTISED_TP);
11388 } else {
51c1a580 11389 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8 11390 link_config,
a22f0788 11391 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11392 return;
11393 }
11394 break;
a2fbb9ea 11395
f85582f8 11396 case PORT_FEATURE_LINK_SPEED_10M_HALF:
a22f0788
YR		 11397 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11398 bp->link_params.req_line_speed[idx] =
11399 SPEED_10;
11400 bp->link_params.req_duplex[idx] =
11401 DUPLEX_HALF;
11402 bp->port.advertising[idx] |=
11403 (ADVERTISED_10baseT_Half |
f85582f8
DK		 11404 ADVERTISED_TP);
11405 } else {
51c1a580 11406 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11407 link_config,
11408 bp->link_params.speed_cap_mask[idx]);
11409 return;
11410 }
11411 break;
a2fbb9ea 11412
f85582f8
DK		 11413 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11414 if (bp->port.supported[idx] &
11415 SUPPORTED_100baseT_Full) {
a22f0788
YR		 11416 bp->link_params.req_line_speed[idx] =
11417 SPEED_100;
11418 bp->port.advertising[idx] |=
11419 (ADVERTISED_100baseT_Full |
f85582f8
DK		 11420 ADVERTISED_TP);
11421 } else {
51c1a580 11422 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
f85582f8
DK		 11423 link_config,
11424 bp->link_params.speed_cap_mask[idx]);
11425 return;
11426 }
11427 break;
a2fbb9ea 11428
f85582f8
DK		 11429 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11430 if (bp->port.supported[idx] &
11431 SUPPORTED_100baseT_Half) {
11432 bp->link_params.req_line_speed[idx] =
11433 SPEED_100;
11434 bp->link_params.req_duplex[idx] =
11435 DUPLEX_HALF;
a22f0788
YR		 11436 bp->port.advertising[idx] |=
11437 (ADVERTISED_100baseT_Half |
f85582f8
DK		 11438 ADVERTISED_TP);
11439 } else {
51c1a580 11440 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11441 link_config,
11442 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11443 return;
11444 }
11445 break;
a2fbb9ea 11446
f85582f8 11447 case PORT_FEATURE_LINK_SPEED_1G:
a22f0788
YR		 11448 if (bp->port.supported[idx] &
11449 SUPPORTED_1000baseT_Full) {
11450 bp->link_params.req_line_speed[idx] =
11451 SPEED_1000;
11452 bp->port.advertising[idx] |=
11453 (ADVERTISED_1000baseT_Full |
f85582f8 11454 ADVERTISED_TP);
5d67c1c5
YM		 11455 } else if (bp->port.supported[idx] &
11456 SUPPORTED_1000baseKX_Full) {
11457 bp->link_params.req_line_speed[idx] =
11458 SPEED_1000;
11459 bp->port.advertising[idx] |=
11460 ADVERTISED_1000baseKX_Full;
f85582f8 11461 } else {
51c1a580 11462 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788
YR		 11463 link_config,
11464 bp->link_params.speed_cap_mask[idx]);
f85582f8
DK		 11465 return;
11466 }
11467 break;
a2fbb9ea 11468
f85582f8 11469 case PORT_FEATURE_LINK_SPEED_2_5G:
a22f0788
YR		 11470 if (bp->port.supported[idx] &
11471 SUPPORTED_2500baseX_Full) {
11472 bp->link_params.req_line_speed[idx] =
11473 SPEED_2500;
11474 bp->port.advertising[idx] |=
11475 (ADVERTISED_2500baseX_Full |
34f80b04 11476 ADVERTISED_TP);
f85582f8 11477 } else {
51c1a580 11478 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11479 link_config,
f85582f8
DK		 11480 bp->link_params.speed_cap_mask[idx]);
11481 return;
11482 }
11483 break;
a2fbb9ea 11484
f85582f8 11485 case PORT_FEATURE_LINK_SPEED_10G_CX4:
a22f0788
YR		 11486 if (bp->port.supported[idx] &
11487 SUPPORTED_10000baseT_Full) {
11488 bp->link_params.req_line_speed[idx] =
11489 SPEED_10000;
11490 bp->port.advertising[idx] |=
11491 (ADVERTISED_10000baseT_Full |
34f80b04 11492 ADVERTISED_FIBRE);
5d67c1c5
YM		 11493 } else if (bp->port.supported[idx] &
11494 SUPPORTED_10000baseKR_Full) {
11495 bp->link_params.req_line_speed[idx] =
11496 SPEED_10000;
11497 bp->port.advertising[idx] |=
11498 (ADVERTISED_10000baseKR_Full |
11499 ADVERTISED_FIBRE);
f85582f8 11500 } else {
51c1a580 11501 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
a22f0788 11502 link_config,
f85582f8
DK		 11503 bp->link_params.speed_cap_mask[idx]);
11504 return;
11505 }
11506 break;
3c9ada22
YR		 11507 case PORT_FEATURE_LINK_SPEED_20G:
11508 bp->link_params.req_line_speed[idx] = SPEED_20000;
a2fbb9ea 11509
3c9ada22 11510 break;
f85582f8 11511 default:
51c1a580 11512 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
754a2f52 11513 link_config);
f85582f8
DK		 11514 bp->link_params.req_line_speed[idx] =
11515 SPEED_AUTO_NEG;
11516 bp->port.advertising[idx] =
11517 bp->port.supported[idx];
11518 break;
11519 }
a2fbb9ea 11520
a22f0788 11521 bp->link_params.req_flow_ctrl[idx] = (link_config &
34f80b04 11522 PORT_FEATURE_FLOW_CONTROL_MASK);
cd1dfce2
YM		 11523 if (bp->link_params.req_flow_ctrl[idx] ==
11524 BNX2X_FLOW_CTRL_AUTO) {
11525 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11526 bp->link_params.req_flow_ctrl[idx] =
11527 BNX2X_FLOW_CTRL_NONE;
11528 else
11529 bnx2x_set_requested_fc(bp);
a22f0788 11530 }
a2fbb9ea 11531
51c1a580 11532 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
a22f0788
YR		 11533 bp->link_params.req_line_speed[idx],
11534 bp->link_params.req_duplex[idx],
11535 bp->link_params.req_flow_ctrl[idx],
11536 bp->port.advertising[idx]);
11537 }
a2fbb9ea
ET		 11538}
11539
0329aba1 11540static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
e665bfda 11541{
86564c3f
YM		 11542 __be16 mac_hi_be = cpu_to_be16(mac_hi);
11543 __be32 mac_lo_be = cpu_to_be32(mac_lo);
11544 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11545 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
e665bfda
MC		 11546}
11547
0329aba1 11548static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
a2fbb9ea 11549{
34f80b04 11550 int port = BP_PORT(bp);
589abe3a 11551 u32 config;
c8c60d88 11552 u32 ext_phy_type, ext_phy_config, eee_mode;
a2fbb9ea 11553
c18487ee 11554 bp->link_params.bp = bp;
34f80b04 11555 bp->link_params.port = port;
c18487ee 11556
c18487ee 11557 bp->link_params.lane_config =
a2fbb9ea 11558 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
4d295db0 11559
a22f0788 11560 bp->link_params.speed_cap_mask[0] =
a2fbb9ea 11561 SHMEM_RD(bp,
b0261926
YR		 11562 dev_info.port_hw_config[port].speed_capability_mask) &
11563 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788
YR		 11564 bp->link_params.speed_cap_mask[1] =
11565 SHMEM_RD(bp,
b0261926
YR		 11566 dev_info.port_hw_config[port].speed_capability_mask2) &
11567 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
a22f0788 11568 bp->port.link_config[0] =
a2fbb9ea
ET		 11569 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11570
a22f0788
YR		 11571 bp->port.link_config[1] =
11572 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
c2c8b03e 11573
a22f0788
YR		 11574 bp->link_params.multi_phy_config =
11575 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
3ce2c3f9
EG		 11576 /* If the device is capable of WoL, set the default state according
11577 * to the HW
11578 */
4d295db0 11579 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
3ce2c3f9
EG		 11580 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11581 (config & PORT_FEATURE_WOL_ENABLED));
11582
4ba7699b
YM		 11583 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11584 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11585 bp->flags |= NO_ISCSI_FLAG;
11586 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11587 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11588 bp->flags |= NO_FCOE_FLAG;
11589
51c1a580 11590 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
c18487ee 11591 bp->link_params.lane_config,
a22f0788
YR		 11592 bp->link_params.speed_cap_mask[0],
11593 bp->port.link_config[0]);
a2fbb9ea 11594
a22f0788 11595 bp->link_params.switch_cfg = (bp->port.link_config[0] &
f85582f8 11596 PORT_FEATURE_CONNECTED_SWITCH_MASK);
b7737c9b 11597 bnx2x_phy_probe(&bp->link_params);
c18487ee 11598 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
a2fbb9ea
ET		 11599
11600 bnx2x_link_settings_requested(bp);
11601
01cd4528
EG		 11602 /*
11603 * If connected directly, work with the internal PHY, otherwise, work
11604 * with the external PHY
11605 */
b7737c9b
YR		 11606 ext_phy_config =
11607 SHMEM_RD(bp,
11608 dev_info.port_hw_config[port].external_phy_config);
11609 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
01cd4528 11610 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
b7737c9b 11611 bp->mdio.prtad = bp->port.phy_addr;
01cd4528
EG		 11612
11613 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11614 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11615 bp->mdio.prtad =
b7737c9b 11616 XGXS_EXT_PHY_ADDR(ext_phy_config);
5866df6d 11617
c8c60d88
YM		 11618 /* Configure link feature according to nvram value */
11619 eee_mode = (((SHMEM_RD(bp, dev_info.
11620 port_feature_config[port].eee_power_mode)) &
11621 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11622 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11623 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11624 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11625 EEE_MODE_ENABLE_LPI |
11626 EEE_MODE_OUTPUT_TIME;
11627 } else {
11628 bp->link_params.eee_mode = 0;
11629 }
0793f83f 11630}
01cd4528 11631
b306f5ed 11632void bnx2x_get_iscsi_info(struct bnx2x *bp)
2ba45142 11633{
9e62e912 11634 u32 no_flags = NO_ISCSI_FLAG;
bf61ee14 11635 int port = BP_PORT(bp);
2ba45142 11636 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
bf61ee14 11637 drv_lic_key[port].max_iscsi_conn);
2ba45142 11638
55c11941
MS		 11639 if (!CNIC_SUPPORT(bp)) {
11640 bp->flags |= no_flags;
11641 return;
11642 }
11643
b306f5ed 11644 /* Get the number of maximum allowed iSCSI connections */
2ba45142
VZ		 11645 bp->cnic_eth_dev.max_iscsi_conn =
11646 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11647 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11648
b306f5ed
DK		 11649 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11650 bp->cnic_eth_dev.max_iscsi_conn);
11651
11652 /*
11653 * If maximum allowed number of connections is zero -
11654 * disable the feature.
11655 */
11656 if (!bp->cnic_eth_dev.max_iscsi_conn)
9e62e912 11657 bp->flags |= no_flags;
b306f5ed
DK		 11658}
11659
0329aba1 11660static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
9e62e912
DK		 11661{
11662 /* Port info */
11663 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11664 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11665 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11666 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11667
11668 /* Node info */
11669 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11670 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11671 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11672 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11673}
86800194
DK		 11674
11675static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11676{
11677 u8 count = 0;
11678
11679 if (IS_MF(bp)) {
11680 u8 fid;
11681
11682 /* iterate over absolute function ids for this path: */
11683 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11684 if (IS_MF_SD(bp)) {
11685 u32 cfg = MF_CFG_RD(bp,
11686 func_mf_config[fid].config);
11687
11688 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11689 ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11690 FUNC_MF_CFG_PROTOCOL_FCOE))
11691 count++;
11692 } else {
11693 u32 cfg = MF_CFG_RD(bp,
11694 func_ext_config[fid].
11695 func_cfg);
11696
11697 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11698 (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11699 count++;
11700 }
11701 }
11702 } else { /* SF */
11703 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11704
11705 for (port = 0; port < port_cnt; port++) {
11706 u32 lic = SHMEM_RD(bp,
11707 drv_lic_key[port].max_fcoe_conn) ^
11708 FW_ENCODE_32BIT_PATTERN;
11709 if (lic)
11710 count++;
11711 }
11712 }
11713
11714 return count;
11715}
11716
0329aba1 11717static void bnx2x_get_fcoe_info(struct bnx2x *bp)
b306f5ed
DK		 11718{
11719 int port = BP_PORT(bp);
11720 int func = BP_ABS_FUNC(bp);
b306f5ed
DK		 11721 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11722 drv_lic_key[port].max_fcoe_conn);
86800194 11723 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
b306f5ed 11724
55c11941
MS		 11725 if (!CNIC_SUPPORT(bp)) {
11726 bp->flags |= NO_FCOE_FLAG;
11727 return;
11728 }
11729
b306f5ed 11730 /* Get the number of maximum allowed FCoE connections */
2ba45142
VZ		 11731 bp->cnic_eth_dev.max_fcoe_conn =
11732 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11733 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11734
0eb43b4b
BPG		 11735 /* Calculate the number of maximum allowed FCoE tasks */
11736 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
86800194
DK		 11737
11738 /* check if FCoE resources must be shared between different functions */
11739 if (num_fcoe_func)
11740 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
0eb43b4b 11741
bf61ee14
VZ		 11742 /* Read the WWN: */
11743 if (!IS_MF(bp)) {
11744 /* Port info */
11745 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11746 SHMEM_RD(bp,
2de67439 11747 dev_info.port_hw_config[port].
bf61ee14
VZ		 11748 fcoe_wwn_port_name_upper);
11749 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11750 SHMEM_RD(bp,
2de67439 11751 dev_info.port_hw_config[port].
bf61ee14
VZ		 11752 fcoe_wwn_port_name_lower);
11753
11754 /* Node info */
11755 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11756 SHMEM_RD(bp,
2de67439 11757 dev_info.port_hw_config[port].
bf61ee14
VZ		 11758 fcoe_wwn_node_name_upper);
11759 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11760 SHMEM_RD(bp,
2de67439 11761 dev_info.port_hw_config[port].
bf61ee14
VZ		 11762 fcoe_wwn_node_name_lower);
11763 } else if (!IS_MF_SD(bp)) {
2e98ffc2 11764 /* Read the WWN info only if the FCoE feature is enabled for
bf61ee14
VZ		 11765 * this function.
11766 */
2e98ffc2
DK		 11767 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11768 bnx2x_get_ext_wwn_info(bp, func);
11769 } else {
11770 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
9e62e912 11771 bnx2x_get_ext_wwn_info(bp, func);
382e513a 11772 }
bf61ee14 11773
b306f5ed 11774 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
2ba45142 11775
bf61ee14
VZ		 11776 /*
11777 * If maximum allowed number of connections is zero -
2ba45142
VZ		 11778 * disable the feature.
11779 */
bbf666c1 11780 if (!bp->cnic_eth_dev.max_fcoe_conn) {
2ba45142 11781 bp->flags |= NO_FCOE_FLAG;
bbf666c1
SRK		 11782 eth_zero_addr(bp->fip_mac);
11783 }
2ba45142 11784}
b306f5ed 11785
0329aba1 11786static void bnx2x_get_cnic_info(struct bnx2x *bp)
b306f5ed
DK		 11787{
11788 /*
11789 * iSCSI may be dynamically disabled but reading
11790 * info here we will decrease memory usage by driver
11791 * if the feature is disabled for good
11792 */
11793 bnx2x_get_iscsi_info(bp);
11794 bnx2x_get_fcoe_info(bp);
11795}
2ba45142 11796
0329aba1 11797static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
0793f83f
DK		 11798{
11799 u32 val, val2;
11800 int func = BP_ABS_FUNC(bp);
11801 int port = BP_PORT(bp);
2ba45142
VZ		 11802 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11803 u8 *fip_mac = bp->fip_mac;
0793f83f 11804
55c11941
MS		 11805 if (IS_MF(bp)) {
11806 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
2ba45142 11807 * FCoE MAC then the appropriate feature should be disabled.
55c11941
MS		 11808 * In non SD mode features configuration comes from struct
11809 * func_ext_config.
2ba45142 11810 */
2e98ffc2 11811 if (!IS_MF_SD(bp)) {
0793f83f
DK		 11812 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11813 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11814 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11815 iscsi_mac_addr_upper);
0793f83f 11816 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11817 iscsi_mac_addr_lower);
2ba45142 11818 bnx2x_set_mac_buf(iscsi_mac, val, val2);
55c11941
MS		 11819 BNX2X_DEV_INFO
11820 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11821 } else {
2ba45142 11822 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
55c11941 11823 }
2ba45142
VZ		 11824
11825 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11826 val2 = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11827 fcoe_mac_addr_upper);
2ba45142 11828 val = MF_CFG_RD(bp, func_ext_config[func].
55c11941 11829 fcoe_mac_addr_lower);
2ba45142 11830 bnx2x_set_mac_buf(fip_mac, val, val2);
55c11941
MS		 11831 BNX2X_DEV_INFO
11832 ("Read FCoE L2 MAC: %pM\n", fip_mac);
11833 } else {
2ba45142 11834 bp->flags |= NO_FCOE_FLAG;
55c11941 11835 }
a3348722
BW		 11836
11837 bp->mf_ext_config = cfg;
11838
9e62e912 11839 } else { /* SD MODE */
55c11941
MS		 11840 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11841 /* use primary mac as iscsi mac */
11842 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11843
11844 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11845 BNX2X_DEV_INFO
11846 ("Read iSCSI MAC: %pM\n", iscsi_mac);
11847 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11848 /* use primary mac as fip mac */
11849 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11850 BNX2X_DEV_INFO("SD FCoE MODE\n");
11851 BNX2X_DEV_INFO
11852 ("Read FIP MAC: %pM\n", fip_mac);
614c76df 11853 }
0793f83f 11854 }
a3348722 11855
82594f8f
YM		 11856 /* If this is a storage-only interface, use SAN mac as
11857 * primary MAC. Notice that for SD this is already the case,
11858 * as the SAN mac was copied from the primary MAC.
11859 */
11860 if (IS_MF_FCOE_AFEX(bp))
a3348722 11861 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
0793f83f 11862 } else {
0793f83f 11863 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11864 iscsi_mac_upper);
0793f83f 11865 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11866 iscsi_mac_lower);
2ba45142 11867 bnx2x_set_mac_buf(iscsi_mac, val, val2);
c03bd39c
VZ		 11868
11869 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11870 fcoe_fip_mac_upper);
c03bd39c 11871 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
55c11941 11872 fcoe_fip_mac_lower);
c03bd39c 11873 bnx2x_set_mac_buf(fip_mac, val, val2);
0793f83f
DK		 11874 }
11875
55c11941 11876 /* Disable iSCSI OOO if MAC configuration is invalid. */
426b9241 11877 if (!is_valid_ether_addr(iscsi_mac)) {
55c11941 11878 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
c7bf7169 11879 eth_zero_addr(iscsi_mac);
426b9241
DK		 11880 }
11881
55c11941 11882 /* Disable FCoE if MAC configuration is invalid. */
426b9241
DK		 11883 if (!is_valid_ether_addr(fip_mac)) {
11884 bp->flags |= NO_FCOE_FLAG;
c7bf7169 11885 eth_zero_addr(bp->fip_mac);
426b9241 11886 }
55c11941
MS		 11887}
11888
0329aba1 11889static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
55c11941
MS		 11890{
11891 u32 val, val2;
11892 int func = BP_ABS_FUNC(bp);
11893 int port = BP_PORT(bp);
11894
11895 /* Zero primary MAC configuration */
c7bf7169 11896 eth_zero_addr(bp->dev->dev_addr);
55c11941
MS		 11897
11898 if (BP_NOMCP(bp)) {
11899 BNX2X_ERROR("warning: random MAC workaround active\n");
11900 eth_hw_addr_random(bp->dev);
11901 } else if (IS_MF(bp)) {
11902 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11903 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11904 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11905 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11906 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11907
11908 if (CNIC_SUPPORT(bp))
11909 bnx2x_get_cnic_mac_hwinfo(bp);
11910 } else {
11911 /* in SF read MACs from port configuration */
11912 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11913 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11914 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11915
11916 if (CNIC_SUPPORT(bp))
11917 bnx2x_get_cnic_mac_hwinfo(bp);
11918 }
11919
3d7d562c
YM		 11920 if (!BP_NOMCP(bp)) {
11921 /* Read physical port identifier from shmem */
11922 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11923 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11924 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11925 bp->flags |= HAS_PHYS_PORT_ID;
11926 }
11927
55c11941 11928 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
619c5cb6 11929
2e98ffc2 11930 if (!is_valid_ether_addr(bp->dev->dev_addr))
619c5cb6 11931 dev_err(&bp->pdev->dev,
51c1a580
MS		 11932 "bad Ethernet MAC address configuration: %pM\n"
11933 "change it manually before bringing up the appropriate network interface\n",
0f9dad10 11934 bp->dev->dev_addr);
7964211d 11935}
51c1a580 11936
0329aba1 11937static bool bnx2x_get_dropless_info(struct bnx2x *bp)
7964211d
YM		 11938{
11939 int tmp;
11940 u32 cfg;
51c1a580 11941
aeeddb8b 11942 if (IS_VF(bp))
4e833c59 11943 return false;
aeeddb8b 11944
7964211d
YM		 11945 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11946 /* Take function: tmp = func */
11947 tmp = BP_ABS_FUNC(bp);
11948 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11949 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11950 } else {
11951 /* Take port: tmp = port */
11952 tmp = BP_PORT(bp);
11953 cfg = SHMEM_RD(bp,
11954 dev_info.port_hw_config[tmp].generic_features);
11955 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11956 }
11957 return cfg;
34f80b04
EG		 11958}
11959
83bad206
YM		 11960static void validate_set_si_mode(struct bnx2x *bp)
11961{
11962 u8 func = BP_ABS_FUNC(bp);
11963 u32 val;
11964
11965 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11966
11967 /* check for legal mac (upper bytes) */
11968 if (val != 0xffff) {
11969 bp->mf_mode = MULTI_FUNCTION_SI;
11970 bp->mf_config[BP_VN(bp)] =
11971 MF_CFG_RD(bp, func_mf_config[func].config);
11972 } else
11973 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11974}
11975
0329aba1 11976static int bnx2x_get_hwinfo(struct bnx2x *bp)
34f80b04 11977{
0793f83f 11978 int /*abs*/func = BP_ABS_FUNC(bp);
230d00eb 11979 int vn, mfw_vn;
83bad206 11980 u32 val = 0, val2 = 0;
34f80b04 11981 int rc = 0;
a2fbb9ea 11982
0f587f1b
YM		 11983 /* Validate that chip access is feasible */
11984 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) {
11985 dev_err(&bp->pdev->dev,
11986 "Chip read returns all Fs. Preventing probe from continuing\n");
11987 return -EINVAL;
11988 }
11989
34f80b04 11990 bnx2x_get_common_hwinfo(bp);
a2fbb9ea 11991
6383c0b3
AE		 11992 /*
11993 * initialize IGU parameters
11994 */
f2e0899f
DK		 11995 if (CHIP_IS_E1x(bp)) {
11996 bp->common.int_block = INT_BLOCK_HC;
11997
11998 bp->igu_dsb_id = DEF_SB_IGU_ID;
11999 bp->igu_base_sb = 0;
f2e0899f
DK		 12000 } else {
12001 bp->common.int_block = INT_BLOCK_IGU;
7a06a122 12002
16a5fd92 12003 /* do not allow device reset during IGU info processing */
7a06a122
DK		 12004 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
12005
f2e0899f 12006 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
619c5cb6
VZ		 12007
12008 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
12009 int tout = 5000;
12010
12011 BNX2X_DEV_INFO("FORCING Normal Mode\n");
12012
12013 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
12014 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
12015 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
12016
12017 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12018 tout--;
0926d499 12019 usleep_range(1000, 2000);
619c5cb6
VZ		 12020 }
12021
12022 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
12023 dev_err(&bp->pdev->dev,
12024 "FORCING Normal Mode failed!!!\n");
9b341bb1
BW		 12025 bnx2x_release_hw_lock(bp,
12026 HW_LOCK_RESOURCE_RESET);
619c5cb6
VZ		 12027 return -EPERM;
12028 }
12029 }
12030
f2e0899f 12031 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
619c5cb6 12032 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
f2e0899f
DK		 12033 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
12034 } else
619c5cb6 12035 BNX2X_DEV_INFO("IGU Normal Mode\n");
523224a3 12036
9b341bb1 12037 rc = bnx2x_get_igu_cam_info(bp);
7a06a122 12038 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9b341bb1
BW		 12039 if (rc)
12040 return rc;
f2e0899f 12041 }
619c5cb6
VZ		 12042
12043 /*
12044 * set base FW non-default (fast path) status block id, this value is
12045 * used to initialize the fw_sb_id saved on the fp/queue structure to
12046 * determine the id used by the FW.
12047 */
12048 if (CHIP_IS_E1x(bp))
12049 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
12050 else /*
12051 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
12052 * the same queue are indicated on the same IGU SB). So we prefer
12053 * FW and IGU SBs to be the same value.
12054 */
12055 bp->base_fw_ndsb = bp->igu_base_sb;
12056
12057 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12058 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
12059 bp->igu_sb_cnt, bp->base_fw_ndsb);
f2e0899f
DK		 12060
12061 /*
12062 * Initialize MF configuration
12063 */
523224a3 12064
fb3bff17
DK		 12065 bp->mf_ov = 0;
12066 bp->mf_mode = 0;
7609647e 12067 bp->mf_sub_mode = 0;
3395a033 12068 vn = BP_VN(bp);
230d00eb 12069 mfw_vn = BP_FW_MB_IDX(bp);
0793f83f 12070
f2e0899f 12071 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
619c5cb6
VZ		 12072 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12073 bp->common.shmem2_base, SHMEM2_RD(bp, size),
12074 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
12075
f2e0899f
DK		 12076 if (SHMEM2_HAS(bp, mf_cfg_addr))
12077 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
12078 else
12079 bp->common.mf_cfg_base = bp->common.shmem_base +
523224a3
DK		 12080 offsetof(struct shmem_region, func_mb) +
12081 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
0793f83f
DK		 12082 /*
12083 * get mf configuration:
16a5fd92 12084 * 1. Existence of MF configuration
0793f83f
DK		 12085 * 2. MAC address must be legal (check only upper bytes)
12086 * for Switch-Independent mode;
12087 * OVLAN must be legal for Switch-Dependent mode
12088 * 3. SF_MODE configures specific MF mode
12089 */
12090 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12091 /* get mf configuration */
12092 val = SHMEM_RD(bp,
12093 dev_info.shared_feature_config.config);
12094 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
12095
12096 switch (val) {
12097 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
83bad206 12098 validate_set_si_mode(bp);
0793f83f 12099 break;
a3348722
BW		 12100 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
12101 if ((!CHIP_IS_E1x(bp)) &&
12102 (MF_CFG_RD(bp, func_mf_config[func].
12103 mac_upper) != 0xffff) &&
12104 (SHMEM2_HAS(bp,
12105 afex_driver_support))) {
12106 bp->mf_mode = MULTI_FUNCTION_AFEX;
12107 bp->mf_config[vn] = MF_CFG_RD(bp,
12108 func_mf_config[func].config);
12109 } else {
12110 BNX2X_DEV_INFO("can not configure afex mode\n");
12111 }
12112 break;
0793f83f
DK		 12113 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
12114 /* get OV configuration */
12115 val = MF_CFG_RD(bp,
12116 func_mf_config[FUNC_0].e1hov_tag);
12117 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
12118
12119 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
12120 bp->mf_mode = MULTI_FUNCTION_SD;
12121 bp->mf_config[vn] = MF_CFG_RD(bp,
12122 func_mf_config[func].config);
12123 } else
754a2f52 12124 BNX2X_DEV_INFO("illegal OV for SD\n");
0793f83f 12125 break;
230d00eb
YM		 12126 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
12127 bp->mf_mode = MULTI_FUNCTION_SD;
12128 bp->mf_sub_mode = SUB_MF_MODE_BD;
12129 bp->mf_config[vn] =
12130 MF_CFG_RD(bp,
12131 func_mf_config[func].config);
12132
12133 if (SHMEM2_HAS(bp, mtu_size)) {
12134 int mtu_idx = BP_FW_MB_IDX(bp);
12135 u16 mtu_size;
12136 u32 mtu;
12137
12138 mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
12139 mtu_size = (u16)mtu;
12140 DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
12141 mtu_size, mtu);
12142
12143 /* if valid: update device mtu */
e1c6dcca 12144 if ((mtu_size >= ETH_MIN_PACKET_SIZE) &&
230d00eb
YM		 12145 (mtu_size <=
12146 ETH_MAX_JUMBO_PACKET_SIZE))
12147 bp->dev->mtu = mtu_size;
12148 }
12149 break;
7609647e
YM		 12150 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
12151 bp->mf_mode = MULTI_FUNCTION_SD;
12152 bp->mf_sub_mode = SUB_MF_MODE_UFP;
12153 bp->mf_config[vn] =
12154 MF_CFG_RD(bp,
12155 func_mf_config[func].config);
12156 break;
3786b942
AE		 12157 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
12158 bp->mf_config[vn] = 0;
12159 break;
83bad206
YM		 12160 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
12161 val2 = SHMEM_RD(bp,
12162 dev_info.shared_hw_config.config_3);
12163 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
12164 switch (val2) {
12165 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
12166 validate_set_si_mode(bp);
12167 bp->mf_sub_mode =
12168 SUB_MF_MODE_NPAR1_DOT_5;
12169 break;
12170 default:
12171 /* Unknown configuration */
12172 bp->mf_config[vn] = 0;
12173 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12174 val);
12175 }
12176 break;
0793f83f
DK		 12177 default:
12178 /* Unknown configuration: reset mf_config */
12179 bp->mf_config[vn] = 0;
51c1a580 12180 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
0793f83f
DK		 12181 }
12182 }
a2fbb9ea 12183
2691d51d 12184 BNX2X_DEV_INFO("%s function mode\n",
fb3bff17 12185 IS_MF(bp) ? "multi" : "single");
2691d51d 12186
0793f83f
DK		 12187 switch (bp->mf_mode) {
12188 case MULTI_FUNCTION_SD:
12189 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
12190 FUNC_MF_CFG_E1HOV_TAG_MASK;
2691d51d 12191 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
fb3bff17 12192 bp->mf_ov = val;
619c5cb6
VZ		 12193 bp->path_has_ovlan = true;
12194
51c1a580
MS		 12195 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12196 func, bp->mf_ov, bp->mf_ov);
230d00eb
YM		 12197 } else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
12198 (bp->mf_sub_mode == SUB_MF_MODE_BD)) {
7609647e 12199 dev_err(&bp->pdev->dev,
230d00eb 12200 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
7609647e
YM		 12201 func);
12202 bp->path_has_ovlan = true;
2691d51d 12203 } else {
619c5cb6 12204 dev_err(&bp->pdev->dev,
51c1a580
MS		 12205 "No valid MF OV for func %d, aborting\n",
12206 func);
619c5cb6 12207 return -EPERM;
34f80b04 12208 }
0793f83f 12209 break;
a3348722
BW		 12210 case MULTI_FUNCTION_AFEX:
12211 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
12212 break;
0793f83f 12213 case MULTI_FUNCTION_SI:
51c1a580
MS		 12214 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12215 func);
0793f83f
DK		 12216 break;
12217 default:
12218 if (vn) {
619c5cb6 12219 dev_err(&bp->pdev->dev,
51c1a580
MS		 12220 "VN %d is in a single function mode, aborting\n",
12221 vn);
619c5cb6 12222 return -EPERM;
2691d51d 12223 }
0793f83f 12224 break;
34f80b04 12225 }
0793f83f 12226
619c5cb6
VZ		 12227 /* check if other port on the path needs ovlan:
12228 * Since MF configuration is shared between ports
12229 * Possible mixed modes are only
12230 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12231 */
12232 if (CHIP_MODE_IS_4_PORT(bp) &&
12233 !bp->path_has_ovlan &&
12234 !IS_MF(bp) &&
12235 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
12236 u8 other_port = !BP_PORT(bp);
12237 u8 other_func = BP_PATH(bp) + 2*other_port;
12238 val = MF_CFG_RD(bp,
12239 func_mf_config[other_func].e1hov_tag);
12240 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
12241 bp->path_has_ovlan = true;
12242 }
34f80b04 12243 }
a2fbb9ea 12244
e848582c
DK		 12245 /* adjust igu_sb_cnt to MF for E1H */
12246 if (CHIP_IS_E1H(bp) && IS_MF(bp))
12247 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
523224a3 12248
619c5cb6
VZ		 12249 /* port info */
12250 bnx2x_get_port_hwinfo(bp);
f2e0899f 12251
0793f83f
DK		 12252 /* Get MAC addresses */
12253 bnx2x_get_mac_hwinfo(bp);
a2fbb9ea 12254
2ba45142 12255 bnx2x_get_cnic_info(bp);
2ba45142 12256
34f80b04
EG		 12257 return rc;
12258}
12259
0329aba1 12260static void bnx2x_read_fwinfo(struct bnx2x *bp)
34f24c7f
VZ		 12261{
12262 int cnt, i, block_end, rodi;
fcdf95cb 12263 char vpd_start[BNX2X_VPD_LEN+1];
34f24c7f
VZ		 12264 char str_id_reg[VENDOR_ID_LEN+1];
12265 char str_id_cap[VENDOR_ID_LEN+1];
fcdf95cb
BW		 12266 char *vpd_data;
12267 char *vpd_extended_data = NULL;
34f24c7f
VZ		 12268 u8 len;
12269
fcdf95cb 12270 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
34f24c7f
VZ		 12271 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
12272
12273 if (cnt < BNX2X_VPD_LEN)
12274 goto out_not_found;
12275
fcdf95cb
BW		 12276 /* VPD RO tag should be first tag after identifier string, hence
12277 * we should be able to find it in first BNX2X_VPD_LEN chars
12278 */
12279 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
34f24c7f
VZ		 12280 PCI_VPD_LRDT_RO_DATA);
12281 if (i < 0)
12282 goto out_not_found;
12283
34f24c7f 12284 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
fcdf95cb 12285 pci_vpd_lrdt_size(&vpd_start[i]);
34f24c7f
VZ		 12286
12287 i += PCI_VPD_LRDT_TAG_SIZE;
12288
fcdf95cb
BW		 12289 if (block_end > BNX2X_VPD_LEN) {
12290 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
12291 if (vpd_extended_data == NULL)
12292 goto out_not_found;
12293
12294 /* read rest of vpd image into vpd_extended_data */
12295 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
12296 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
12297 block_end - BNX2X_VPD_LEN,
12298 vpd_extended_data + BNX2X_VPD_LEN);
12299 if (cnt < (block_end - BNX2X_VPD_LEN))
12300 goto out_not_found;
12301 vpd_data = vpd_extended_data;
12302 } else
12303 vpd_data = vpd_start;
12304
12305 /* now vpd_data holds full vpd content in both cases */
34f24c7f
VZ		 12306
12307 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12308 PCI_VPD_RO_KEYWORD_MFR_ID);
12309 if (rodi < 0)
12310 goto out_not_found;
12311
12312 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12313
12314 if (len != VENDOR_ID_LEN)
12315 goto out_not_found;
12316
12317 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12318
12319 /* vendor specific info */
12320 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
12321 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
12322 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
12323 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
12324
12325 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
12326 PCI_VPD_RO_KEYWORD_VENDOR0);
12327 if (rodi >= 0) {
12328 len = pci_vpd_info_field_size(&vpd_data[rodi]);
12329
12330 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
12331
12332 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
12333 memcpy(bp->fw_ver, &vpd_data[rodi], len);
12334 bp->fw_ver[len] = ' ';
12335 }
12336 }
fcdf95cb 12337 kfree(vpd_extended_data);
34f24c7f
VZ		 12338 return;
12339 }
12340out_not_found:
fcdf95cb 12341 kfree(vpd_extended_data);
34f24c7f
VZ		 12342 return;
12343}
12344
0329aba1 12345static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
619c5cb6
VZ		 12346{
12347 u32 flags = 0;
12348
12349 if (CHIP_REV_IS_FPGA(bp))
12350 SET_FLAGS(flags, MODE_FPGA);
12351 else if (CHIP_REV_IS_EMUL(bp))
12352 SET_FLAGS(flags, MODE_EMUL);
12353 else
12354 SET_FLAGS(flags, MODE_ASIC);
12355
12356 if (CHIP_MODE_IS_4_PORT(bp))
12357 SET_FLAGS(flags, MODE_PORT4);
12358 else
12359 SET_FLAGS(flags, MODE_PORT2);
12360
12361 if (CHIP_IS_E2(bp))
12362 SET_FLAGS(flags, MODE_E2);
12363 else if (CHIP_IS_E3(bp)) {
12364 SET_FLAGS(flags, MODE_E3);
12365 if (CHIP_REV(bp) == CHIP_REV_Ax)
12366 SET_FLAGS(flags, MODE_E3_A0);
6383c0b3
AE		 12367 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12368 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
619c5cb6
VZ		 12369 }
12370
12371 if (IS_MF(bp)) {
12372 SET_FLAGS(flags, MODE_MF);
12373 switch (bp->mf_mode) {
12374 case MULTI_FUNCTION_SD:
12375 SET_FLAGS(flags, MODE_MF_SD);
12376 break;
12377 case MULTI_FUNCTION_SI:
12378 SET_FLAGS(flags, MODE_MF_SI);
12379 break;
a3348722
BW		 12380 case MULTI_FUNCTION_AFEX:
12381 SET_FLAGS(flags, MODE_MF_AFEX);
12382 break;
619c5cb6
VZ		 12383 }
12384 } else
12385 SET_FLAGS(flags, MODE_SF);
12386
12387#if defined(__LITTLE_ENDIAN)
12388 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12389#else /*(__BIG_ENDIAN)*/
12390 SET_FLAGS(flags, MODE_BIG_ENDIAN);
12391#endif
12392 INIT_MODE_FLAGS(bp) = flags;
12393}
12394
0329aba1 12395static int bnx2x_init_bp(struct bnx2x *bp)
34f80b04 12396{
f2e0899f 12397 int func;
34f80b04
EG		 12398 int rc;
12399
34f80b04 12400 mutex_init(&bp->port.phy_mutex);
c4ff7cbf 12401 mutex_init(&bp->fw_mb_mutex);
42f8277f 12402 mutex_init(&bp->drv_info_mutex);
c6e36d8c 12403 sema_init(&bp->stats_lock, 1);
42f8277f 12404 bp->drv_info_mng_owner = false;
05cc5a39 12405 INIT_LIST_HEAD(&bp->vlan_reg);
55c11941 12406
1cf167f2 12407 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
7be08a72 12408 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
3deb8167 12409 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
370d4a26 12410 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
1ab4434c
AE		 12411 if (IS_PF(bp)) {
12412 rc = bnx2x_get_hwinfo(bp);
12413 if (rc)
12414 return rc;
12415 } else {
e09b74d0 12416 eth_zero_addr(bp->dev->dev_addr);
1ab4434c 12417 }
34f80b04 12418
619c5cb6
VZ		 12419 bnx2x_set_modes_bitmap(bp);
12420
12421 rc = bnx2x_alloc_mem_bp(bp);
12422 if (rc)
12423 return rc;
523224a3 12424
34f24c7f 12425 bnx2x_read_fwinfo(bp);
f2e0899f
DK		 12426
12427 func = BP_FUNC(bp);
12428
34f80b04 12429 /* need to reset chip if undi was active */
1ab4434c 12430 if (IS_PF(bp) && !BP_NOMCP(bp)) {
452427b0
YM		 12431 /* init fw_seq */
12432 bp->fw_seq =
12433 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12434 DRV_MSG_SEQ_NUMBER_MASK;
12435 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12436
91ebb929
YM		 12437 rc = bnx2x_prev_unload(bp);
12438 if (rc) {
12439 bnx2x_free_mem_bp(bp);
12440 return rc;
12441 }
452427b0
YM		 12442 }
12443
34f80b04 12444 if (CHIP_REV_IS_FPGA(bp))
cdaa7cb8 12445 dev_err(&bp->pdev->dev, "FPGA detected\n");
34f80b04
EG		 12446
12447 if (BP_NOMCP(bp) && (func == 0))
51c1a580 12448 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
34f80b04 12449
614c76df 12450 bp->disable_tpa = disable_tpa;
2e98ffc2 12451 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
94d9de3c 12452 /* Reduce memory usage in kdump environment by disabling TPA */
c9931896 12453 bp->disable_tpa |= is_kdump_kernel();
614c76df 12454
7a9b2557 12455 /* Set TPA flags */
614c76df 12456 if (bp->disable_tpa) {
3c3def5f
MC		 12457 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12458 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
7a9b2557
VZ		 12459 }
12460
a18f5128
EG		 12461 if (CHIP_IS_E1(bp))
12462 bp->dropless_fc = 0;
12463 else
7964211d 12464 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
a18f5128 12465
8d5726c4 12466 bp->mrrs = mrrs;
7a9b2557 12467
2e98ffc2 12468 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
1ab4434c
AE		 12469 if (IS_VF(bp))
12470 bp->rx_ring_size = MAX_RX_AVAIL;
34f80b04 12471
7d323bfd 12472 /* make sure that the numbers are in the right granularity */
523224a3
DK		 12473 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12474 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
34f80b04 12475
fc543637 12476 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
34f80b04 12477
e99e88a9 12478 timer_setup(&bp->timer, bnx2x_timer, 0);
34f80b04 12479 bp->timer.expires = jiffies + bp->current_interval;
34f80b04 12480
0370cf90
BW		 12481 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12482 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
9c73267d 12483 SHMEM2_HAS(bp, dcbx_en) &&
0370cf90 12484 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
9c73267d
YM		 12485 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset) &&
12486 SHMEM2_RD(bp, dcbx_en[BP_PORT(bp)])) {
0370cf90
BW		 12487 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12488 bnx2x_dcbx_init_params(bp);
12489 } else {
12490 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12491 }
e4901dde 12492
619c5cb6
VZ		 12493 if (CHIP_IS_E1x(bp))
12494 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12495 else
12496 bp->cnic_base_cl_id = FP_SB_MAX_E2;
619c5cb6 12497
6383c0b3 12498 /* multiple tx priority */
1ab4434c
AE		 12499 if (IS_VF(bp))
12500 bp->max_cos = 1;
12501 else if (CHIP_IS_E1x(bp))
6383c0b3 12502 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
1ab4434c 12503 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
6383c0b3 12504 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
1ab4434c 12505 else if (CHIP_IS_E3B0(bp))
6383c0b3 12506 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
1ab4434c
AE		 12507 else
12508 BNX2X_ERR("unknown chip %x revision %x\n",
12509 CHIP_NUM(bp), CHIP_REV(bp));
12510 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
6383c0b3 12511
55c11941
MS		 12512 /* We need at least one default status block for slow-path events,
12513 * second status block for the L2 queue, and a third status block for
16a5fd92 12514 * CNIC if supported.
55c11941 12515 */
60cad4e6
AE		 12516 if (IS_VF(bp))
12517 bp->min_msix_vec_cnt = 1;
12518 else if (CNIC_SUPPORT(bp))
55c11941 12519 bp->min_msix_vec_cnt = 3;
60cad4e6 12520 else /* PF w/o cnic */
55c11941
MS		 12521 bp->min_msix_vec_cnt = 2;
12522 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12523
5bb680d6
MS		 12524 bp->dump_preset_idx = 1;
12525
eeed018c
MK		 12526 if (CHIP_IS_E3B0(bp))
12527 bp->flags |= PTP_SUPPORTED;
12528
34f80b04 12529 return rc;
a2fbb9ea
ET		 12530}
12531
de0c62db
DK		 12532/****************************************************************************
12533* General service functions
12534****************************************************************************/
a2fbb9ea 12535
619c5cb6
VZ		 12536/*
12537 * net_device service functions
12538 */
12539
bb2a0f7a 12540/* called with rtnl_lock */
a2fbb9ea
ET		 12541static int bnx2x_open(struct net_device *dev)
12542{
12543 struct bnx2x *bp = netdev_priv(dev);
8395be5e 12544 int rc;
a2fbb9ea 12545
1355b704
MY		 12546 bp->stats_init = true;
12547
6eccabb3
EG		 12548 netif_carrier_off(dev);
12549
a2fbb9ea
ET		 12550 bnx2x_set_power_state(bp, PCI_D0);
12551
ad5afc89 12552 /* If parity had happen during the unload, then attentions
c9ee9206
VZ		 12553 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12554 * want the first function loaded on the current engine to
12555 * complete the recovery.
ad5afc89 12556 * Parity recovery is only relevant for PF driver.
c9ee9206 12557 */
ad5afc89 12558 if (IS_PF(bp)) {
1a6974b2
YM		 12559 int other_engine = BP_PATH(bp) ? 0 : 1;
12560 bool other_load_status, load_status;
12561 bool global = false;
12562
ad5afc89
AE		 12563 other_load_status = bnx2x_get_load_status(bp, other_engine);
12564 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12565 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12566 bnx2x_chk_parity_attn(bp, &global, true)) {
12567 do {
12568 /* If there are attentions and they are in a
12569 * global blocks, set the GLOBAL_RESET bit
12570 * regardless whether it will be this function
12571 * that will complete the recovery or not.
12572 */
12573 if (global)
12574 bnx2x_set_reset_global(bp);
72fd0718 12575
ad5afc89
AE		 12576 /* Only the first function on the current
12577 * engine should try to recover in open. In case
12578 * of attentions in global blocks only the first
12579 * in the chip should try to recover.
12580 */
12581 if ((!load_status &&
12582 (!global || !other_load_status)) &&
12583 bnx2x_trylock_leader_lock(bp) &&
12584 !bnx2x_leader_reset(bp)) {
12585 netdev_info(bp->dev,
12586 "Recovered in open\n");
12587 break;
12588 }
72fd0718 12589
ad5afc89
AE		 12590 /* recovery has failed... */
12591 bnx2x_set_power_state(bp, PCI_D3hot);
12592 bp->recovery_state = BNX2X_RECOVERY_FAILED;
72fd0718 12593
ad5afc89
AE		 12594 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12595 "If you still see this message after a few retries then power cycle is required.\n");
72fd0718 12596
ad5afc89
AE		 12597 return -EAGAIN;
12598 } while (0);
12599 }
12600 }
72fd0718
VZ		 12601
12602 bp->recovery_state = BNX2X_RECOVERY_DONE;
8395be5e
AE		 12603 rc = bnx2x_nic_load(bp, LOAD_OPEN);
12604 if (rc)
12605 return rc;
f34fa14c 12606
883ce97d 12607 if (IS_PF(bp))
6b352912 12608 udp_tunnel_get_rx_info(dev);
f34fa14c 12609
9a8130bc 12610 return 0;
a2fbb9ea
ET		 12611}
12612
bb2a0f7a 12613/* called with rtnl_lock */
56ad3152 12614static int bnx2x_close(struct net_device *dev)
a2fbb9ea 12615{
a2fbb9ea
ET		 12616 struct bnx2x *bp = netdev_priv(dev);
12617
12618 /* Unload the driver, release IRQs */
5d07d868 12619 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
c9ee9206 12620
a2fbb9ea
ET		 12621 return 0;
12622}
12623
e8c6ae9f 12624struct bnx2x_mcast_list_elem_group
6e30dd4e 12625{
e8c6ae9f
JB		 12626 struct list_head mcast_group_link;
12627 struct bnx2x_mcast_list_elem mcast_elems[];
12628};
6e30dd4e 12629
e8c6ae9f
JB		 12630#define MCAST_ELEMS_PER_PG \
12631 ((PAGE_SIZE - sizeof(struct bnx2x_mcast_list_elem_group)) / \
12632 sizeof(struct bnx2x_mcast_list_elem))
12633
12634static void bnx2x_free_mcast_macs_list(struct list_head *mcast_group_list)
12635{
12636 struct bnx2x_mcast_list_elem_group *current_mcast_group;
12637
12638 while (!list_empty(mcast_group_list)) {
12639 current_mcast_group = list_first_entry(mcast_group_list,
12640 struct bnx2x_mcast_list_elem_group,
12641 mcast_group_link);
12642 list_del(&current_mcast_group->mcast_group_link);
12643 free_page((unsigned long)current_mcast_group);
c7b7b483 12644 }
e8c6ae9f 12645}
6e30dd4e 12646
e8c6ae9f
JB		 12647static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12648 struct bnx2x_mcast_ramrod_params *p,
12649 struct list_head *mcast_group_list)
12650{
12651 struct bnx2x_mcast_list_elem *mc_mac;
12652 struct netdev_hw_addr *ha;
12653 struct bnx2x_mcast_list_elem_group *current_mcast_group = NULL;
12654 int mc_count = netdev_mc_count(bp->dev);
12655 int offset = 0;
6e30dd4e 12656
e8c6ae9f 12657 INIT_LIST_HEAD(&p->mcast_list);
619c5cb6 12658 netdev_for_each_mc_addr(ha, bp->dev) {
e8c6ae9f
JB		 12659 if (!offset) {
12660 current_mcast_group =
12661 (struct bnx2x_mcast_list_elem_group *)
12662 __get_free_page(GFP_ATOMIC);
12663 if (!current_mcast_group) {
12664 bnx2x_free_mcast_macs_list(mcast_group_list);
12665 BNX2X_ERR("Failed to allocate mc MAC list\n");
12666 return -ENOMEM;
12667 }
12668 list_add(&current_mcast_group->mcast_group_link,
12669 mcast_group_list);
12670 }
12671 mc_mac = &current_mcast_group->mcast_elems[offset];
619c5cb6
VZ		 12672 mc_mac->mac = bnx2x_mc_addr(ha);
12673 list_add_tail(&mc_mac->link, &p->mcast_list);
e8c6ae9f
JB		 12674 offset++;
12675 if (offset == MCAST_ELEMS_PER_PG)
12676 offset = 0;
6e30dd4e 12677 }
619c5cb6 12678 p->mcast_list_len = mc_count;
619c5cb6 12679 return 0;
6e30dd4e
VZ		 12680}
12681
619c5cb6
VZ		 12682/**
12683 * bnx2x_set_uc_list - configure a new unicast MACs list.
12684 *
12685 * @bp: driver handle
6e30dd4e 12686 *
619c5cb6 12687 * We will use zero (0) as a MAC type for these MACs.
6e30dd4e 12688 */
1191cb83 12689static int bnx2x_set_uc_list(struct bnx2x *bp)
6e30dd4e 12690{
619c5cb6 12691 int rc;
6e30dd4e 12692 struct net_device *dev = bp->dev;
6e30dd4e 12693 struct netdev_hw_addr *ha;
15192a8c 12694 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
619c5cb6 12695 unsigned long ramrod_flags = 0;
6e30dd4e 12696
619c5cb6
VZ		 12697 /* First schedule a cleanup up of old configuration */
12698 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12699 if (rc < 0) {
12700 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12701 return rc;
12702 }
6e30dd4e
VZ		 12703
12704 netdev_for_each_uc_addr(ha, dev) {
619c5cb6
VZ		 12705 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12706 BNX2X_UC_LIST_MAC, &ramrod_flags);
7b5342d9
YM		 12707 if (rc == -EEXIST) {
12708 DP(BNX2X_MSG_SP,
12709 "Failed to schedule ADD operations: %d\n", rc);
12710 /* do not treat adding same MAC as error */
12711 rc = 0;
12712
12713 } else if (rc < 0) {
12714
619c5cb6
VZ		 12715 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12716 rc);
12717 return rc;
6e30dd4e
VZ		 12718 }
12719 }
12720
619c5cb6
VZ		 12721 /* Execute the pending commands */
12722 __set_bit(RAMROD_CONT, &ramrod_flags);
12723 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12724 BNX2X_UC_LIST_MAC, &ramrod_flags);
6e30dd4e
VZ		 12725}
12726
c7b7b483 12727static int bnx2x_set_mc_list_e1x(struct bnx2x *bp)
6e30dd4e 12728{
e8c6ae9f 12729 LIST_HEAD(mcast_group_list);
619c5cb6 12730 struct net_device *dev = bp->dev;
3b603066 12731 struct bnx2x_mcast_ramrod_params rparam = {NULL};
619c5cb6 12732 int rc = 0;
6e30dd4e 12733
619c5cb6 12734 rparam.mcast_obj = &bp->mcast_obj;
6e30dd4e 12735
619c5cb6
VZ		 12736 /* first, clear all configured multicast MACs */
12737 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12738 if (rc < 0) {
51c1a580 12739 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
619c5cb6
VZ		 12740 return rc;
12741 }
6e30dd4e 12742
619c5cb6
VZ		 12743 /* then, configure a new MACs list */
12744 if (netdev_mc_count(dev)) {
e8c6ae9f 12745 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
c7b7b483 12746 if (rc)
619c5cb6 12747 return rc;
6e30dd4e 12748
619c5cb6
VZ		 12749 /* Now add the new MACs */
12750 rc = bnx2x_config_mcast(bp, &rparam,
12751 BNX2X_MCAST_CMD_ADD);
12752 if (rc < 0)
51c1a580
MS		 12753 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12754 rc);
6e30dd4e 12755
e8c6ae9f 12756 bnx2x_free_mcast_macs_list(&mcast_group_list);
619c5cb6 12757 }
6e30dd4e 12758
619c5cb6 12759 return rc;
6e30dd4e
VZ		 12760}
12761
c7b7b483
YM		 12762static int bnx2x_set_mc_list(struct bnx2x *bp)
12763{
e8c6ae9f 12764 LIST_HEAD(mcast_group_list);
c7b7b483
YM		 12765 struct bnx2x_mcast_ramrod_params rparam = {NULL};
12766 struct net_device *dev = bp->dev;
12767 int rc = 0;
12768
12769 /* On older adapters, we need to flush and re-add filters */
12770 if (CHIP_IS_E1x(bp))
12771 return bnx2x_set_mc_list_e1x(bp);
12772
12773 rparam.mcast_obj = &bp->mcast_obj;
12774
12775 if (netdev_mc_count(dev)) {
e8c6ae9f 12776 rc = bnx2x_init_mcast_macs_list(bp, &rparam, &mcast_group_list);
c7b7b483
YM		 12777 if (rc)
12778 return rc;
12779
12780 /* Override the curently configured set of mc filters */
12781 rc = bnx2x_config_mcast(bp, &rparam,
12782 BNX2X_MCAST_CMD_SET);
12783 if (rc < 0)
12784 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12785 rc);
12786
e8c6ae9f 12787 bnx2x_free_mcast_macs_list(&mcast_group_list);
c7b7b483
YM		 12788 } else {
12789 /* If no mc addresses are required, flush the configuration */
12790 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
d0c32a16 12791 if (rc < 0)
c7b7b483
YM		 12792 BNX2X_ERR("Failed to clear multicast configuration %d\n",
12793 rc);
12794 }
12795
12796 return rc;
12797}
12798
619c5cb6 12799/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
a8f47eb7 12800static void bnx2x_set_rx_mode(struct net_device *dev)
34f80b04
EG		 12801{
12802 struct bnx2x *bp = netdev_priv(dev);
34f80b04
EG		 12803
12804 if (bp->state != BNX2X_STATE_OPEN) {
12805 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12806 return;
8b09be5f
YM		 12807 } else {
12808 /* Schedule an SP task to handle rest of change */
230bb0f3
YM		 12809 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12810 NETIF_MSG_IFUP);
34f80b04 12811 }
8b09be5f
YM		 12812}
12813
12814void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12815{
12816 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
34f80b04 12817
619c5cb6 12818 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
34f80b04 12819
8b09be5f
YM		 12820 netif_addr_lock_bh(bp->dev);
12821
12822 if (bp->dev->flags & IFF_PROMISC) {
34f80b04 12823 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f
YM		 12824 } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12825 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12826 CHIP_IS_E1(bp))) {
34f80b04 12827 rx_mode = BNX2X_RX_MODE_ALLMULTI;
8b09be5f 12828 } else {
381ac16b
AE		 12829 if (IS_PF(bp)) {
12830 /* some multicasts */
12831 if (bnx2x_set_mc_list(bp) < 0)
12832 rx_mode = BNX2X_RX_MODE_ALLMULTI;
34f80b04 12833
8b09be5f
YM		 12834 /* release bh lock, as bnx2x_set_uc_list might sleep */
12835 netif_addr_unlock_bh(bp->dev);
381ac16b
AE		 12836 if (bnx2x_set_uc_list(bp) < 0)
12837 rx_mode = BNX2X_RX_MODE_PROMISC;
8b09be5f 12838 netif_addr_lock_bh(bp->dev);
381ac16b
AE		 12839 } else {
12840 /* configuring mcast to a vf involves sleeping (when we
8b09be5f 12841 * wait for the pf's response).
381ac16b 12842 */
230bb0f3
YM		 12843 bnx2x_schedule_sp_rtnl(bp,
12844 BNX2X_SP_RTNL_VFPF_MCAST, 0);
381ac16b 12845 }
34f80b04
EG		 12846 }
12847
12848 bp->rx_mode = rx_mode;
614c76df 12849 /* handle ISCSI SD mode */
2e98ffc2 12850 if (IS_MF_ISCSI_ONLY(bp))
614c76df 12851 bp->rx_mode = BNX2X_RX_MODE_NONE;
619c5cb6
VZ		 12852
12853 /* Schedule the rx_mode command */
12854 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12855 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8b09be5f 12856 netif_addr_unlock_bh(bp->dev);
619c5cb6
VZ		 12857 return;
12858 }
12859
381ac16b
AE		 12860 if (IS_PF(bp)) {
12861 bnx2x_set_storm_rx_mode(bp);
8b09be5f 12862 netif_addr_unlock_bh(bp->dev);
381ac16b 12863 } else {
8b09be5f
YM		 12864 /* VF will need to request the PF to make this change, and so
12865 * the VF needs to release the bottom-half lock prior to the
12866 * request (as it will likely require sleep on the VF side)
381ac16b 12867 */
8b09be5f
YM		 12868 netif_addr_unlock_bh(bp->dev);
12869 bnx2x_vfpf_storm_rx_mode(bp);
381ac16b 12870 }
34f80b04
EG		 12871}
12872
c18487ee 12873/* called with rtnl_lock */
01cd4528
EG		 12874static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12875 int devad, u16 addr)
a2fbb9ea 12876{
01cd4528
EG		 12877 struct bnx2x *bp = netdev_priv(netdev);
12878 u16 value;
12879 int rc;
a2fbb9ea 12880
01cd4528
EG		 12881 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12882 prtad, devad, addr);
a2fbb9ea 12883
01cd4528
EG		 12884 /* The HW expects different devad if CL22 is used */
12885 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
c18487ee 12886
01cd4528 12887 bnx2x_acquire_phy_lock(bp);
e10bc84d 12888 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
01cd4528
EG		 12889 bnx2x_release_phy_lock(bp);
12890 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
a2fbb9ea 12891
01cd4528
EG		 12892 if (!rc)
12893 rc = value;
12894 return rc;
12895}
a2fbb9ea 12896
01cd4528
EG		 12897/* called with rtnl_lock */
12898static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12899 u16 addr, u16 value)
12900{
12901 struct bnx2x *bp = netdev_priv(netdev);
01cd4528
EG		 12902 int rc;
12903
51c1a580
MS		 12904 DP(NETIF_MSG_LINK,
12905 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12906 prtad, devad, addr, value);
01cd4528 12907
01cd4528
EG		 12908 /* The HW expects different devad if CL22 is used */
12909 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
a2fbb9ea 12910
01cd4528 12911 bnx2x_acquire_phy_lock(bp);
e10bc84d 12912 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
01cd4528
EG		 12913 bnx2x_release_phy_lock(bp);
12914 return rc;
12915}
c18487ee 12916
01cd4528
EG		 12917/* called with rtnl_lock */
12918static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12919{
12920 struct bnx2x *bp = netdev_priv(dev);
12921 struct mii_ioctl_data *mdio = if_mii(ifr);
a2fbb9ea 12922
01cd4528
EG		 12923 if (!netif_running(dev))
12924 return -EAGAIN;
12925
eeed018c
MK		 12926 switch (cmd) {
12927 case SIOCSHWTSTAMP:
12928 return bnx2x_hwtstamp_ioctl(bp, ifr);
12929 default:
12930 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12931 mdio->phy_id, mdio->reg_num, mdio->val_in);
12932 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12933 }
a2fbb9ea
ET		 12934}
12935
614c76df
DK		 12936static int bnx2x_validate_addr(struct net_device *dev)
12937{
12938 struct bnx2x *bp = netdev_priv(dev);
12939
e09b74d0
AE		 12940 /* query the bulletin board for mac address configured by the PF */
12941 if (IS_VF(bp))
12942 bnx2x_sample_bulletin(bp);
12943
2e98ffc2 12944 if (!is_valid_ether_addr(dev->dev_addr)) {
51c1a580 12945 BNX2X_ERR("Non-valid Ethernet address\n");
614c76df 12946 return -EADDRNOTAVAIL;
51c1a580 12947 }
614c76df
DK		 12948 return 0;
12949}
12950
3d7d562c 12951static int bnx2x_get_phys_port_id(struct net_device *netdev,
02637fce 12952 struct netdev_phys_item_id *ppid)
3d7d562c
YM		 12953{
12954 struct bnx2x *bp = netdev_priv(netdev);
12955
12956 if (!(bp->flags & HAS_PHYS_PORT_ID))
12957 return -EOPNOTSUPP;
12958
12959 ppid->id_len = sizeof(bp->phys_port_id);
12960 memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12961
12962 return 0;
12963}
12964
5f35227e
JG		 12965static netdev_features_t bnx2x_features_check(struct sk_buff *skb,
12966 struct net_device *dev,
12967 netdev_features_t features)
51de7bb9 12968{
8914a595
DA		 12969 /*
12970 * A skb with gso_size + header length > 9700 will cause a
12971 * firmware panic. Drop GSO support.
12972 *
12973 * Eventually the upper layer should not pass these packets down.
12974 *
12975 * For speed, if the gso_size is <= 9000, assume there will
12976 * not be 700 bytes of headers and pass it through. Only do a
12977 * full (slow) validation if the gso_size is > 9000.
12978 *
12979 * (Due to the way SKB_BY_FRAGS works this will also do a full
12980 * validation in that case.)
12981 */
12982 if (unlikely(skb_is_gso(skb) &&
12983 (skb_shinfo(skb)->gso_size > 9000) &&
12984 !skb_gso_validate_mac_len(skb, 9700)))
12985 features &= ~NETIF_F_GSO_MASK;
12986
8cb65d00 12987 features = vlan_features_check(skb, features);
5f35227e 12988 return vxlan_features_check(skb, features);
51de7bb9
JS		 12989}
12990
05cc5a39
YM		 12991static int __bnx2x_vlan_configure_vid(struct bnx2x *bp, u16 vid, bool add)
12992{
12993 int rc;
12994
12995 if (IS_PF(bp)) {
12996 unsigned long ramrod_flags = 0;
12997
12998 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12999 rc = bnx2x_set_vlan_one(bp, vid, &bp->sp_objs->vlan_obj,
13000 add, &ramrod_flags);
13001 } else {
13002 rc = bnx2x_vfpf_update_vlan(bp, vid, bp->fp->index, add);
13003 }
13004
13005 return rc;
13006}
13007
a02cc9d3 13008static int bnx2x_vlan_configure_vid_list(struct bnx2x *bp)
05cc5a39
YM		 13009{
13010 struct bnx2x_vlan_entry *vlan;
13011 int rc = 0;
13012
a02cc9d3 13013 /* Configure all non-configured entries */
05cc5a39 13014 list_for_each_entry(vlan, &bp->vlan_reg, link) {
a02cc9d3 13015 if (vlan->hw)
05cc5a39
YM		 13016 continue;
13017
a02cc9d3
MS		 13018 if (bp->vlan_cnt >= bp->vlan_credit)
13019 return -ENOBUFS;
05cc5a39
YM		 13020
13021 rc = __bnx2x_vlan_configure_vid(bp, vlan->vid, true);
13022 if (rc) {
a02cc9d3
MS		 13023 BNX2X_ERR("Unable to config VLAN %d\n", vlan->vid);
13024 return rc;
05cc5a39 13025 }
a02cc9d3
MS		 13026
13027 DP(NETIF_MSG_IFUP, "HW configured for VLAN %d\n", vlan->vid);
13028 vlan->hw = true;
13029 bp->vlan_cnt++;
05cc5a39
YM		 13030 }
13031
a02cc9d3
MS		 13032 return 0;
13033}
13034
13035static void bnx2x_vlan_configure(struct bnx2x *bp, bool set_rx_mode)
13036{
13037 bool need_accept_any_vlan;
13038
13039 need_accept_any_vlan = !!bnx2x_vlan_configure_vid_list(bp);
13040
13041 if (bp->accept_any_vlan != need_accept_any_vlan) {
13042 bp->accept_any_vlan = need_accept_any_vlan;
13043 DP(NETIF_MSG_IFUP, "Accept all VLAN %s\n",
13044 bp->accept_any_vlan ? "raised" : "cleared");
13045 if (set_rx_mode) {
13046 if (IS_PF(bp))
13047 bnx2x_set_rx_mode_inner(bp);
13048 else
13049 bnx2x_vfpf_storm_rx_mode(bp);
13050 }
13051 }
13052}
13053
13054int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp)
13055{
a02cc9d3
MS		 13056 /* Don't set rx mode here. Our caller will do it. */
13057 bnx2x_vlan_configure(bp, false);
13058
13059 return 0;
05cc5a39
YM		 13060}
13061
13062static int bnx2x_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
13063{
13064 struct bnx2x *bp = netdev_priv(dev);
13065 struct bnx2x_vlan_entry *vlan;
05cc5a39
YM		 13066
13067 DP(NETIF_MSG_IFUP, "Adding VLAN %d\n", vid);
13068
13069 vlan = kmalloc(sizeof(*vlan), GFP_KERNEL);
13070 if (!vlan)
13071 return -ENOMEM;
13072
05cc5a39 13073 vlan->vid = vid;
a02cc9d3
MS		 13074 vlan->hw = false;
13075 list_add_tail(&vlan->link, &bp->vlan_reg);
05cc5a39 13076
a02cc9d3
MS		 13077 if (netif_running(dev))
13078 bnx2x_vlan_configure(bp, true);
05cc5a39 13079
a02cc9d3 13080 return 0;
05cc5a39
YM		 13081}
13082
13083static int bnx2x_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
13084{
13085 struct bnx2x *bp = netdev_priv(dev);
13086 struct bnx2x_vlan_entry *vlan;
a02cc9d3 13087 bool found = false;
05cc5a39
YM		 13088 int rc = 0;
13089
05cc5a39
YM		 13090 DP(NETIF_MSG_IFUP, "Removing VLAN %d\n", vid);
13091
05cc5a39 13092 list_for_each_entry(vlan, &bp->vlan_reg, link)
a02cc9d3
MS		 13093 if (vlan->vid == vid) {
13094 found = true;
05cc5a39 13095 break;
a02cc9d3 13096 }
05cc5a39 13097
a02cc9d3 13098 if (!found) {
05cc5a39
YM		 13099 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid);
13100 return -EINVAL;
13101 }
13102
a02cc9d3 13103 if (netif_running(dev) && vlan->hw) {
05cc5a39 13104 rc = __bnx2x_vlan_configure_vid(bp, vid, false);
a02cc9d3
MS		 13105 DP(NETIF_MSG_IFUP, "HW deconfigured for VLAN %d\n", vid);
13106 bp->vlan_cnt--;
13107 }
05cc5a39
YM		 13108
13109 list_del(&vlan->link);
13110 kfree(vlan);
13111
a02cc9d3
MS		 13112 if (netif_running(dev))
13113 bnx2x_vlan_configure(bp, true);
05cc5a39
YM		 13114
13115 DP(NETIF_MSG_IFUP, "Removing VLAN result %d\n", rc);
13116
13117 return rc;
13118}
13119
c64213cd
SH		 13120static const struct net_device_ops bnx2x_netdev_ops = {
13121 .ndo_open = bnx2x_open,
13122 .ndo_stop = bnx2x_close,
13123 .ndo_start_xmit = bnx2x_start_xmit,
8307fa3e 13124 .ndo_select_queue = bnx2x_select_queue,
6e30dd4e 13125 .ndo_set_rx_mode = bnx2x_set_rx_mode,
c64213cd 13126 .ndo_set_mac_address = bnx2x_change_mac_addr,
614c76df 13127 .ndo_validate_addr = bnx2x_validate_addr,
c64213cd
SH		 13128 .ndo_do_ioctl = bnx2x_ioctl,
13129 .ndo_change_mtu = bnx2x_change_mtu,
66371c44
MM		 13130 .ndo_fix_features = bnx2x_fix_features,
13131 .ndo_set_features = bnx2x_set_features,
c64213cd 13132 .ndo_tx_timeout = bnx2x_tx_timeout,
05cc5a39
YM		 13133 .ndo_vlan_rx_add_vid = bnx2x_vlan_rx_add_vid,
13134 .ndo_vlan_rx_kill_vid = bnx2x_vlan_rx_kill_vid,
e4c6734e 13135 .ndo_setup_tc = __bnx2x_setup_tc,
6411280a 13136#ifdef CONFIG_BNX2X_SRIOV
abc5a021 13137 .ndo_set_vf_mac = bnx2x_set_vf_mac,
3cdeec22 13138 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
3ec9f9ca 13139 .ndo_get_vf_config = bnx2x_get_vf_config,
75303965 13140 .ndo_set_vf_spoofchk = bnx2x_set_vf_spoofchk,
6411280a 13141#endif
55c11941 13142#ifdef NETDEV_FCOE_WWNN
bf61ee14
VZ		 13143 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
13144#endif
8f20aa57 13145
3d7d562c 13146 .ndo_get_phys_port_id = bnx2x_get_phys_port_id,
6495d15a 13147 .ndo_set_vf_link_state = bnx2x_set_vf_link_state,
5f35227e 13148 .ndo_features_check = bnx2x_features_check,
6b352912
AD		 13149 .ndo_udp_tunnel_add = bnx2x_udp_tunnel_add,
13150 .ndo_udp_tunnel_del = bnx2x_udp_tunnel_del,
c64213cd
SH		 13151};
13152
1191cb83 13153static int bnx2x_set_coherency_mask(struct bnx2x *bp)
619c5cb6
VZ		 13154{
13155 struct device *dev = &bp->pdev->dev;
13156
8ceafbfa
LT		 13157 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
13158 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
619c5cb6
VZ		 13159 dev_err(dev, "System does not support DMA, aborting\n");
13160 return -EIO;
13161 }
13162
13163 return 0;
13164}
13165
33d8e6a5
YM		 13166static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
13167{
13168 if (bp->flags & AER_ENABLED) {
13169 pci_disable_pcie_error_reporting(bp->pdev);
13170 bp->flags &= ~AER_ENABLED;
13171 }
13172}
13173
1ab4434c
AE		 13174static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
13175 struct net_device *dev, unsigned long board_type)
a2fbb9ea 13176{
a2fbb9ea 13177 int rc;
c22610d0 13178 u32 pci_cfg_dword;
65087cfe
AE		 13179 bool chip_is_e1x = (board_type == BCM57710 ||
13180 board_type == BCM57711 ||
13181 board_type == BCM57711E);
a2fbb9ea
ET		 13182
13183 SET_NETDEV_DEV(dev, &pdev->dev);
a2fbb9ea 13184
34f80b04
EG		 13185 bp->dev = dev;
13186 bp->pdev = pdev;
a2fbb9ea
ET		 13187
13188 rc = pci_enable_device(pdev);
13189 if (rc) {
cdaa7cb8
VZ		 13190 dev_err(&bp->pdev->dev,
13191 "Cannot enable PCI device, aborting\n");
a2fbb9ea
ET		 13192 goto err_out;
13193 }
13194
13195 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
cdaa7cb8
VZ		 13196 dev_err(&bp->pdev->dev,
13197 "Cannot find PCI device base address, aborting\n");
a2fbb9ea
ET		 13198 rc = -ENODEV;
13199 goto err_out_disable;
13200 }
13201
1ab4434c
AE		 13202 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13203 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
a2fbb9ea
ET		 13204 rc = -ENODEV;
13205 goto err_out_disable;
13206 }
13207
092a5fc9
YR		 13208 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
13209 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
13210 PCICFG_REVESION_ID_ERROR_VAL) {
13211 pr_err("PCI device error, probably due to fan failure, aborting\n");
13212 rc = -ENODEV;
13213 goto err_out_disable;
13214 }
13215
34f80b04
EG		 13216 if (atomic_read(&pdev->enable_cnt) == 1) {
13217 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
13218 if (rc) {
cdaa7cb8
VZ		 13219 dev_err(&bp->pdev->dev,
13220 "Cannot obtain PCI resources, aborting\n");
34f80b04
EG		 13221 goto err_out_disable;
13222 }
a2fbb9ea 13223
34f80b04
EG		 13224 pci_set_master(pdev);
13225 pci_save_state(pdev);
13226 }
a2fbb9ea 13227
1ab4434c 13228 if (IS_PF(bp)) {
29ed74c3 13229 if (!pdev->pm_cap) {
1ab4434c
AE		 13230 dev_err(&bp->pdev->dev,
13231 "Cannot find power management capability, aborting\n");
13232 rc = -EIO;
13233 goto err_out_release;
13234 }
a2fbb9ea
ET		 13235 }
13236
77c98e6a 13237 if (!pci_is_pcie(pdev)) {
51c1a580 13238 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
a2fbb9ea
ET		 13239 rc = -EIO;
13240 goto err_out_release;
13241 }
13242
619c5cb6
VZ		 13243 rc = bnx2x_set_coherency_mask(bp);
13244 if (rc)
a2fbb9ea 13245 goto err_out_release;
a2fbb9ea 13246
34f80b04
EG		 13247 dev->mem_start = pci_resource_start(pdev, 0);
13248 dev->base_addr = dev->mem_start;
13249 dev->mem_end = pci_resource_end(pdev, 0);
a2fbb9ea
ET		 13250
13251 dev->irq = pdev->irq;
13252
275f165f 13253 bp->regview = pci_ioremap_bar(pdev, 0);
a2fbb9ea 13254 if (!bp->regview) {
cdaa7cb8
VZ		 13255 dev_err(&bp->pdev->dev,
13256 "Cannot map register space, aborting\n");
a2fbb9ea
ET		 13257 rc = -ENOMEM;
13258 goto err_out_release;
13259 }
13260
c22610d0
AE		 13261 /* In E1/E1H use pci device function given by kernel.
13262 * In E2/E3 read physical function from ME register since these chips
13263 * support Physical Device Assignment where kernel BDF maybe arbitrary
13264 * (depending on hypervisor).
13265 */
2de67439 13266 if (chip_is_e1x) {
c22610d0 13267 bp->pf_num = PCI_FUNC(pdev->devfn);
2de67439
YM		 13268 } else {
13269 /* chip is E2/3*/
c22610d0
AE		 13270 pci_read_config_dword(bp->pdev,
13271 PCICFG_ME_REGISTER, &pci_cfg_dword);
13272 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
2de67439 13273 ME_REG_ABS_PF_NUM_SHIFT);
c22610d0 13274 }
51c1a580 13275 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
c22610d0 13276
34f80b04
EG		 13277 /* clean indirect addresses */
13278 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
13279 PCICFG_VENDOR_ID_OFFSET);
33d8e6a5 13280
da293700
BK		 13281 /* Set PCIe reset type to fundamental for EEH recovery */
13282 pdev->needs_freset = 1;
13283
33d8e6a5
YM		 13284 /* AER (Advanced Error reporting) configuration */
13285 rc = pci_enable_pcie_error_reporting(pdev);
13286 if (!rc)
13287 bp->flags |= AER_ENABLED;
13288 else
13289 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
13290
a5c53dbc
DK		 13291 /*
13292 * Clean the following indirect addresses for all functions since it
9f0096a1
DK		 13293 * is not used by the driver.
13294 */
1ab4434c
AE		 13295 if (IS_PF(bp)) {
13296 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
13297 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
13298 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
13299 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
13300
13301 if (chip_is_e1x) {
13302 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
13303 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
13304 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
13305 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
13306 }
a5c53dbc 13307
1ab4434c
AE		 13308 /* Enable internal target-read (in case we are probed after PF
13309 * FLR). Must be done prior to any BAR read access. Only for
13310 * 57712 and up
13311 */
13312 if (!chip_is_e1x)
13313 REG_WR(bp,
13314 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
a5c53dbc 13315 }
a2fbb9ea 13316
34f80b04 13317 dev->watchdog_timeo = TX_TIMEOUT;
a2fbb9ea 13318
c64213cd 13319 dev->netdev_ops = &bnx2x_netdev_ops;
005a07ba 13320 bnx2x_set_ethtool_ops(bp, dev);
5316bc0b 13321
01789349
JP		 13322 dev->priv_flags |= IFF_UNICAST_FLT;
13323
66371c44 13324 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
621b4d66 13325 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
3c3def5f 13326 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO | NETIF_F_GRO_HW |
f646968f 13327 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
a8e0c246 13328 if (!chip_is_e1x) {
736c4c1d
AD		 13329 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13330 NETIF_F_GSO_IPXIP4 |
13331 NETIF_F_GSO_UDP_TUNNEL |
13332 NETIF_F_GSO_UDP_TUNNEL_CSUM |
13333 NETIF_F_GSO_PARTIAL;
13334
a848ade4
DK		 13335 dev->hw_enc_features =
13336 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
13337 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
7e13318d 13338 NETIF_F_GSO_IPXIP4 |
736c4c1d
AD		 13339 NETIF_F_GSO_GRE | NETIF_F_GSO_GRE_CSUM |
13340 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_UDP_TUNNEL_CSUM |
13341 NETIF_F_GSO_PARTIAL;
13342
13343 dev->gso_partial_features = NETIF_F_GSO_GRE_CSUM |
13344 NETIF_F_GSO_UDP_TUNNEL_CSUM;
a848ade4 13345 }
66371c44
MM		 13346
13347 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
13348 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
13349
05cc5a39 13350 if (IS_PF(bp)) {
ab6d7846 13351 if (chip_is_e1x)
05cc5a39
YM		 13352 bp->accept_any_vlan = true;
13353 else
13354 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
05cc5a39 13355 }
83bd9eb8
MS		 13356 /* For VF we'll know whether to enable VLAN filtering after
13357 * getting a response to CHANNEL_TLV_ACQUIRE from PF.
13358 */
05cc5a39 13359
f646968f 13360 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
edd31476 13361 dev->features |= NETIF_F_HIGHDMA;
3c3def5f
MC		 13362 if (dev->features & NETIF_F_LRO)
13363 dev->features &= ~NETIF_F_GRO_HW;
a2fbb9ea 13364
538dd2e3
MB		 13365 /* Add Loopback capability to the device */
13366 dev->hw_features |= NETIF_F_LOOPBACK;
13367
98507672 13368#ifdef BCM_DCBNL
785b9b1a
SR		 13369 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
13370#endif
13371
e1c6dcca
JW		 13372 /* MTU range, 46 - 9600 */
13373 dev->min_mtu = ETH_MIN_PACKET_SIZE;
13374 dev->max_mtu = ETH_MAX_JUMBO_PACKET_SIZE;
13375
01cd4528
EG		 13376 /* get_port_hwinfo() will set prtad and mmds properly */
13377 bp->mdio.prtad = MDIO_PRTAD_NONE;
13378 bp->mdio.mmds = 0;
13379 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
13380 bp->mdio.dev = dev;
13381 bp->mdio.mdio_read = bnx2x_mdio_read;
13382 bp->mdio.mdio_write = bnx2x_mdio_write;
13383
a2fbb9ea
ET		 13384 return 0;
13385
a2fbb9ea 13386err_out_release:
34f80b04
EG		 13387 if (atomic_read(&pdev->enable_cnt) == 1)
13388 pci_release_regions(pdev);
a2fbb9ea
ET		 13389
13390err_out_disable:
13391 pci_disable_device(pdev);
a2fbb9ea
ET		 13392
13393err_out:
13394 return rc;
13395}
13396
6891dd25 13397static int bnx2x_check_firmware(struct bnx2x *bp)
94a78b79 13398{
37f9ce62 13399 const struct firmware *firmware = bp->firmware;
94a78b79
VZ		 13400 struct bnx2x_fw_file_hdr *fw_hdr;
13401 struct bnx2x_fw_file_section *sections;
94a78b79 13402 u32 offset, len, num_ops;
86564c3f 13403 __be16 *ops_offsets;
94a78b79 13404 int i;
37f9ce62 13405 const u8 *fw_ver;
94a78b79 13406
51c1a580
MS		 13407 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
13408 BNX2X_ERR("Wrong FW size\n");
94a78b79 13409 return -EINVAL;
51c1a580 13410 }
94a78b79
VZ		 13411
13412 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
13413 sections = (struct bnx2x_fw_file_section *)fw_hdr;
13414
13415 /* Make sure none of the offsets and sizes make us read beyond
13416 * the end of the firmware data */
13417 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
13418 offset = be32_to_cpu(sections[i].offset);
13419 len = be32_to_cpu(sections[i].len);
13420 if (offset + len > firmware->size) {
51c1a580 13421 BNX2X_ERR("Section %d length is out of bounds\n", i);
94a78b79
VZ		 13422 return -EINVAL;
13423 }
13424 }
13425
13426 /* Likewise for the init_ops offsets */
13427 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
86564c3f 13428 ops_offsets = (__force __be16 *)(firmware->data + offset);
94a78b79
VZ		 13429 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
13430
13431 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
13432 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
51c1a580 13433 BNX2X_ERR("Section offset %d is out of bounds\n", i);
94a78b79
VZ		 13434 return -EINVAL;
13435 }
13436 }
13437
13438 /* Check FW version */
13439 offset = be32_to_cpu(fw_hdr->fw_version.offset);
13440 fw_ver = firmware->data + offset;
13441 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
13442 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
13443 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
13444 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
51c1a580
MS		 13445 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13446 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
13447 BCM_5710_FW_MAJOR_VERSION,
94a78b79
VZ		 13448 BCM_5710_FW_MINOR_VERSION,
13449 BCM_5710_FW_REVISION_VERSION,
13450 BCM_5710_FW_ENGINEERING_VERSION);
ab6ad5a4 13451 return -EINVAL;
94a78b79
VZ		 13452 }
13453
13454 return 0;
13455}
13456
1191cb83 13457static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13458{
ab6ad5a4
EG		 13459 const __be32 *source = (const __be32 *)_source;
13460 u32 *target = (u32 *)_target;
94a78b79 13461 u32 i;
94a78b79
VZ		 13462
13463 for (i = 0; i < n/4; i++)
13464 target[i] = be32_to_cpu(source[i]);
13465}
13466
13467/*
13468 Ops array is stored in the following format:
13469 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13470 */
1191cb83 13471static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
94a78b79 13472{
ab6ad5a4
EG		 13473 const __be32 *source = (const __be32 *)_source;
13474 struct raw_op *target = (struct raw_op *)_target;
94a78b79 13475 u32 i, j, tmp;
94a78b79 13476
ab6ad5a4 13477 for (i = 0, j = 0; i < n/8; i++, j += 2) {
94a78b79
VZ		 13478 tmp = be32_to_cpu(source[j]);
13479 target[i].op = (tmp >> 24) & 0xff;
cdaa7cb8
VZ		 13480 target[i].offset = tmp & 0xffffff;
13481 target[i].raw_data = be32_to_cpu(source[j + 1]);
94a78b79
VZ		 13482 }
13483}
ab6ad5a4 13484
1aa8b471 13485/* IRO array is stored in the following format:
523224a3
DK		 13486 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13487 */
1191cb83 13488static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
523224a3
DK		 13489{
13490 const __be32 *source = (const __be32 *)_source;
13491 struct iro *target = (struct iro *)_target;
13492 u32 i, j, tmp;
13493
13494 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
13495 target[i].base = be32_to_cpu(source[j]);
13496 j++;
13497 tmp = be32_to_cpu(source[j]);
13498 target[i].m1 = (tmp >> 16) & 0xffff;
13499 target[i].m2 = tmp & 0xffff;
13500 j++;
13501 tmp = be32_to_cpu(source[j]);
13502 target[i].m3 = (tmp >> 16) & 0xffff;
13503 target[i].size = tmp & 0xffff;
13504 j++;
13505 }
13506}
13507
1191cb83 13508static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
94a78b79 13509{
ab6ad5a4
EG		 13510 const __be16 *source = (const __be16 *)_source;
13511 u16 *target = (u16 *)_target;
94a78b79 13512 u32 i;
94a78b79
VZ		 13513
13514 for (i = 0; i < n/2; i++)
13515 target[i] = be16_to_cpu(source[i]);
13516}
13517
7995c64e
JP		 13518#define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13519do { \
13520 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13521 bp->arr = kmalloc(len, GFP_KERNEL); \
e404decb 13522 if (!bp->arr) \
7995c64e 13523 goto lbl; \
7995c64e
JP		 13524 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13525 (u8 *)bp->arr, len); \
13526} while (0)
94a78b79 13527
3b603066 13528static int bnx2x_init_firmware(struct bnx2x *bp)
94a78b79 13529{
c0ea452e 13530 const char *fw_file_name;
94a78b79 13531 struct bnx2x_fw_file_hdr *fw_hdr;
45229b42 13532 int rc;
94a78b79 13533
c0ea452e
MS		 13534 if (bp->firmware)
13535 return 0;
94a78b79 13536
c0ea452e
MS		 13537 if (CHIP_IS_E1(bp))
13538 fw_file_name = FW_FILE_NAME_E1;
13539 else if (CHIP_IS_E1H(bp))
13540 fw_file_name = FW_FILE_NAME_E1H;
13541 else if (!CHIP_IS_E1x(bp))
13542 fw_file_name = FW_FILE_NAME_E2;
13543 else {
13544 BNX2X_ERR("Unsupported chip revision\n");
13545 return -EINVAL;
13546 }
13547 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
94a78b79 13548
c0ea452e
MS		 13549 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
13550 if (rc) {
13551 BNX2X_ERR("Can't load firmware file %s\n",
13552 fw_file_name);
13553 goto request_firmware_exit;
13554 }
eb2afd4a 13555
c0ea452e
MS		 13556 rc = bnx2x_check_firmware(bp);
13557 if (rc) {
13558 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
13559 goto request_firmware_exit;
94a78b79
VZ		 13560 }
13561
13562 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
13563
13564 /* Initialize the pointers to the init arrays */
13565 /* Blob */
005f7e68 13566 rc = -ENOMEM;
94a78b79
VZ		 13567 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
13568
13569 /* Opcodes */
13570 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
13571
13572 /* Offsets */
ab6ad5a4
EG		 13573 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
13574 be16_to_cpu_n);
94a78b79
VZ		 13575
13576 /* STORMs firmware */
573f2035
EG		 13577 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13578 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
13579 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
13580 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
13581 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13582 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
13583 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
13584 be32_to_cpu(fw_hdr->usem_pram_data.offset);
13585 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13586 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
13587 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
13588 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13589 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13590 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13591 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
13592 be32_to_cpu(fw_hdr->csem_pram_data.offset);
523224a3
DK		 13593 /* IRO */
13594 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
94a78b79
VZ		 13595
13596 return 0;
ab6ad5a4 13597
523224a3
DK		 13598iro_alloc_err:
13599 kfree(bp->init_ops_offsets);
94a78b79
VZ		 13600init_offsets_alloc_err:
13601 kfree(bp->init_ops);
13602init_ops_alloc_err:
13603 kfree(bp->init_data);
13604request_firmware_exit:
13605 release_firmware(bp->firmware);
127d0a19 13606 bp->firmware = NULL;
94a78b79
VZ		 13607
13608 return rc;
13609}
13610
619c5cb6
VZ		 13611static void bnx2x_release_firmware(struct bnx2x *bp)
13612{
13613 kfree(bp->init_ops_offsets);
13614 kfree(bp->init_ops);
13615 kfree(bp->init_data);
13616 release_firmware(bp->firmware);
eb2afd4a 13617 bp->firmware = NULL;
619c5cb6
VZ		 13618}
13619
619c5cb6
VZ		 13620static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13621 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13622 .init_hw_cmn = bnx2x_init_hw_common,
13623 .init_hw_port = bnx2x_init_hw_port,
13624 .init_hw_func = bnx2x_init_hw_func,
13625
13626 .reset_hw_cmn = bnx2x_reset_common,
13627 .reset_hw_port = bnx2x_reset_port,
13628 .reset_hw_func = bnx2x_reset_func,
13629
13630 .gunzip_init = bnx2x_gunzip_init,
13631 .gunzip_end = bnx2x_gunzip_end,
13632
13633 .init_fw = bnx2x_init_firmware,
13634 .release_fw = bnx2x_release_firmware,
13635};
13636
13637void bnx2x__init_func_obj(struct bnx2x *bp)
13638{
13639 /* Prepare DMAE related driver resources */
13640 bnx2x_setup_dmae(bp);
13641
13642 bnx2x_init_func_obj(bp, &bp->func_obj,
13643 bnx2x_sp(bp, func_rdata),
13644 bnx2x_sp_mapping(bp, func_rdata),
a3348722
BW		 13645 bnx2x_sp(bp, func_afex_rdata),
13646 bnx2x_sp_mapping(bp, func_afex_rdata),
619c5cb6
VZ		 13647 &bnx2x_func_sp_drv);
13648}
13649
13650/* must be called after sriov-enable */
1191cb83 13651static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
523224a3 13652{
37ae41a9 13653 int cid_count = BNX2X_L2_MAX_CID(bp);
94a78b79 13654
290ca2bb
AE		 13655 if (IS_SRIOV(bp))
13656 cid_count += BNX2X_VF_CIDS;
13657
55c11941
MS		 13658 if (CNIC_SUPPORT(bp))
13659 cid_count += CNIC_CID_MAX;
290ca2bb 13660
523224a3
DK		 13661 return roundup(cid_count, QM_CID_ROUND);
13662}
f85582f8 13663
619c5cb6 13664/**
6383c0b3 13665 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
619c5cb6
VZ		 13666 *
13667 * @dev: pci device
13668 *
13669 */
60cad4e6 13670static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
619c5cb6 13671{
ae2104be 13672 int index;
1ab4434c 13673 u16 control = 0;
619c5cb6 13674
6383c0b3
AE		 13675 /*
13676 * If MSI-X is not supported - return number of SBs needed to support
13677 * one fast path queue: one FP queue + SB for CNIC
13678 */
ae2104be 13679 if (!pdev->msix_cap) {
1ab4434c 13680 dev_info(&pdev->dev, "no msix capability found\n");
55c11941 13681 return 1 + cnic_cnt;
1ab4434c
AE		 13682 }
13683 dev_info(&pdev->dev, "msix capability found\n");
619c5cb6 13684
6383c0b3
AE		 13685 /*
13686 * The value in the PCI configuration space is the index of the last
13687 * entry, namely one less than the actual size of the table, which is
13688 * exactly what we want to return from this function: number of all SBs
13689 * without the default SB.
1ab4434c 13690 * For VFs there is no default SB, then we return (index+1).
6383c0b3 13691 */
73413ffa 13692 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
619c5cb6 13693
1ab4434c 13694 index = control & PCI_MSIX_FLAGS_QSIZE;
4bd9b0ff 13695
60cad4e6 13696 return index;
1ab4434c 13697}
523224a3 13698
1ab4434c
AE		 13699static int set_max_cos_est(int chip_id)
13700{
13701 switch (chip_id) {
f2e0899f
DK		 13702 case BCM57710:
13703 case BCM57711:
13704 case BCM57711E:
1ab4434c 13705 return BNX2X_MULTI_TX_COS_E1X;
f2e0899f 13706 case BCM57712:
619c5cb6 13707 case BCM57712_MF:
1ab4434c 13708 return BNX2X_MULTI_TX_COS_E2_E3A0;
619c5cb6
VZ		 13709 case BCM57800:
13710 case BCM57800_MF:
13711 case BCM57810:
13712 case BCM57810_MF:
c3def943
YM		 13713 case BCM57840_4_10:
13714 case BCM57840_2_20:
1ab4434c 13715 case BCM57840_O:
c3def943 13716 case BCM57840_MFO:
619c5cb6 13717 case BCM57840_MF:
7e8e02df
BW		 13718 case BCM57811:
13719 case BCM57811_MF:
1ab4434c 13720 return BNX2X_MULTI_TX_COS_E3B0;
b1239723
YM		 13721 case BCM57712_VF:
13722 case BCM57800_VF:
13723 case BCM57810_VF:
13724 case BCM57840_VF:
13725 case BCM57811_VF:
1ab4434c 13726 return 1;
f2e0899f 13727 default:
1ab4434c 13728 pr_err("Unknown board_type (%d), aborting\n", chip_id);
870634b0 13729 return -ENODEV;
f2e0899f 13730 }
1ab4434c 13731}
f2e0899f 13732
1ab4434c
AE		 13733static int set_is_vf(int chip_id)
13734{
13735 switch (chip_id) {
13736 case BCM57712_VF:
13737 case BCM57800_VF:
13738 case BCM57810_VF:
13739 case BCM57840_VF:
13740 case BCM57811_VF:
13741 return true;
13742 default:
13743 return false;
13744 }
13745}
6383c0b3 13746
eeed018c
MK		 13747/* nig_tsgen registers relative address */
13748#define tsgen_ctrl 0x0
13749#define tsgen_freecount 0x10
13750#define tsgen_synctime_t0 0x20
13751#define tsgen_offset_t0 0x28
13752#define tsgen_drift_t0 0x30
13753#define tsgen_synctime_t1 0x58
13754#define tsgen_offset_t1 0x60
13755#define tsgen_drift_t1 0x68
13756
13757/* FW workaround for setting drift */
13758static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13759 int best_val, int best_period)
13760{
13761 struct bnx2x_func_state_params func_params = {NULL};
13762 struct bnx2x_func_set_timesync_params *set_timesync_params =
13763 &func_params.params.set_timesync;
13764
13765 /* Prepare parameters for function state transitions */
13766 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13767 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13768
13769 func_params.f_obj = &bp->func_obj;
13770 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13771
13772 /* Function parameters */
13773 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13774 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13775 set_timesync_params->add_sub_drift_adjust_value =
13776 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13777 set_timesync_params->drift_adjust_value = best_val;
13778 set_timesync_params->drift_adjust_period = best_period;
13779
13780 return bnx2x_func_state_change(bp, &func_params);
13781}
13782
13783static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13784{
13785 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13786 int rc;
13787 int drift_dir = 1;
13788 int val, period, period1, period2, dif, dif1, dif2;
13789 int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13790
13791 DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13792
13793 if (!netif_running(bp->dev)) {
13794 DP(BNX2X_MSG_PTP,
13795 "PTP adjfreq called while the interface is down\n");
466e8bf1 13796 return -ENETDOWN;
eeed018c
MK		 13797 }
13798
13799 if (ppb < 0) {
13800 ppb = -ppb;
13801 drift_dir = 0;
13802 }
13803
13804 if (ppb == 0) {
13805 best_val = 1;
13806 best_period = 0x1FFFFFF;
13807 } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13808 best_val = 31;
13809 best_period = 1;
13810 } else {
13811 /* Changed not to allow val = 8, 16, 24 as these values
13812 * are not supported in workaround.
13813 */
13814 for (val = 0; val <= 31; val++) {
13815 if ((val & 0x7) == 0)
13816 continue;
13817 period1 = val * 1000000 / ppb;
13818 period2 = period1 + 1;
13819 if (period1 != 0)
13820 dif1 = ppb - (val * 1000000 / period1);
13821 else
13822 dif1 = BNX2X_MAX_PHC_DRIFT;
13823 if (dif1 < 0)
13824 dif1 = -dif1;
13825 dif2 = ppb - (val * 1000000 / period2);
13826 if (dif2 < 0)
13827 dif2 = -dif2;
13828 dif = (dif1 < dif2) ? dif1 : dif2;
13829 period = (dif1 < dif2) ? period1 : period2;
13830 if (dif < best_dif) {
13831 best_dif = dif;
13832 best_val = val;
13833 best_period = period;
13834 }
13835 }
13836 }
13837
13838 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13839 best_period);
13840 if (rc) {
13841 BNX2X_ERR("Failed to set drift\n");
13842 return -EFAULT;
13843 }
13844
bf27c353 13845 DP(BNX2X_MSG_PTP, "Configured val = %d, period = %d\n", best_val,
eeed018c
MK		 13846 best_period);
13847
13848 return 0;
13849}
13850
13851static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13852{
13853 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
eeed018c 13854
466e8bf1
MS		 13855 if (!netif_running(bp->dev)) {
13856 DP(BNX2X_MSG_PTP,
13857 "PTP adjtime called while the interface is down\n");
13858 return -ENETDOWN;
13859 }
13860
eeed018c
MK		 13861 DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13862
2e5601f9 13863 timecounter_adjtime(&bp->timecounter, delta);
eeed018c
MK		 13864
13865 return 0;
13866}
13867
5d45186b 13868static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
eeed018c
MK		 13869{
13870 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13871 u64 ns;
eeed018c 13872
466e8bf1
MS		 13873 if (!netif_running(bp->dev)) {
13874 DP(BNX2X_MSG_PTP,
13875 "PTP gettime called while the interface is down\n");
13876 return -ENETDOWN;
13877 }
13878
eeed018c
MK		 13879 ns = timecounter_read(&bp->timecounter);
13880
13881 DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13882
f7dcdefe 13883 *ts = ns_to_timespec64(ns);
eeed018c
MK		 13884
13885 return 0;
13886}
13887
13888static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
5d45186b 13889 const struct timespec64 *ts)
eeed018c
MK		 13890{
13891 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13892 u64 ns;
13893
466e8bf1
MS		 13894 if (!netif_running(bp->dev)) {
13895 DP(BNX2X_MSG_PTP,
13896 "PTP settime called while the interface is down\n");
13897 return -ENETDOWN;
13898 }
13899
f7dcdefe 13900 ns = timespec64_to_ns(ts);
eeed018c
MK		 13901
13902 DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13903
13904 /* Re-init the timecounter */
13905 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13906
13907 return 0;
13908}
13909
13910/* Enable (or disable) ancillary features of the phc subsystem */
13911static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13912 struct ptp_clock_request *rq, int on)
13913{
13914 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13915
13916 BNX2X_ERR("PHC ancillary features are not supported\n");
13917 return -ENOTSUPP;
13918}
13919
1444c301 13920static void bnx2x_register_phc(struct bnx2x *bp)
eeed018c
MK		 13921{
13922 /* Fill the ptp_clock_info struct and register PTP clock*/
13923 bp->ptp_clock_info.owner = THIS_MODULE;
13924 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13925 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13926 bp->ptp_clock_info.n_alarm = 0;
13927 bp->ptp_clock_info.n_ext_ts = 0;
13928 bp->ptp_clock_info.n_per_out = 0;
13929 bp->ptp_clock_info.pps = 0;
13930 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13931 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
5d45186b
RC		 13932 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime;
13933 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime;
eeed018c
MK		 13934 bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13935
13936 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13937 if (IS_ERR(bp->ptp_clock)) {
13938 bp->ptp_clock = NULL;
924613d3 13939 BNX2X_ERR("PTP clock registration failed\n");
eeed018c
MK		 13940 }
13941}
13942
1ab4434c
AE		 13943static int bnx2x_init_one(struct pci_dev *pdev,
13944 const struct pci_device_id *ent)
13945{
13946 struct net_device *dev = NULL;
13947 struct bnx2x *bp;
1ab4434c
AE		 13948 int rc, max_non_def_sbs;
13949 int rx_count, tx_count, rss_count, doorbell_size;
13950 int max_cos_est;
13951 bool is_vf;
13952 int cnic_cnt;
13953
12a8541d
YM		 13954 /* Management FW 'remembers' living interfaces. Allow it some time
13955 * to forget previously living interfaces, allowing a proper re-load.
13956 */
cd9c3997
MS		 13957 if (is_kdump_kernel()) {
13958 ktime_t now = ktime_get_boottime();
13959 ktime_t fw_ready_time = ktime_set(5, 0);
13960
13961 if (ktime_before(now, fw_ready_time))
13962 msleep(ktime_ms_delta(fw_ready_time, now));
13963 }
12a8541d 13964
1ab4434c
AE		 13965 /* An estimated maximum supported CoS number according to the chip
13966 * version.
13967 * We will try to roughly estimate the maximum number of CoSes this chip
13968 * may support in order to minimize the memory allocated for Tx
13969 * netdev_queue's. This number will be accurately calculated during the
13970 * initialization of bp->max_cos based on the chip versions AND chip
13971 * revision in the bnx2x_init_bp().
13972 */
13973 max_cos_est = set_max_cos_est(ent->driver_data);
13974 if (max_cos_est < 0)
13975 return max_cos_est;
13976 is_vf = set_is_vf(ent->driver_data);
13977 cnic_cnt = is_vf ? 0 : 1;
13978
60cad4e6
AE		 13979 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13980
13981 /* add another SB for VF as it has no default SB */
13982 max_non_def_sbs += is_vf ? 1 : 0;
6383c0b3
AE		 13983
13984 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
60cad4e6 13985 rss_count = max_non_def_sbs - cnic_cnt;
1ab4434c
AE		 13986
13987 if (rss_count < 1)
13988 return -EINVAL;
6383c0b3
AE		 13989
13990 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
55c11941 13991 rx_count = rss_count + cnic_cnt;
6383c0b3 13992
1ab4434c 13993 /* Maximum number of netdev Tx queues:
37ae41a9 13994 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
6383c0b3 13995 */
55c11941 13996 tx_count = rss_count * max_cos_est + cnic_cnt;
f85582f8 13997
a2fbb9ea 13998 /* dev zeroed in init_etherdev */
6383c0b3 13999 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
41de8d4c 14000 if (!dev)
a2fbb9ea
ET		 14001 return -ENOMEM;
14002
a2fbb9ea 14003 bp = netdev_priv(dev);
a2fbb9ea 14004
1ab4434c
AE		 14005 bp->flags = 0;
14006 if (is_vf)
14007 bp->flags |= IS_VF_FLAG;
14008
6383c0b3 14009 bp->igu_sb_cnt = max_non_def_sbs;
1ab4434c 14010 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
6383c0b3 14011 bp->msg_enable = debug;
55c11941 14012 bp->cnic_support = cnic_cnt;
4bd9b0ff 14013 bp->cnic_probe = bnx2x_cnic_probe;
55c11941 14014
6383c0b3 14015 pci_set_drvdata(pdev, dev);
523224a3 14016
1ab4434c 14017 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
a2fbb9ea
ET		 14018 if (rc < 0) {
14019 free_netdev(dev);
14020 return rc;
14021 }
14022
1ab4434c
AE		 14023 BNX2X_DEV_INFO("This is a %s function\n",
14024 IS_PF(bp) ? "physical" : "virtual");
55c11941 14025 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
1ab4434c 14026 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
60aa0509 14027 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
2de67439 14028 tx_count, rx_count);
60aa0509 14029
34f80b04 14030 rc = bnx2x_init_bp(bp);
693fc0d1
EG		 14031 if (rc)
14032 goto init_one_exit;
14033
1ab4434c
AE		 14034 /* Map doorbells here as we need the real value of bp->max_cos which
14035 * is initialized in bnx2x_init_bp() to determine the number of
14036 * l2 connections.
6383c0b3 14037 */
1ab4434c 14038 if (IS_VF(bp)) {
1d6f3cd8 14039 bp->doorbells = bnx2x_vf_doorbells(bp);
6411280a
AE		 14040 rc = bnx2x_vf_pci_alloc(bp);
14041 if (rc)
bae5499c 14042 goto init_one_freemem;
1ab4434c
AE		 14043 } else {
14044 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
14045 if (doorbell_size > pci_resource_len(pdev, 2)) {
14046 dev_err(&bp->pdev->dev,
14047 "Cannot map doorbells, bar size too small, aborting\n");
14048 rc = -ENOMEM;
bae5499c 14049 goto init_one_freemem;
1ab4434c
AE		 14050 }
14051 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
14052 doorbell_size);
37ae41a9 14053 }
6383c0b3
AE		 14054 if (!bp->doorbells) {
14055 dev_err(&bp->pdev->dev,
14056 "Cannot map doorbell space, aborting\n");
14057 rc = -ENOMEM;
bae5499c 14058 goto init_one_freemem;
6383c0b3
AE		 14059 }
14060
be1f1ffa
AE		 14061 if (IS_VF(bp)) {
14062 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
14063 if (rc)
bae5499c 14064 goto init_one_freemem;
83bd9eb8
MS		 14065
14066#ifdef CONFIG_BNX2X_SRIOV
14067 /* VF with OLD Hypervisor or old PF do not support filtering */
14068 if (bp->acquire_resp.pfdev_info.pf_cap & PFVF_CAP_VLAN_FILTER) {
14069 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14070 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
14071 }
14072#endif
be1f1ffa
AE		 14073 }
14074
3c76feff
AE		 14075 /* Enable SRIOV if capability found in configuration space */
14076 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
290ca2bb 14077 if (rc)
bae5499c 14078 goto init_one_freemem;
290ca2bb 14079
523224a3 14080 /* calc qm_cid_count */
6383c0b3 14081 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
1ab4434c 14082 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
523224a3 14083
55c11941 14084 /* disable FCOE L2 queue for E1x*/
62ac0dc9 14085 if (CHIP_IS_E1x(bp))
ec6ba945
VZ		 14086 bp->flags |= NO_FCOE_FLAG;
14087
0e8d2ec5
MS		 14088 /* Set bp->num_queues for MSI-X mode*/
14089 bnx2x_set_num_queues(bp);
14090
25985edc 14091 /* Configure interrupt mode: try to enable MSI-X/MSI if
0e8d2ec5 14092 * needed.
d6214d7a 14093 */
1ab4434c
AE		 14094 rc = bnx2x_set_int_mode(bp);
14095 if (rc) {
14096 dev_err(&pdev->dev, "Cannot set interrupts\n");
bae5499c 14097 goto init_one_freemem;
1ab4434c 14098 }
04c46736 14099 BNX2X_DEV_INFO("set interrupts successfully\n");
d6214d7a 14100
1ab4434c 14101 /* register the net device */
b340007f
VZ		 14102 rc = register_netdev(dev);
14103 if (rc) {
14104 dev_err(&pdev->dev, "Cannot register net device\n");
bae5499c 14105 goto init_one_freemem;
b340007f 14106 }
1ab4434c 14107 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
b340007f 14108
ec6ba945
VZ		 14109 if (!NO_FCOE(bp)) {
14110 /* Add storage MAC address */
14111 rtnl_lock();
14112 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14113 rtnl_unlock();
14114 }
cc04a1dd
BH		 14115 BNX2X_DEV_INFO(
14116 "%s (%c%d) PCI-E found at mem %lx, IRQ %d, node addr %pM\n",
14117 board_info[ent->driver_data].name,
14118 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
14119 dev->base_addr, bp->pdev->irq, dev->dev_addr);
14120 pcie_print_link_status(bp->pdev);
c016201c 14121
eeed018c
MK		 14122 bnx2x_register_phc(bp);
14123
230d00eb
YM		 14124 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
14125 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
14126
a2fbb9ea 14127 return 0;
34f80b04 14128
bae5499c
VK		 14129init_one_freemem:
14130 bnx2x_free_mem_bp(bp);
14131
34f80b04 14132init_one_exit:
33d8e6a5
YM		 14133 bnx2x_disable_pcie_error_reporting(bp);
14134
34f80b04
EG		 14135 if (bp->regview)
14136 iounmap(bp->regview);
14137
1ab4434c 14138 if (IS_PF(bp) && bp->doorbells)
34f80b04
EG		 14139 iounmap(bp->doorbells);
14140
14141 free_netdev(dev);
14142
14143 if (atomic_read(&pdev->enable_cnt) == 1)
14144 pci_release_regions(pdev);
14145
14146 pci_disable_device(pdev);
34f80b04
EG		 14147
14148 return rc;
a2fbb9ea
ET		 14149}
14150
b030ed2f
YM		 14151static void __bnx2x_remove(struct pci_dev *pdev,
14152 struct net_device *dev,
14153 struct bnx2x *bp,
14154 bool remove_netdev)
a2fbb9ea 14155{
eeed018c
MK		 14156 if (bp->ptp_clock) {
14157 ptp_clock_unregister(bp->ptp_clock);
14158 bp->ptp_clock = NULL;
14159 }
14160
ec6ba945
VZ		 14161 /* Delete storage MAC address */
14162 if (!NO_FCOE(bp)) {
14163 rtnl_lock();
14164 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
14165 rtnl_unlock();
14166 }
ec6ba945 14167
98507672
SR		 14168#ifdef BCM_DCBNL
14169 /* Delete app tlvs from dcbnl */
14170 bnx2x_dcbnl_update_applist(bp, true);
14171#endif
14172
a6d3a5ba
BW		 14173 if (IS_PF(bp) &&
14174 !BP_NOMCP(bp) &&
14175 (bp->flags & BC_SUPPORTS_RMMOD_CMD))
14176 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
14177
b030ed2f
YM		 14178 /* Close the interface - either directly or implicitly */
14179 if (remove_netdev) {
14180 unregister_netdev(dev);
14181 } else {
14182 rtnl_lock();
6ef5a92c 14183 dev_close(dev);
b030ed2f
YM		 14184 rtnl_unlock();
14185 }
a2fbb9ea 14186
78c3bcc5
AE		 14187 bnx2x_iov_remove_one(bp);
14188
084d6cbb 14189 /* Power on: we can't let PCI layer write to us while we are in D3 */
04860eb7 14190 if (IS_PF(bp)) {
1ab4434c 14191 bnx2x_set_power_state(bp, PCI_D0);
230d00eb 14192 bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
084d6cbb 14193
04860eb7
MC		 14194 /* Set endianity registers to reset values in case next driver
14195 * boots in different endianty environment.
14196 */
14197 bnx2x_reset_endianity(bp);
14198 }
14199
d6214d7a
DK		 14200 /* Disable MSI/MSI-X */
14201 bnx2x_disable_msi(bp);
f85582f8 14202
084d6cbb 14203 /* Power off */
1ab4434c
AE		 14204 if (IS_PF(bp))
14205 bnx2x_set_power_state(bp, PCI_D3hot);
084d6cbb 14206
72fd0718 14207 /* Make sure RESET task is not scheduled before continuing */
7be08a72 14208 cancel_delayed_work_sync(&bp->sp_rtnl_task);
290ca2bb 14209
4513f925
AE		 14210 /* send message via vfpf channel to release the resources of this vf */
14211 if (IS_VF(bp))
14212 bnx2x_vfpf_release(bp);
72fd0718 14213
b030ed2f
YM		 14214 /* Assumes no further PCIe PM changes will occur */
14215 if (system_state == SYSTEM_POWER_OFF) {
14216 pci_wake_from_d3(pdev, bp->wol);
14217 pci_set_power_state(pdev, PCI_D3hot);
14218 }
14219
33d8e6a5 14220 bnx2x_disable_pcie_error_reporting(bp);
d9aee591
YM		 14221 if (remove_netdev) {
14222 if (bp->regview)
14223 iounmap(bp->regview);
33d8e6a5 14224
d9aee591
YM		 14225 /* For vfs, doorbells are part of the regview and were unmapped
14226 * along with it. FW is only loaded by PF.
14227 */
14228 if (IS_PF(bp)) {
14229 if (bp->doorbells)
14230 iounmap(bp->doorbells);
eb2afd4a 14231
d9aee591 14232 bnx2x_release_firmware(bp);
e2a367f8
YM		 14233 } else {
14234 bnx2x_vf_pci_dealloc(bp);
d9aee591
YM		 14235 }
14236 bnx2x_free_mem_bp(bp);
523224a3 14237
b030ed2f 14238 free_netdev(dev);
34f80b04 14239
d9aee591
YM		 14240 if (atomic_read(&pdev->enable_cnt) == 1)
14241 pci_release_regions(pdev);
34f80b04 14242
5f6db130
YM		 14243 pci_disable_device(pdev);
14244 }
a2fbb9ea
ET		 14245}
14246
b030ed2f
YM		 14247static void bnx2x_remove_one(struct pci_dev *pdev)
14248{
14249 struct net_device *dev = pci_get_drvdata(pdev);
14250 struct bnx2x *bp;
14251
14252 if (!dev) {
14253 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
14254 return;
14255 }
14256 bp = netdev_priv(dev);
14257
14258 __bnx2x_remove(pdev, dev, bp, true);
14259}
14260
f8ef6e44
YG		 14261static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
14262{
7fa6f340 14263 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
f8ef6e44
YG		 14264
14265 bp->rx_mode = BNX2X_RX_MODE_NONE;
14266
55c11941
MS		 14267 if (CNIC_LOADED(bp))
14268 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
14269
619c5cb6
VZ		 14270 /* Stop Tx */
14271 bnx2x_tx_disable(bp);
26614ba5
MS		 14272 /* Delete all NAPI objects */
14273 bnx2x_del_all_napi(bp);
55c11941
MS		 14274 if (CNIC_LOADED(bp))
14275 bnx2x_del_all_napi_cnic(bp);
7fa6f340 14276 netdev_reset_tc(bp->dev);
f8ef6e44
YG		 14277
14278 del_timer_sync(&bp->timer);
0c0e6341 14279 cancel_delayed_work_sync(&bp->sp_task);
14280 cancel_delayed_work_sync(&bp->period_task);
619c5cb6 14281
c6e36d8c
YM		 14282 if (!down_timeout(&bp->stats_lock, HZ / 10)) {
14283 bp->stats_state = STATS_STATE_DISABLED;
14284 up(&bp->stats_lock);
14285 }
f8ef6e44 14286
7fa6f340 14287 bnx2x_save_statistics(bp);
f8ef6e44 14288
619c5cb6
VZ		 14289 netif_carrier_off(bp->dev);
14290
f8ef6e44
YG		 14291 return 0;
14292}
14293
493adb1f
WX		 14294/**
14295 * bnx2x_io_error_detected - called when PCI error is detected
14296 * @pdev: Pointer to PCI device
14297 * @state: The current pci connection state
14298 *
14299 * This function is called after a PCI bus error affecting
14300 * this device has been detected.
14301 */
14302static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
14303 pci_channel_state_t state)
14304{
14305 struct net_device *dev = pci_get_drvdata(pdev);
14306 struct bnx2x *bp = netdev_priv(dev);
14307
14308 rtnl_lock();
14309
7fa6f340
YM		 14310 BNX2X_ERR("IO error detected\n");
14311
493adb1f
WX		 14312 netif_device_detach(dev);
14313
07ce50e4
DN		 14314 if (state == pci_channel_io_perm_failure) {
14315 rtnl_unlock();
14316 return PCI_ERS_RESULT_DISCONNECT;
14317 }
14318
493adb1f 14319 if (netif_running(dev))
f8ef6e44 14320 bnx2x_eeh_nic_unload(bp);
493adb1f 14321
7fa6f340
YM		 14322 bnx2x_prev_path_mark_eeh(bp);
14323
493adb1f
WX		 14324 pci_disable_device(pdev);
14325
14326 rtnl_unlock();
14327
14328 /* Request a slot reset */
14329 return PCI_ERS_RESULT_NEED_RESET;
14330}
14331
14332/**
14333 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14334 * @pdev: Pointer to PCI device
14335 *
14336 * Restart the card from scratch, as if from a cold-boot.
14337 */
14338static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
14339{
14340 struct net_device *dev = pci_get_drvdata(pdev);
14341 struct bnx2x *bp = netdev_priv(dev);
7fa6f340 14342 int i;
493adb1f
WX		 14343
14344 rtnl_lock();
7fa6f340 14345 BNX2X_ERR("IO slot reset initializing...\n");
493adb1f
WX		 14346 if (pci_enable_device(pdev)) {
14347 dev_err(&pdev->dev,
14348 "Cannot re-enable PCI device after reset\n");
14349 rtnl_unlock();
14350 return PCI_ERS_RESULT_DISCONNECT;
14351 }
14352
14353 pci_set_master(pdev);
14354 pci_restore_state(pdev);
70632d0a 14355 pci_save_state(pdev);
493adb1f
WX		 14356
14357 if (netif_running(dev))
14358 bnx2x_set_power_state(bp, PCI_D0);
14359
7fa6f340
YM		 14360 if (netif_running(dev)) {
14361 BNX2X_ERR("IO slot reset --> driver unload\n");
e68072ef
YM		 14362
14363 /* MCP should have been reset; Need to wait for validity */
f7084059
GP		 14364 if (bnx2x_init_shmem(bp)) {
14365 rtnl_unlock();
14366 return PCI_ERS_RESULT_DISCONNECT;
14367 }
e68072ef 14368
7fa6f340
YM		 14369 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
14370 u32 v;
14371
14372 v = SHMEM2_RD(bp,
14373 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
14374 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
14375 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
14376 }
14377 bnx2x_drain_tx_queues(bp);
14378 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
14379 bnx2x_netif_stop(bp, 1);
14380 bnx2x_free_irq(bp);
14381
14382 /* Report UNLOAD_DONE to MCP */
14383 bnx2x_send_unload_done(bp, true);
14384
14385 bp->sp_state = 0;
14386 bp->port.pmf = 0;
14387
14388 bnx2x_prev_unload(bp);
14389
16a5fd92 14390 /* We should have reseted the engine, so It's fair to
7fa6f340
YM		 14391 * assume the FW will no longer write to the bnx2x driver.
14392 */
14393 bnx2x_squeeze_objects(bp);
14394 bnx2x_free_skbs(bp);
14395 for_each_rx_queue(bp, i)
14396 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
14397 bnx2x_free_fp_mem(bp);
14398 bnx2x_free_mem(bp);
14399
14400 bp->state = BNX2X_STATE_CLOSED;
14401 }
14402
493adb1f
WX		 14403 rtnl_unlock();
14404
14405 return PCI_ERS_RESULT_RECOVERED;
14406}
14407
14408/**
14409 * bnx2x_io_resume - called when traffic can start flowing again
14410 * @pdev: Pointer to PCI device
14411 *
14412 * This callback is called when the error recovery driver tells us that
14413 * its OK to resume normal operation.
14414 */
14415static void bnx2x_io_resume(struct pci_dev *pdev)
14416{
14417 struct net_device *dev = pci_get_drvdata(pdev);
14418 struct bnx2x *bp = netdev_priv(dev);
14419
72fd0718 14420 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
51c1a580 14421 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
72fd0718
VZ		 14422 return;
14423 }
14424
493adb1f
WX		 14425 rtnl_lock();
14426
7fa6f340
YM		 14427 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
14428 DRV_MSG_SEQ_NUMBER_MASK;
14429
493adb1f 14430 if (netif_running(dev))
f8ef6e44 14431 bnx2x_nic_load(bp, LOAD_NORMAL);
493adb1f
WX		 14432
14433 netif_device_attach(dev);
14434
14435 rtnl_unlock();
14436}
14437
3646f0e5 14438static const struct pci_error_handlers bnx2x_err_handler = {
493adb1f 14439 .error_detected = bnx2x_io_error_detected,
356e2385
EG		 14440 .slot_reset = bnx2x_io_slot_reset,
14441 .resume = bnx2x_io_resume,
493adb1f
WX		 14442};
14443
b030ed2f
YM		 14444static void bnx2x_shutdown(struct pci_dev *pdev)
14445{
14446 struct net_device *dev = pci_get_drvdata(pdev);
14447 struct bnx2x *bp;
14448
14449 if (!dev)
14450 return;
14451
14452 bp = netdev_priv(dev);
14453 if (!bp)
14454 return;
14455
14456 rtnl_lock();
14457 netif_device_detach(dev);
14458 rtnl_unlock();
14459
14460 /* Don't remove the netdevice, as there are scenarios which will cause
14461 * the kernel to hang, e.g., when trying to remove bnx2i while the
14462 * rootfs is mounted from SAN.
14463 */
14464 __bnx2x_remove(pdev, dev, bp, false);
14465}
14466
a2fbb9ea 14467static struct pci_driver bnx2x_pci_driver = {
493adb1f
WX		 14468 .name = DRV_MODULE_NAME,
14469 .id_table = bnx2x_pci_tbl,
14470 .probe = bnx2x_init_one,
0329aba1 14471 .remove = bnx2x_remove_one,
493adb1f
WX		 14472 .suspend = bnx2x_suspend,
14473 .resume = bnx2x_resume,
14474 .err_handler = &bnx2x_err_handler,
3c76feff
AE		 14475#ifdef CONFIG_BNX2X_SRIOV
14476 .sriov_configure = bnx2x_sriov_configure,
14477#endif
b030ed2f 14478 .shutdown = bnx2x_shutdown,
a2fbb9ea
ET		 14479};
14480
14481static int __init bnx2x_init(void)
14482{
dd21ca6d
SG		 14483 int ret;
14484
7995c64e 14485 pr_info("%s", version);
938cf541 14486
1cf167f2
EG		 14487 bnx2x_wq = create_singlethread_workqueue("bnx2x");
14488 if (bnx2x_wq == NULL) {
7995c64e 14489 pr_err("Cannot create workqueue\n");
1cf167f2
EG		 14490 return -ENOMEM;
14491 }
370d4a26
YM		 14492 bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
14493 if (!bnx2x_iov_wq) {
14494 pr_err("Cannot create iov workqueue\n");
14495 destroy_workqueue(bnx2x_wq);
14496 return -ENOMEM;
14497 }
1cf167f2 14498
dd21ca6d
SG		 14499 ret = pci_register_driver(&bnx2x_pci_driver);
14500 if (ret) {
7995c64e 14501 pr_err("Cannot register driver\n");
dd21ca6d 14502 destroy_workqueue(bnx2x_wq);
370d4a26 14503 destroy_workqueue(bnx2x_iov_wq);
dd21ca6d
SG		 14504 }
14505 return ret;
a2fbb9ea
ET		 14506}
14507
14508static void __exit bnx2x_cleanup(void)
14509{
452427b0 14510 struct list_head *pos, *q;
d76a6111 14511
a2fbb9ea 14512 pci_unregister_driver(&bnx2x_pci_driver);
1cf167f2
EG		 14513
14514 destroy_workqueue(bnx2x_wq);
370d4a26 14515 destroy_workqueue(bnx2x_iov_wq);
452427b0 14516
16a5fd92 14517 /* Free globally allocated resources */
452427b0
YM		 14518 list_for_each_safe(pos, q, &bnx2x_prev_list) {
14519 struct bnx2x_prev_path_list *tmp =
14520 list_entry(pos, struct bnx2x_prev_path_list, list);
14521 list_del(pos);
14522 kfree(tmp);
14523 }
a2fbb9ea
ET		 14524}
14525
3deb8167
YR		 14526void bnx2x_notify_link_changed(struct bnx2x *bp)
14527{
14528 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
14529}
14530
a2fbb9ea
ET		 14531module_init(bnx2x_init);
14532module_exit(bnx2x_cleanup);
14533
619c5cb6
VZ		 14534/**
14535 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14536 *
14537 * @bp: driver handle
14538 * @set: set or clear the CAM entry
14539 *
16a5fd92 14540 * This function will wait until the ramrod completion returns.
619c5cb6
VZ		 14541 * Return 0 if success, -ENODEV if ramrod doesn't return.
14542 */
1191cb83 14543static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
619c5cb6
VZ		 14544{
14545 unsigned long ramrod_flags = 0;
14546
14547 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
14548 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
14549 &bp->iscsi_l2_mac_obj, true,
14550 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
14551}
993ac7b5
MC		 14552
14553/* count denotes the number of new completions we have seen */
14554static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
14555{
14556 struct eth_spe *spe;
a052997e 14557 int cxt_index, cxt_offset;
993ac7b5
MC		 14558
14559#ifdef BNX2X_STOP_ON_ERROR
14560 if (unlikely(bp->panic))
14561 return;
14562#endif
14563
14564 spin_lock_bh(&bp->spq_lock);
c2bff63f 14565 BUG_ON(bp->cnic_spq_pending < count);
993ac7b5
MC		 14566 bp->cnic_spq_pending -= count;
14567
c2bff63f
DK		 14568 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
14569 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
14570 & SPE_HDR_CONN_TYPE) >>
14571 SPE_HDR_CONN_TYPE_SHIFT;
619c5cb6
VZ		 14572 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
14573 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
c2bff63f
DK		 14574
14575 /* Set validation for iSCSI L2 client before sending SETUP
14576 * ramrod
14577 */
14578 if (type == ETH_CONNECTION_TYPE) {
a052997e 14579 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
37ae41a9 14580 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
a052997e 14581 ILT_PAGE_CIDS;
37ae41a9 14582 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
a052997e
MS		 14583 (cxt_index * ILT_PAGE_CIDS);
14584 bnx2x_set_ctx_validation(bp,
14585 &bp->context[cxt_index].
14586 vcxt[cxt_offset].eth,
37ae41a9 14587 BNX2X_ISCSI_ETH_CID(bp));
a052997e 14588 }
c2bff63f
DK		 14589 }
14590
619c5cb6
VZ		 14591 /*
14592 * There may be not more than 8 L2, not more than 8 L5 SPEs
14593 * and in the air. We also check that number of outstanding
6e30dd4e
VZ		 14594 * COMMON ramrods is not more than the EQ and SPQ can
14595 * accommodate.
c2bff63f 14596 */
6e30dd4e
VZ		 14597 if (type == ETH_CONNECTION_TYPE) {
14598 if (!atomic_read(&bp->cq_spq_left))
14599 break;
14600 else
14601 atomic_dec(&bp->cq_spq_left);
14602 } else if (type == NONE_CONNECTION_TYPE) {
14603 if (!atomic_read(&bp->eq_spq_left))
c2bff63f
DK		 14604 break;
14605 else
6e30dd4e 14606 atomic_dec(&bp->eq_spq_left);
ec6ba945
VZ		 14607 } else if ((type == ISCSI_CONNECTION_TYPE) ||
14608 (type == FCOE_CONNECTION_TYPE)) {
c2bff63f
DK		 14609 if (bp->cnic_spq_pending >=
14610 bp->cnic_eth_dev.max_kwqe_pending)
14611 break;
14612 else
14613 bp->cnic_spq_pending++;
14614 } else {
14615 BNX2X_ERR("Unknown SPE type: %d\n", type);
14616 bnx2x_panic();
993ac7b5 14617 break;
c2bff63f 14618 }
993ac7b5
MC		 14619
14620 spe = bnx2x_sp_get_next(bp);
14621 *spe = *bp->cnic_kwq_cons;
14622
51c1a580 14623 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
993ac7b5
MC		 14624 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14625
14626 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14627 bp->cnic_kwq_cons = bp->cnic_kwq;
14628 else
14629 bp->cnic_kwq_cons++;
14630 }
14631 bnx2x_sp_prod_update(bp);
14632 spin_unlock_bh(&bp->spq_lock);
14633}
14634
14635static int bnx2x_cnic_sp_queue(struct net_device *dev,
14636 struct kwqe_16 *kwqes[], u32 count)
14637{
14638 struct bnx2x *bp = netdev_priv(dev);
14639 int i;
14640
14641#ifdef BNX2X_STOP_ON_ERROR
51c1a580
MS		 14642 if (unlikely(bp->panic)) {
14643 BNX2X_ERR("Can't post to SP queue while panic\n");
993ac7b5 14644 return -EIO;
51c1a580 14645 }
993ac7b5
MC		 14646#endif
14647
95c6c616
AE		 14648 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14649 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
51c1a580 14650 BNX2X_ERR("Handling parity error recovery. Try again later\n");
95c6c616
AE		 14651 return -EAGAIN;
14652 }
14653
993ac7b5
MC		 14654 spin_lock_bh(&bp->spq_lock);
14655
14656 for (i = 0; i < count; i++) {
14657 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14658
14659 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14660 break;
14661
14662 *bp->cnic_kwq_prod = *spe;
14663
14664 bp->cnic_kwq_pending++;
14665
51c1a580 14666 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
993ac7b5 14667 spe->hdr.conn_and_cmd_data, spe->hdr.type,
523224a3
DK		 14668 spe->data.update_data_addr.hi,
14669 spe->data.update_data_addr.lo,
993ac7b5
MC		 14670 bp->cnic_kwq_pending);
14671
14672 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14673 bp->cnic_kwq_prod = bp->cnic_kwq;
14674 else
14675 bp->cnic_kwq_prod++;
14676 }
14677
14678 spin_unlock_bh(&bp->spq_lock);
14679
14680 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14681 bnx2x_cnic_sp_post(bp, 0);
14682
14683 return i;
14684}
14685
14686static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14687{
14688 struct cnic_ops *c_ops;
14689 int rc = 0;
14690
14691 mutex_lock(&bp->cnic_mutex);
13707f9e
ED		 14692 c_ops = rcu_dereference_protected(bp->cnic_ops,
14693 lockdep_is_held(&bp->cnic_mutex));
993ac7b5
MC		 14694 if (c_ops)
14695 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14696 mutex_unlock(&bp->cnic_mutex);
14697
14698 return rc;
14699}
14700
14701static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14702{
14703 struct cnic_ops *c_ops;
14704 int rc = 0;
14705
14706 rcu_read_lock();
14707 c_ops = rcu_dereference(bp->cnic_ops);
14708 if (c_ops)
14709 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14710 rcu_read_unlock();
14711
14712 return rc;
14713}
14714
14715/*
14716 * for commands that have no data
14717 */
9f6c9258 14718int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
993ac7b5
MC		 14719{
14720 struct cnic_ctl_info ctl = {0};
14721
14722 ctl.cmd = cmd;
14723
14724 return bnx2x_cnic_ctl_send(bp, &ctl);
14725}
14726
619c5cb6 14727static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
993ac7b5 14728{
619c5cb6 14729 struct cnic_ctl_info ctl = {0};
993ac7b5
MC		 14730
14731 /* first we tell CNIC and only then we count this as a completion */
14732 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14733 ctl.data.comp.cid = cid;
619c5cb6 14734 ctl.data.comp.error = err;
993ac7b5
MC		 14735
14736 bnx2x_cnic_ctl_send_bh(bp, &ctl);
c2bff63f 14737 bnx2x_cnic_sp_post(bp, 0);
993ac7b5
MC		 14738}
14739
619c5cb6
VZ		 14740/* Called with netif_addr_lock_bh() taken.
14741 * Sets an rx_mode config for an iSCSI ETH client.
14742 * Doesn't block.
14743 * Completion should be checked outside.
14744 */
14745static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14746{
14747 unsigned long accept_flags = 0, ramrod_flags = 0;
14748 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14749 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14750
14751 if (start) {
14752 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14753 * because it's the only way for UIO Queue to accept
14754 * multicasts (in non-promiscuous mode only one Queue per
14755 * function will receive multicast packets (leading in our
14756 * case).
14757 */
14758 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14759 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14760 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14761 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14762
14763 /* Clear STOP_PENDING bit if START is requested */
14764 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14765
14766 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14767 } else
14768 /* Clear START_PENDING bit if STOP is requested */
14769 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14770
14771 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14772 set_bit(sched_state, &bp->sp_state);
14773 else {
14774 __set_bit(RAMROD_RX, &ramrod_flags);
14775 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14776 ramrod_flags);
14777 }
14778}
14779
993ac7b5
MC		 14780static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14781{
14782 struct bnx2x *bp = netdev_priv(dev);
14783 int rc = 0;
14784
14785 switch (ctl->cmd) {
14786 case DRV_CTL_CTXTBL_WR_CMD: {
14787 u32 index = ctl->data.io.offset;
14788 dma_addr_t addr = ctl->data.io.dma_addr;
14789
14790 bnx2x_ilt_wr(bp, index, addr);
14791 break;
14792 }
14793
c2bff63f
DK		 14794 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14795 int count = ctl->data.credit.credit_count;
993ac7b5
MC		 14796
14797 bnx2x_cnic_sp_post(bp, count);
14798 break;
14799 }
14800
14801 /* rtnl_lock is held. */
14802 case DRV_CTL_START_L2_CMD: {
619c5cb6
VZ		 14803 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14804 unsigned long sp_bits = 0;
14805
14806 /* Configure the iSCSI classification object */
14807 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14808 cp->iscsi_l2_client_id,
14809 cp->iscsi_l2_cid, BP_FUNC(bp),
14810 bnx2x_sp(bp, mac_rdata),
14811 bnx2x_sp_mapping(bp, mac_rdata),
14812 BNX2X_FILTER_MAC_PENDING,
14813 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14814 &bp->macs_pool);
ec6ba945 14815
523224a3 14816 /* Set iSCSI MAC address */
619c5cb6
VZ		 14817 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14818 if (rc)
14819 break;
523224a3
DK		 14820
14821 mmiowb();
14822 barrier();
14823
619c5cb6
VZ		 14824 /* Start accepting on iSCSI L2 ring */
14825
14826 netif_addr_lock_bh(dev);
14827 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14828 netif_addr_unlock_bh(dev);
14829
14830 /* bits to wait on */
14831 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14832 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14833
14834 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14835 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3 14836
993ac7b5
MC		 14837 break;
14838 }
14839
14840 /* rtnl_lock is held. */
14841 case DRV_CTL_STOP_L2_CMD: {
619c5cb6 14842 unsigned long sp_bits = 0;
993ac7b5 14843
523224a3 14844 /* Stop accepting on iSCSI L2 ring */
619c5cb6
VZ		 14845 netif_addr_lock_bh(dev);
14846 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14847 netif_addr_unlock_bh(dev);
14848
14849 /* bits to wait on */
14850 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14851 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14852
14853 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14854 BNX2X_ERR("rx_mode completion timed out!\n");
523224a3
DK		 14855
14856 mmiowb();
14857 barrier();
14858
14859 /* Unset iSCSI L2 MAC */
619c5cb6
VZ		 14860 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14861 BNX2X_ISCSI_ETH_MAC, true);
993ac7b5
MC		 14862 break;
14863 }
c2bff63f
DK		 14864 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14865 int count = ctl->data.credit.credit_count;
14866
4e857c58 14867 smp_mb__before_atomic();
6e30dd4e 14868 atomic_add(count, &bp->cq_spq_left);
4e857c58 14869 smp_mb__after_atomic();
c2bff63f
DK		 14870 break;
14871 }
1d187b34 14872 case DRV_CTL_ULP_REGISTER_CMD: {
2e499d3c 14873 int ulp_type = ctl->data.register_data.ulp_type;
1d187b34
BW		 14874
14875 if (CHIP_IS_E3(bp)) {
14876 int idx = BP_FW_MB_IDX(bp);
2e499d3c
BW		 14877 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14878 int path = BP_PATH(bp);
14879 int port = BP_PORT(bp);
14880 int i;
14881 u32 scratch_offset;
14882 u32 *host_addr;
1d187b34 14883
2e499d3c 14884 /* first write capability to shmem2 */
1d187b34
BW		 14885 if (ulp_type == CNIC_ULP_ISCSI)
14886 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14887 else if (ulp_type == CNIC_ULP_FCOE)
14888 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14889 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
2e499d3c
BW		 14890
14891 if ((ulp_type != CNIC_ULP_FCOE) ||
14892 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14893 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
14894 break;
14895
14896 /* if reached here - should write fcoe capabilities */
14897 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14898 if (!scratch_offset)
14899 break;
14900 scratch_offset += offsetof(struct glob_ncsi_oem_data,
14901 fcoe_features[path][port]);
14902 host_addr = (u32 *) &(ctl->data.register_data.
14903 fcoe_features);
14904 for (i = 0; i < sizeof(struct fcoe_capabilities);
14905 i += 4)
14906 REG_WR(bp, scratch_offset + i,
14907 *(host_addr + i/4));
1d187b34 14908 }
42f8277f 14909 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14910 break;
14911 }
2e499d3c 14912
1d187b34
BW		 14913 case DRV_CTL_ULP_UNREGISTER_CMD: {
14914 int ulp_type = ctl->data.ulp_type;
14915
14916 if (CHIP_IS_E3(bp)) {
14917 int idx = BP_FW_MB_IDX(bp);
14918 u32 cap;
14919
14920 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14921 if (ulp_type == CNIC_ULP_ISCSI)
14922 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14923 else if (ulp_type == CNIC_ULP_FCOE)
14924 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14925 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14926 }
42f8277f 14927 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
1d187b34
BW		 14928 break;
14929 }
993ac7b5
MC		 14930
14931 default:
14932 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14933 rc = -EINVAL;
14934 }
14935
97ac4ef7
YM		 14936 /* For storage-only interfaces, change driver state */
14937 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp)) {
14938 switch (ctl->drv_state) {
14939 case DRV_NOP:
14940 break;
14941 case DRV_ACTIVE:
14942 bnx2x_set_os_driver_state(bp,
14943 OS_DRIVER_STATE_ACTIVE);
14944 break;
14945 case DRV_INACTIVE:
14946 bnx2x_set_os_driver_state(bp,
14947 OS_DRIVER_STATE_DISABLED);
14948 break;
14949 case DRV_UNLOADED:
14950 bnx2x_set_os_driver_state(bp,
14951 OS_DRIVER_STATE_NOT_LOADED);
14952 break;
14953 default:
14954 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl->drv_state);
14955 }
14956 }
14957
14958 return rc;
14959}
14960
14961static int bnx2x_get_fc_npiv(struct net_device *dev,
14962 struct cnic_fc_npiv_tbl *cnic_tbl)
14963{
14964 struct bnx2x *bp = netdev_priv(dev);
14965 struct bdn_fc_npiv_tbl *tbl = NULL;
14966 u32 offset, entries;
14967 int rc = -EINVAL;
14968 int i;
14969
14970 if (!SHMEM2_HAS(bp, fc_npiv_nvram_tbl_addr[0]))
14971 goto out;
14972
14973 DP(BNX2X_MSG_MCP, "About to read the FC-NPIV table\n");
14974
14975 tbl = kmalloc(sizeof(*tbl), GFP_KERNEL);
14976 if (!tbl) {
14977 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14978 goto out;
14979 }
14980
14981 offset = SHMEM2_RD(bp, fc_npiv_nvram_tbl_addr[BP_PORT(bp)]);
1e6bb1a3
YM		 14982 if (!offset) {
14983 DP(BNX2X_MSG_MCP, "No FC-NPIV in NVRAM\n");
14984 goto out;
14985 }
97ac4ef7
YM		 14986 DP(BNX2X_MSG_MCP, "Offset of FC-NPIV in NVRAM: %08x\n", offset);
14987
14988 /* Read the table contents from nvram */
14989 if (bnx2x_nvram_read(bp, offset, (u8 *)tbl, sizeof(*tbl))) {
14990 BNX2X_ERR("Failed to read FC-NPIV table\n");
14991 goto out;
14992 }
14993
14994 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14995 * the number of entries back to cpu endianness.
14996 */
14997 entries = tbl->fc_npiv_cfg.num_of_npiv;
14998 entries = (__force u32)be32_to_cpu((__force __be32)entries);
14999 tbl->fc_npiv_cfg.num_of_npiv = entries;
15000
15001 if (!tbl->fc_npiv_cfg.num_of_npiv) {
15002 DP(BNX2X_MSG_MCP,
15003 "No FC-NPIV table [valid, simply not present]\n");
15004 goto out;
15005 } else if (tbl->fc_npiv_cfg.num_of_npiv > MAX_NUMBER_NPIV) {
15006 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
15007 tbl->fc_npiv_cfg.num_of_npiv);
15008 goto out;
15009 } else {
15010 DP(BNX2X_MSG_MCP, "Read 0x%08x entries from NVRAM\n",
15011 tbl->fc_npiv_cfg.num_of_npiv);
15012 }
15013
15014 /* Copy the data into cnic-provided struct */
15015 cnic_tbl->count = tbl->fc_npiv_cfg.num_of_npiv;
15016 for (i = 0; i < cnic_tbl->count; i++) {
15017 memcpy(cnic_tbl->wwpn[i], tbl->settings[i].npiv_wwpn, 8);
15018 memcpy(cnic_tbl->wwnn[i], tbl->settings[i].npiv_wwnn, 8);
15019 }
15020
15021 rc = 0;
15022out:
15023 kfree(tbl);
993ac7b5
MC		 15024 return rc;
15025}
15026
9f6c9258 15027void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
993ac7b5
MC		 15028{
15029 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15030
15031 if (bp->flags & USING_MSIX_FLAG) {
15032 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
15033 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
15034 cp->irq_arr[0].vector = bp->msix_table[1].vector;
15035 } else {
15036 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
15037 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
15038 }
619c5cb6 15039 if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 15040 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
15041 else
15042 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
15043
619c5cb6
VZ		 15044 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
15045 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
993ac7b5
MC		 15046 cp->irq_arr[1].status_blk = bp->def_status_blk;
15047 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
523224a3 15048 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
993ac7b5
MC		 15049
15050 cp->num_irq = 2;
15051}
15052
37ae41a9
MS		 15053void bnx2x_setup_cnic_info(struct bnx2x *bp)
15054{
15055 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15056
37ae41a9
MS		 15057 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15058 bnx2x_cid_ilt_lines(bp);
15059 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
15060 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
15061 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
15062
f78afb35
MC		 15063 DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
15064 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
15065 cp->iscsi_l2_cid);
15066
37ae41a9
MS		 15067 if (NO_ISCSI_OOO(bp))
15068 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15069}
15070
993ac7b5
MC		 15071static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
15072 void *data)
15073{
15074 struct bnx2x *bp = netdev_priv(dev);
15075 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
55c11941
MS		 15076 int rc;
15077
15078 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
993ac7b5 15079
51c1a580
MS		 15080 if (ops == NULL) {
15081 BNX2X_ERR("NULL ops received\n");
993ac7b5 15082 return -EINVAL;
51c1a580 15083 }
993ac7b5 15084
55c11941
MS		 15085 if (!CNIC_SUPPORT(bp)) {
15086 BNX2X_ERR("Can't register CNIC when not supported\n");
15087 return -EOPNOTSUPP;
15088 }
15089
15090 if (!CNIC_LOADED(bp)) {
15091 rc = bnx2x_load_cnic(bp);
15092 if (rc) {
15093 BNX2X_ERR("CNIC-related load failed\n");
15094 return rc;
15095 }
55c11941
MS		 15096 }
15097
15098 bp->cnic_enabled = true;
15099
993ac7b5
MC		 15100 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
15101 if (!bp->cnic_kwq)
15102 return -ENOMEM;
15103
15104 bp->cnic_kwq_cons = bp->cnic_kwq;
15105 bp->cnic_kwq_prod = bp->cnic_kwq;
15106 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
15107
15108 bp->cnic_spq_pending = 0;
15109 bp->cnic_kwq_pending = 0;
15110
15111 bp->cnic_data = data;
15112
15113 cp->num_irq = 0;
619c5cb6 15114 cp->drv_state |= CNIC_DRV_STATE_REGD;
523224a3 15115 cp->iro_arr = bp->iro_arr;
993ac7b5 15116
993ac7b5 15117 bnx2x_setup_cnic_irq_info(bp);
c2bff63f 15118
993ac7b5
MC		 15119 rcu_assign_pointer(bp->cnic_ops, ops);
15120
42f8277f
YM		 15121 /* Schedule driver to read CNIC driver versions */
15122 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
15123
993ac7b5
MC		 15124 return 0;
15125}
15126
15127static int bnx2x_unregister_cnic(struct net_device *dev)
15128{
15129 struct bnx2x *bp = netdev_priv(dev);
15130 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15131
15132 mutex_lock(&bp->cnic_mutex);
993ac7b5 15133 cp->drv_state = 0;
2cfa5a04 15134 RCU_INIT_POINTER(bp->cnic_ops, NULL);
993ac7b5
MC		 15135 mutex_unlock(&bp->cnic_mutex);
15136 synchronize_rcu();
fea75645 15137 bp->cnic_enabled = false;
993ac7b5
MC		 15138 kfree(bp->cnic_kwq);
15139 bp->cnic_kwq = NULL;
15140
15141 return 0;
15142}
15143
a8f47eb7 15144static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
993ac7b5
MC		 15145{
15146 struct bnx2x *bp = netdev_priv(dev);
15147 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
15148
2ba45142
VZ		 15149 /* If both iSCSI and FCoE are disabled - return NULL in
15150 * order to indicate CNIC that it should not try to work
15151 * with this device.
15152 */
15153 if (NO_ISCSI(bp) && NO_FCOE(bp))
15154 return NULL;
15155
993ac7b5
MC		 15156 cp->drv_owner = THIS_MODULE;
15157 cp->chip_id = CHIP_ID(bp);
15158 cp->pdev = bp->pdev;
15159 cp->io_base = bp->regview;
15160 cp->io_base2 = bp->doorbells;
15161 cp->max_kwqe_pending = 8;
523224a3 15162 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
c2bff63f
DK		 15163 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
15164 bnx2x_cid_ilt_lines(bp);
993ac7b5 15165 cp->ctx_tbl_len = CNIC_ILT_LINES;
c2bff63f 15166 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
993ac7b5
MC		 15167 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
15168 cp->drv_ctl = bnx2x_drv_ctl;
97ac4ef7 15169 cp->drv_get_fc_npiv_tbl = bnx2x_get_fc_npiv;
993ac7b5
MC		 15170 cp->drv_register_cnic = bnx2x_register_cnic;
15171 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
37ae41a9 15172 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
619c5cb6
VZ		 15173 cp->iscsi_l2_client_id =
15174 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
37ae41a9 15175 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
c2bff63f 15176
2ba45142
VZ		 15177 if (NO_ISCSI_OOO(bp))
15178 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
15179
15180 if (NO_ISCSI(bp))
15181 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
15182
15183 if (NO_FCOE(bp))
15184 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
15185
51c1a580
MS		 15186 BNX2X_DEV_INFO(
15187 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
c2bff63f
DK		 15188 cp->ctx_blk_size,
15189 cp->ctx_tbl_offset,
15190 cp->ctx_tbl_len,
15191 cp->starting_cid);
993ac7b5
MC		 15192 return cp;
15193}
993ac7b5 15194
a8f47eb7 15195static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
9b176b6b 15196{
6411280a
AE		 15197 struct bnx2x *bp = fp->bp;
15198 u32 offset = BAR_USTRORM_INTMEM;
abc5a021 15199
6411280a
AE		 15200 if (IS_VF(bp))
15201 return bnx2x_vf_ustorm_prods_offset(bp, fp);
15202 else if (!CHIP_IS_E1x(bp))
15203 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
15204 else
15205 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
8d9ac297 15206
6411280a 15207 return offset;
8d9ac297 15208}
381ac16b 15209
6411280a
AE		 15210/* called only on E1H or E2.
15211 * When pretending to be PF, the pretend value is the function number 0...7
15212 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15213 * combination
15214 */
15215int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
381ac16b 15216{
6411280a 15217 u32 pretend_reg;
381ac16b 15218
23826850 15219 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
6411280a 15220 return -1;
381ac16b 15221
6411280a
AE		 15222 /* get my own pretend register */
15223 pretend_reg = bnx2x_get_pretend_reg(bp);
15224 REG_WR(bp, pretend_reg, pretend_func_val);
15225 REG_RD(bp, pretend_reg);
381ac16b
AE		 15226 return 0;
15227}
eeed018c
MK		 15228
15229static void bnx2x_ptp_task(struct work_struct *work)
15230{
15231 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
15232 int port = BP_PORT(bp);
15233 u32 val_seq;
15234 u64 timestamp, ns;
15235 struct skb_shared_hwtstamps shhwtstamps;
15236
15237 /* Read Tx timestamp registers */
15238 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15239 NIG_REG_P0_TLLH_PTP_BUF_SEQID);
15240 if (val_seq & 0x10000) {
15241 /* There is a valid timestamp value */
15242 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
15243 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
15244 timestamp <<= 32;
15245 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
15246 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
15247 /* Reset timestamp register to allow new timestamp */
15248 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15249 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15250 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15251
15252 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
15253 shhwtstamps.hwtstamp = ns_to_ktime(ns);
15254 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
15255 dev_kfree_skb_any(bp->ptp_tx_skb);
15256 bp->ptp_tx_skb = NULL;
15257
15258 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15259 timestamp, ns);
15260 } else {
15261 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
15262 /* Reschedule to keep checking for a valid timestamp value */
15263 schedule_work(&bp->ptp_task);
15264 }
15265}
15266
15267void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
15268{
15269 int port = BP_PORT(bp);
15270 u64 timestamp, ns;
15271
15272 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
15273 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
15274 timestamp <<= 32;
15275 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
15276 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
15277
15278 /* Reset timestamp register to allow new timestamp */
15279 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15280 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15281
15282 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
15283
15284 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
15285
15286 DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15287 timestamp, ns);
15288}
15289
15290/* Read the PHC */
a5a1d1c2 15291static u64 bnx2x_cyclecounter_read(const struct cyclecounter *cc)
eeed018c
MK		 15292{
15293 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
15294 int port = BP_PORT(bp);
15295 u32 wb_data[2];
15296 u64 phc_cycles;
15297
15298 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
15299 NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
15300 phc_cycles = wb_data[1];
15301 phc_cycles = (phc_cycles << 32) + wb_data[0];
15302
15303 DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
15304
15305 return phc_cycles;
15306}
15307
15308static void bnx2x_init_cyclecounter(struct bnx2x *bp)
15309{
15310 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
15311 bp->cyclecounter.read = bnx2x_cyclecounter_read;
f28ba401 15312 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64);
a6e2846c 15313 bp->cyclecounter.shift = 0;
eeed018c
MK		 15314 bp->cyclecounter.mult = 1;
15315}
15316
15317static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
15318{
15319 struct bnx2x_func_state_params func_params = {NULL};
15320 struct bnx2x_func_set_timesync_params *set_timesync_params =
15321 &func_params.params.set_timesync;
15322
15323 /* Prepare parameters for function state transitions */
15324 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
15325 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
15326
15327 func_params.f_obj = &bp->func_obj;
15328 func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
15329
15330 /* Function parameters */
15331 set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
15332 set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
15333
15334 return bnx2x_func_state_change(bp, &func_params);
15335}
15336
1444c301 15337static int bnx2x_enable_ptp_packets(struct bnx2x *bp)
eeed018c
MK		 15338{
15339 struct bnx2x_queue_state_params q_params;
15340 int rc, i;
15341
15342 /* send queue update ramrod to enable PTP packets */
15343 memset(&q_params, 0, sizeof(q_params));
15344 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
15345 q_params.cmd = BNX2X_Q_CMD_UPDATE;
15346 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
15347 &q_params.params.update.update_flags);
15348 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
15349 &q_params.params.update.update_flags);
15350
15351 /* send the ramrod on all the queues of the PF */
15352 for_each_eth_queue(bp, i) {
15353 struct bnx2x_fastpath *fp = &bp->fp[i];
15354
15355 /* Set the appropriate Queue object */
15356 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
15357
15358 /* Update the Queue state */
15359 rc = bnx2x_queue_state_change(bp, &q_params);
15360 if (rc) {
15361 BNX2X_ERR("Failed to enable PTP packets\n");
15362 return rc;
15363 }
15364 }
15365
15366 return 0;
15367}
15368
15369int bnx2x_configure_ptp_filters(struct bnx2x *bp)
15370{
15371 int port = BP_PORT(bp);
15372 int rc;
15373
15374 if (!bp->hwtstamp_ioctl_called)
15375 return 0;
15376
15377 switch (bp->tx_type) {
15378 case HWTSTAMP_TX_ON:
15379 bp->flags |= TX_TIMESTAMPING_EN;
15380 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15381 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
15382 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15383 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
15384 break;
15385 case HWTSTAMP_TX_ONESTEP_SYNC:
15386 BNX2X_ERR("One-step timestamping is not supported\n");
15387 return -ERANGE;
15388 }
15389
15390 switch (bp->rx_filter) {
15391 case HWTSTAMP_FILTER_NONE:
15392 break;
15393 case HWTSTAMP_FILTER_ALL:
15394 case HWTSTAMP_FILTER_SOME:
e3412575 15395 case HWTSTAMP_FILTER_NTP_ALL:
eeed018c
MK		 15396 bp->rx_filter = HWTSTAMP_FILTER_NONE;
15397 break;
15398 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
15399 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
15400 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
15401 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
15402 /* Initialize PTP detection for UDP/IPv4 events */
15403 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15404 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
15405 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15406 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
15407 break;
15408 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
15409 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
15410 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
15411 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
15412 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15413 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15414 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
15415 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15416 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
15417 break;
15418 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
15419 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
15420 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
15421 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
15422 /* Initialize PTP detection L2 events */
15423 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15424 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
15425 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15426 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
15427
15428 break;
15429 case HWTSTAMP_FILTER_PTP_V2_EVENT:
15430 case HWTSTAMP_FILTER_PTP_V2_SYNC:
15431 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
15432 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
15433 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15434 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15435 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
15436 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15437 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
15438 break;
15439 }
15440
15441 /* Indicate to FW that this PF expects recorded PTP packets */
15442 rc = bnx2x_enable_ptp_packets(bp);
15443 if (rc)
15444 return rc;
15445
15446 /* Enable sending PTP packets to host */
15447 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15448 NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
15449
15450 return 0;
15451}
15452
15453static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
15454{
15455 struct hwtstamp_config config;
15456 int rc;
15457
15458 DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
15459
15460 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
15461 return -EFAULT;
15462
15463 DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
15464 config.tx_type, config.rx_filter);
15465
15466 if (config.flags) {
15467 BNX2X_ERR("config.flags is reserved for future use\n");
15468 return -EINVAL;
15469 }
15470
15471 bp->hwtstamp_ioctl_called = 1;
15472 bp->tx_type = config.tx_type;
15473 bp->rx_filter = config.rx_filter;
15474
15475 rc = bnx2x_configure_ptp_filters(bp);
15476 if (rc)
15477 return rc;
15478
15479 config.rx_filter = bp->rx_filter;
15480
15481 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
15482 -EFAULT : 0;
15483}
15484
bf27c353 15485/* Configures HW for PTP */
eeed018c
MK		 15486static int bnx2x_configure_ptp(struct bnx2x *bp)
15487{
15488 int rc, port = BP_PORT(bp);
15489 u32 wb_data[2];
15490
15491 /* Reset PTP event detection rules - will be configured in the IOCTL */
15492 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
15493 NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
15494 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
15495 NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
15496 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
15497 NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
15498 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
15499 NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
15500
15501 /* Disable PTP packets to host - will be configured in the IOCTL*/
15502 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
15503 NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
15504
15505 /* Enable the PTP feature */
15506 REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
15507 NIG_REG_P0_PTP_EN, 0x3F);
15508
15509 /* Enable the free-running counter */
15510 wb_data[0] = 0;
15511 wb_data[1] = 0;
15512 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
15513
15514 /* Reset drift register (offset register is not reset) */
15515 rc = bnx2x_send_reset_timesync_ramrod(bp);
15516 if (rc) {
15517 BNX2X_ERR("Failed to reset PHC drift register\n");
15518 return -EFAULT;
15519 }
15520
15521 /* Reset possibly old timestamps */
15522 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
15523 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
15524 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
15525 NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
15526
15527 return 0;
15528}
15529
15530/* Called during load, to initialize PTP-related stuff */
15531void bnx2x_init_ptp(struct bnx2x *bp)
15532{
15533 int rc;
15534
15535 /* Configure PTP in HW */
15536 rc = bnx2x_configure_ptp(bp);
15537 if (rc) {
15538 BNX2X_ERR("Stopping PTP initialization\n");
15539 return;
15540 }
15541
15542 /* Init work queue for Tx timestamping */
15543 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
15544
15545 /* Init cyclecounter and timecounter. This is done only in the first
15546 * load. If done in every load, PTP application will fail when doing
15547 * unload / load (e.g. MTU change) while it is running.
15548 */
15549 if (!bp->timecounter_init_done) {
15550 bnx2x_init_cyclecounter(bp);
15551 timecounter_init(&bp->timecounter, &bp->cyclecounter,
15552 ktime_to_ns(ktime_get_real()));
15553 bp->timecounter_init_done = 1;
15554 }
15555
15556 DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
15557}
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