]> git.ipfire.org Git - thirdparty/linux.git/blame - drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'hyperv-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git...
[thirdparty/linux.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
2c81bfd5 34#include "en/port.h"
db05815b 35#include "en/xsk/umem.h"
6dbc80ca 36#include "lib/clock.h"
f62b8bb8 37
076b0936
ES		 38void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
f62b8bb8 40{
f62b8bb8
AV		 41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 44 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
f72e6c3e 50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
f62b8bb8
AV		 51 sizeof(drvinfo->bus_info));
52}
53
076b0936
ES		 54static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56{
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60}
61
665bc539
GP		 62struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8
AV		 65};
66
6a897372
AL		 67static
68struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69static
70struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
665bc539 71
6a897372 72#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
665bc539
GP		 73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
6a897372
AL		 76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
665bc539
GP		 78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
6a897372
AL		 83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
665bc539
GP		 87 } \
88 })
89
90void mlx5e_build_ptys2ethtool_map(void)
91{
6a897372
AL		 92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
665bc539 95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
665bc539 97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
6a897372 98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
665bc539 99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
665bc539 101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
6a897372 102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
665bc539 103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
665bc539 105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
6a897372 106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
665bc539 107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
6a897372 108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
665bc539 109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
6a897372 110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
665bc539 111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
6a897372 112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
665bc539 113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
665bc539 115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
665bc539 117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
6a897372 118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
665bc539 119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
6a897372 120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
665bc539 121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
6a897372 122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
665bc539 123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
6a897372 124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
665bc539 125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
6a897372 126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
665bc539 127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
6a897372 128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
665bc539 129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
6a897372 130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
665bc539 131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
6a897372 132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
665bc539 133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
6a897372 134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
665bc539 135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
6a897372 136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
665bc539 137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
6a897372 138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
665bc539 139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
6a897372 140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
665bc539 141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
6a897372 142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
665bc539 143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
6a897372
AL		 144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197}
198
199static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
200 struct ptys2ethtool_config **arr,
201 u32 *size)
202{
203 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
204
205 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
206 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
207 ARRAY_SIZE(ptys2legacy_ethtool_table);
665bc539
GP		 208}
209
8ff57c18
TT		 210typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
211
212struct pflag_desc {
213 char name[ETH_GSTRING_LEN];
214 mlx5e_pflag_handler handler;
d2408205
KH		 215};
216
8ff57c18
TT		 217static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
218
076b0936 219int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 220{
c0752f2b
KH		 221 int i, num_stats = 0;
222
f62b8bb8
AV		 223 switch (sset) {
224 case ETH_SS_STATS:
c0752f2b
KH		 225 for (i = 0; i < mlx5e_num_stats_grps; i++)
226 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
1fe85006 227 return num_stats;
4e59e288 228 case ETH_SS_PRIV_FLAGS:
8ff57c18 229 return MLX5E_NUM_PFLAGS;
d605d668
KH		 230 case ETH_SS_TEST:
231 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 232 /* fallthrough */
233 default:
234 return -EOPNOTSUPP;
235 }
236}
237
076b0936
ES		 238static int mlx5e_get_sset_count(struct net_device *dev, int sset)
239{
240 struct mlx5e_priv *priv = netdev_priv(dev);
241
242 return mlx5e_ethtool_get_sset_count(priv, sset);
243}
244
c045deef 245static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 246{
1fe85006 247 int i, idx = 0;
9218b44d 248
c0752f2b
KH		 249 for (i = 0; i < mlx5e_num_stats_grps; i++)
250 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
9218b44d
GP		 251}
252
c045deef 253void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 254{
4e59e288 255 int i;
f62b8bb8
AV		 256
257 switch (stringset) {
258 case ETH_SS_PRIV_FLAGS:
8ff57c18
TT		 259 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
260 strcpy(data + i * ETH_GSTRING_LEN,
261 mlx5e_priv_flags[i].name);
f62b8bb8
AV		 262 break;
263
264 case ETH_SS_TEST:
d605d668
KH		 265 for (i = 0; i < mlx5e_self_test_num(priv); i++)
266 strcpy(data + i * ETH_GSTRING_LEN,
267 mlx5e_self_tests[i]);
f62b8bb8
AV		 268 break;
269
270 case ETH_SS_STATS:
9218b44d 271 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 272 break;
273 }
274}
275
c045deef 276static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 277{
278 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 279
280 mlx5e_ethtool_get_strings(priv, stringset, data);
281}
282
283void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
284 struct ethtool_stats *stats, u64 *data)
285{
1fe85006 286 int i, idx = 0;
f62b8bb8 287
f62b8bb8 288 mutex_lock(&priv->state_lock);
19386177 289 mlx5e_update_stats(priv);
f62b8bb8
AV		 290 mutex_unlock(&priv->state_lock);
291
c0752f2b
KH		 292 for (i = 0; i < mlx5e_num_stats_grps; i++)
293 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
f62b8bb8
AV		 294}
295
076b0936
ES		 296static void mlx5e_get_ethtool_stats(struct net_device *dev,
297 struct ethtool_stats *stats,
298 u64 *data)
299{
300 struct mlx5e_priv *priv = netdev_priv(dev);
301
302 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
303}
304
076b0936
ES		 305void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
306 struct ethtool_ringparam *param)
f62b8bb8 307{
73281b78 308 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
f62b8bb8 309 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
73281b78 310 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
6a9764ef 311 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 312}
313
076b0936
ES		 314static void mlx5e_get_ringparam(struct net_device *dev,
315 struct ethtool_ringparam *param)
f62b8bb8
AV		 316{
317 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 318
319 mlx5e_ethtool_get_ringparam(priv, param);
320}
321
322int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
323 struct ethtool_ringparam *param)
324{
546f18ed 325 struct mlx5e_channels new_channels = {};
f62b8bb8
AV		 326 u8 log_rq_size;
327 u8 log_sq_size;
328 int err = 0;
329
330 if (param->rx_jumbo_pending) {
076b0936 331 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 332 __func__);
333 return -EINVAL;
334 }
335 if (param->rx_mini_pending) {
076b0936 336 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 337 __func__);
338 return -EINVAL;
339 }
cc8e9ebf 340
73281b78 341 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
076b0936 342 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 343 __func__, param->rx_pending,
73281b78 344 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
fe4c988b
SM		 345 return -EINVAL;
346 }
347
f62b8bb8 348 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 349 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 350 __func__, param->tx_pending,
351 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
352 return -EINVAL;
353 }
f62b8bb8 354
73281b78 355 log_rq_size = order_base_2(param->rx_pending);
f62b8bb8 356 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 357
73281b78 358 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
6a9764ef 359 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 360 return 0;
361
362 mutex_lock(&priv->state_lock);
98e81b0a 363
546f18ed 364 new_channels.params = priv->channels.params;
73281b78 365 new_channels.params.log_rq_mtu_frames = log_rq_size;
546f18ed 366 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 367
546f18ed
SM		 368 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
369 priv->channels.params = new_channels.params;
370 goto unlock;
371 }
98e81b0a 372
877662e2 373 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
98e81b0a 374
546f18ed 375unlock:
f62b8bb8
AV		 376 mutex_unlock(&priv->state_lock);
377
378 return err;
379}
380
076b0936
ES		 381static int mlx5e_set_ringparam(struct net_device *dev,
382 struct ethtool_ringparam *param)
f62b8bb8
AV		 383{
384 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 385
076b0936
ES		 386 return mlx5e_ethtool_set_ringparam(priv, param);
387}
388
389void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
390 struct ethtool_channels *ch)
391{
db05815b
MM		 392 mutex_lock(&priv->state_lock);
393
694826e3 394 ch->max_combined = priv->max_nch;
6a9764ef 395 ch->combined_count = priv->channels.params.num_channels;
db05815b
MM		 396 if (priv->xsk.refcnt) {
397 /* The upper half are XSK queues. */
398 ch->max_combined *= 2;
399 ch->combined_count *= 2;
400 }
401
402 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 403}
404
076b0936
ES		 405static void mlx5e_get_channels(struct net_device *dev,
406 struct ethtool_channels *ch)
f62b8bb8
AV		 407{
408 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 409
410 mlx5e_ethtool_get_channels(priv, ch);
411}
412
413int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
414 struct ethtool_channels *ch)
415{
db05815b 416 struct mlx5e_params *cur_params = &priv->channels.params;
f62b8bb8 417 unsigned int count = ch->combined_count;
55c2503d 418 struct mlx5e_channels new_channels = {};
45bf454a 419 bool arfs_enabled;
f62b8bb8
AV		 420 int err = 0;
421
422 if (!count) {
076b0936 423 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 424 __func__);
425 return -EINVAL;
426 }
f62b8bb8 427
db05815b 428 if (cur_params->num_channels == count)
f62b8bb8
AV		 429 return 0;
430
431 mutex_lock(&priv->state_lock);
98e81b0a 432
db05815b
MM		 433 /* Don't allow changing the number of channels if there is an active
434 * XSK, because the numeration of the XSK and regular RQs will change.
435 */
436 if (priv->xsk.refcnt) {
437 err = -EINVAL;
438 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
439 __func__);
440 goto out;
441 }
442
55c2503d
SM		 443 new_channels.params = priv->channels.params;
444 new_channels.params.num_channels = count;
55c2503d
SM		 445
446 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
db05815b 447 *cur_params = new_channels.params;
c475e11e
TT		 448 if (!netif_is_rxfh_configured(priv->netdev))
449 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
450 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM		 451 goto out;
452 }
453
076b0936 454 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 455 if (arfs_enabled)
456 mlx5e_arfs_disable(priv);
457
fb35c534
MP		 458 if (!netif_is_rxfh_configured(priv->netdev))
459 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
460 MLX5E_INDIR_RQT_SIZE, count);
461
55c2503d 462 /* Switch to new channels, set new parameters and close old ones */
877662e2 463 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
45bf454a
MG		 464
465 if (arfs_enabled) {
877662e2
TT		 466 int err2 = mlx5e_arfs_enable(priv);
467
468 if (err2)
076b0936 469 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
877662e2 470 __func__, err2);
45bf454a 471 }
98e81b0a 472
45bf454a 473out:
f62b8bb8
AV		 474 mutex_unlock(&priv->state_lock);
475
476 return err;
477}
478
076b0936
ES		 479static int mlx5e_set_channels(struct net_device *dev,
480 struct ethtool_channels *ch)
f62b8bb8 481{
076b0936
ES		 482 struct mlx5e_priv *priv = netdev_priv(dev);
483
484 return mlx5e_ethtool_set_channels(priv, ch);
485}
f62b8bb8 486
076b0936
ES		 487int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
488 struct ethtool_coalesce *coal)
489{
8960b389 490 struct dim_cq_moder *rx_moder, *tx_moder;
cbce4f44 491
7524a5d8 492 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 493 return -EOPNOTSUPP;
7524a5d8 494
cbce4f44
TG		 495 rx_moder = &priv->channels.params.rx_cq_moderation;
496 coal->rx_coalesce_usecs = rx_moder->usec;
497 coal->rx_max_coalesced_frames = rx_moder->pkts;
498 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
499
500 tx_moder = &priv->channels.params.tx_cq_moderation;
501 coal->tx_coalesce_usecs = tx_moder->usec;
502 coal->tx_max_coalesced_frames = tx_moder->pkts;
503 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
f62b8bb8
AV		 504
505 return 0;
506}
507
076b0936
ES		 508static int mlx5e_get_coalesce(struct net_device *netdev,
509 struct ethtool_coalesce *coal)
510{
511 struct mlx5e_priv *priv = netdev_priv(netdev);
512
513 return mlx5e_ethtool_get_coalesce(priv, coal);
514}
515
b392a207
MS		 516#define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
517#define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
518
546f18ed
SM		 519static void
520mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 521{
f62b8bb8 522 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 523 int tc;
524 int i;
525
ff9c852f
SM		 526 for (i = 0; i < priv->channels.num; ++i) {
527 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 528
529 for (tc = 0; tc < c->num_tc; tc++) {
530 mlx5_core_modify_cq_moderation(mdev,
531 &c->sq[tc].cq.mcq,
532 coal->tx_coalesce_usecs,
533 coal->tx_max_coalesced_frames);
534 }
535
536 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
537 coal->rx_coalesce_usecs,
538 coal->rx_max_coalesced_frames);
539 }
546f18ed 540}
f62b8bb8 541
076b0936
ES		 542int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
543 struct ethtool_coalesce *coal)
546f18ed 544{
8960b389 545 struct dim_cq_moder *rx_moder, *tx_moder;
546f18ed
SM		 546 struct mlx5_core_dev *mdev = priv->mdev;
547 struct mlx5e_channels new_channels = {};
548 int err = 0;
549 bool reset;
cb3c7fd4 550
546f18ed
SM		 551 if (!MLX5_CAP_GEN(mdev, cq_moderation))
552 return -EOPNOTSUPP;
553
b392a207
MS		 554 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
555 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
556 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
557 __func__, MLX5E_MAX_COAL_TIME);
558 return -ERANGE;
559 }
560
561 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
562 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
563 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
564 __func__, MLX5E_MAX_COAL_FRAMES);
565 return -ERANGE;
566 }
567
546f18ed
SM		 568 mutex_lock(&priv->state_lock);
569 new_channels.params = priv->channels.params;
570
cbce4f44
TG		 571 rx_moder = &new_channels.params.rx_cq_moderation;
572 rx_moder->usec = coal->rx_coalesce_usecs;
573 rx_moder->pkts = coal->rx_max_coalesced_frames;
574 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
575
576 tx_moder = &new_channels.params.tx_cq_moderation;
577 tx_moder->usec = coal->tx_coalesce_usecs;
578 tx_moder->pkts = coal->tx_max_coalesced_frames;
579 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
546f18ed
SM		 580
581 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
582 priv->channels.params = new_channels.params;
583 goto out;
584 }
585 /* we are opened */
586
cbce4f44
TG		 587 reset = (!!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled) ||
588 (!!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled);
589
546f18ed
SM		 590 if (!reset) {
591 mlx5e_set_priv_channels_coalesce(priv, coal);
592 priv->channels.params = new_channels.params;
593 goto out;
594 }
595
877662e2 596 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
546f18ed
SM		 597
598out:
2fcb92fb 599 mutex_unlock(&priv->state_lock);
cb3c7fd4 600 return err;
f62b8bb8
AV		 601}
602
076b0936
ES		 603static int mlx5e_set_coalesce(struct net_device *netdev,
604 struct ethtool_coalesce *coal)
605{
606 struct mlx5e_priv *priv = netdev_priv(netdev);
607
608 return mlx5e_ethtool_set_coalesce(priv, coal);
609}
610
6a897372
AL		 611static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
612 unsigned long *supported_modes,
665bc539 613 u32 eth_proto_cap)
f62b8bb8 614{
7abc2110 615 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 616 struct ptys2ethtool_config *table;
617 u32 max_size;
665bc539 618 int proto;
f62b8bb8 619
6a897372
AL		 620 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
621 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 622 bitmap_or(supported_modes, supported_modes,
6a897372 623 table[proto].supported,
665bc539 624 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 625}
626
dd1b9e09
AL		 627static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
628 u32 eth_proto_cap, bool ext)
f62b8bb8 629{
7abc2110 630 unsigned long proto_cap = eth_proto_cap;
6a897372
AL		 631 struct ptys2ethtool_config *table;
632 u32 max_size;
665bc539 633 int proto;
f62b8bb8 634
dd1b9e09
AL		 635 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
636 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
637 ARRAY_SIZE(ptys2legacy_ethtool_table);
638
6a897372 639 for_each_set_bit(proto, &proto_cap, max_size)
665bc539 640 bitmap_or(advertising_modes, advertising_modes,
6a897372 641 table[proto].advertised,
665bc539 642 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 643}
644
6cfa9460
SA		 645static const u32 pplm_fec_2_ethtool[] = {
646 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
647 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
648 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
649};
650
651static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
652{
653 int mode = 0;
654
655 if (!fec_mode)
656 return ETHTOOL_FEC_AUTO;
657
658 mode = find_first_bit(&fec_mode, size);
659
660 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
661 return pplm_fec_2_ethtool[mode];
662
663 return 0;
664}
665
666/* we use ETHTOOL_FEC_* offset and apply it to ETHTOOL_LINK_MODE_FEC_*_BIT */
667static u32 ethtool_fec2ethtool_caps(u_long ethtool_fec_code)
668{
669 u32 offset;
670
671 offset = find_first_bit(&ethtool_fec_code, sizeof(u32));
672 offset -= ETHTOOL_FEC_OFF_BIT;
673 offset += ETHTOOL_LINK_MODE_FEC_NONE_BIT;
674
675 return offset;
676}
677
678static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
679 struct ethtool_link_ksettings *link_ksettings)
680{
681 u_long fec_caps = 0;
682 u32 active_fec = 0;
683 u32 offset;
684 u32 bitn;
685 int err;
686
687 err = mlx5e_get_fec_caps(dev, (u8 *)&fec_caps);
688 if (err)
689 return (err == -EOPNOTSUPP) ? 0 : err;
690
691 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
692 if (err)
693 return err;
694
695 for_each_set_bit(bitn, &fec_caps, ARRAY_SIZE(pplm_fec_2_ethtool)) {
696 u_long ethtool_bitmask = pplm_fec_2_ethtool[bitn];
697
698 offset = ethtool_fec2ethtool_caps(ethtool_bitmask);
699 __set_bit(offset, link_ksettings->link_modes.supported);
700 }
701
702 active_fec = pplm2ethtool_fec(active_fec, sizeof(u32) * BITS_PER_BYTE);
703 offset = ethtool_fec2ethtool_caps(active_fec);
704 __set_bit(offset, link_ksettings->link_modes.advertising);
705
706 return 0;
707}
708
46e9d0b6
EBE		 709static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
710 u32 eth_proto_cap,
711 u8 connector_type)
f62b8bb8 712{
46e9d0b6
EBE		 713 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
714 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
715 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
716 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
717 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
718 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
719 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
720 ethtool_link_ksettings_add_link_mode(link_ksettings,
721 supported,
722 FIBRE);
723 ethtool_link_ksettings_add_link_mode(link_ksettings,
724 advertising,
725 FIBRE);
726 }
727
728 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
729 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
730 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
731 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
732 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
733 ethtool_link_ksettings_add_link_mode(link_ksettings,
734 supported,
735 Backplane);
736 ethtool_link_ksettings_add_link_mode(link_ksettings,
737 advertising,
738 Backplane);
739 }
740 return;
f62b8bb8
AV		 741 }
742
46e9d0b6
EBE		 743 switch (connector_type) {
744 case MLX5E_PORT_TP:
745 ethtool_link_ksettings_add_link_mode(link_ksettings,
746 supported, TP);
747 ethtool_link_ksettings_add_link_mode(link_ksettings,
748 advertising, TP);
749 break;
750 case MLX5E_PORT_AUI:
751 ethtool_link_ksettings_add_link_mode(link_ksettings,
752 supported, AUI);
753 ethtool_link_ksettings_add_link_mode(link_ksettings,
754 advertising, AUI);
755 break;
756 case MLX5E_PORT_BNC:
757 ethtool_link_ksettings_add_link_mode(link_ksettings,
758 supported, BNC);
759 ethtool_link_ksettings_add_link_mode(link_ksettings,
760 advertising, BNC);
761 break;
762 case MLX5E_PORT_MII:
763 ethtool_link_ksettings_add_link_mode(link_ksettings,
764 supported, MII);
765 ethtool_link_ksettings_add_link_mode(link_ksettings,
766 advertising, MII);
767 break;
768 case MLX5E_PORT_FIBRE:
769 ethtool_link_ksettings_add_link_mode(link_ksettings,
770 supported, FIBRE);
771 ethtool_link_ksettings_add_link_mode(link_ksettings,
772 advertising, FIBRE);
773 break;
774 case MLX5E_PORT_DA:
775 ethtool_link_ksettings_add_link_mode(link_ksettings,
776 supported, Backplane);
777 ethtool_link_ksettings_add_link_mode(link_ksettings,
778 advertising, Backplane);
779 break;
780 case MLX5E_PORT_NONE:
781 case MLX5E_PORT_OTHER:
782 default:
783 break;
f62b8bb8 784 }
f62b8bb8
AV		 785}
786
787static void get_speed_duplex(struct net_device *netdev,
4b95840a 788 u32 eth_proto_oper, bool force_legacy,
665bc539 789 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 790{
a08b4ed1 791 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 792 u32 speed = SPEED_UNKNOWN;
793 u8 duplex = DUPLEX_UNKNOWN;
794
795 if (!netif_carrier_ok(netdev))
796 goto out;
797
4b95840a 798 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
2c81bfd5
HN		 799 if (!speed) {
800 speed = SPEED_UNKNOWN;
801 goto out;
f62b8bb8 802 }
2c81bfd5
HN		 803
804 duplex = DUPLEX_FULL;
805
f62b8bb8 806out:
665bc539
GP		 807 link_ksettings->base.speed = speed;
808 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 809}
810
6a897372 811static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
665bc539 812 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 813{
665bc539 814 unsigned long *supported = link_ksettings->link_modes.supported;
6a897372 815 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
665bc539 816
665bc539 817 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 818}
819
dd1b9e09
AL		 820static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
821 struct ethtool_link_ksettings *link_ksettings,
822 bool ext)
f62b8bb8 823{
665bc539 824 unsigned long *advertising = link_ksettings->link_modes.advertising;
dd1b9e09 825 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
665bc539 826
e3c19503 827 if (rx_pause)
665bc539
GP		 828 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
829 if (tx_pause ^ rx_pause)
830 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 831}
832
5b4793f8
EBE		 833static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
834 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
835 [MLX5E_PORT_NONE] = PORT_NONE,
836 [MLX5E_PORT_TP] = PORT_TP,
837 [MLX5E_PORT_AUI] = PORT_AUI,
838 [MLX5E_PORT_BNC] = PORT_BNC,
839 [MLX5E_PORT_MII] = PORT_MII,
840 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
841 [MLX5E_PORT_DA] = PORT_DA,
842 [MLX5E_PORT_OTHER] = PORT_OTHER,
843 };
844
845static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 846{
5b4793f8
EBE		 847 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
848 return ptys2connector_type[connector_type];
849
61bf2125
OG		 850 if (eth_proto &
851 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
852 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
853 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
854 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
855 return PORT_FIBRE;
f62b8bb8
AV		 856 }
857
61bf2125
OG		 858 if (eth_proto &
859 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
860 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
861 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
862 return PORT_DA;
f62b8bb8
AV		 863 }
864
61bf2125
OG		 865 if (eth_proto &
866 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
867 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
868 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
869 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
870 return PORT_NONE;
f62b8bb8
AV		 871 }
872
873 return PORT_OTHER;
874}
875
6a897372 876static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
665bc539 877 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 878{
665bc539 879 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
dd1b9e09 880 bool ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
665bc539 881
dd1b9e09 882 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
f62b8bb8
AV		 883}
884
371289b6
OG		 885int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
886 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 887{
f62b8bb8 888 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 889 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 890 u32 rx_pause = 0;
891 u32 tx_pause = 0;
f62b8bb8
AV		 892 u32 eth_proto_cap;
893 u32 eth_proto_admin;
894 u32 eth_proto_lp;
895 u32 eth_proto_oper;
52244d96
GP		 896 u8 an_disable_admin;
897 u8 an_status;
5b4793f8 898 u8 connector_type;
dd1b9e09 899 bool admin_ext;
6a897372 900 bool ext;
f62b8bb8
AV		 901 int err;
902
a05bdefa 903 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8 904 if (err) {
371289b6 905 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
f62b8bb8 906 __func__, err);
6cfa9460 907 goto err_query_regs;
f62b8bb8 908 }
6a897372
AL		 909 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
910 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
911 eth_proto_capability);
912 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
913 eth_proto_admin);
dd1b9e09
AL		 914 /* Fields: eth_proto_admin and ext_eth_proto_admin are
915 * mutually exclusive. Hence try reading legacy advertising
916 * when extended advertising is zero.
4b95840a
AL		 917 * admin_ext indicates which proto_admin (ext vs. legacy)
918 * should be read and interpreted
dd1b9e09
AL		 919 */
920 admin_ext = ext;
921 if (ext && !eth_proto_admin) {
922 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
923 eth_proto_admin);
924 admin_ext = false;
925 }
926
4b95840a 927 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
6a897372
AL		 928 eth_proto_oper);
929 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
930 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
931 an_status = MLX5_GET(ptys_reg, out, an_status);
932 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 933
b383b544
GP		 934 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
935
665bc539
GP		 936 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
937 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 938
6a897372 939 get_supported(mdev, eth_proto_cap, link_ksettings);
dd1b9e09
AL		 940 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
941 admin_ext);
4b95840a
AL		 942 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
943 link_ksettings);
f62b8bb8
AV		 944
945 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
946
5b4793f8
EBE		 947 link_ksettings->base.port = get_connector_port(eth_proto_oper,
948 connector_type);
46e9d0b6
EBE		 949 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
950 connector_type);
6a897372 951 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
f62b8bb8 952
52244d96
GP		 953 if (an_status == MLX5_AN_COMPLETE)
954 ethtool_link_ksettings_add_link_mode(link_ksettings,
955 lp_advertising, Autoneg);
956
957 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
958 AUTONEG_ENABLE;
959 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
960 Autoneg);
6cfa9460 961
2eb1e425
SA		 962 err = get_fec_supported_advertised(mdev, link_ksettings);
963 if (err) {
371289b6 964 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
6cfa9460 965 __func__, err);
2eb1e425
SA		 966 err = 0; /* don't fail caps query because of FEC error */
967 }
6cfa9460 968
52244d96
GP		 969 if (!an_disable_admin)
970 ethtool_link_ksettings_add_link_mode(link_ksettings,
971 advertising, Autoneg);
972
6cfa9460 973err_query_regs:
f62b8bb8
AV		 974 return err;
975}
976
371289b6
OG		 977static int mlx5e_get_link_ksettings(struct net_device *netdev,
978 struct ethtool_link_ksettings *link_ksettings)
979{
980 struct mlx5e_priv *priv = netdev_priv(netdev);
981
982 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
983}
984
665bc539 985static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 986{
987 u32 i, ptys_modes = 0;
988
989 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
6a897372
AL		 990 if (*ptys2legacy_ethtool_table[i].advertised == 0)
991 continue;
992 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
665bc539
GP		 993 link_modes,
994 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 995 ptys_modes |= MLX5E_PROT_MASK(i);
996 }
997
998 return ptys_modes;
999}
1000
6a897372
AL		 1001static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1002{
1003 u32 i, ptys_modes = 0;
1004 unsigned long modes[2];
1005
1006 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1007 if (*ptys2ext_ethtool_table[i].advertised == 0)
1008 continue;
1009 memset(modes, 0, sizeof(modes));
1010 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1011 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1012
1013 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1014 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1015 ptys_modes |= MLX5E_PROT_MASK(i);
1016 }
1017 return ptys_modes;
1018}
1019
4b95840a
AL		 1020static bool ext_link_mode_requested(const unsigned long *adver)
1021{
1022#define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1023 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1024 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes);
1025
1026 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1027 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1028}
1029
1030static bool ext_speed_requested(u32 speed)
1031{
1032#define MLX5E_MAX_PTYS_LEGACY_SPEED 100000
1033 return !!(speed > MLX5E_MAX_PTYS_LEGACY_SPEED);
1034}
1035
1036static bool ext_requested(u8 autoneg, const unsigned long *adver, u32 speed)
1037{
1038 bool ext_link_mode = ext_link_mode_requested(adver);
1039 bool ext_speed = ext_speed_requested(speed);
1040
1041 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_speed;
1042}
1043
371289b6
OG		 1044int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1045 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 1046{
f62b8bb8 1047 struct mlx5_core_dev *mdev = priv->mdev;
bc4e12ff 1048 struct mlx5e_port_eth_proto eproto;
4b95840a 1049 const unsigned long *adver;
52244d96
GP		 1050 bool an_changes = false;
1051 u8 an_disable_admin;
6a897372 1052 bool ext_supported;
52244d96
GP		 1053 u8 an_disable_cap;
1054 bool an_disable;
f62b8bb8 1055 u32 link_modes;
52244d96 1056 u8 an_status;
4b95840a 1057 u8 autoneg;
f62b8bb8 1058 u32 speed;
4b95840a 1059 bool ext;
f62b8bb8
AV		 1060 int err;
1061
6a897372 1062 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
f62b8bb8 1063
4b95840a
AL		 1064 adver = link_ksettings->link_modes.advertising;
1065 autoneg = link_ksettings->base.autoneg;
1066 speed = link_ksettings->base.speed;
6a897372 1067
4b95840a 1068 ext = ext_requested(autoneg, adver, speed),
6a897372 1069 ext_supported = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
4b95840a
AL		 1070 if (!ext_supported && ext)
1071 return -EOPNOTSUPP;
f62b8bb8 1072
4b95840a 1073 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
6a897372 1074 mlx5e_ethtool2ptys_adver_link;
4b95840a 1075 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
f62b8bb8 1076 if (err) {
bc4e12ff 1077 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
f62b8bb8
AV		 1078 __func__, err);
1079 goto out;
1080 }
4b95840a
AL		 1081 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1082 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
f62b8bb8 1083
bc4e12ff 1084 link_modes = link_modes & eproto.cap;
f62b8bb8 1085 if (!link_modes) {
371289b6 1086 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
f62b8bb8
AV		 1087 __func__);
1088 err = -EINVAL;
1089 goto out;
1090 }
1091
bc4e12ff
AL		 1092 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1093 &an_disable_admin);
52244d96 1094
4b95840a 1095 an_disable = autoneg == AUTONEG_DISABLE;
52244d96
GP		 1096 an_changes = ((!an_disable && an_disable_admin) ||
1097 (an_disable && !an_disable_admin));
1098
bc4e12ff 1099 if (!an_changes && link_modes == eproto.admin)
f62b8bb8
AV		 1100 goto out;
1101
4b95840a 1102 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
667daeda 1103 mlx5_toggle_port_link(mdev);
f62b8bb8 1104
f62b8bb8
AV		 1105out:
1106 return err;
1107}
1108
371289b6
OG		 1109static int mlx5e_set_link_ksettings(struct net_device *netdev,
1110 const struct ethtool_link_ksettings *link_ksettings)
1111{
1112 struct mlx5e_priv *priv = netdev_priv(netdev);
1113
1114 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1115}
1116
a5355de8
OG		 1117u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1118{
bbeb53b8 1119 return sizeof(priv->rss_params.toeplitz_hash_key);
a5355de8
OG		 1120}
1121
2d75b2bc
AS		 1122static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1123{
1124 struct mlx5e_priv *priv = netdev_priv(netdev);
1125
a5355de8 1126 return mlx5e_ethtool_get_rxfh_key_size(priv);
2d75b2bc
AS		 1127}
1128
a5355de8 1129u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
2d75b2bc
AS		 1130{
1131 return MLX5E_INDIR_RQT_SIZE;
1132}
1133
a5355de8
OG		 1134static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1135{
1136 struct mlx5e_priv *priv = netdev_priv(netdev);
1137
1138 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1139}
1140
2be6967c
SM		 1141static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1142 u8 *hfunc)
1143{
1144 struct mlx5e_priv *priv = netdev_priv(netdev);
bbeb53b8 1145 struct mlx5e_rss_params *rss = &priv->rss_params;
2be6967c 1146
2d75b2bc 1147 if (indir)
bbeb53b8
AL		 1148 memcpy(indir, rss->indirection_rqt,
1149 sizeof(rss->indirection_rqt));
2d75b2bc
AS		 1150
1151 if (key)
bbeb53b8
AL		 1152 memcpy(key, rss->toeplitz_hash_key,
1153 sizeof(rss->toeplitz_hash_key));
2d75b2bc 1154
2be6967c 1155 if (hfunc)
bbeb53b8 1156 *hfunc = rss->hfunc;
2be6967c
SM		 1157
1158 return 0;
1159}
1160
98e81b0a 1161static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1162 const u8 *key, const u8 hfunc)
1163{
98e81b0a 1164 struct mlx5e_priv *priv = netdev_priv(dev);
bbeb53b8 1165 struct mlx5e_rss_params *rss = &priv->rss_params;
bdfc028d 1166 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1167 bool hash_changed = false;
bdfc028d 1168 void *in;
2be6967c 1169
2d75b2bc
AS		 1170 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1171 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1172 (hfunc != ETH_RSS_HASH_TOP))
1173 return -EINVAL;
1174
1b9a07ee 1175 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1176 if (!in)
1177 return -ENOMEM;
1178
2be6967c
SM		 1179 mutex_lock(&priv->state_lock);
1180
bbeb53b8
AL		 1181 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1182 rss->hfunc = hfunc;
1d3398fa
GP		 1183 hash_changed = true;
1184 }
1185
a5f97fee 1186 if (indir) {
bbeb53b8
AL		 1187 memcpy(rss->indirection_rqt, indir,
1188 sizeof(rss->indirection_rqt));
a5f97fee
SM		 1189
1190 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1191 u32 rqtn = priv->indir_rqt.rqtn;
1192 struct mlx5e_redirect_rqt_param rrp = {
1193 .is_rss = true,
e270e966
AM		 1194 {
1195 .rss = {
bbeb53b8 1196 .hfunc = rss->hfunc,
e270e966
AM		 1197 .channels = &priv->channels,
1198 },
1199 },
a5f97fee
SM		 1200 };
1201
1202 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1203 }
1204 }
1205
1d3398fa 1206 if (key) {
bbeb53b8
AL		 1207 memcpy(rss->toeplitz_hash_key, key,
1208 sizeof(rss->toeplitz_hash_key));
1209 hash_changed = hash_changed || rss->hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1210 }
2d75b2bc 1211
1d3398fa
GP		 1212 if (hash_changed)
1213 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1214
2be6967c
SM		 1215 mutex_unlock(&priv->state_lock);
1216
bdfc028d
TT		 1217 kvfree(in);
1218
1219 return 0;
2be6967c
SM		 1220}
1221
2afa609f
IK		 1222#define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1223#define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1224#define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1225#define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1226#define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1227 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1228 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1229
1230static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1231 u16 *pfc_prevention_tout)
1232{
1233 struct mlx5e_priv *priv = netdev_priv(netdev);
1234 struct mlx5_core_dev *mdev = priv->mdev;
1235
1236 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1237 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1238 return -EOPNOTSUPP;
1239
1240 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1241}
1242
1243static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1244 u16 pfc_preven)
1245{
1246 struct mlx5e_priv *priv = netdev_priv(netdev);
1247 struct mlx5_core_dev *mdev = priv->mdev;
1248 u16 critical_tout;
1249 u16 minor;
1250
1251 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1252 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1253 return -EOPNOTSUPP;
1254
1255 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1256 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1257 pfc_preven;
1258
1259 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1260 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1261 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1262 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1263 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1264 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1265 return -EINVAL;
1266 }
1267
1268 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1269 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1270 minor);
1271}
1272
58d52291
AS		 1273static int mlx5e_get_tunable(struct net_device *dev,
1274 const struct ethtool_tunable *tuna,
1275 void *data)
1276{
c4554fbc 1277 int err;
58d52291
AS		 1278
1279 switch (tuna->id) {
2afa609f
IK		 1280 case ETHTOOL_PFC_PREVENTION_TOUT:
1281 err = mlx5e_get_pfc_prevention_tout(dev, data);
1282 break;
58d52291
AS		 1283 default:
1284 err = -EINVAL;
1285 break;
1286 }
1287
1288 return err;
1289}
1290
1291static int mlx5e_set_tunable(struct net_device *dev,
1292 const struct ethtool_tunable *tuna,
1293 const void *data)
1294{
1295 struct mlx5e_priv *priv = netdev_priv(dev);
c4554fbc 1296 int err;
546f18ed
SM		 1297
1298 mutex_lock(&priv->state_lock);
58d52291
AS		 1299
1300 switch (tuna->id) {
2afa609f
IK		 1301 case ETHTOOL_PFC_PREVENTION_TOUT:
1302 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
58d52291
AS		 1303 break;
1304 default:
1305 err = -EINVAL;
1306 break;
1307 }
1308
546f18ed 1309 mutex_unlock(&priv->state_lock);
58d52291
AS		 1310 return err;
1311}
1312
371289b6
OG		 1313void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1314 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1315{
3c2d18ef
AS		 1316 struct mlx5_core_dev *mdev = priv->mdev;
1317 int err;
1318
1319 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1320 &pauseparam->tx_pause);
1321 if (err) {
371289b6 1322 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
3c2d18ef
AS		 1323 __func__, err);
1324 }
1325}
1326
371289b6
OG		 1327static void mlx5e_get_pauseparam(struct net_device *netdev,
1328 struct ethtool_pauseparam *pauseparam)
1329{
1330 struct mlx5e_priv *priv = netdev_priv(netdev);
1331
1332 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1333}
1334
1335int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1336 struct ethtool_pauseparam *pauseparam)
3c2d18ef 1337{
3c2d18ef
AS		 1338 struct mlx5_core_dev *mdev = priv->mdev;
1339 int err;
1340
1341 if (pauseparam->autoneg)
1342 return -EINVAL;
1343
1344 err = mlx5_set_port_pause(mdev,
1345 pauseparam->rx_pause ? 1 : 0,
1346 pauseparam->tx_pause ? 1 : 0);
1347 if (err) {
371289b6 1348 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
3c2d18ef
AS		 1349 __func__, err);
1350 }
1351
1352 return err;
1353}
1354
371289b6
OG		 1355static int mlx5e_set_pauseparam(struct net_device *netdev,
1356 struct ethtool_pauseparam *pauseparam)
1357{
1358 struct mlx5e_priv *priv = netdev_priv(netdev);
1359
1360 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1361}
1362
3844b07e
FD		 1363int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1364 struct ethtool_ts_info *info)
ef9814de 1365{
7c39afb3 1366 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de 1367
6dbc80ca 1368 info->phc_index = mlx5_clock_get_ptp_index(mdev);
ef9814de 1369
6dbc80ca
MS		 1370 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1371 info->phc_index == -1)
ef9814de
EBE		 1372 return 0;
1373
47654204
AH		 1374 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1375 SOF_TIMESTAMPING_RX_HARDWARE |
1376 SOF_TIMESTAMPING_RAW_HARDWARE;
ef9814de 1377
f0b38117
MD		 1378 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1379 BIT(HWTSTAMP_TX_ON);
ef9814de 1380
f0b38117
MD		 1381 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1382 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1383
1384 return 0;
1385}
1386
3844b07e
FD		 1387static int mlx5e_get_ts_info(struct net_device *dev,
1388 struct ethtool_ts_info *info)
1389{
1390 struct mlx5e_priv *priv = netdev_priv(dev);
1391
1392 return mlx5e_ethtool_get_ts_info(priv, info);
1393}
1394
928cfe87
TT		 1395static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1396{
1397 __u32 ret = 0;
1398
1399 if (MLX5_CAP_GEN(mdev, wol_g))
1400 ret |= WAKE_MAGIC;
1401
1402 if (MLX5_CAP_GEN(mdev, wol_s))
1403 ret |= WAKE_MAGICSECURE;
1404
1405 if (MLX5_CAP_GEN(mdev, wol_a))
1406 ret |= WAKE_ARP;
1407
1408 if (MLX5_CAP_GEN(mdev, wol_b))
1409 ret |= WAKE_BCAST;
1410
1411 if (MLX5_CAP_GEN(mdev, wol_m))
1412 ret |= WAKE_MCAST;
1413
1414 if (MLX5_CAP_GEN(mdev, wol_u))
1415 ret |= WAKE_UCAST;
1416
1417 if (MLX5_CAP_GEN(mdev, wol_p))
1418 ret |= WAKE_PHY;
1419
1420 return ret;
1421}
1422
1423static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1424{
1425 __u32 ret = 0;
1426
1427 if (mode & MLX5_WOL_MAGIC)
1428 ret |= WAKE_MAGIC;
1429
1430 if (mode & MLX5_WOL_SECURED_MAGIC)
1431 ret |= WAKE_MAGICSECURE;
1432
1433 if (mode & MLX5_WOL_ARP)
1434 ret |= WAKE_ARP;
1435
1436 if (mode & MLX5_WOL_BROADCAST)
1437 ret |= WAKE_BCAST;
1438
1439 if (mode & MLX5_WOL_MULTICAST)
1440 ret |= WAKE_MCAST;
1441
1442 if (mode & MLX5_WOL_UNICAST)
1443 ret |= WAKE_UCAST;
1444
1445 if (mode & MLX5_WOL_PHY_ACTIVITY)
1446 ret |= WAKE_PHY;
1447
1448 return ret;
1449}
1450
1451static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1452{
1453 u8 ret = 0;
1454
1455 if (mode & WAKE_MAGIC)
1456 ret |= MLX5_WOL_MAGIC;
1457
1458 if (mode & WAKE_MAGICSECURE)
1459 ret |= MLX5_WOL_SECURED_MAGIC;
1460
1461 if (mode & WAKE_ARP)
1462 ret |= MLX5_WOL_ARP;
1463
1464 if (mode & WAKE_BCAST)
1465 ret |= MLX5_WOL_BROADCAST;
1466
1467 if (mode & WAKE_MCAST)
1468 ret |= MLX5_WOL_MULTICAST;
1469
1470 if (mode & WAKE_UCAST)
1471 ret |= MLX5_WOL_UNICAST;
1472
1473 if (mode & WAKE_PHY)
1474 ret |= MLX5_WOL_PHY_ACTIVITY;
1475
1476 return ret;
1477}
1478
1479static void mlx5e_get_wol(struct net_device *netdev,
1480 struct ethtool_wolinfo *wol)
1481{
1482 struct mlx5e_priv *priv = netdev_priv(netdev);
1483 struct mlx5_core_dev *mdev = priv->mdev;
1484 u8 mlx5_wol_mode;
1485 int err;
1486
1487 memset(wol, 0, sizeof(*wol));
1488
1489 wol->supported = mlx5e_get_wol_supported(mdev);
1490 if (!wol->supported)
1491 return;
1492
1493 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1494 if (err)
1495 return;
1496
1497 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1498}
1499
1500static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1501{
1502 struct mlx5e_priv *priv = netdev_priv(netdev);
1503 struct mlx5_core_dev *mdev = priv->mdev;
1504 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1505 u32 mlx5_wol_mode;
1506
1507 if (!wol_supported)
9eb78923 1508 return -EOPNOTSUPP;
928cfe87
TT		 1509
1510 if (wol->wolopts & ~wol_supported)
1511 return -EINVAL;
1512
1513 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1514
1515 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1516}
1517
6cfa9460
SA		 1518static int mlx5e_get_fecparam(struct net_device *netdev,
1519 struct ethtool_fecparam *fecparam)
1520{
1521 struct mlx5e_priv *priv = netdev_priv(netdev);
1522 struct mlx5_core_dev *mdev = priv->mdev;
1523 u8 fec_configured = 0;
1524 u32 fec_active = 0;
1525 int err;
1526
1527 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1528
1529 if (err)
1530 return err;
1531
1532 fecparam->active_fec = pplm2ethtool_fec((u_long)fec_active,
1533 sizeof(u32) * BITS_PER_BYTE);
1534
1535 if (!fecparam->active_fec)
1536 return -EOPNOTSUPP;
1537
1538 fecparam->fec = pplm2ethtool_fec((u_long)fec_configured,
1539 sizeof(u8) * BITS_PER_BYTE);
1540
1541 return 0;
1542}
1543
1544static int mlx5e_set_fecparam(struct net_device *netdev,
1545 struct ethtool_fecparam *fecparam)
1546{
1547 struct mlx5e_priv *priv = netdev_priv(netdev);
1548 struct mlx5_core_dev *mdev = priv->mdev;
1549 u8 fec_policy = 0;
1550 int mode;
1551 int err;
1552
1553 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1554 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1555 continue;
1556 fec_policy |= (1 << mode);
1557 break;
1558 }
1559
1560 err = mlx5e_set_fec_mode(mdev, fec_policy);
1561
1562 if (err)
1563 return err;
1564
1565 mlx5_toggle_port_link(mdev);
1566
1567 return 0;
1568}
1569
79c48764
GP		 1570static u32 mlx5e_get_msglevel(struct net_device *dev)
1571{
1572 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1573}
1574
1575static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1576{
1577 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1578}
1579
da54d24e
GP		 1580static int mlx5e_set_phys_id(struct net_device *dev,
1581 enum ethtool_phys_id_state state)
1582{
1583 struct mlx5e_priv *priv = netdev_priv(dev);
1584 struct mlx5_core_dev *mdev = priv->mdev;
1585 u16 beacon_duration;
1586
1587 if (!MLX5_CAP_GEN(mdev, beacon_led))
1588 return -EOPNOTSUPP;
1589
1590 switch (state) {
1591 case ETHTOOL_ID_ACTIVE:
1592 beacon_duration = MLX5_BEACON_DURATION_INF;
1593 break;
1594 case ETHTOOL_ID_INACTIVE:
1595 beacon_duration = MLX5_BEACON_DURATION_OFF;
1596 break;
1597 default:
1598 return -EOPNOTSUPP;
1599 }
1600
1601 return mlx5_set_port_beacon(mdev, beacon_duration);
1602}
1603
bb64143e
GP		 1604static int mlx5e_get_module_info(struct net_device *netdev,
1605 struct ethtool_modinfo *modinfo)
1606{
1607 struct mlx5e_priv *priv = netdev_priv(netdev);
1608 struct mlx5_core_dev *dev = priv->mdev;
1609 int size_read = 0;
a708fb7b 1610 u8 data[4] = {0};
bb64143e
GP		 1611
1612 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1613 if (size_read < 2)
1614 return -EIO;
1615
1616 /* data[0] = identifier byte */
1617 switch (data[0]) {
1618 case MLX5_MODULE_ID_QSFP:
1619 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1620 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1621 break;
1622 case MLX5_MODULE_ID_QSFP_PLUS:
1623 case MLX5_MODULE_ID_QSFP28:
1624 /* data[1] = revision id */
1625 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1626 modinfo->type = ETH_MODULE_SFF_8636;
a708fb7b 1627 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
bb64143e
GP		 1628 } else {
1629 modinfo->type = ETH_MODULE_SFF_8436;
a708fb7b 1630 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
bb64143e
GP		 1631 }
1632 break;
1633 case MLX5_MODULE_ID_SFP:
1634 modinfo->type = ETH_MODULE_SFF_8472;
ace329f4 1635 modinfo->eeprom_len = MLX5_EEPROM_PAGE_LENGTH;
bb64143e
GP		 1636 break;
1637 default:
1638 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1639 __func__, data[0]);
1640 return -EINVAL;
1641 }
1642
1643 return 0;
1644}
1645
1646static int mlx5e_get_module_eeprom(struct net_device *netdev,
1647 struct ethtool_eeprom *ee,
1648 u8 *data)
1649{
1650 struct mlx5e_priv *priv = netdev_priv(netdev);
1651 struct mlx5_core_dev *mdev = priv->mdev;
1652 int offset = ee->offset;
1653 int size_read;
1654 int i = 0;
1655
1656 if (!ee->len)
1657 return -EINVAL;
1658
1659 memset(data, 0, ee->len);
1660
1661 while (i < ee->len) {
1662 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1663 data + i);
1664
1665 if (!size_read)
1666 /* Done reading */
1667 return 0;
1668
1669 if (size_read < 0) {
1670 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1671 __func__, size_read);
1672 return 0;
1673 }
1674
1675 i += size_read;
1676 offset += size_read;
1677 }
1678
1679 return 0;
1680}
1681
0088cbbc
TG		 1682static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1683 bool is_rx_cq)
4e59e288 1684{
9908aa29
TT		 1685 struct mlx5e_priv *priv = netdev_priv(netdev);
1686 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1687 struct mlx5e_channels new_channels = {};
0088cbbc
TG		 1688 bool mode_changed;
1689 u8 cq_period_mode, current_cq_period_mode;
9908aa29 1690
0088cbbc 1691 cq_period_mode = enable ?
9908aa29
TT		 1692 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1693 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
0088cbbc
TG		 1694 current_cq_period_mode = is_rx_cq ?
1695 priv->channels.params.rx_cq_moderation.cq_period_mode :
1696 priv->channels.params.tx_cq_moderation.cq_period_mode;
1697 mode_changed = cq_period_mode != current_cq_period_mode;
9908aa29 1698
0088cbbc 1699 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
9908aa29 1700 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1701 return -EOPNOTSUPP;
9908aa29 1702
0088cbbc 1703 if (!mode_changed)
9908aa29
TT		 1704 return 0;
1705
be7e87f9 1706 new_channels.params = priv->channels.params;
0088cbbc
TG		 1707 if (is_rx_cq)
1708 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1709 else
1710 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
9908aa29 1711
be7e87f9
SM		 1712 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1713 priv->channels.params = new_channels.params;
1714 return 0;
1715 }
1716
877662e2 1717 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9 1718}
9908aa29 1719
0088cbbc
TG		 1720static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1721{
1722 return set_pflag_cqe_based_moder(netdev, enable, false);
1723}
1724
1725static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1726{
1727 return set_pflag_cqe_based_moder(netdev, enable, true);
1728}
1729
be7e87f9
SM		 1730int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1731{
1732 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1733 struct mlx5e_channels new_channels = {};
1734 int err = 0;
1735
1736 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1737 return new_val ? -EOPNOTSUPP : 0;
1738
1739 if (curr_val == new_val)
1740 return 0;
1741
1742 new_channels.params = priv->channels.params;
1743 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1744
be7e87f9
SM		 1745 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1746 priv->channels.params = new_channels.params;
1747 return 0;
1748 }
1749
877662e2 1750 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1751 if (err)
1752 return err;
1753
696a97cf
EE		 1754 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1755 MLX5E_GET_PFLAG(&priv->channels.params,
1756 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1757
be7e87f9 1758 return 0;
4e59e288
GP		 1759}
1760
9bcc8606
SD		 1761static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1762 bool enable)
1763{
1764 struct mlx5e_priv *priv = netdev_priv(netdev);
1765 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1766
1767 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1768 return -EOPNOTSUPP;
9bcc8606 1769
7c39afb3 1770 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1771 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1772 return -EINVAL;
1773 }
1774
5eb0249b 1775 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1776 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1777
5eb0249b 1778 return 0;
9bcc8606
SD		 1779}
1780
2ccb0a79
TT		 1781static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1782{
1783 struct mlx5e_priv *priv = netdev_priv(netdev);
1784 struct mlx5_core_dev *mdev = priv->mdev;
1785 struct mlx5e_channels new_channels = {};
2ccb0a79
TT		 1786
1787 if (enable) {
1788 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1789 return -EOPNOTSUPP;
1790 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1791 return -EINVAL;
6c3a823e
TT		 1792 } else if (priv->channels.params.lro_en) {
1793 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1794 return -EINVAL;
2ccb0a79
TT		 1795 }
1796
1797 new_channels.params = priv->channels.params;
1798
1799 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1800 mlx5e_set_rq_type(mdev, &new_channels.params);
1801
1802 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1803 priv->channels.params = new_channels.params;
1804 return 0;
1805 }
1806
877662e2 1807 return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2ccb0a79
TT		 1808}
1809
b856df28
OG		 1810static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1811{
1812 struct mlx5e_priv *priv = netdev_priv(netdev);
1813 struct mlx5e_channels *channels = &priv->channels;
1814 struct mlx5e_channel *c;
1815 int i;
1816
5d0bb3ba
SM		 1817 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1818 priv->channels.params.xdp_prog)
b856df28
OG		 1819 return 0;
1820
1821 for (i = 0; i < channels->num; i++) {
1822 c = channels->c[i];
1823 if (enable)
1824 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1825 else
1826 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1827 }
1828
1829 return 0;
1830}
1831
6277053a
TT		 1832static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1833{
1834 struct mlx5e_priv *priv = netdev_priv(netdev);
1835 struct mlx5_core_dev *mdev = priv->mdev;
1836 struct mlx5e_channels new_channels = {};
1837 int err;
1838
1839 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1840 return -EOPNOTSUPP;
1841
1842 new_channels.params = priv->channels.params;
1843
1844 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1845
1846 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1847 priv->channels.params = new_channels.params;
1848 return 0;
1849 }
1850
877662e2
TT		 1851 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
1852 return err;
6277053a
TT		 1853}
1854
8ff57c18
TT		 1855static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1856 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1857 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1858 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1859 { "rx_striding_rq", set_pflag_rx_striding_rq },
1860 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
6277053a 1861 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
8ff57c18
TT		 1862};
1863
4e59e288
GP		 1864static int mlx5e_handle_pflag(struct net_device *netdev,
1865 u32 wanted_flags,
8ff57c18 1866 enum mlx5e_priv_flag flag)
4e59e288
GP		 1867{
1868 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1869 bool enable = !!(wanted_flags & BIT(flag));
6a9764ef 1870 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1871 int err;
1872
8ff57c18 1873 if (!(changes & BIT(flag)))
4e59e288
GP		 1874 return 0;
1875
8ff57c18 1876 err = mlx5e_priv_flags[flag].handler(netdev, enable);
4e59e288 1877 if (err) {
8ff57c18
TT		 1878 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1879 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
4e59e288
GP		 1880 return err;
1881 }
1882
6a9764ef 1883 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1884 return 0;
1885}
1886
1887static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1888{
1889 struct mlx5e_priv *priv = netdev_priv(netdev);
8ff57c18 1890 enum mlx5e_priv_flag pflag;
4e59e288
GP		 1891 int err;
1892
1893 mutex_lock(&priv->state_lock);
2ccb0a79 1894
8ff57c18
TT		 1895 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1896 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1897 if (err)
1898 break;
1899 }
9bcc8606 1900
4e59e288 1901 mutex_unlock(&priv->state_lock);
6c3a823e
TT		 1902
1903 /* Need to fix some features.. */
1904 netdev_update_features(netdev);
1905
9bcc8606 1906 return err;
4e59e288
GP		 1907}
1908
1909static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1910{
1911 struct mlx5e_priv *priv = netdev_priv(netdev);
1912
6a9764ef 1913 return priv->channels.params.pflags;
4e59e288
GP		 1914}
1915
8f0916c6
SM		 1916#ifndef CONFIG_MLX5_EN_RXNFC
1917/* When CONFIG_MLX5_EN_RXNFC=n we only support ETHTOOL_GRXRINGS
1918 * otherwise this function will be defined from en_fs_ethtool.c
1919 */
1920static int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, u32 *rule_locs)
1921{
1922 struct mlx5e_priv *priv = netdev_priv(dev);
1923
1924 if (info->cmd != ETHTOOL_GRXRINGS)
1925 return -EOPNOTSUPP;
1926 /* ring_count is needed by ethtool -x */
1927 info->data = priv->channels.params.num_channels;
1928 return 0;
1929}
1930#endif
1931
f62b8bb8
AV		 1932const struct ethtool_ops mlx5e_ethtool_ops = {
1933 .get_drvinfo = mlx5e_get_drvinfo,
1934 .get_link = ethtool_op_get_link,
1935 .get_strings = mlx5e_get_strings,
1936 .get_sset_count = mlx5e_get_sset_count,
1937 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1938 .get_ringparam = mlx5e_get_ringparam,
1939 .set_ringparam = mlx5e_set_ringparam,
1940 .get_channels = mlx5e_get_channels,
1941 .set_channels = mlx5e_set_channels,
1942 .get_coalesce = mlx5e_get_coalesce,
1943 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1944 .get_link_ksettings = mlx5e_get_link_ksettings,
1945 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1946 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1947 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1948 .get_rxfh = mlx5e_get_rxfh,
1949 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1950 .get_rxnfc = mlx5e_get_rxnfc,
8f0916c6 1951#ifdef CONFIG_MLX5_EN_RXNFC
6dc6071c 1952 .set_rxnfc = mlx5e_set_rxnfc,
fe6d86b3 1953#endif
58d52291
AS		 1954 .get_tunable = mlx5e_get_tunable,
1955 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1956 .get_pauseparam = mlx5e_get_pauseparam,
1957 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1958 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1959 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1960 .get_wol = mlx5e_get_wol,
1961 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1962 .get_module_info = mlx5e_get_module_info,
1963 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1964 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1965 .set_priv_flags = mlx5e_set_priv_flags,
1966 .self_test = mlx5e_self_test,
79c48764
GP		 1967 .get_msglevel = mlx5e_get_msglevel,
1968 .set_msglevel = mlx5e_set_msglevel,
6cfa9460
SA		 1969 .get_fecparam = mlx5e_get_fecparam,
1970 .set_fecparam = mlx5e_set_fecparam,
f62b8bb8 1971};
A mirror of Linus' kernel repository