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net: myri10ge: fix memory leaks
[thirdparty/linux.git] / drivers / net / ethernet / myricom / myri10ge / myri10ge.c
CommitLineData
0da34b6d
BG		 1/*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
3bea1237 4 * Copyright (C) 2005 - 2011 Myricom, Inc.
0da34b6d
BG		 5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
4a2e612a
BG		 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
0da34b6d 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
4a2e612a
BG		 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
0da34b6d
BG		 30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
78ca90ea
JP		 41#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
42
0da34b6d
BG		 43#include <linux/tcp.h>
44#include <linux/netdevice.h>
45#include <linux/skbuff.h>
46#include <linux/string.h>
47#include <linux/module.h>
48#include <linux/pci.h>
b10c0668 49#include <linux/dma-mapping.h>
0da34b6d
BG		 50#include <linux/etherdevice.h>
51#include <linux/if_ether.h>
52#include <linux/if_vlan.h>
981813d8 53#include <linux/dca.h>
0da34b6d
BG		 54#include <linux/ip.h>
55#include <linux/inet.h>
56#include <linux/in.h>
57#include <linux/ethtool.h>
58#include <linux/firmware.h>
59#include <linux/delay.h>
0da34b6d
BG		 60#include <linux/timer.h>
61#include <linux/vmalloc.h>
62#include <linux/crc32.h>
63#include <linux/moduleparam.h>
64#include <linux/io.h>
199126a2 65#include <linux/log2.h>
5a0e3ad6 66#include <linux/slab.h>
70c71606 67#include <linux/prefetch.h>
0da34b6d 68#include <net/checksum.h>
1e6e9342
AG		 69#include <net/ip.h>
70#include <net/tcp.h>
0da34b6d 71#include <asm/byteorder.h>
0da34b6d 72#include <asm/processor.h>
0da34b6d
BG		 73
74#include "myri10ge_mcp.h"
75#include "myri10ge_mcp_gen_header.h"
76
3bea1237 77#define MYRI10GE_VERSION_STR "1.5.3-1.534"
0da34b6d
BG		 78
79MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
80MODULE_AUTHOR("Maintainer: help@myri.com");
81MODULE_VERSION(MYRI10GE_VERSION_STR);
82MODULE_LICENSE("Dual BSD/GPL");
83
84#define MYRI10GE_MAX_ETHER_MTU 9014
85
86#define MYRI10GE_ETH_STOPPED 0
87#define MYRI10GE_ETH_STOPPING 1
88#define MYRI10GE_ETH_STARTING 2
89#define MYRI10GE_ETH_RUNNING 3
90#define MYRI10GE_ETH_OPEN_FAILED 4
91
92#define MYRI10GE_EEPROM_STRINGS_SIZE 256
93#define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
94
40f6cff5 95#define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
0da34b6d
BG		 96#define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
97
dd50f336
BG		 98#define MYRI10GE_ALLOC_ORDER 0
99#define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
100#define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
101
236bb5e6
BG		 102#define MYRI10GE_MAX_SLICES 32
103
0da34b6d 104struct myri10ge_rx_buffer_state {
dd50f336
BG		 105 struct page *page;
106 int page_offset;
c755b4b6
FT		 107 DEFINE_DMA_UNMAP_ADDR(bus);
108 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 109};
110
111struct myri10ge_tx_buffer_state {
112 struct sk_buff *skb;
113 int last;
c755b4b6
FT		 114 DEFINE_DMA_UNMAP_ADDR(bus);
115 DEFINE_DMA_UNMAP_LEN(len);
0da34b6d
BG		 116};
117
118struct myri10ge_cmd {
119 u32 data0;
120 u32 data1;
121 u32 data2;
122};
123
124struct myri10ge_rx_buf {
125 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
0da34b6d
BG		 126 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
127 struct myri10ge_rx_buffer_state *info;
dd50f336
BG		 128 struct page *page;
129 dma_addr_t bus;
130 int page_offset;
0da34b6d 131 int cnt;
dd50f336 132 int fill_cnt;
0da34b6d
BG		 133 int alloc_fail;
134 int mask; /* number of rx slots -1 */
dd50f336 135 int watchdog_needed;
0da34b6d
BG		 136};
137
138struct myri10ge_tx_buf {
139 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
236bb5e6
BG		 140 __be32 __iomem *send_go; /* "go" doorbell ptr */
141 __be32 __iomem *send_stop; /* "stop" doorbell ptr */
0da34b6d
BG		 142 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
143 char *req_bytes;
144 struct myri10ge_tx_buffer_state *info;
145 int mask; /* number of transmit slots -1 */
0da34b6d
BG		 146 int req ____cacheline_aligned; /* transmit slots submitted */
147 int pkt_start; /* packets started */
b53bef84
BG		 148 int stop_queue;
149 int linearized;
0da34b6d
BG		 150 int done ____cacheline_aligned; /* transmit slots completed */
151 int pkt_done; /* packets completed */
b53bef84 152 int wake_queue;
236bb5e6 153 int queue_active;
0da34b6d
BG		 154};
155
156struct myri10ge_rx_done {
157 struct mcp_slot *entry;
158 dma_addr_t bus;
159 int cnt;
160 int idx;
161};
162
b53bef84
BG		 163struct myri10ge_slice_netstats {
164 unsigned long rx_packets;
165 unsigned long tx_packets;
166 unsigned long rx_bytes;
167 unsigned long tx_bytes;
168 unsigned long rx_dropped;
169 unsigned long tx_dropped;
170};
171
172struct myri10ge_slice_state {
0da34b6d
BG		 173 struct myri10ge_tx_buf tx; /* transmit ring */
174 struct myri10ge_rx_buf rx_small;
175 struct myri10ge_rx_buf rx_big;
176 struct myri10ge_rx_done rx_done;
b53bef84
BG		 177 struct net_device *dev;
178 struct napi_struct napi;
179 struct myri10ge_priv *mgp;
180 struct myri10ge_slice_netstats stats;
181 __be32 __iomem *irq_claim;
182 struct mcp_irq_data *fw_stats;
183 dma_addr_t fw_stats_bus;
184 int watchdog_tx_done;
185 int watchdog_tx_req;
d0234215 186 int watchdog_rx_done;
c689b81b 187 int stuck;
5dd2d332 188#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 189 int cached_dca_tag;
190 int cpu;
191 __be32 __iomem *dca_tag;
192#endif
0dcffac1 193 char irq_desc[32];
b53bef84
BG		 194};
195
196struct myri10ge_priv {
0dcffac1 197 struct myri10ge_slice_state *ss;
b53bef84 198 int tx_boundary; /* boundary transmits cannot cross */
0dcffac1 199 int num_slices;
b53bef84 200 int running; /* running? */
0da34b6d 201 int small_bytes;
dd50f336 202 int big_bytes;
fa0a90d9 203 int max_intr_slots;
0da34b6d 204 struct net_device *dev;
0da34b6d
BG		 205 u8 __iomem *sram;
206 int sram_size;
207 unsigned long board_span;
208 unsigned long iomem_base;
40f6cff5 209 __be32 __iomem *irq_deassert;
0da34b6d
BG		 210 char *mac_addr_string;
211 struct mcp_cmd_response *cmd;
212 dma_addr_t cmd_bus;
0da34b6d
BG		 213 struct pci_dev *pdev;
214 int msi_enabled;
0dcffac1
BG		 215 int msix_enabled;
216 struct msix_entry *msix_vectors;
5dd2d332 217#ifdef CONFIG_MYRI10GE_DCA
981813d8 218 int dca_enabled;
ef09aadf 219 int relaxed_order;
981813d8 220#endif
66341fff 221 u32 link_state;
0da34b6d
BG		 222 unsigned int rdma_tags_available;
223 int intr_coal_delay;
40f6cff5 224 __be32 __iomem *intr_coal_delay_ptr;
e4b6c303 225 int wc_cookie;
0da34b6d
BG		 226 int down_cnt;
227 wait_queue_head_t down_wq;
228 struct work_struct watchdog_work;
229 struct timer_list watchdog_timer;
0da34b6d 230 int watchdog_resets;
b53bef84 231 int watchdog_pause;
0da34b6d 232 int pause;
7d351035 233 bool fw_name_allocated;
0da34b6d
BG		 234 char *fw_name;
235 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
c0bf8801 236 char *product_code_string;
0da34b6d 237 char fw_version[128];
9dc6f0e7
BG		 238 int fw_ver_major;
239 int fw_ver_minor;
240 int fw_ver_tiny;
241 int adopted_rx_filter_bug;
1409a932 242 u8 mac_addr[ETH_ALEN]; /* eeprom mac address */
0da34b6d
BG		 243 unsigned long serial_number;
244 int vendor_specific_offset;
85a7ea1b 245 int fw_multicast_support;
04ed3e74 246 u32 features;
4f93fde0 247 u32 max_tso6;
0da34b6d
BG		 248 u32 read_dma;
249 u32 write_dma;
250 u32 read_write_dma;
c58ac5ca
BG		 251 u32 link_changes;
252 u32 msg_enable;
2d90b0aa 253 unsigned int board_number;
d0234215 254 int rebooted;
0da34b6d
BG		 255};
256
257static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
258static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
0dcffac1
BG		 259static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
260static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
b9721d5a
BH		 261MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
262MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
263MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
264MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
0da34b6d 265
b51d23e4 266/* Careful: must be accessed under kernel_param_lock() */
0da34b6d 267static char *myri10ge_fw_name = NULL;
d3757ba4 268module_param(myri10ge_fw_name, charp, 0644);
d1ce3a0f 269MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
0da34b6d 270
2d90b0aa
BG		 271#define MYRI10GE_MAX_BOARDS 8
272static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
7fe624f5 273 {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
2d90b0aa
BG		 274module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
275 0444);
1a61a8f1 276MODULE_PARM_DESC(myri10ge_fw_names, "Firmware image names per board");
2d90b0aa 277
0da34b6d 278static int myri10ge_ecrc_enable = 1;
d3757ba4 279module_param(myri10ge_ecrc_enable, int, 0444);
d1ce3a0f 280MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
0da34b6d 281
0da34b6d 282static int myri10ge_small_bytes = -1; /* -1 == auto */
d3757ba4 283module_param(myri10ge_small_bytes, int, 0644);
d1ce3a0f 284MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
0da34b6d
BG		 285
286static int myri10ge_msi = 1; /* enable msi by default */
d3757ba4 287module_param(myri10ge_msi, int, 0644);
d1ce3a0f 288MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
0da34b6d 289
f761fae1 290static int myri10ge_intr_coal_delay = 75;
d3757ba4 291module_param(myri10ge_intr_coal_delay, int, 0444);
d1ce3a0f 292MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
0da34b6d
BG		 293
294static int myri10ge_flow_control = 1;
d3757ba4 295module_param(myri10ge_flow_control, int, 0444);
d1ce3a0f 296MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
0da34b6d
BG		 297
298static int myri10ge_deassert_wait = 1;
d3757ba4 299module_param(myri10ge_deassert_wait, int, 0644);
0da34b6d 300MODULE_PARM_DESC(myri10ge_deassert_wait,
d1ce3a0f 301 "Wait when deasserting legacy interrupts");
0da34b6d
BG		 302
303static int myri10ge_force_firmware = 0;
d3757ba4 304module_param(myri10ge_force_firmware, int, 0444);
0da34b6d 305MODULE_PARM_DESC(myri10ge_force_firmware,
d1ce3a0f 306 "Force firmware to assume aligned completions");
0da34b6d 307
0da34b6d 308static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
d3757ba4 309module_param(myri10ge_initial_mtu, int, 0444);
d1ce3a0f 310MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
0da34b6d
BG		 311
312static int myri10ge_napi_weight = 64;
d3757ba4 313module_param(myri10ge_napi_weight, int, 0444);
d1ce3a0f 314MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
0da34b6d
BG		 315
316static int myri10ge_watchdog_timeout = 1;
d3757ba4 317module_param(myri10ge_watchdog_timeout, int, 0444);
d1ce3a0f 318MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
0da34b6d
BG		 319
320static int myri10ge_max_irq_loops = 1048576;
d3757ba4 321module_param(myri10ge_max_irq_loops, int, 0444);
0da34b6d 322MODULE_PARM_DESC(myri10ge_max_irq_loops,
d1ce3a0f 323 "Set stuck legacy IRQ detection threshold");
0da34b6d 324
c58ac5ca
BG		 325#define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
326
327static int myri10ge_debug = -1; /* defaults above */
328module_param(myri10ge_debug, int, 0);
329MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
330
dd50f336 331static int myri10ge_fill_thresh = 256;
d3757ba4 332module_param(myri10ge_fill_thresh, int, 0644);
d1ce3a0f 333MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
dd50f336 334
f181137f
BG		 335static int myri10ge_reset_recover = 1;
336
0dcffac1 337static int myri10ge_max_slices = 1;
d3757ba4 338module_param(myri10ge_max_slices, int, 0444);
0dcffac1
BG		 339MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
340
4b860abf 341static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
d3757ba4 342module_param(myri10ge_rss_hash, int, 0444);
0dcffac1
BG		 343MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
344
981813d8 345static int myri10ge_dca = 1;
d3757ba4 346module_param(myri10ge_dca, int, 0444);
981813d8
BG		 347MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
348
0da34b6d
BG		 349#define MYRI10GE_FW_OFFSET 1024*1024
350#define MYRI10GE_HIGHPART_TO_U32(X) \
351(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
352#define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
353
354#define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
355
2f76216f 356static void myri10ge_set_multicast_list(struct net_device *dev);
61357325
SH		 357static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
358 struct net_device *dev);
2f76216f 359
6250223e 360static inline void put_be32(__be32 val, __be32 __iomem * p)
40f6cff5 361{
6250223e 362 __raw_writel((__force __u32) val, (__force void __iomem *)p);
40f6cff5
AV		 363}
364
bc1f4470 365static void myri10ge_get_stats(struct net_device *dev,
366 struct rtnl_link_stats64 *stats);
59081825 367
7d351035
RR		 368static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
369{
370 if (mgp->fw_name_allocated)
371 kfree(mgp->fw_name);
372 mgp->fw_name = name;
373 mgp->fw_name_allocated = allocated;
374}
375
0da34b6d
BG		 376static int
377myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
378 struct myri10ge_cmd *data, int atomic)
379{
380 struct mcp_cmd *buf;
381 char buf_bytes[sizeof(*buf) + 8];
382 struct mcp_cmd_response *response = mgp->cmd;
e700f9f4 383 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
0da34b6d
BG		 384 u32 dma_low, dma_high, result, value;
385 int sleep_total = 0;
386
387 /* ensure buf is aligned to 8 bytes */
388 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
389
390 buf->data0 = htonl(data->data0);
391 buf->data1 = htonl(data->data1);
392 buf->data2 = htonl(data->data2);
393 buf->cmd = htonl(cmd);
394 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
395 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
396
397 buf->response_addr.low = htonl(dma_low);
398 buf->response_addr.high = htonl(dma_high);
40f6cff5 399 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 400 mb();
401 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
402
403 /* wait up to 15ms. Longest command is the DMA benchmark,
404 * which is capped at 5ms, but runs from a timeout handler
405 * that runs every 7.8ms. So a 15ms timeout leaves us with
406 * a 2.2ms margin
407 */
408 if (atomic) {
409 /* if atomic is set, do not sleep,
410 * and try to get the completion quickly
411 * (1ms will be enough for those commands) */
412 for (sleep_total = 0;
8e95a202
JP		 413 sleep_total < 1000 &&
414 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
bd2db0cf 415 sleep_total += 10) {
0da34b6d 416 udelay(10);
bd2db0cf
BG		 417 mb();
418 }
0da34b6d
BG		 419 } else {
420 /* use msleep for most command */
421 for (sleep_total = 0;
8e95a202
JP		 422 sleep_total < 15 &&
423 response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
0da34b6d
BG		 424 sleep_total++)
425 msleep(1);
426 }
427
428 result = ntohl(response->result);
429 value = ntohl(response->data);
430 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
431 if (result == 0) {
432 data->data0 = value;
433 return 0;
85a7ea1b
BG		 434 } else if (result == MXGEFW_CMD_UNKNOWN) {
435 return -ENOSYS;
5443e9ea
BG		 436 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
437 return -E2BIG;
236bb5e6
BG		 438 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
439 cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
440 (data->
441 data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
442 0) {
443 return -ERANGE;
0da34b6d
BG		 444 } else {
445 dev_err(&mgp->pdev->dev,
446 "command %d failed, result = %d\n",
447 cmd, result);
448 return -ENXIO;
449 }
450 }
451
452 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
453 cmd, result);
454 return -EAGAIN;
455}
456
457/*
458 * The eeprom strings on the lanaiX have the format
459 * SN=x\0
460 * MAC=x:x:x:x:x:x\0
461 * PT:ddd mmm xx xx:xx:xx xx\0
462 * PV:ddd mmm xx xx:xx:xx xx\0
463 */
464static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
465{
466 char *ptr, *limit;
467 int i;
468
469 ptr = mgp->eeprom_strings;
470 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
471
472 while (*ptr != '\0' && ptr < limit) {
473 if (memcmp(ptr, "MAC=", 4) == 0) {
474 ptr += 4;
475 mgp->mac_addr_string = ptr;
476 for (i = 0; i < 6; i++) {
477 if ((ptr + 2) > limit)
478 goto abort;
479 mgp->mac_addr[i] =
480 simple_strtoul(ptr, &ptr, 16);
481 ptr += 1;
482 }
483 }
c0bf8801
BG		 484 if (memcmp(ptr, "PC=", 3) == 0) {
485 ptr += 3;
486 mgp->product_code_string = ptr;
487 }
0da34b6d
BG		 488 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
489 ptr += 3;
490 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
491 }
492 while (ptr < limit && *ptr++) ;
493 }
494
495 return 0;
496
497abort:
498 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
499 return -ENXIO;
500}
501
502/*
503 * Enable or disable periodic RDMAs from the host to make certain
504 * chipsets resend dropped PCIe messages
505 */
506
507static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
508{
509 char __iomem *submit;
f8fd57c1 510 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 511 u32 dma_low, dma_high;
512 int i;
513
514 /* clear confirmation addr */
515 mgp->cmd->data = 0;
516 mb();
517
518 /* send a rdma command to the PCIe engine, and wait for the
519 * response in the confirmation address. The firmware should
520 * write a -1 there to indicate it is alive and well
521 */
522 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
523 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
524
525 buf[0] = htonl(dma_high); /* confirm addr MSW */
526 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 527 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 528 buf[3] = htonl(dma_high); /* dummy addr MSW */
529 buf[4] = htonl(dma_low); /* dummy addr LSW */
530 buf[5] = htonl(enable); /* enable? */
531
e700f9f4 532 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
0da34b6d
BG		 533
534 myri10ge_pio_copy(submit, &buf, sizeof(buf));
535 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
536 msleep(1);
537 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
538 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
539 (enable ? "enable" : "disable"));
540}
541
542static int
543myri10ge_validate_firmware(struct myri10ge_priv *mgp,
544 struct mcp_gen_header *hdr)
545{
546 struct device *dev = &mgp->pdev->dev;
0da34b6d
BG		 547
548 /* check firmware type */
549 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
550 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
551 return -EINVAL;
552 }
553
554 /* save firmware version for ethtool */
555 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
8dff81e8 556 mgp->fw_version[sizeof(mgp->fw_version) - 1] = '\0';
0da34b6d 557
9dc6f0e7
BG		 558 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
559 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
0da34b6d 560
8e95a202
JP		 561 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
562 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
0da34b6d
BG		 563 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
564 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
565 MXGEFW_VERSION_MINOR);
566 return -EINVAL;
567 }
568 return 0;
569}
570
571static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
572{
573 unsigned crc, reread_crc;
574 const struct firmware *fw;
575 struct device *dev = &mgp->pdev->dev;
b0d31d6b 576 unsigned char *fw_readback;
0da34b6d
BG		 577 struct mcp_gen_header *hdr;
578 size_t hdr_offset;
579 int status;
e454358a 580 unsigned i;
0da34b6d
BG		 581
582 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
583 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
584 mgp->fw_name);
585 status = -EINVAL;
586 goto abort_with_nothing;
587 }
588
589 /* check size */
590
591 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
592 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
593 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
594 status = -EINVAL;
595 goto abort_with_fw;
596 }
597
598 /* check id */
40f6cff5 599 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 600 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
601 dev_err(dev, "Bad firmware file\n");
602 status = -EINVAL;
603 goto abort_with_fw;
604 }
605 hdr = (void *)(fw->data + hdr_offset);
606
607 status = myri10ge_validate_firmware(mgp, hdr);
608 if (status != 0)
609 goto abort_with_fw;
610
611 crc = crc32(~0, fw->data, fw->size);
e454358a
BG		 612 for (i = 0; i < fw->size; i += 256) {
613 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
614 fw->data + i,
615 min(256U, (unsigned)(fw->size - i)));
616 mb();
617 readb(mgp->sram);
b10c0668 618 }
b0d31d6b
DW		 619 fw_readback = vmalloc(fw->size);
620 if (!fw_readback) {
621 status = -ENOMEM;
622 goto abort_with_fw;
623 }
0da34b6d 624 /* corruption checking is good for parity recovery and buggy chipset */
b0d31d6b
DW		 625 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
626 reread_crc = crc32(~0, fw_readback, fw->size);
627 vfree(fw_readback);
0da34b6d
BG		 628 if (crc != reread_crc) {
629 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
630 (unsigned)fw->size, reread_crc, crc);
631 status = -EIO;
632 goto abort_with_fw;
633 }
634 *size = (u32) fw->size;
635
636abort_with_fw:
637 release_firmware(fw);
638
639abort_with_nothing:
640 return status;
641}
642
643static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
644{
645 struct mcp_gen_header *hdr;
646 struct device *dev = &mgp->pdev->dev;
647 const size_t bytes = sizeof(struct mcp_gen_header);
648 size_t hdr_offset;
649 int status;
650
651 /* find running firmware header */
66341fff 652 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
0da34b6d
BG		 653
654 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
655 dev_err(dev, "Running firmware has bad header offset (%d)\n",
656 (int)hdr_offset);
657 return -EIO;
658 }
659
660 /* copy header of running firmware from SRAM to host memory to
661 * validate firmware */
662 hdr = kmalloc(bytes, GFP_KERNEL);
b2adaca9 663 if (hdr == NULL)
0da34b6d 664 return -ENOMEM;
b2adaca9 665
0da34b6d
BG		 666 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
667 status = myri10ge_validate_firmware(mgp, hdr);
668 kfree(hdr);
9dc6f0e7
BG		 669
670 /* check to see if adopted firmware has bug where adopting
671 * it will cause broadcasts to be filtered unless the NIC
672 * is kept in ALLMULTI mode */
673 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
674 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
675 mgp->adopted_rx_filter_bug = 1;
676 dev_warn(dev, "Adopting fw %d.%d.%d: "
677 "working around rx filter bug\n",
678 mgp->fw_ver_major, mgp->fw_ver_minor,
679 mgp->fw_ver_tiny);
680 }
0da34b6d
BG		 681 return status;
682}
683
0178ec3d 684static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
fa0a90d9
BG		 685{
686 struct myri10ge_cmd cmd;
687 int status;
688
689 /* probe for IPv6 TSO support */
690 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
691 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
692 &cmd, 0);
693 if (status == 0) {
694 mgp->max_tso6 = cmd.data0;
695 mgp->features |= NETIF_F_TSO6;
696 }
697
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
699 if (status != 0) {
700 dev_err(&mgp->pdev->dev,
701 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
702 return -ENXIO;
703 }
704
705 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
706
707 return 0;
708}
709
0dcffac1 710static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
0da34b6d
BG		 711{
712 char __iomem *submit;
f8fd57c1 713 __be32 buf[16] __attribute__ ((__aligned__(8)));
0da34b6d
BG		 714 u32 dma_low, dma_high, size;
715 int status, i;
716
b10c0668 717 size = 0;
0da34b6d
BG		 718 status = myri10ge_load_hotplug_firmware(mgp, &size);
719 if (status) {
0dcffac1
BG		 720 if (!adopt)
721 return status;
0da34b6d
BG		 722 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
723
724 /* Do not attempt to adopt firmware if there
725 * was a bad crc */
726 if (status == -EIO)
727 return status;
728
729 status = myri10ge_adopt_running_firmware(mgp);
730 if (status != 0) {
731 dev_err(&mgp->pdev->dev,
732 "failed to adopt running firmware\n");
733 return status;
734 }
735 dev_info(&mgp->pdev->dev,
736 "Successfully adopted running firmware\n");
b53bef84 737 if (mgp->tx_boundary == 4096) {
0da34b6d
BG		 738 dev_warn(&mgp->pdev->dev,
739 "Using firmware currently running on NIC"
740 ". For optimal\n");
741 dev_warn(&mgp->pdev->dev,
742 "performance consider loading optimized "
743 "firmware\n");
744 dev_warn(&mgp->pdev->dev, "via hotplug\n");
745 }
746
7d351035 747 set_fw_name(mgp, "adopted", false);
b53bef84 748 mgp->tx_boundary = 2048;
fa0a90d9
BG		 749 myri10ge_dummy_rdma(mgp, 1);
750 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d
BG		 751 return status;
752 }
753
754 /* clear confirmation addr */
755 mgp->cmd->data = 0;
756 mb();
757
758 /* send a reload command to the bootstrap MCP, and wait for the
759 * response in the confirmation address. The firmware should
760 * write a -1 there to indicate it is alive and well
761 */
762 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
763 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
764
765 buf[0] = htonl(dma_high); /* confirm addr MSW */
766 buf[1] = htonl(dma_low); /* confirm addr LSW */
40f6cff5 767 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
0da34b6d
BG		 768
769 /* FIX: All newest firmware should un-protect the bottom of
770 * the sram before handoff. However, the very first interfaces
771 * do not. Therefore the handoff copy must skip the first 8 bytes
772 */
773 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
774 buf[4] = htonl(size - 8); /* length of code */
775 buf[5] = htonl(8); /* where to copy to */
776 buf[6] = htonl(0); /* where to jump to */
777
e700f9f4 778 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
0da34b6d
BG		 779
780 myri10ge_pio_copy(submit, &buf, sizeof(buf));
781 mb();
782 msleep(1);
783 mb();
784 i = 0;
d93ca2a4
BG		 785 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
786 msleep(1 << i);
0da34b6d
BG		 787 i++;
788 }
789 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
790 dev_err(&mgp->pdev->dev, "handoff failed\n");
791 return -ENXIO;
792 }
9a71db72 793 myri10ge_dummy_rdma(mgp, 1);
fa0a90d9 794 status = myri10ge_get_firmware_capabilities(mgp);
0da34b6d 795
fa0a90d9 796 return status;
0da34b6d
BG		 797}
798
799static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
800{
801 struct myri10ge_cmd cmd;
802 int status;
803
804 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
805 | (addr[2] << 8) | addr[3]);
806
807 cmd.data1 = ((addr[4] << 8) | (addr[5]));
808
809 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
810 return status;
811}
812
813static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
814{
815 struct myri10ge_cmd cmd;
816 int status, ctl;
817
818 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
819 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
820
821 if (status) {
78ca90ea 822 netdev_err(mgp->dev, "Failed to set flow control mode\n");
0da34b6d
BG		 823 return status;
824 }
825 mgp->pause = pause;
826 return 0;
827}
828
829static void
830myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
831{
832 struct myri10ge_cmd cmd;
833 int status, ctl;
834
835 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
836 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
837 if (status)
78ca90ea 838 netdev_err(mgp->dev, "Failed to set promisc mode\n");
0da34b6d
BG		 839}
840
0d6ac257 841static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
0da34b6d
BG		 842{
843 struct myri10ge_cmd cmd;
844 int status;
0da34b6d 845 u32 len;
34fdccea
BG		 846 struct page *dmatest_page;
847 dma_addr_t dmatest_bus;
0d6ac257
BG		 848 char *test = " ";
849
850 dmatest_page = alloc_page(GFP_KERNEL);
851 if (!dmatest_page)
852 return -ENOMEM;
853 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
854 DMA_BIDIRECTIONAL);
10545937
SG		 855 if (unlikely(pci_dma_mapping_error(mgp->pdev, dmatest_bus))) {
856 __free_page(dmatest_page);
857 return -ENOMEM;
858 }
0d6ac257
BG		 859
860 /* Run a small DMA test.
861 * The magic multipliers to the length tell the firmware
862 * to do DMA read, write, or read+write tests. The
863 * results are returned in cmd.data0. The upper 16
864 * bits or the return is the number of transfers completed.
865 * The lower 16 bits is the time in 0.5us ticks that the
866 * transfers took to complete.
867 */
868
b53bef84 869 len = mgp->tx_boundary;
0d6ac257
BG		 870
871 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
872 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
873 cmd.data2 = len * 0x10000;
874 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
875 if (status != 0) {
876 test = "read";
877 goto abort;
878 }
879 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
880 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
881 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
882 cmd.data2 = len * 0x1;
883 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
884 if (status != 0) {
885 test = "write";
886 goto abort;
887 }
888 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
889
890 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
891 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
892 cmd.data2 = len * 0x10001;
893 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
894 if (status != 0) {
895 test = "read/write";
896 goto abort;
897 }
898 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
899 (cmd.data0 & 0xffff);
900
901abort:
902 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
903 put_page(dmatest_page);
904
905 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
906 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
907 test, status);
908
909 return status;
910}
911
912static int myri10ge_reset(struct myri10ge_priv *mgp)
913{
914 struct myri10ge_cmd cmd;
0dcffac1
BG		 915 struct myri10ge_slice_state *ss;
916 int i, status;
0d6ac257 917 size_t bytes;
5dd2d332 918#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 919 unsigned long dca_tag_off;
920#endif
0da34b6d
BG		 921
922 /* try to send a reset command to the card to see if it
923 * is alive */
924 memset(&cmd, 0, sizeof(cmd));
925 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
926 if (status != 0) {
927 dev_err(&mgp->pdev->dev, "failed reset\n");
928 return -ENXIO;
929 }
0d6ac257
BG		 930
931 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
0dcffac1
BG		 932 /*
933 * Use non-ndis mcp_slot (eg, 4 bytes total,
934 * no toeplitz hash value returned. Older firmware will
935 * not understand this command, but will use the correct
936 * sized mcp_slot, so we ignore error returns
937 */
938 cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
939 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
0da34b6d
BG		 940
941 /* Now exchange information about interrupts */
942
0dcffac1 943 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
0da34b6d
BG		 944 cmd.data0 = (u32) bytes;
945 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
0dcffac1
BG		 946
947 /*
948 * Even though we already know how many slices are supported
949 * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
950 * has magic side effects, and must be called after a reset.
951 * It must be called prior to calling any RSS related cmds,
952 * including assigning an interrupt queue for anything but
953 * slice 0. It must also be called *after*
954 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
955 * the firmware to compute offsets.
956 */
957
958 if (mgp->num_slices > 1) {
959
960 /* ask the maximum number of slices it supports */
961 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
962 &cmd, 0);
963 if (status != 0) {
964 dev_err(&mgp->pdev->dev,
965 "failed to get number of slices\n");
966 }
967
968 /*
969 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
970 * to setting up the interrupt queue DMA
971 */
972
973 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 974 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
975 if (mgp->dev->real_num_tx_queues > 1)
976 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 977 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
978 &cmd, 0);
236bb5e6
BG		 979
980 /* Firmware older than 1.4.32 only supports multiple
981 * RX queues, so if we get an error, first retry using a
982 * single TX queue before giving up */
983 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
c9920268 984 netif_set_real_num_tx_queues(mgp->dev, 1);
236bb5e6
BG		 985 cmd.data0 = mgp->num_slices;
986 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
987 status = myri10ge_send_cmd(mgp,
988 MXGEFW_CMD_ENABLE_RSS_QUEUES,
989 &cmd, 0);
990 }
991
0dcffac1
BG		 992 if (status != 0) {
993 dev_err(&mgp->pdev->dev,
994 "failed to set number of slices\n");
995
996 return status;
997 }
998 }
999 for (i = 0; i < mgp->num_slices; i++) {
1000 ss = &mgp->ss[i];
1001 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1002 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1003 cmd.data2 = i;
1004 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1005 &cmd, 0);
6403eab1 1006 }
0da34b6d
BG		 1007
1008 status |=
1009 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
0dcffac1
BG		 1010 for (i = 0; i < mgp->num_slices; i++) {
1011 ss = &mgp->ss[i];
1012 ss->irq_claim =
1013 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1014 }
df30a740
BG		 1015 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1016 &cmd, 0);
1017 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d 1018
0da34b6d
BG		 1019 status |= myri10ge_send_cmd
1020 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
40f6cff5 1021 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
0da34b6d
BG		 1022 if (status != 0) {
1023 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1024 return status;
1025 }
40f6cff5 1026 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d 1027
5dd2d332 1028#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1029 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1030 dca_tag_off = cmd.data0;
1031 for (i = 0; i < mgp->num_slices; i++) {
1032 ss = &mgp->ss[i];
1033 if (status == 0) {
1034 ss->dca_tag = (__iomem __be32 *)
1035 (mgp->sram + dca_tag_off + 4 * i);
1036 } else {
1037 ss->dca_tag = NULL;
1038 }
1039 }
4ee2ac51 1040#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1041
0da34b6d 1042 /* reset mcp/driver shared state back to 0 */
0dcffac1 1043
c58ac5ca 1044 mgp->link_changes = 0;
0dcffac1
BG		 1045 for (i = 0; i < mgp->num_slices; i++) {
1046 ss = &mgp->ss[i];
1047
1048 memset(ss->rx_done.entry, 0, bytes);
1049 ss->tx.req = 0;
1050 ss->tx.done = 0;
1051 ss->tx.pkt_start = 0;
1052 ss->tx.pkt_done = 0;
1053 ss->rx_big.cnt = 0;
1054 ss->rx_small.cnt = 0;
1055 ss->rx_done.idx = 0;
1056 ss->rx_done.cnt = 0;
1057 ss->tx.wake_queue = 0;
1058 ss->tx.stop_queue = 0;
1059 }
1060
0da34b6d 1061 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
0da34b6d 1062 myri10ge_change_pause(mgp, mgp->pause);
2f76216f 1063 myri10ge_set_multicast_list(mgp->dev);
0da34b6d
BG		 1064 return status;
1065}
1066
5dd2d332 1067#ifdef CONFIG_MYRI10GE_DCA
ef09aadf
AG		 1068static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1069{
9503e255 1070 int ret;
ef09aadf
AG		 1071 u16 ctl;
1072
9503e255 1073 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &ctl);
b3b6ae2c 1074
ef09aadf
AG		 1075 ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1076 if (ret != on) {
1077 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1078 ctl |= (on << 4);
9503e255 1079 pcie_capability_write_word(pdev, PCI_EXP_DEVCTL, ctl);
ef09aadf
AG		 1080 }
1081 return ret;
1082}
1083
981813d8
BG		 1084static void
1085myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1086{
981813d8
BG		 1087 ss->cached_dca_tag = tag;
1088 put_be32(htonl(tag), ss->dca_tag);
1089}
1090
1091static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1092{
1093 int cpu = get_cpu();
1094 int tag;
1095
1096 if (cpu != ss->cpu) {
ef09aadf 1097 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
981813d8
BG		 1098 if (ss->cached_dca_tag != tag)
1099 myri10ge_write_dca(ss, cpu, tag);
ef09aadf 1100 ss->cpu = cpu;
981813d8
BG		 1101 }
1102 put_cpu();
1103}
1104
1105static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1106{
1107 int err, i;
1108 struct pci_dev *pdev = mgp->pdev;
1109
1110 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1111 return;
1112 if (!myri10ge_dca) {
1113 dev_err(&pdev->dev, "dca disabled by administrator\n");
1114 return;
1115 }
1116 err = dca_add_requester(&pdev->dev);
1117 if (err) {
330554cb
BG		 1118 if (err != -ENODEV)
1119 dev_err(&pdev->dev,
1120 "dca_add_requester() failed, err=%d\n", err);
981813d8
BG		 1121 return;
1122 }
ef09aadf 1123 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
981813d8 1124 mgp->dca_enabled = 1;
ef09aadf
AG		 1125 for (i = 0; i < mgp->num_slices; i++) {
1126 mgp->ss[i].cpu = -1;
1127 mgp->ss[i].cached_dca_tag = -1;
1128 myri10ge_update_dca(&mgp->ss[i]);
b3b6ae2c 1129 }
981813d8
BG		 1130}
1131
1132static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1133{
1134 struct pci_dev *pdev = mgp->pdev;
981813d8
BG		 1135
1136 if (!mgp->dca_enabled)
1137 return;
1138 mgp->dca_enabled = 0;
ef09aadf
AG		 1139 if (mgp->relaxed_order)
1140 myri10ge_toggle_relaxed(pdev, 1);
b3b6ae2c 1141 dca_remove_requester(&pdev->dev);
981813d8
BG		 1142}
1143
1144static int myri10ge_notify_dca_device(struct device *dev, void *data)
1145{
1146 struct myri10ge_priv *mgp;
1147 unsigned long event;
1148
1149 mgp = dev_get_drvdata(dev);
1150 event = *(unsigned long *)data;
1151
1152 if (event == DCA_PROVIDER_ADD)
1153 myri10ge_setup_dca(mgp);
1154 else if (event == DCA_PROVIDER_REMOVE)
1155 myri10ge_teardown_dca(mgp);
1156 return 0;
1157}
4ee2ac51 1158#endif /* CONFIG_MYRI10GE_DCA */
981813d8 1159
0da34b6d
BG		 1160static inline void
1161myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1162 struct mcp_kreq_ether_recv *src)
1163{
40f6cff5 1164 __be32 low;
0da34b6d
BG		 1165
1166 low = src->addr_low;
284901a9 1167 src->addr_low = htonl(DMA_BIT_MASK(32));
e67bda55
BG		 1168 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1169 mb();
1170 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
0da34b6d
BG		 1171 mb();
1172 src->addr_low = low;
40f6cff5 1173 put_be32(low, &dst->addr_low);
0da34b6d
BG		 1174 mb();
1175}
1176
40f6cff5 1177static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
0da34b6d
BG		 1178{
1179 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1180
40f6cff5 1181 if ((skb->protocol == htons(ETH_P_8021Q)) &&
0da34b6d
BG		 1182 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1183 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1184 skb->csum = hw_csum;
84fa7933 1185 skb->ip_summed = CHECKSUM_COMPLETE;
0da34b6d
BG		 1186 }
1187}
1188
dd50f336
BG		 1189static void
1190myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1191 int bytes, int watchdog)
1192{
1193 struct page *page;
10545937 1194 dma_addr_t bus;
dd50f336 1195 int idx;
2a3f2790
BG		 1196#if MYRI10GE_ALLOC_SIZE > 4096
1197 int end_offset;
1198#endif
dd50f336
BG		 1199
1200 if (unlikely(rx->watchdog_needed && !watchdog))
1201 return;
1202
1203 /* try to refill entire ring */
1204 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1205 idx = rx->fill_cnt & rx->mask;
ae8509b1 1206 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
dd50f336
BG		 1207 /* we can use part of previous page */
1208 get_page(rx->page);
1209 } else {
1210 /* we need a new page */
1211 page =
1212 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1213 MYRI10GE_ALLOC_ORDER);
1214 if (unlikely(page == NULL)) {
1215 if (rx->fill_cnt - rx->cnt < 16)
1216 rx->watchdog_needed = 1;
1217 return;
1218 }
10545937
SG		 1219
1220 bus = pci_map_page(mgp->pdev, page, 0,
1221 MYRI10GE_ALLOC_SIZE,
1222 PCI_DMA_FROMDEVICE);
1223 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus))) {
1224 __free_pages(page, MYRI10GE_ALLOC_ORDER);
1225 if (rx->fill_cnt - rx->cnt < 16)
1226 rx->watchdog_needed = 1;
1227 return;
1228 }
1229
dd50f336
BG		 1230 rx->page = page;
1231 rx->page_offset = 0;
10545937
SG		 1232 rx->bus = bus;
1233
dd50f336
BG		 1234 }
1235 rx->info[idx].page = rx->page;
1236 rx->info[idx].page_offset = rx->page_offset;
1237 /* note that this is the address of the start of the
1238 * page */
c755b4b6 1239 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
dd50f336
BG		 1240 rx->shadow[idx].addr_low =
1241 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1242 rx->shadow[idx].addr_high =
1243 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1244
1245 /* start next packet on a cacheline boundary */
1246 rx->page_offset += SKB_DATA_ALIGN(bytes);
ae8509b1
BG		 1247
1248#if MYRI10GE_ALLOC_SIZE > 4096
1249 /* don't cross a 4KB boundary */
2a3f2790
BG		 1250 end_offset = rx->page_offset + bytes - 1;
1251 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1252 rx->page_offset = end_offset & ~4095;
ae8509b1 1253#endif
dd50f336
BG		 1254 rx->fill_cnt++;
1255
1256 /* copy 8 descriptors to the firmware at a time */
1257 if ((idx & 7) == 7) {
e454e7e2
BG		 1258 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1259 &rx->shadow[idx - 7]);
dd50f336
BG		 1260 }
1261 }
1262}
1263
1264static inline void
1265myri10ge_unmap_rx_page(struct pci_dev *pdev,
1266 struct myri10ge_rx_buffer_state *info, int bytes)
1267{
1268 /* unmap the recvd page if we're the only or last user of it */
1269 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1270 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
c755b4b6 1271 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
dd50f336
BG		 1272 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1273 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1274 }
1275}
1276
1b4c44e6
AG		 1277/*
1278 * GRO does not support acceleration of tagged vlan frames, and
1279 * this NIC does not support vlan tag offload, so we must pop
1280 * the tag ourselves to be able to achieve GRO performance that
1281 * is comparable to LRO.
1282 */
1283
1284static inline void
1285myri10ge_vlan_rx(struct net_device *dev, void *addr, struct sk_buff *skb)
1286{
1287 u8 *va;
1288 struct vlan_ethhdr *veh;
1289 struct skb_frag_struct *frag;
1290 __wsum vsum;
1291
1292 va = addr;
1293 va += MXGEFW_PAD;
1294 veh = (struct vlan_ethhdr *)va;
f646968f
PM		 1295 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
1296 NETIF_F_HW_VLAN_CTAG_RX &&
30828d2b 1297 veh->h_vlan_proto == htons(ETH_P_8021Q)) {
1b4c44e6
AG		 1298 /* fixup csum if needed */
1299 if (skb->ip_summed == CHECKSUM_COMPLETE) {
1300 vsum = csum_partial(va + ETH_HLEN, VLAN_HLEN, 0);
1301 skb->csum = csum_sub(skb->csum, vsum);
1302 }
1303 /* pop tag */
86a9bad3 1304 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(veh->h_vlan_TCI));
1b4c44e6
AG		 1305 memmove(va + VLAN_HLEN, va, 2 * ETH_ALEN);
1306 skb->len -= VLAN_HLEN;
1307 skb->data_len -= VLAN_HLEN;
1308 frag = skb_shinfo(skb)->frags;
1309 frag->page_offset += VLAN_HLEN;
1310 skb_frag_size_set(frag, skb_frag_size(frag) - VLAN_HLEN);
1311 }
1312}
1313
0dde8026
HYK		 1314#define MYRI10GE_HLEN 64 /* Bytes to copy from page to skb linear memory */
1315
dd50f336 1316static inline int
4ca3221f 1317myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum)
dd50f336 1318{
b53bef84 1319 struct myri10ge_priv *mgp = ss->mgp;
dd50f336 1320 struct sk_buff *skb;
4ca3221f 1321 struct skb_frag_struct *rx_frags;
b3cd9657 1322 struct myri10ge_rx_buf *rx;
4ca3221f 1323 int i, idx, remainder, bytes;
dd50f336
BG		 1324 struct pci_dev *pdev = mgp->pdev;
1325 struct net_device *dev = mgp->dev;
1326 u8 *va;
1327
b3cd9657
SG		 1328 if (len <= mgp->small_bytes) {
1329 rx = &ss->rx_small;
1330 bytes = mgp->small_bytes;
1331 } else {
1332 rx = &ss->rx_big;
1333 bytes = mgp->big_bytes;
1334 }
1335
dd50f336
BG		 1336 len += MXGEFW_PAD;
1337 idx = rx->cnt & rx->mask;
1338 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1339 prefetch(va);
4ca3221f 1340
362108b5 1341 skb = napi_get_frags(&ss->napi);
4ca3221f
AG		 1342 if (unlikely(skb == NULL)) {
1343 ss->stats.rx_dropped++;
1344 for (i = 0, remainder = len; remainder > 0; i++) {
1345 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1346 put_page(rx->info[idx].page);
1347 rx->cnt++;
1348 idx = rx->cnt & rx->mask;
1349 remainder -= MYRI10GE_ALLOC_SIZE;
1350 }
1351 return 0;
1352 }
1353 rx_frags = skb_shinfo(skb)->frags;
dd50f336
BG		 1354 /* Fill skb_frag_struct(s) with data from our receive */
1355 for (i = 0, remainder = len; remainder > 0; i++) {
1356 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
4ca3221f
AG		 1357 skb_fill_page_desc(skb, i, rx->info[idx].page,
1358 rx->info[idx].page_offset,
1359 remainder < MYRI10GE_ALLOC_SIZE ?
1360 remainder : MYRI10GE_ALLOC_SIZE);
dd50f336
BG		 1361 rx->cnt++;
1362 idx = rx->cnt & rx->mask;
1363 remainder -= MYRI10GE_ALLOC_SIZE;
1364 }
1365
4ca3221f
AG		 1366 /* remove padding */
1367 rx_frags[0].page_offset += MXGEFW_PAD;
1368 rx_frags[0].size -= MXGEFW_PAD;
1369 len -= MXGEFW_PAD;
dd50f336 1370
4ca3221f
AG		 1371 skb->len = len;
1372 skb->data_len = len;
1373 skb->truesize += len;
1374 if (dev->features & NETIF_F_RXCSUM) {
1375 skb->ip_summed = CHECKSUM_COMPLETE;
1376 skb->csum = csum;
dd50f336 1377 }
1b4c44e6 1378 myri10ge_vlan_rx(mgp->dev, va, skb);
0c8dfc83 1379 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
0dde8026 1380
362108b5 1381 napi_gro_frags(&ss->napi);
dd50f336 1382
dd50f336
BG		 1383 return 1;
1384}
1385
b53bef84
BG		 1386static inline void
1387myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
0da34b6d 1388{
b53bef84
BG		 1389 struct pci_dev *pdev = ss->mgp->pdev;
1390 struct myri10ge_tx_buf *tx = &ss->tx;
236bb5e6 1391 struct netdev_queue *dev_queue;
0da34b6d
BG		 1392 struct sk_buff *skb;
1393 int idx, len;
0da34b6d
BG		 1394
1395 while (tx->pkt_done != mcp_index) {
1396 idx = tx->done & tx->mask;
1397 skb = tx->info[idx].skb;
1398
1399 /* Mark as free */
1400 tx->info[idx].skb = NULL;
1401 if (tx->info[idx].last) {
1402 tx->pkt_done++;
1403 tx->info[idx].last = 0;
1404 }
1405 tx->done++;
c755b4b6
FT		 1406 len = dma_unmap_len(&tx->info[idx], len);
1407 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 1408 if (skb) {
b53bef84
BG		 1409 ss->stats.tx_bytes += skb->len;
1410 ss->stats.tx_packets++;
5fbc136b 1411 dev_consume_skb_irq(skb);
0da34b6d
BG		 1412 if (len)
1413 pci_unmap_single(pdev,
c755b4b6 1414 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1415 bus), len,
1416 PCI_DMA_TODEVICE);
1417 } else {
1418 if (len)
1419 pci_unmap_page(pdev,
c755b4b6 1420 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 1421 bus), len,
1422 PCI_DMA_TODEVICE);
1423 }
0da34b6d 1424 }
236bb5e6
BG		 1425
1426 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1427 /*
1428 * Make a minimal effort to prevent the NIC from polling an
1429 * idle tx queue. If we can't get the lock we leave the queue
1430 * active. In this case, either a thread was about to start
1431 * using the queue anyway, or we lost a race and the NIC will
1432 * waste some of its resources polling an inactive queue for a
1433 * while.
1434 */
1435
1436 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1437 __netif_tx_trylock(dev_queue)) {
1438 if (tx->req == tx->done) {
1439 tx->queue_active = 0;
1440 put_be32(htonl(1), tx->send_stop);
8c2f5fa5 1441 mb();
236bb5e6
BG		 1442 }
1443 __netif_tx_unlock(dev_queue);
1444 }
1445
0da34b6d 1446 /* start the queue if we've stopped it */
8e95a202 1447 if (netif_tx_queue_stopped(dev_queue) &&
3b20b2dc
JM		 1448 tx->req - tx->done < (tx->mask >> 1) &&
1449 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
b53bef84 1450 tx->wake_queue++;
236bb5e6 1451 netif_tx_wake_queue(dev_queue);
0da34b6d
BG		 1452 }
1453}
1454
b53bef84
BG		 1455static inline int
1456myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
0da34b6d 1457{
b53bef84
BG		 1458 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1459 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 1460 unsigned long rx_bytes = 0;
1461 unsigned long rx_packets = 0;
1462 unsigned long rx_ok;
0da34b6d
BG		 1463 int idx = rx_done->idx;
1464 int cnt = rx_done->cnt;
bea3348e 1465 int work_done = 0;
0da34b6d 1466 u16 length;
40f6cff5 1467 __wsum checksum;
0da34b6d 1468
c956a240 1469 while (rx_done->entry[idx].length != 0 && work_done < budget) {
0da34b6d
BG		 1470 length = ntohs(rx_done->entry[idx].length);
1471 rx_done->entry[idx].length = 0;
40f6cff5 1472 checksum = csum_unfold(rx_done->entry[idx].checksum);
4ca3221f 1473 rx_ok = myri10ge_rx_done(ss, length, checksum);
0da34b6d
BG		 1474 rx_packets += rx_ok;
1475 rx_bytes += rx_ok * (unsigned long)length;
1476 cnt++;
014377a1 1477 idx = cnt & (mgp->max_intr_slots - 1);
c956a240 1478 work_done++;
0da34b6d
BG		 1479 }
1480 rx_done->idx = idx;
1481 rx_done->cnt = cnt;
b53bef84
BG		 1482 ss->stats.rx_packets += rx_packets;
1483 ss->stats.rx_bytes += rx_bytes;
c7dab99b
BG		 1484
1485 /* restock receive rings if needed */
b53bef84
BG		 1486 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1487 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
c7dab99b 1488 mgp->small_bytes + MXGEFW_PAD, 0);
b53bef84
BG		 1489 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1490 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
c7dab99b 1491
bea3348e 1492 return work_done;
0da34b6d
BG		 1493}
1494
1495static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1496{
0dcffac1 1497 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
0da34b6d
BG		 1498
1499 if (unlikely(stats->stats_updated)) {
798a95db
BG		 1500 unsigned link_up = ntohl(stats->link_up);
1501 if (mgp->link_state != link_up) {
1502 mgp->link_state = link_up;
1503
1504 if (mgp->link_state == MXGEFW_LINK_UP) {
b3b6ae2c 1505 netif_info(mgp, link, mgp->dev, "link up\n");
0da34b6d 1506 netif_carrier_on(mgp->dev);
c58ac5ca 1507 mgp->link_changes++;
0da34b6d 1508 } else {
b3b6ae2c
JM		 1509 netif_info(mgp, link, mgp->dev, "link %s\n",
1510 (link_up == MXGEFW_LINK_MYRINET ?
78ca90ea 1511 "mismatch (Myrinet detected)" :
b3b6ae2c 1512 "down"));
0da34b6d 1513 netif_carrier_off(mgp->dev);
c58ac5ca 1514 mgp->link_changes++;
0da34b6d
BG		 1515 }
1516 }
1517 if (mgp->rdma_tags_available !=
b53bef84 1518 ntohl(stats->rdma_tags_available)) {
0da34b6d 1519 mgp->rdma_tags_available =
b53bef84 1520 ntohl(stats->rdma_tags_available);
78ca90ea
JP		 1521 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1522 mgp->rdma_tags_available);
0da34b6d
BG		 1523 }
1524 mgp->down_cnt += stats->link_down;
1525 if (stats->link_down)
1526 wake_up(&mgp->down_wq);
1527 }
1528}
1529
bea3348e 1530static int myri10ge_poll(struct napi_struct *napi, int budget)
0da34b6d 1531{
b53bef84
BG		 1532 struct myri10ge_slice_state *ss =
1533 container_of(napi, struct myri10ge_slice_state, napi);
bea3348e 1534 int work_done;
0da34b6d 1535
5dd2d332 1536#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1537 if (ss->mgp->dca_enabled)
1538 myri10ge_update_dca(ss);
1539#endif
0da34b6d 1540 /* process as many rx events as NAPI will allow */
b53bef84 1541 work_done = myri10ge_clean_rx_done(ss, budget);
0da34b6d 1542
4ec24119 1543 if (work_done < budget) {
6ad20165 1544 napi_complete_done(napi, work_done);
b53bef84 1545 put_be32(htonl(3), ss->irq_claim);
0da34b6d 1546 }
bea3348e 1547 return work_done;
0da34b6d
BG		 1548}
1549
7d12e780 1550static irqreturn_t myri10ge_intr(int irq, void *arg)
0da34b6d 1551{
b53bef84
BG		 1552 struct myri10ge_slice_state *ss = arg;
1553 struct myri10ge_priv *mgp = ss->mgp;
1554 struct mcp_irq_data *stats = ss->fw_stats;
1555 struct myri10ge_tx_buf *tx = &ss->tx;
0da34b6d
BG		 1556 u32 send_done_count;
1557 int i;
1558
236bb5e6
BG		 1559 /* an interrupt on a non-zero receive-only slice is implicitly
1560 * valid since MSI-X irqs are not shared */
1561 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
288379f0 1562 napi_schedule(&ss->napi);
807540ba 1563 return IRQ_HANDLED;
0dcffac1
BG		 1564 }
1565
0da34b6d
BG		 1566 /* make sure it is our IRQ, and that the DMA has finished */
1567 if (unlikely(!stats->valid))
807540ba 1568 return IRQ_NONE;
0da34b6d
BG		 1569
1570 /* low bit indicates receives are present, so schedule
1571 * napi poll handler */
1572 if (stats->valid & 1)
288379f0 1573 napi_schedule(&ss->napi);
0da34b6d 1574
0dcffac1 1575 if (!mgp->msi_enabled && !mgp->msix_enabled) {
40f6cff5 1576 put_be32(0, mgp->irq_deassert);
0da34b6d
BG		 1577 if (!myri10ge_deassert_wait)
1578 stats->valid = 0;
1579 mb();
1580 } else
1581 stats->valid = 0;
1582
1583 /* Wait for IRQ line to go low, if using INTx */
1584 i = 0;
1585 while (1) {
1586 i++;
1587 /* check for transmit completes and receives */
1588 send_done_count = ntohl(stats->send_done_count);
1589 if (send_done_count != tx->pkt_done)
b53bef84 1590 myri10ge_tx_done(ss, (int)send_done_count);
0da34b6d 1591 if (unlikely(i > myri10ge_max_irq_loops)) {
b3b6ae2c 1592 netdev_warn(mgp->dev, "irq stuck?\n");
0da34b6d
BG		 1593 stats->valid = 0;
1594 schedule_work(&mgp->watchdog_work);
1595 }
1596 if (likely(stats->valid == 0))
1597 break;
1598 cpu_relax();
1599 barrier();
1600 }
1601
236bb5e6
BG		 1602 /* Only slice 0 updates stats */
1603 if (ss == mgp->ss)
1604 myri10ge_check_statblock(mgp);
0da34b6d 1605
b53bef84 1606 put_be32(htonl(3), ss->irq_claim + 1);
807540ba 1607 return IRQ_HANDLED;
0da34b6d
BG		 1608}
1609
1610static int
cf901656
PR		 1611myri10ge_get_link_ksettings(struct net_device *netdev,
1612 struct ethtool_link_ksettings *cmd)
0da34b6d 1613{
c0bf8801
BG		 1614 struct myri10ge_priv *mgp = netdev_priv(netdev);
1615 char *ptr;
1616 int i;
1617
cf901656
PR		 1618 cmd->base.autoneg = AUTONEG_DISABLE;
1619 cmd->base.speed = SPEED_10000;
1620 cmd->base.duplex = DUPLEX_FULL;
c0bf8801
BG		 1621
1622 /*
1623 * parse the product code to deterimine the interface type
1624 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1625 * after the 3rd dash in the driver's cached copy of the
1626 * EEPROM's product code string.
1627 */
1628 ptr = mgp->product_code_string;
1629 if (ptr == NULL) {
78ca90ea 1630 netdev_err(netdev, "Missing product code\n");
c0bf8801
BG		 1631 return 0;
1632 }
1633 for (i = 0; i < 3; i++, ptr++) {
1634 ptr = strchr(ptr, '-');
1635 if (ptr == NULL) {
78ca90ea
JP		 1636 netdev_err(netdev, "Invalid product code %s\n",
1637 mgp->product_code_string);
c0bf8801
BG		 1638 return 0;
1639 }
1640 }
196f17eb
BG		 1641 if (*ptr == '2')
1642 ptr++;
1643 if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1644 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
cf901656
PR		 1645 cmd->base.port = PORT_FIBRE;
1646 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1647 ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
196f17eb 1648 } else {
cf901656 1649 cmd->base.port = PORT_OTHER;
c0bf8801 1650 }
196f17eb 1651
0da34b6d
BG		 1652 return 0;
1653}
1654
1655static void
1656myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1657{
1658 struct myri10ge_priv *mgp = netdev_priv(netdev);
1659
1660 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1661 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1662 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1663 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1664}
1665
1666static int
1667myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1668{
1669 struct myri10ge_priv *mgp = netdev_priv(netdev);
99f5f87e 1670
0da34b6d
BG		 1671 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1672 return 0;
1673}
1674
1675static int
1676myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1677{
1678 struct myri10ge_priv *mgp = netdev_priv(netdev);
1679
1680 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
40f6cff5 1681 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
0da34b6d
BG		 1682 return 0;
1683}
1684
1685static void
1686myri10ge_get_pauseparam(struct net_device *netdev,
1687 struct ethtool_pauseparam *pause)
1688{
1689 struct myri10ge_priv *mgp = netdev_priv(netdev);
1690
1691 pause->autoneg = 0;
1692 pause->rx_pause = mgp->pause;
1693 pause->tx_pause = mgp->pause;
1694}
1695
1696static int
1697myri10ge_set_pauseparam(struct net_device *netdev,
1698 struct ethtool_pauseparam *pause)
1699{
1700 struct myri10ge_priv *mgp = netdev_priv(netdev);
1701
1702 if (pause->tx_pause != mgp->pause)
1703 return myri10ge_change_pause(mgp, pause->tx_pause);
1704 if (pause->rx_pause != mgp->pause)
2488f56d 1705 return myri10ge_change_pause(mgp, pause->rx_pause);
0da34b6d
BG		 1706 if (pause->autoneg != 0)
1707 return -EINVAL;
1708 return 0;
1709}
1710
1711static void
1712myri10ge_get_ringparam(struct net_device *netdev,
1713 struct ethtool_ringparam *ring)
1714{
1715 struct myri10ge_priv *mgp = netdev_priv(netdev);
1716
0dcffac1
BG		 1717 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1718 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
0da34b6d 1719 ring->rx_jumbo_max_pending = 0;
6498be3f 1720 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
0da34b6d
BG		 1721 ring->rx_mini_pending = ring->rx_mini_max_pending;
1722 ring->rx_pending = ring->rx_max_pending;
1723 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1724 ring->tx_pending = ring->tx_max_pending;
1725}
1726
b53bef84 1727static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
0da34b6d
BG		 1728 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1729 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1730 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1731 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1732 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1733 "tx_heartbeat_errors", "tx_window_errors",
1734 /* device-specific stats */
e4b6c303 1735 "tx_boundary", "irq", "MSI", "MSIX",
0da34b6d 1736 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
b53bef84 1737 "serial_number", "watchdog_resets",
5dd2d332 1738#ifdef CONFIG_MYRI10GE_DCA
9a6b3b54 1739 "dca_capable_firmware", "dca_device_present",
981813d8 1740#endif
c58ac5ca 1741 "link_changes", "link_up", "dropped_link_overflow",
cee505db
BG		 1742 "dropped_link_error_or_filtered",
1743 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1744 "dropped_unicast_filtered", "dropped_multicast_filtered",
0da34b6d 1745 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
b53bef84
BG		 1746 "dropped_no_big_buffer"
1747};
1748
1749static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1750 "----------- slice ---------",
1751 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1752 "rx_small_cnt", "rx_big_cnt",
b3b6ae2c 1753 "wake_queue", "stop_queue", "tx_linearized",
0da34b6d
BG		 1754};
1755
1756#define MYRI10GE_NET_STATS_LEN 21
b53bef84
BG		 1757#define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1758#define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
0da34b6d
BG		 1759
1760static void
1761myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1762{
0dcffac1
BG		 1763 struct myri10ge_priv *mgp = netdev_priv(netdev);
1764 int i;
1765
0da34b6d
BG		 1766 switch (stringset) {
1767 case ETH_SS_STATS:
b53bef84
BG		 1768 memcpy(data, *myri10ge_gstrings_main_stats,
1769 sizeof(myri10ge_gstrings_main_stats));
1770 data += sizeof(myri10ge_gstrings_main_stats);
0dcffac1
BG		 1771 for (i = 0; i < mgp->num_slices; i++) {
1772 memcpy(data, *myri10ge_gstrings_slice_stats,
1773 sizeof(myri10ge_gstrings_slice_stats));
1774 data += sizeof(myri10ge_gstrings_slice_stats);
1775 }
0da34b6d
BG		 1776 break;
1777 }
1778}
1779
b9f2c044 1780static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
0da34b6d 1781{
0dcffac1
BG		 1782 struct myri10ge_priv *mgp = netdev_priv(netdev);
1783
b9f2c044
JG		 1784 switch (sset) {
1785 case ETH_SS_STATS:
0dcffac1
BG		 1786 return MYRI10GE_MAIN_STATS_LEN +
1787 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
b9f2c044
JG		 1788 default:
1789 return -EOPNOTSUPP;
1790 }
0da34b6d
BG		 1791}
1792
1793static void
1794myri10ge_get_ethtool_stats(struct net_device *netdev,
1795 struct ethtool_stats *stats, u64 * data)
1796{
1797 struct myri10ge_priv *mgp = netdev_priv(netdev);
b53bef84 1798 struct myri10ge_slice_state *ss;
c5f7ef72 1799 struct rtnl_link_stats64 link_stats;
0dcffac1 1800 int slice;
0da34b6d
BG		 1801 int i;
1802
59081825 1803 /* force stats update */
306ff6eb 1804 memset(&link_stats, 0, sizeof(link_stats));
c5f7ef72 1805 (void)myri10ge_get_stats(netdev, &link_stats);
0da34b6d 1806 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
c5f7ef72 1807 data[i] = ((u64 *)&link_stats)[i];
0da34b6d 1808
b53bef84 1809 data[i++] = (unsigned int)mgp->tx_boundary;
2c1a1088
BG		 1810 data[i++] = (unsigned int)mgp->pdev->irq;
1811 data[i++] = (unsigned int)mgp->msi_enabled;
0dcffac1 1812 data[i++] = (unsigned int)mgp->msix_enabled;
0da34b6d
BG		 1813 data[i++] = (unsigned int)mgp->read_dma;
1814 data[i++] = (unsigned int)mgp->write_dma;
1815 data[i++] = (unsigned int)mgp->read_write_dma;
1816 data[i++] = (unsigned int)mgp->serial_number;
0da34b6d 1817 data[i++] = (unsigned int)mgp->watchdog_resets;
5dd2d332 1818#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 1819 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1820 data[i++] = (unsigned int)(mgp->dca_enabled);
1821#endif
c58ac5ca 1822 data[i++] = (unsigned int)mgp->link_changes;
b53bef84
BG		 1823
1824 /* firmware stats are useful only in the first slice */
0dcffac1 1825 ss = &mgp->ss[0];
b53bef84
BG		 1826 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1827 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
cee505db 1828 data[i++] =
b53bef84
BG		 1829 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1830 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1831 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1832 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1833 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
85a7ea1b 1834 data[i++] =
b53bef84
BG		 1835 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1836 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1837 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1838 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1839 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1840
0dcffac1
BG		 1841 for (slice = 0; slice < mgp->num_slices; slice++) {
1842 ss = &mgp->ss[slice];
1843 data[i++] = slice;
1844 data[i++] = (unsigned int)ss->tx.pkt_start;
1845 data[i++] = (unsigned int)ss->tx.pkt_done;
1846 data[i++] = (unsigned int)ss->tx.req;
1847 data[i++] = (unsigned int)ss->tx.done;
1848 data[i++] = (unsigned int)ss->rx_small.cnt;
1849 data[i++] = (unsigned int)ss->rx_big.cnt;
1850 data[i++] = (unsigned int)ss->tx.wake_queue;
1851 data[i++] = (unsigned int)ss->tx.stop_queue;
1852 data[i++] = (unsigned int)ss->tx.linearized;
0dcffac1 1853 }
0da34b6d
BG		 1854}
1855
c58ac5ca
BG		 1856static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1857{
1858 struct myri10ge_priv *mgp = netdev_priv(netdev);
1859 mgp->msg_enable = value;
1860}
1861
1862static u32 myri10ge_get_msglevel(struct net_device *netdev)
1863{
1864 struct myri10ge_priv *mgp = netdev_priv(netdev);
1865 return mgp->msg_enable;
1866}
1867
5dcd8467
JM		 1868/*
1869 * Use a low-level command to change the LED behavior. Rather than
1870 * blinking (which is the normal case), when identify is used, the
1871 * yellow LED turns solid.
1872 */
1873static int myri10ge_led(struct myri10ge_priv *mgp, int on)
1874{
1875 struct mcp_gen_header *hdr;
1876 struct device *dev = &mgp->pdev->dev;
1877 size_t hdr_off, pattern_off, hdr_len;
1878 u32 pattern = 0xfffffffe;
1879
1880 /* find running firmware header */
1881 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
1882 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
1883 dev_err(dev, "Running firmware has bad header offset (%d)\n",
1884 (int)hdr_off);
1885 return -EIO;
1886 }
1887 hdr_len = swab32(readl(mgp->sram + hdr_off +
1888 offsetof(struct mcp_gen_header, header_length)));
1889 pattern_off = hdr_off + offsetof(struct mcp_gen_header, led_pattern);
1890 if (pattern_off >= (hdr_len + hdr_off)) {
1891 dev_info(dev, "Firmware does not support LED identification\n");
1892 return -EINVAL;
1893 }
1894 if (!on)
1895 pattern = swab32(readl(mgp->sram + pattern_off + 4));
59e955ed 1896 writel(swab32(pattern), mgp->sram + pattern_off);
5dcd8467
JM		 1897 return 0;
1898}
1899
1900static int
1901myri10ge_phys_id(struct net_device *netdev, enum ethtool_phys_id_state state)
1902{
1903 struct myri10ge_priv *mgp = netdev_priv(netdev);
1904 int rc;
1905
1906 switch (state) {
1907 case ETHTOOL_ID_ACTIVE:
1908 rc = myri10ge_led(mgp, 1);
1909 break;
1910
1911 case ETHTOOL_ID_INACTIVE:
1912 rc = myri10ge_led(mgp, 0);
1913 break;
1914
1915 default:
1916 rc = -EINVAL;
1917 }
1918
1919 return rc;
1920}
1921
7282d491 1922static const struct ethtool_ops myri10ge_ethtool_ops = {
0da34b6d
BG		 1923 .get_drvinfo = myri10ge_get_drvinfo,
1924 .get_coalesce = myri10ge_get_coalesce,
1925 .set_coalesce = myri10ge_set_coalesce,
1926 .get_pauseparam = myri10ge_get_pauseparam,
1927 .set_pauseparam = myri10ge_set_pauseparam,
1928 .get_ringparam = myri10ge_get_ringparam,
6ffdd071 1929 .get_link = ethtool_op_get_link,
0da34b6d 1930 .get_strings = myri10ge_get_strings,
b9f2c044 1931 .get_sset_count = myri10ge_get_sset_count,
c58ac5ca
BG		 1932 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1933 .set_msglevel = myri10ge_set_msglevel,
3a0c7d2d 1934 .get_msglevel = myri10ge_get_msglevel,
5dcd8467 1935 .set_phys_id = myri10ge_phys_id,
cf901656 1936 .get_link_ksettings = myri10ge_get_link_ksettings,
0da34b6d
BG		 1937};
1938
b53bef84 1939static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
0da34b6d 1940{
b53bef84 1941 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d 1942 struct myri10ge_cmd cmd;
b53bef84 1943 struct net_device *dev = mgp->dev;
0da34b6d
BG		 1944 int tx_ring_size, rx_ring_size;
1945 int tx_ring_entries, rx_ring_entries;
0dcffac1 1946 int i, slice, status;
0da34b6d
BG		 1947 size_t bytes;
1948
0da34b6d 1949 /* get ring sizes */
0dcffac1
BG		 1950 slice = ss - mgp->ss;
1951 cmd.data0 = slice;
0da34b6d
BG		 1952 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1953 tx_ring_size = cmd.data0;
0dcffac1 1954 cmd.data0 = slice;
0da34b6d 1955 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
355c7265
BG		 1956 if (status != 0)
1957 return status;
0da34b6d
BG		 1958 rx_ring_size = cmd.data0;
1959
1960 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1961 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
b53bef84
BG		 1962 ss->tx.mask = tx_ring_entries - 1;
1963 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
0da34b6d 1964
355c7265
BG		 1965 status = -ENOMEM;
1966
0da34b6d
BG		 1967 /* allocate the host shadow rings */
1968
1969 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
b53bef84
BG		 1970 * sizeof(*ss->tx.req_list);
1971 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1972 if (ss->tx.req_bytes == NULL)
0da34b6d
BG		 1973 goto abort_with_nothing;
1974
1975 /* ensure req_list entries are aligned to 8 bytes */
b53bef84
BG		 1976 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1977 ALIGN((unsigned long)ss->tx.req_bytes, 8);
236bb5e6 1978 ss->tx.queue_active = 0;
0da34b6d 1979
b53bef84
BG		 1980 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1981 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1982 if (ss->rx_small.shadow == NULL)
0da34b6d
BG		 1983 goto abort_with_tx_req_bytes;
1984
b53bef84
BG		 1985 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1986 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1987 if (ss->rx_big.shadow == NULL)
0da34b6d
BG		 1988 goto abort_with_rx_small_shadow;
1989
1990 /* allocate the host info rings */
1991
b53bef84
BG		 1992 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1993 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1994 if (ss->tx.info == NULL)
0da34b6d
BG		 1995 goto abort_with_rx_big_shadow;
1996
b53bef84
BG		 1997 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1998 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1999 if (ss->rx_small.info == NULL)
0da34b6d
BG		 2000 goto abort_with_tx_info;
2001
b53bef84
BG		 2002 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2003 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2004 if (ss->rx_big.info == NULL)
0da34b6d
BG		 2005 goto abort_with_rx_small_info;
2006
2007 /* Fill the receive rings */
b53bef84
BG		 2008 ss->rx_big.cnt = 0;
2009 ss->rx_small.cnt = 0;
2010 ss->rx_big.fill_cnt = 0;
2011 ss->rx_small.fill_cnt = 0;
2012 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2013 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2014 ss->rx_small.watchdog_needed = 0;
2015 ss->rx_big.watchdog_needed = 0;
4b47638a
JM		 2016 if (mgp->small_bytes == 0) {
2017 ss->rx_small.fill_cnt = ss->rx_small.mask + 1;
2018 } else {
2019 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2020 mgp->small_bytes + MXGEFW_PAD, 0);
2021 }
0da34b6d 2022
b53bef84 2023 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
78ca90ea
JP		 2024 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2025 slice, ss->rx_small.fill_cnt);
c7dab99b 2026 goto abort_with_rx_small_ring;
0da34b6d
BG		 2027 }
2028
b53bef84
BG		 2029 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2030 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
78ca90ea
JP		 2031 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2032 slice, ss->rx_big.fill_cnt);
c7dab99b 2033 goto abort_with_rx_big_ring;
0da34b6d
BG		 2034 }
2035
2036 return 0;
2037
2038abort_with_rx_big_ring:
b53bef84
BG		 2039 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2040 int idx = i & ss->rx_big.mask;
2041 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2042 mgp->big_bytes);
b53bef84 2043 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2044 }
2045
2046abort_with_rx_small_ring:
4b47638a
JM		 2047 if (mgp->small_bytes == 0)
2048 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2049 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2050 int idx = i & ss->rx_small.mask;
2051 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2052 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2053 put_page(ss->rx_small.info[idx].page);
0da34b6d 2054 }
c7dab99b 2055
b53bef84 2056 kfree(ss->rx_big.info);
0da34b6d
BG		 2057
2058abort_with_rx_small_info:
b53bef84 2059 kfree(ss->rx_small.info);
0da34b6d
BG		 2060
2061abort_with_tx_info:
b53bef84 2062 kfree(ss->tx.info);
0da34b6d
BG		 2063
2064abort_with_rx_big_shadow:
b53bef84 2065 kfree(ss->rx_big.shadow);
0da34b6d
BG		 2066
2067abort_with_rx_small_shadow:
b53bef84 2068 kfree(ss->rx_small.shadow);
0da34b6d
BG		 2069
2070abort_with_tx_req_bytes:
b53bef84
BG		 2071 kfree(ss->tx.req_bytes);
2072 ss->tx.req_bytes = NULL;
2073 ss->tx.req_list = NULL;
0da34b6d
BG		 2074
2075abort_with_nothing:
2076 return status;
2077}
2078
b53bef84 2079static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
0da34b6d 2080{
b53bef84 2081 struct myri10ge_priv *mgp = ss->mgp;
0da34b6d
BG		 2082 struct sk_buff *skb;
2083 struct myri10ge_tx_buf *tx;
2084 int i, len, idx;
2085
0dcffac1
BG		 2086 /* If not allocated, skip it */
2087 if (ss->tx.req_list == NULL)
2088 return;
2089
b53bef84
BG		 2090 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2091 idx = i & ss->rx_big.mask;
2092 if (i == ss->rx_big.fill_cnt - 1)
2093 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2094 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
c7dab99b 2095 mgp->big_bytes);
b53bef84 2096 put_page(ss->rx_big.info[idx].page);
0da34b6d
BG		 2097 }
2098
4b47638a
JM		 2099 if (mgp->small_bytes == 0)
2100 ss->rx_small.fill_cnt = ss->rx_small.cnt;
b53bef84
BG		 2101 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2102 idx = i & ss->rx_small.mask;
2103 if (i == ss->rx_small.fill_cnt - 1)
2104 ss->rx_small.info[idx].page_offset =
c7dab99b 2105 MYRI10GE_ALLOC_SIZE;
b53bef84 2106 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
c7dab99b 2107 mgp->small_bytes + MXGEFW_PAD);
b53bef84 2108 put_page(ss->rx_small.info[idx].page);
c7dab99b 2109 }
b53bef84 2110 tx = &ss->tx;
0da34b6d
BG		 2111 while (tx->done != tx->req) {
2112 idx = tx->done & tx->mask;
2113 skb = tx->info[idx].skb;
2114
2115 /* Mark as free */
2116 tx->info[idx].skb = NULL;
2117 tx->done++;
c755b4b6
FT		 2118 len = dma_unmap_len(&tx->info[idx], len);
2119 dma_unmap_len_set(&tx->info[idx], len, 0);
0da34b6d 2120 if (skb) {
b53bef84 2121 ss->stats.tx_dropped++;
0da34b6d
BG		 2122 dev_kfree_skb_any(skb);
2123 if (len)
2124 pci_unmap_single(mgp->pdev,
c755b4b6 2125 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2126 bus), len,
2127 PCI_DMA_TODEVICE);
2128 } else {
2129 if (len)
2130 pci_unmap_page(mgp->pdev,
c755b4b6 2131 dma_unmap_addr(&tx->info[idx],
0da34b6d
BG		 2132 bus), len,
2133 PCI_DMA_TODEVICE);
2134 }
2135 }
b53bef84 2136 kfree(ss->rx_big.info);
0da34b6d 2137
b53bef84 2138 kfree(ss->rx_small.info);
0da34b6d 2139
b53bef84 2140 kfree(ss->tx.info);
0da34b6d 2141
b53bef84 2142 kfree(ss->rx_big.shadow);
0da34b6d 2143
b53bef84 2144 kfree(ss->rx_small.shadow);
0da34b6d 2145
b53bef84
BG		 2146 kfree(ss->tx.req_bytes);
2147 ss->tx.req_bytes = NULL;
2148 ss->tx.req_list = NULL;
0da34b6d
BG		 2149}
2150
df30a740
BG		 2151static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2152{
2153 struct pci_dev *pdev = mgp->pdev;
0dcffac1
BG		 2154 struct myri10ge_slice_state *ss;
2155 struct net_device *netdev = mgp->dev;
2156 int i;
df30a740
BG		 2157 int status;
2158
0dcffac1
BG		 2159 mgp->msi_enabled = 0;
2160 mgp->msix_enabled = 0;
2161 status = 0;
df30a740 2162 if (myri10ge_msi) {
0dcffac1 2163 if (mgp->num_slices > 1) {
0729cc0c
AG		 2164 status = pci_enable_msix_range(pdev, mgp->msix_vectors,
2165 mgp->num_slices, mgp->num_slices);
2166 if (status < 0) {
0dcffac1
BG		 2167 dev_err(&pdev->dev,
2168 "Error %d setting up MSI-X\n", status);
2169 return status;
2170 }
0729cc0c 2171 mgp->msix_enabled = 1;
0dcffac1
BG		 2172 }
2173 if (mgp->msix_enabled == 0) {
2174 status = pci_enable_msi(pdev);
2175 if (status != 0) {
2176 dev_err(&pdev->dev,
2177 "Error %d setting up MSI; falling back to xPIC\n",
2178 status);
2179 } else {
2180 mgp->msi_enabled = 1;
2181 }
2182 }
df30a740 2183 }
0dcffac1
BG		 2184 if (mgp->msix_enabled) {
2185 for (i = 0; i < mgp->num_slices; i++) {
2186 ss = &mgp->ss[i];
2187 snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2188 "%s:slice-%d", netdev->name, i);
2189 status = request_irq(mgp->msix_vectors[i].vector,
2190 myri10ge_intr, 0, ss->irq_desc,
2191 ss);
2192 if (status != 0) {
2193 dev_err(&pdev->dev,
2194 "slice %d failed to allocate IRQ\n", i);
2195 i--;
2196 while (i >= 0) {
2197 free_irq(mgp->msix_vectors[i].vector,
2198 &mgp->ss[i]);
2199 i--;
2200 }
2201 pci_disable_msix(pdev);
2202 return status;
2203 }
2204 }
2205 } else {
2206 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2207 mgp->dev->name, &mgp->ss[0]);
2208 if (status != 0) {
2209 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2210 if (mgp->msi_enabled)
2211 pci_disable_msi(pdev);
2212 }
df30a740
BG		 2213 }
2214 return status;
2215}
2216
2217static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2218{
2219 struct pci_dev *pdev = mgp->pdev;
0dcffac1 2220 int i;
df30a740 2221
0dcffac1
BG		 2222 if (mgp->msix_enabled) {
2223 for (i = 0; i < mgp->num_slices; i++)
2224 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2225 } else {
2226 free_irq(pdev->irq, &mgp->ss[0]);
2227 }
df30a740
BG		 2228 if (mgp->msi_enabled)
2229 pci_disable_msi(pdev);
0dcffac1
BG		 2230 if (mgp->msix_enabled)
2231 pci_disable_msix(pdev);
df30a740
BG		 2232}
2233
77929732
BG		 2234static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2235{
2236 struct myri10ge_cmd cmd;
2237 struct myri10ge_slice_state *ss;
2238 int status;
2239
2240 ss = &mgp->ss[slice];
236bb5e6
BG		 2241 status = 0;
2242 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2243 cmd.data0 = slice;
2244 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2245 &cmd, 0);
2246 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2247 (mgp->sram + cmd.data0);
2248 }
77929732
BG		 2249 cmd.data0 = slice;
2250 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2251 &cmd, 0);
2252 ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2253 (mgp->sram + cmd.data0);
2254
2255 cmd.data0 = slice;
2256 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2257 ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2258 (mgp->sram + cmd.data0);
2259
236bb5e6
BG		 2260 ss->tx.send_go = (__iomem __be32 *)
2261 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2262 ss->tx.send_stop = (__iomem __be32 *)
2263 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
77929732
BG		 2264 return status;
2265
2266}
2267
2268static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2269{
2270 struct myri10ge_cmd cmd;
2271 struct myri10ge_slice_state *ss;
2272 int status;
2273
2274 ss = &mgp->ss[slice];
2275 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2276 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
236bb5e6 2277 cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
77929732
BG		 2278 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2279 if (status == -ENOSYS) {
2280 dma_addr_t bus = ss->fw_stats_bus;
2281 if (slice != 0)
2282 return -EINVAL;
2283 bus += offsetof(struct mcp_irq_data, send_done_count);
2284 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2285 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2286 status = myri10ge_send_cmd(mgp,
2287 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2288 &cmd, 0);
2289 /* Firmware cannot support multicast without STATS_DMA_V2 */
2290 mgp->fw_multicast_support = 0;
2291 } else {
2292 mgp->fw_multicast_support = 1;
2293 }
2294 return 0;
2295}
77929732 2296
0da34b6d
BG		 2297static int myri10ge_open(struct net_device *dev)
2298{
0dcffac1 2299 struct myri10ge_slice_state *ss;
b53bef84 2300 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d 2301 struct myri10ge_cmd cmd;
0dcffac1 2302 int i, status, big_pow2, slice;
59e955ed 2303 u8 __iomem *itable;
0da34b6d 2304
0da34b6d
BG		 2305 if (mgp->running != MYRI10GE_ETH_STOPPED)
2306 return -EBUSY;
2307
2308 mgp->running = MYRI10GE_ETH_STARTING;
2309 status = myri10ge_reset(mgp);
2310 if (status != 0) {
78ca90ea 2311 netdev_err(dev, "failed reset\n");
df30a740 2312 goto abort_with_nothing;
0da34b6d
BG		 2313 }
2314
0dcffac1
BG		 2315 if (mgp->num_slices > 1) {
2316 cmd.data0 = mgp->num_slices;
236bb5e6
BG		 2317 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2318 if (mgp->dev->real_num_tx_queues > 1)
2319 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
0dcffac1
BG		 2320 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2321 &cmd, 0);
2322 if (status != 0) {
78ca90ea 2323 netdev_err(dev, "failed to set number of slices\n");
0dcffac1
BG		 2324 goto abort_with_nothing;
2325 }
2326 /* setup the indirection table */
2327 cmd.data0 = mgp->num_slices;
2328 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2329 &cmd, 0);
2330
2331 status |= myri10ge_send_cmd(mgp,
2332 MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2333 &cmd, 0);
2334 if (status != 0) {
78ca90ea 2335 netdev_err(dev, "failed to setup rss tables\n");
236bb5e6 2336 goto abort_with_nothing;
0dcffac1
BG		 2337 }
2338
2339 /* just enable an identity mapping */
2340 itable = mgp->sram + cmd.data0;
2341 for (i = 0; i < mgp->num_slices; i++)
2342 __raw_writeb(i, &itable[i]);
2343
2344 cmd.data0 = 1;
2345 cmd.data1 = myri10ge_rss_hash;
2346 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2347 &cmd, 0);
2348 if (status != 0) {
78ca90ea 2349 netdev_err(dev, "failed to enable slices\n");
0dcffac1
BG		 2350 goto abort_with_nothing;
2351 }
2352 }
2353
df30a740
BG		 2354 status = myri10ge_request_irq(mgp);
2355 if (status != 0)
2356 goto abort_with_nothing;
2357
0da34b6d
BG		 2358 /* decide what small buffer size to use. For good TCP rx
2359 * performance, it is important to not receive 1514 byte
2360 * frames into jumbo buffers, as it confuses the socket buffer
2361 * accounting code, leading to drops and erratic performance.
2362 */
2363
2364 if (dev->mtu <= ETH_DATA_LEN)
c7dab99b
BG		 2365 /* enough for a TCP header */
2366 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2367 ? (128 - MXGEFW_PAD)
2368 : (SMP_CACHE_BYTES - MXGEFW_PAD);
0da34b6d 2369 else
de3c4507
BG		 2370 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2371 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
0da34b6d
BG		 2372
2373 /* Override the small buffer size? */
4b47638a 2374 if (myri10ge_small_bytes >= 0)
0da34b6d
BG		 2375 mgp->small_bytes = myri10ge_small_bytes;
2376
0da34b6d
BG		 2377 /* Firmware needs the big buff size as a power of 2. Lie and
2378 * tell him the buffer is larger, because we only use 1
2379 * buffer/pkt, and the mtu will prevent overruns.
2380 */
13348bee 2381 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b 2382 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
199126a2 2383 while (!is_power_of_2(big_pow2))
c7dab99b 2384 big_pow2++;
13348bee 2385 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
c7dab99b
BG		 2386 } else {
2387 big_pow2 = MYRI10GE_ALLOC_SIZE;
2388 mgp->big_bytes = big_pow2;
2389 }
2390
0dcffac1
BG		 2391 /* setup the per-slice data structures */
2392 for (slice = 0; slice < mgp->num_slices; slice++) {
2393 ss = &mgp->ss[slice];
2394
2395 status = myri10ge_get_txrx(mgp, slice);
2396 if (status != 0) {
78ca90ea 2397 netdev_err(dev, "failed to get ring sizes or locations\n");
0dcffac1
BG		 2398 goto abort_with_rings;
2399 }
2400 status = myri10ge_allocate_rings(ss);
2401 if (status != 0)
2402 goto abort_with_rings;
236bb5e6
BG		 2403
2404 /* only firmware which supports multiple TX queues
2405 * supports setting up the tx stats on non-zero
2406 * slices */
2407 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
0dcffac1
BG		 2408 status = myri10ge_set_stats(mgp, slice);
2409 if (status) {
78ca90ea 2410 netdev_err(dev, "Couldn't set stats DMA\n");
0dcffac1
BG		 2411 goto abort_with_rings;
2412 }
2413
0dcffac1
BG		 2414 /* must happen prior to any irq */
2415 napi_enable(&(ss)->napi);
2416 }
0da34b6d
BG		 2417
2418 /* now give firmware buffers sizes, and MTU */
2419 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2420 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2421 cmd.data0 = mgp->small_bytes;
2422 status |=
2423 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2424 cmd.data0 = big_pow2;
2425 status |=
2426 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2427 if (status) {
78ca90ea 2428 netdev_err(dev, "Couldn't set buffer sizes\n");
0da34b6d
BG		 2429 goto abort_with_rings;
2430 }
2431
0dcffac1
BG		 2432 /*
2433 * Set Linux style TSO mode; this is needed only on newer
2434 * firmware versions. Older versions default to Linux
2435 * style TSO
2436 */
2437 cmd.data0 = 0;
2438 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2439 if (status && status != -ENOSYS) {
78ca90ea 2440 netdev_err(dev, "Couldn't set TSO mode\n");
0da34b6d
BG		 2441 goto abort_with_rings;
2442 }
2443
66341fff 2444 mgp->link_state = ~0U;
0da34b6d
BG		 2445 mgp->rdma_tags_available = 15;
2446
0da34b6d
BG		 2447 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2448 if (status) {
78ca90ea 2449 netdev_err(dev, "Couldn't bring up link\n");
0da34b6d
BG		 2450 goto abort_with_rings;
2451 }
2452
0da34b6d
BG		 2453 mgp->running = MYRI10GE_ETH_RUNNING;
2454 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2455 add_timer(&mgp->watchdog_timer);
236bb5e6
BG		 2456 netif_tx_wake_all_queues(dev);
2457
0da34b6d
BG		 2458 return 0;
2459
2460abort_with_rings:
051d36f3
BG		 2461 while (slice) {
2462 slice--;
2463 napi_disable(&mgp->ss[slice].napi);
2464 }
0dcffac1
BG		 2465 for (i = 0; i < mgp->num_slices; i++)
2466 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d 2467
df30a740
BG		 2468 myri10ge_free_irq(mgp);
2469
0da34b6d
BG		 2470abort_with_nothing:
2471 mgp->running = MYRI10GE_ETH_STOPPED;
2472 return -ENOMEM;
2473}
2474
2475static int myri10ge_close(struct net_device *dev)
2476{
b53bef84 2477 struct myri10ge_priv *mgp = netdev_priv(dev);
0da34b6d
BG		 2478 struct myri10ge_cmd cmd;
2479 int status, old_down_cnt;
0dcffac1 2480 int i;
0da34b6d 2481
0da34b6d
BG		 2482 if (mgp->running != MYRI10GE_ETH_RUNNING)
2483 return 0;
2484
0dcffac1 2485 if (mgp->ss[0].tx.req_bytes == NULL)
0da34b6d
BG		 2486 return 0;
2487
2488 del_timer_sync(&mgp->watchdog_timer);
2489 mgp->running = MYRI10GE_ETH_STOPPING;
362108b5 2490 for (i = 0; i < mgp->num_slices; i++)
0dcffac1 2491 napi_disable(&mgp->ss[i].napi);
362108b5 2492
0da34b6d 2493 netif_carrier_off(dev);
236bb5e6
BG		 2494
2495 netif_tx_stop_all_queues(dev);
d0234215
BG		 2496 if (mgp->rebooted == 0) {
2497 old_down_cnt = mgp->down_cnt;
2498 mb();
2499 status =
2500 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2501 if (status)
78ca90ea 2502 netdev_err(dev, "Couldn't bring down link\n");
0da34b6d 2503
d0234215
BG		 2504 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2505 HZ);
2506 if (old_down_cnt == mgp->down_cnt)
78ca90ea 2507 netdev_err(dev, "never got down irq\n");
d0234215 2508 }
0da34b6d 2509 netif_tx_disable(dev);
df30a740 2510 myri10ge_free_irq(mgp);
0dcffac1
BG		 2511 for (i = 0; i < mgp->num_slices; i++)
2512 myri10ge_free_rings(&mgp->ss[i]);
0da34b6d
BG		 2513
2514 mgp->running = MYRI10GE_ETH_STOPPED;
2515 return 0;
2516}
2517
2518/* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2519 * backwards one at a time and handle ring wraps */
2520
2521static inline void
2522myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2523 struct mcp_kreq_ether_send *src, int cnt)
2524{
2525 int idx, starting_slot;
2526 starting_slot = tx->req;
2527 while (cnt > 1) {
2528 cnt--;
2529 idx = (starting_slot + cnt) & tx->mask;
2530 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2531 mb();
2532 }
2533}
2534
2535/*
2536 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2537 * at most 32 bytes at a time, so as to avoid involving the software
2538 * pio handler in the nic. We re-write the first segment's flags
2539 * to mark them valid only after writing the entire chain.
2540 */
2541
2542static inline void
2543myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2544 int cnt)
2545{
2546 int idx, i;
2547 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2548 struct mcp_kreq_ether_send *srcp;
2549 u8 last_flags;
2550
2551 idx = tx->req & tx->mask;
2552
2553 last_flags = src->flags;
2554 src->flags = 0;
2555 mb();
2556 dst = dstp = &tx->lanai[idx];
2557 srcp = src;
2558
2559 if ((idx + cnt) < tx->mask) {
2560 for (i = 0; i < (cnt - 1); i += 2) {
2561 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2562 mb(); /* force write every 32 bytes */
2563 srcp += 2;
2564 dstp += 2;
2565 }
2566 } else {
2567 /* submit all but the first request, and ensure
2568 * that it is submitted below */
2569 myri10ge_submit_req_backwards(tx, src, cnt);
2570 i = 0;
2571 }
2572 if (i < cnt) {
2573 /* submit the first request */
2574 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2575 mb(); /* barrier before setting valid flag */
2576 }
2577
2578 /* re-write the last 32-bits with the valid flags */
2579 src->flags = last_flags;
40f6cff5 2580 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
0da34b6d
BG		 2581 tx->req += cnt;
2582 mb();
2583}
2584
10545937
SG		 2585static void myri10ge_unmap_tx_dma(struct myri10ge_priv *mgp,
2586 struct myri10ge_tx_buf *tx, int idx)
2587{
2588 unsigned int len;
2589 int last_idx;
2590
2591 /* Free any DMA resources we've alloced and clear out the skb slot */
2592 last_idx = (idx + 1) & tx->mask;
2593 idx = tx->req & tx->mask;
2594 do {
2595 len = dma_unmap_len(&tx->info[idx], len);
2596 if (len) {
2597 if (tx->info[idx].skb != NULL)
2598 pci_unmap_single(mgp->pdev,
2599 dma_unmap_addr(&tx->info[idx],
2600 bus), len,
2601 PCI_DMA_TODEVICE);
2602 else
2603 pci_unmap_page(mgp->pdev,
2604 dma_unmap_addr(&tx->info[idx],
2605 bus), len,
2606 PCI_DMA_TODEVICE);
2607 dma_unmap_len_set(&tx->info[idx], len, 0);
2608 tx->info[idx].skb = NULL;
2609 }
2610 idx = (idx + 1) & tx->mask;
2611 } while (idx != last_idx);
2612}
2613
0da34b6d
BG		 2614/*
2615 * Transmit a packet. We need to split the packet so that a single
b53bef84 2616 * segment does not cross myri10ge->tx_boundary, so this makes segment
0da34b6d
BG		 2617 * counting tricky. So rather than try to count segments up front, we
2618 * just give up if there are too few segments to hold a reasonably
2619 * fragmented packet currently available. If we run
2620 * out of segments while preparing a packet for DMA, we just linearize
2621 * it and try again.
2622 */
2623
61357325
SH		 2624static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2625 struct net_device *dev)
0da34b6d
BG		 2626{
2627 struct myri10ge_priv *mgp = netdev_priv(dev);
b53bef84 2628 struct myri10ge_slice_state *ss;
0da34b6d 2629 struct mcp_kreq_ether_send *req;
b53bef84 2630 struct myri10ge_tx_buf *tx;
0da34b6d 2631 struct skb_frag_struct *frag;
236bb5e6 2632 struct netdev_queue *netdev_queue;
0da34b6d 2633 dma_addr_t bus;
40f6cff5
AV		 2634 u32 low;
2635 __be32 high_swapped;
0da34b6d 2636 unsigned int len;
10545937 2637 int idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
236bb5e6 2638 u16 pseudo_hdr_offset, cksum_offset, queue;
0da34b6d
BG		 2639 int cum_len, seglen, boundary, rdma_count;
2640 u8 flags, odd_flag;
2641
236bb5e6 2642 queue = skb_get_queue_mapping(skb);
236bb5e6
BG		 2643 ss = &mgp->ss[queue];
2644 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
b53bef84 2645 tx = &ss->tx;
236bb5e6 2646
0da34b6d
BG		 2647again:
2648 req = tx->req_list;
2649 avail = tx->mask - 1 - (tx->req - tx->done);
2650
2651 mss = 0;
2652 max_segments = MXGEFW_MAX_SEND_DESC;
2653
917690cd 2654 if (skb_is_gso(skb)) {
7967168c 2655 mss = skb_shinfo(skb)->gso_size;
917690cd 2656 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
0da34b6d 2657 }
0da34b6d
BG		 2658
2659 if ((unlikely(avail < max_segments))) {
2660 /* we are out of transmit resources */
b53bef84 2661 tx->stop_queue++;
236bb5e6 2662 netif_tx_stop_queue(netdev_queue);
5b548140 2663 return NETDEV_TX_BUSY;
0da34b6d
BG		 2664 }
2665
2666 /* Setup checksum offloading, if needed */
2667 cksum_offset = 0;
2668 pseudo_hdr_offset = 0;
2669 odd_flag = 0;
2670 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
84fa7933 2671 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
0d0b1672 2672 cksum_offset = skb_checksum_start_offset(skb);
ff1dcadb 2673 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
0da34b6d
BG		 2674 /* If the headers are excessively large, then we must
2675 * fall back to a software checksum */
4f93fde0
BG		 2676 if (unlikely(!mss && (cksum_offset > 255 ||
2677 pseudo_hdr_offset > 127))) {
84fa7933 2678 if (skb_checksum_help(skb))
0da34b6d
BG		 2679 goto drop;
2680 cksum_offset = 0;
2681 pseudo_hdr_offset = 0;
2682 } else {
0da34b6d
BG		 2683 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2684 flags |= MXGEFW_FLAGS_CKSUM;
2685 }
2686 }
2687
2688 cum_len = 0;
2689
0da34b6d
BG		 2690 if (mss) { /* TSO */
2691 /* this removes any CKSUM flag from before */
2692 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2693
2694 /* negative cum_len signifies to the
2695 * send loop that we are still in the
2696 * header portion of the TSO packet.
4f93fde0 2697 * TSO header can be at most 1KB long */
ab6a5bb6 2698 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
0da34b6d 2699
4f93fde0
BG		 2700 /* for IPv6 TSO, the checksum offset stores the
2701 * TCP header length, to save the firmware from
2702 * the need to parse the headers */
2703 if (skb_is_gso_v6(skb)) {
2704 cksum_offset = tcp_hdrlen(skb);
2705 /* Can only handle headers <= max_tso6 long */
2706 if (unlikely(-cum_len > mgp->max_tso6))
2707 return myri10ge_sw_tso(skb, dev);
2708 }
0da34b6d
BG		 2709 /* for TSO, pseudo_hdr_offset holds mss.
2710 * The firmware figures out where to put
2711 * the checksum by parsing the header. */
40f6cff5 2712 pseudo_hdr_offset = mss;
0da34b6d 2713 } else
0da34b6d
BG		 2714 /* Mark small packets, and pad out tiny packets */
2715 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2716 flags |= MXGEFW_FLAGS_SMALL;
2717
2718 /* pad frames to at least ETH_ZLEN bytes */
b0b9f333
AD		 2719 if (eth_skb_pad(skb)) {
2720 /* The packet is gone, so we must
2721 * return 0 */
2722 ss->stats.tx_dropped += 1;
2723 return NETDEV_TX_OK;
0da34b6d
BG		 2724 }
2725 }
2726
2727 /* map the skb for DMA */
e743d313 2728 len = skb_headlen(skb);
10545937
SG		 2729 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2730 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus)))
2731 goto drop;
2732
0da34b6d
BG		 2733 idx = tx->req & tx->mask;
2734 tx->info[idx].skb = skb;
c755b4b6
FT		 2735 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2736 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2737
2738 frag_cnt = skb_shinfo(skb)->nr_frags;
2739 frag_idx = 0;
2740 count = 0;
2741 rdma_count = 0;
2742
2743 /* "rdma_count" is the number of RDMAs belonging to the
2744 * current packet BEFORE the current send request. For
2745 * non-TSO packets, this is equal to "count".
2746 * For TSO packets, rdma_count needs to be reset
2747 * to 0 after a segment cut.
2748 *
2749 * The rdma_count field of the send request is
2750 * the number of RDMAs of the packet starting at
2751 * that request. For TSO send requests with one ore more cuts
2752 * in the middle, this is the number of RDMAs starting
2753 * after the last cut in the request. All previous
2754 * segments before the last cut implicitly have 1 RDMA.
2755 *
2756 * Since the number of RDMAs is not known beforehand,
2757 * it must be filled-in retroactively - after each
2758 * segmentation cut or at the end of the entire packet.
2759 */
2760
2761 while (1) {
2762 /* Break the SKB or Fragment up into pieces which
b53bef84 2763 * do not cross mgp->tx_boundary */
0da34b6d
BG		 2764 low = MYRI10GE_LOWPART_TO_U32(bus);
2765 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2766 while (len) {
2767 u8 flags_next;
2768 int cum_len_next;
2769
2770 if (unlikely(count == max_segments))
2771 goto abort_linearize;
2772
b53bef84
BG		 2773 boundary =
2774 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
0da34b6d
BG		 2775 seglen = boundary - low;
2776 if (seglen > len)
2777 seglen = len;
2778 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2779 cum_len_next = cum_len + seglen;
0da34b6d
BG		 2780 if (mss) { /* TSO */
2781 (req - rdma_count)->rdma_count = rdma_count + 1;
2782
2783 if (likely(cum_len >= 0)) { /* payload */
2784 int next_is_first, chop;
2785
2786 chop = (cum_len_next > mss);
2787 cum_len_next = cum_len_next % mss;
2788 next_is_first = (cum_len_next == 0);
2789 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2790 flags_next |= next_is_first *
2791 MXGEFW_FLAGS_FIRST;
2792 rdma_count |= -(chop | next_is_first);
59e955ed 2793 rdma_count += chop & ~next_is_first;
0da34b6d
BG		 2794 } else if (likely(cum_len_next >= 0)) { /* header ends */
2795 int small;
2796
2797 rdma_count = -1;
2798 cum_len_next = 0;
2799 seglen = -cum_len;
2800 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2801 flags_next = MXGEFW_FLAGS_TSO_PLD |
2802 MXGEFW_FLAGS_FIRST |
2803 (small * MXGEFW_FLAGS_SMALL);
2804 }
2805 }
0da34b6d
BG		 2806 req->addr_high = high_swapped;
2807 req->addr_low = htonl(low);
40f6cff5 2808 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
0da34b6d
BG		 2809 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2810 req->rdma_count = 1;
2811 req->length = htons(seglen);
2812 req->cksum_offset = cksum_offset;
2813 req->flags = flags | ((cum_len & 1) * odd_flag);
2814
2815 low += seglen;
2816 len -= seglen;
2817 cum_len = cum_len_next;
2818 flags = flags_next;
2819 req++;
2820 count++;
2821 rdma_count++;
4f93fde0
BG		 2822 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2823 if (unlikely(cksum_offset > seglen))
2824 cksum_offset -= seglen;
2825 else
2826 cksum_offset = 0;
2827 }
0da34b6d
BG		 2828 }
2829 if (frag_idx == frag_cnt)
2830 break;
2831
2832 /* map next fragment for DMA */
0da34b6d
BG		 2833 frag = &skb_shinfo(skb)->frags[frag_idx];
2834 frag_idx++;
9e903e08 2835 len = skb_frag_size(frag);
5dc3e196 2836 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
5d6bcdfe 2837 DMA_TO_DEVICE);
10545937
SG		 2838 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus))) {
2839 myri10ge_unmap_tx_dma(mgp, tx, idx);
2840 goto drop;
2841 }
2842 idx = (count + tx->req) & tx->mask;
c755b4b6
FT		 2843 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2844 dma_unmap_len_set(&tx->info[idx], len, len);
0da34b6d
BG		 2845 }
2846
2847 (req - rdma_count)->rdma_count = rdma_count;
0da34b6d
BG		 2848 if (mss)
2849 do {
2850 req--;
2851 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2852 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2853 MXGEFW_FLAGS_FIRST)));
0da34b6d
BG		 2854 idx = ((count - 1) + tx->req) & tx->mask;
2855 tx->info[idx].last = 1;
e454e7e2 2856 myri10ge_submit_req(tx, tx->req_list, count);
236bb5e6
BG		 2857 /* if using multiple tx queues, make sure NIC polls the
2858 * current slice */
2859 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2860 tx->queue_active = 1;
2861 put_be32(htonl(1), tx->send_go);
8c2f5fa5 2862 mb();
236bb5e6 2863 }
0da34b6d
BG		 2864 tx->pkt_start++;
2865 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
b53bef84 2866 tx->stop_queue++;
236bb5e6 2867 netif_tx_stop_queue(netdev_queue);
0da34b6d 2868 }
6ed10654 2869 return NETDEV_TX_OK;
0da34b6d
BG		 2870
2871abort_linearize:
10545937 2872 myri10ge_unmap_tx_dma(mgp, tx, idx);
0da34b6d 2873
89114afd 2874 if (skb_is_gso(skb)) {
78ca90ea 2875 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
0da34b6d
BG		 2876 goto drop;
2877 }
2878
bec0e859 2879 if (skb_linearize(skb))
0da34b6d
BG		 2880 goto drop;
2881
b53bef84 2882 tx->linearized++;
0da34b6d
BG		 2883 goto again;
2884
2885drop:
2886 dev_kfree_skb_any(skb);
b53bef84 2887 ss->stats.tx_dropped += 1;
6ed10654 2888 return NETDEV_TX_OK;
0da34b6d
BG		 2889
2890}
2891
61357325
SH		 2892static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2893 struct net_device *dev)
4f93fde0
BG		 2894{
2895 struct sk_buff *segs, *curr;
b53bef84 2896 struct myri10ge_priv *mgp = netdev_priv(dev);
d6279c88 2897 struct myri10ge_slice_state *ss;
61357325 2898 netdev_tx_t status;
4f93fde0
BG		 2899
2900 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
801678c5 2901 if (IS_ERR(segs))
4f93fde0
BG		 2902 goto drop;
2903
2904 while (segs) {
2905 curr = segs;
2906 segs = segs->next;
2907 curr->next = NULL;
2908 status = myri10ge_xmit(curr, dev);
2909 if (status != 0) {
2910 dev_kfree_skb_any(curr);
2911 if (segs != NULL) {
2912 curr = segs;
2913 segs = segs->next;
2914 curr->next = NULL;
2915 dev_kfree_skb_any(segs);
2916 }
2917 goto drop;
2918 }
2919 }
2920 dev_kfree_skb_any(skb);
ec634fe3 2921 return NETDEV_TX_OK;
4f93fde0
BG		 2922
2923drop:
d6279c88 2924 ss = &mgp->ss[skb_get_queue_mapping(skb)];
4f93fde0 2925 dev_kfree_skb_any(skb);
d6279c88 2926 ss->stats.tx_dropped += 1;
ec634fe3 2927 return NETDEV_TX_OK;
4f93fde0
BG		 2928}
2929
bc1f4470 2930static void myri10ge_get_stats(struct net_device *dev,
2931 struct rtnl_link_stats64 *stats)
0da34b6d 2932{
306ff6eb
ED		 2933 const struct myri10ge_priv *mgp = netdev_priv(dev);
2934 const struct myri10ge_slice_netstats *slice_stats;
0dcffac1
BG		 2935 int i;
2936
0dcffac1
BG		 2937 for (i = 0; i < mgp->num_slices; i++) {
2938 slice_stats = &mgp->ss[i].stats;
2939 stats->rx_packets += slice_stats->rx_packets;
2940 stats->tx_packets += slice_stats->tx_packets;
2941 stats->rx_bytes += slice_stats->rx_bytes;
2942 stats->tx_bytes += slice_stats->tx_bytes;
2943 stats->rx_dropped += slice_stats->rx_dropped;
2944 stats->tx_dropped += slice_stats->tx_dropped;
2945 }
0da34b6d
BG		 2946}
2947
2948static void myri10ge_set_multicast_list(struct net_device *dev)
2949{
b53bef84 2950 struct myri10ge_priv *mgp = netdev_priv(dev);
85a7ea1b 2951 struct myri10ge_cmd cmd;
22bedad3 2952 struct netdev_hw_addr *ha;
6250223e 2953 __be32 data[2] = { 0, 0 };
85a7ea1b
BG		 2954 int err;
2955
0da34b6d
BG		 2956 /* can be called from atomic contexts,
2957 * pass 1 to force atomicity in myri10ge_send_cmd() */
85a7ea1b
BG		 2958 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2959
2960 /* This firmware is known to not support multicast */
2f76216f 2961 if (!mgp->fw_multicast_support)
85a7ea1b
BG		 2962 return;
2963
2964 /* Disable multicast filtering */
2965
2966 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2967 if (err != 0) {
78ca90ea
JP		 2968 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
2969 err);
85a7ea1b
BG		 2970 goto abort;
2971 }
2972
2f76216f 2973 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
85a7ea1b
BG		 2974 /* request to disable multicast filtering, so quit here */
2975 return;
2976 }
2977
2978 /* Flush the filters */
2979
2980 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2981 &cmd, 1);
2982 if (err != 0) {
78ca90ea
JP		 2983 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
2984 err);
85a7ea1b
BG		 2985 goto abort;
2986 }
2987
2988 /* Walk the multicast list, and add each address */
22bedad3 2989 netdev_for_each_mc_addr(ha, dev) {
d458cdf7 2990 memcpy(data, &ha->addr, ETH_ALEN);
40f6cff5
AV		 2991 cmd.data0 = ntohl(data[0]);
2992 cmd.data1 = ntohl(data[1]);
85a7ea1b
BG		 2993 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2994 &cmd, 1);
2995
2996 if (err != 0) {
78ca90ea 2997 netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
22bedad3 2998 err, ha->addr);
85a7ea1b
BG		 2999 goto abort;
3000 }
3001 }
3002 /* Enable multicast filtering */
3003 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3004 if (err != 0) {
78ca90ea
JP		 3005 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3006 err);
85a7ea1b
BG		 3007 goto abort;
3008 }
3009
3010 return;
3011
3012abort:
3013 return;
0da34b6d
BG		 3014}
3015
3016static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3017{
3018 struct sockaddr *sa = addr;
3019 struct myri10ge_priv *mgp = netdev_priv(dev);
3020 int status;
3021
3022 if (!is_valid_ether_addr(sa->sa_data))
3023 return -EADDRNOTAVAIL;
3024
3025 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3026 if (status != 0) {
78ca90ea
JP		 3027 netdev_err(dev, "changing mac address failed with %d\n",
3028 status);
0da34b6d
BG		 3029 return status;
3030 }
3031
3032 /* change the dev structure */
d458cdf7 3033 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
0da34b6d
BG		 3034 return 0;
3035}
3036
3037static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3038{
3039 struct myri10ge_priv *mgp = netdev_priv(dev);
3040 int error = 0;
3041
78ca90ea 3042 netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
0da34b6d
BG		 3043 if (mgp->running) {
3044 /* if we change the mtu on an active device, we must
3045 * reset the device so the firmware sees the change */
3046 myri10ge_close(dev);
3047 dev->mtu = new_mtu;
3048 myri10ge_open(dev);
3049 } else
3050 dev->mtu = new_mtu;
3051
3052 return error;
3053}
3054
3055/*
3056 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3057 * Only do it if the bridge is a root port since we don't want to disturb
3058 * any other device, except if forced with myri10ge_ecrc_enable > 1.
3059 */
3060
0da34b6d
BG		 3061static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3062{
3063 struct pci_dev *bridge = mgp->pdev->bus->self;
3064 struct device *dev = &mgp->pdev->dev;
effd1eda 3065 int cap;
0da34b6d 3066 unsigned err_cap;
0da34b6d
BG		 3067 int ret;
3068
3069 if (!myri10ge_ecrc_enable || !bridge)
3070 return;
3071
3072 /* check that the bridge is a root port */
9503e255 3073 if (pci_pcie_type(bridge) != PCI_EXP_TYPE_ROOT_PORT) {
0da34b6d 3074 if (myri10ge_ecrc_enable > 1) {
eca3fd83 3075 struct pci_dev *prev_bridge, *old_bridge = bridge;
0da34b6d
BG		 3076
3077 /* Walk the hierarchy up to the root port
3078 * where ECRC has to be enabled */
3079 do {
eca3fd83 3080 prev_bridge = bridge;
0da34b6d 3081 bridge = bridge->bus->self;
eca3fd83 3082 if (!bridge || prev_bridge == bridge) {
0da34b6d
BG		 3083 dev_err(dev,
3084 "Failed to find root port"
3085 " to force ECRC\n");
3086 return;
3087 }
9503e255
JL		 3088 } while (pci_pcie_type(bridge) !=
3089 PCI_EXP_TYPE_ROOT_PORT);
0da34b6d
BG		 3090
3091 dev_info(dev,
3092 "Forcing ECRC on non-root port %s"
3093 " (enabling on root port %s)\n",
3094 pci_name(old_bridge), pci_name(bridge));
3095 } else {
3096 dev_err(dev,
3097 "Not enabling ECRC on non-root port %s\n",
3098 pci_name(bridge));
3099 return;
3100 }
3101 }
3102
3103 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
0da34b6d
BG		 3104 if (!cap)
3105 return;
3106
3107 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3108 if (ret) {
3109 dev_err(dev, "failed reading ext-conf-space of %s\n",
3110 pci_name(bridge));
3111 dev_err(dev, "\t pci=nommconf in use? "
3112 "or buggy/incomplete/absent ACPI MCFG attr?\n");
3113 return;
3114 }
3115 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3116 return;
3117
3118 err_cap |= PCI_ERR_CAP_ECRC_GENE;
3119 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3120 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
0da34b6d
BG		 3121}
3122
3123/*
3124 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3125 * when the PCI-E Completion packets are aligned on an 8-byte
3126 * boundary. Some PCI-E chip sets always align Completion packets; on
3127 * the ones that do not, the alignment can be enforced by enabling
3128 * ECRC generation (if supported).
3129 *
3130 * When PCI-E Completion packets are not aligned, it is actually more
3131 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3132 *
3133 * If the driver can neither enable ECRC nor verify that it has
3134 * already been enabled, then it must use a firmware image which works
0dcffac1 3135 * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
0da34b6d 3136 * should also ensure that it never gives the device a Read-DMA which is
b53bef84 3137 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
0dcffac1 3138 * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
b53bef84 3139 * firmware image, and set tx_boundary to 4KB.
0da34b6d
BG		 3140 */
3141
5443e9ea 3142static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
0da34b6d 3143{
5443e9ea
BG		 3144 struct pci_dev *pdev = mgp->pdev;
3145 struct device *dev = &pdev->dev;
302d242c 3146 int status;
0da34b6d 3147
b53bef84 3148 mgp->tx_boundary = 4096;
5443e9ea
BG		 3149 /*
3150 * Verify the max read request size was set to 4KB
3151 * before trying the test with 4KB.
3152 */
302d242c
BG		 3153 status = pcie_get_readrq(pdev);
3154 if (status < 0) {
5443e9ea
BG		 3155 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3156 goto abort;
3157 }
302d242c
BG		 3158 if (status != 4096) {
3159 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
b53bef84 3160 mgp->tx_boundary = 2048;
5443e9ea
BG		 3161 }
3162 /*
3163 * load the optimized firmware (which assumes aligned PCIe
3164 * completions) in order to see if it works on this host.
3165 */
7d351035 3166 set_fw_name(mgp, myri10ge_fw_aligned, false);
0dcffac1 3167 status = myri10ge_load_firmware(mgp, 1);
5443e9ea
BG		 3168 if (status != 0) {
3169 goto abort;
3170 }
3171
3172 /*
3173 * Enable ECRC if possible
3174 */
3175 myri10ge_enable_ecrc(mgp);
3176
3177 /*
3178 * Run a DMA test which watches for unaligned completions and
3179 * aborts on the first one seen.
3180 */
3181
3182 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3183 if (status == 0)
3184 return; /* keep the aligned firmware */
3185
3186 if (status != -E2BIG)
3187 dev_warn(dev, "DMA test failed: %d\n", status);
3188 if (status == -ENOSYS)
3189 dev_warn(dev, "Falling back to ethp! "
3190 "Please install up to date fw\n");
3191abort:
3192 /* fall back to using the unaligned firmware */
b53bef84 3193 mgp->tx_boundary = 2048;
7d351035 3194 set_fw_name(mgp, myri10ge_fw_unaligned, false);
5443e9ea
BG		 3195}
3196
3197static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3198{
2d90b0aa
BG		 3199 int overridden = 0;
3200
0da34b6d 3201 if (myri10ge_force_firmware == 0) {
9503e255 3202 int link_width;
ce7f9368
BG		 3203 u16 lnk;
3204
9503e255 3205 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
ce7f9368
BG		 3206 link_width = (lnk >> 4) & 0x3f;
3207
ce7f9368
BG		 3208 /* Check to see if Link is less than 8 or if the
3209 * upstream bridge is known to provide aligned
3210 * completions */
3211 if (link_width < 8) {
3212 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3213 link_width);
b53bef84 3214 mgp->tx_boundary = 4096;
7d351035 3215 set_fw_name(mgp, myri10ge_fw_aligned, false);
5443e9ea
BG		 3216 } else {
3217 myri10ge_firmware_probe(mgp);
0da34b6d
BG		 3218 }
3219 } else {
3220 if (myri10ge_force_firmware == 1) {
3221 dev_info(&mgp->pdev->dev,
3222 "Assuming aligned completions (forced)\n");
b53bef84 3223 mgp->tx_boundary = 4096;
7d351035 3224 set_fw_name(mgp, myri10ge_fw_aligned, false);
0da34b6d
BG		 3225 } else {
3226 dev_info(&mgp->pdev->dev,
3227 "Assuming unaligned completions (forced)\n");
b53bef84 3228 mgp->tx_boundary = 2048;
7d351035 3229 set_fw_name(mgp, myri10ge_fw_unaligned, false);
0da34b6d
BG		 3230 }
3231 }
7d351035 3232
b51d23e4 3233 kernel_param_lock(THIS_MODULE);
0da34b6d 3234 if (myri10ge_fw_name != NULL) {
7d351035
RR		 3235 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3236 if (fw_name) {
3237 overridden = 1;
3238 set_fw_name(mgp, fw_name, true);
3239 }
0da34b6d 3240 }
b51d23e4 3241 kernel_param_unlock(THIS_MODULE);
7d351035 3242
2d90b0aa
BG		 3243 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3244 myri10ge_fw_names[mgp->board_number] != NULL &&
3245 strlen(myri10ge_fw_names[mgp->board_number])) {
7d351035 3246 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
2d90b0aa
BG		 3247 overridden = 1;
3248 }
3249 if (overridden)
3250 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3251 mgp->fw_name);
0da34b6d
BG		 3252}
3253
7539a613
JM		 3254static void myri10ge_mask_surprise_down(struct pci_dev *pdev)
3255{
3256 struct pci_dev *bridge = pdev->bus->self;
3257 int cap;
3258 u32 mask;
3259
3260 if (bridge == NULL)
3261 return;
3262
3263 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3264 if (cap) {
3265 /* a sram parity error can cause a surprise link
3266 * down; since we expect and can recover from sram
3267 * parity errors, mask surprise link down events */
3268 pci_read_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, &mask);
3269 mask |= 0x20;
3270 pci_write_config_dword(bridge, cap + PCI_ERR_UNCOR_MASK, mask);
3271 }
3272}
3273
0da34b6d 3274#ifdef CONFIG_PM
0da34b6d
BG		 3275static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3276{
3277 struct myri10ge_priv *mgp;
3278 struct net_device *netdev;
3279
3280 mgp = pci_get_drvdata(pdev);
3281 if (mgp == NULL)
3282 return -EINVAL;
3283 netdev = mgp->dev;
3284
3285 netif_device_detach(netdev);
3286 if (netif_running(netdev)) {
78ca90ea 3287 netdev_info(netdev, "closing\n");
0da34b6d
BG		 3288 rtnl_lock();
3289 myri10ge_close(netdev);
3290 rtnl_unlock();
3291 }
3292 myri10ge_dummy_rdma(mgp, 0);
83f6e152 3293 pci_save_state(pdev);
0da34b6d 3294 pci_disable_device(pdev);
1a63e846
BG		 3295
3296 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
0da34b6d
BG		 3297}
3298
3299static int myri10ge_resume(struct pci_dev *pdev)
3300{
3301 struct myri10ge_priv *mgp;
3302 struct net_device *netdev;
3303 int status;
3304 u16 vendor;
3305
3306 mgp = pci_get_drvdata(pdev);
3307 if (mgp == NULL)
3308 return -EINVAL;
3309 netdev = mgp->dev;
1ca01512 3310 pci_set_power_state(pdev, PCI_D0); /* zeros conf space as a side effect */
0da34b6d
BG		 3311 msleep(5); /* give card time to respond */
3312 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3313 if (vendor == 0xffff) {
78ca90ea 3314 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3315 return -EIO;
3316 }
83f6e152 3317
1d3c16a8 3318 pci_restore_state(pdev);
4c2248cc
BG		 3319
3320 status = pci_enable_device(pdev);
1a63e846 3321 if (status) {
4c2248cc 3322 dev_err(&pdev->dev, "failed to enable device\n");
1a63e846 3323 return status;
4c2248cc
BG		 3324 }
3325
0da34b6d
BG		 3326 pci_set_master(pdev);
3327
0da34b6d 3328 myri10ge_reset(mgp);
013b68bf 3329 myri10ge_dummy_rdma(mgp, 1);
0da34b6d
BG		 3330
3331 /* Save configuration space to be restored if the
3332 * nic resets due to a parity error */
83f6e152 3333 pci_save_state(pdev);
0da34b6d
BG		 3334
3335 if (netif_running(netdev)) {
3336 rtnl_lock();
df30a740 3337 status = myri10ge_open(netdev);
0da34b6d 3338 rtnl_unlock();
df30a740
BG		 3339 if (status != 0)
3340 goto abort_with_enabled;
3341
0da34b6d
BG		 3342 }
3343 netif_device_attach(netdev);
3344
3345 return 0;
3346
4c2248cc
BG		 3347abort_with_enabled:
3348 pci_disable_device(pdev);
0da34b6d
BG		 3349 return -EIO;
3350
3351}
0da34b6d
BG		 3352#endif /* CONFIG_PM */
3353
3354static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3355{
3356 struct pci_dev *pdev = mgp->pdev;
3357 int vs = mgp->vendor_specific_offset;
3358 u32 reboot;
3359
3360 /*enter read32 mode */
3361 pci_write_config_byte(pdev, vs + 0x10, 0x3);
3362
3363 /*read REBOOT_STATUS (0xfffffff0) */
3364 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3365 pci_read_config_dword(pdev, vs + 0x14, &reboot);
3366 return reboot;
3367}
3368
c689b81b
JM		 3369static void
3370myri10ge_check_slice(struct myri10ge_slice_state *ss, int *reset_needed,
3371 int *busy_slice_cnt, u32 rx_pause_cnt)
3372{
3373 struct myri10ge_priv *mgp = ss->mgp;
3374 int slice = ss - mgp->ss;
3375
3376 if (ss->tx.req != ss->tx.done &&
3377 ss->tx.done == ss->watchdog_tx_done &&
3378 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3379 /* nic seems like it might be stuck.. */
3380 if (rx_pause_cnt != mgp->watchdog_pause) {
3381 if (net_ratelimit())
3382 netdev_warn(mgp->dev, "slice %d: TX paused, "
3383 "check link partner\n", slice);
3384 } else {
3385 netdev_warn(mgp->dev,
3386 "slice %d: TX stuck %d %d %d %d %d %d\n",
3387 slice, ss->tx.queue_active, ss->tx.req,
3388 ss->tx.done, ss->tx.pkt_start,
3389 ss->tx.pkt_done,
3390 (int)ntohl(mgp->ss[slice].fw_stats->
3391 send_done_count));
3392 *reset_needed = 1;
3393 ss->stuck = 1;
3394 }
3395 }
3396 if (ss->watchdog_tx_done != ss->tx.done ||
3397 ss->watchdog_rx_done != ss->rx_done.cnt) {
3398 *busy_slice_cnt += 1;
3399 }
3400 ss->watchdog_tx_done = ss->tx.done;
3401 ss->watchdog_tx_req = ss->tx.req;
3402 ss->watchdog_rx_done = ss->rx_done.cnt;
3403}
3404
0da34b6d
BG		 3405/*
3406 * This watchdog is used to check whether the board has suffered
3407 * from a parity error and needs to be recovered.
3408 */
c4028958 3409static void myri10ge_watchdog(struct work_struct *work)
0da34b6d 3410{
c4028958 3411 struct myri10ge_priv *mgp =
6250223e 3412 container_of(work, struct myri10ge_priv, watchdog_work);
c689b81b
JM		 3413 struct myri10ge_slice_state *ss;
3414 u32 reboot, rx_pause_cnt;
d0234215 3415 int status, rebooted;
0dcffac1 3416 int i;
c689b81b
JM		 3417 int reset_needed = 0;
3418 int busy_slice_cnt = 0;
0da34b6d
BG		 3419 u16 cmd, vendor;
3420
3421 mgp->watchdog_resets++;
3422 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
d0234215 3423 rebooted = 0;
0da34b6d
BG		 3424 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3425 /* Bus master DMA disabled? Check to see
3426 * if the card rebooted due to a parity error
3427 * For now, just report it */
3428 reboot = myri10ge_read_reboot(mgp);
78ca90ea 3429 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
c689b81b 3430 reboot, myri10ge_reset_recover ? "" : " not");
f181137f
BG		 3431 if (myri10ge_reset_recover == 0)
3432 return;
d0234215
BG		 3433 rtnl_lock();
3434 mgp->rebooted = 1;
3435 rebooted = 1;
3436 myri10ge_close(mgp->dev);
f181137f 3437 myri10ge_reset_recover--;
d0234215 3438 mgp->rebooted = 0;
0da34b6d
BG		 3439 /*
3440 * A rebooted nic will come back with config space as
3441 * it was after power was applied to PCIe bus.
3442 * Attempt to restore config space which was saved
3443 * when the driver was loaded, or the last time the
3444 * nic was resumed from power saving mode.
3445 */
83f6e152 3446 pci_restore_state(mgp->pdev);
7adda30c
BG		 3447
3448 /* save state again for accounting reasons */
83f6e152 3449 pci_save_state(mgp->pdev);
7adda30c 3450
0da34b6d
BG		 3451 } else {
3452 /* if we get back -1's from our slot, perhaps somebody
3453 * powered off our card. Don't try to reset it in
3454 * this case */
3455 if (cmd == 0xffff) {
3456 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3457 if (vendor == 0xffff) {
78ca90ea 3458 netdev_err(mgp->dev, "device disappeared!\n");
0da34b6d
BG		 3459 return;
3460 }
3461 }
c689b81b
JM		 3462 /* Perhaps it is a software error. See if stuck slice
3463 * has recovered, reset if not */
3464 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
0dcffac1 3465 for (i = 0; i < mgp->num_slices; i++) {
c689b81b
JM		 3466 ss = mgp->ss;
3467 if (ss->stuck) {
3468 myri10ge_check_slice(ss, &reset_needed,
3469 &busy_slice_cnt,
3470 rx_pause_cnt);
3471 ss->stuck = 0;
3472 }
0dcffac1 3473 }
c689b81b
JM		 3474 if (!reset_needed) {
3475 netdev_dbg(mgp->dev, "not resetting\n");
3476 return;
3477 }
3478
3479 netdev_err(mgp->dev, "device timeout, resetting\n");
0da34b6d 3480 }
236bb5e6 3481
d0234215
BG		 3482 if (!rebooted) {
3483 rtnl_lock();
3484 myri10ge_close(mgp->dev);
3485 }
0dcffac1 3486 status = myri10ge_load_firmware(mgp, 1);
0da34b6d 3487 if (status != 0)
78ca90ea 3488 netdev_err(mgp->dev, "failed to load firmware\n");
0da34b6d
BG		 3489 else
3490 myri10ge_open(mgp->dev);
3491 rtnl_unlock();
3492}
3493
3494/*
3495 * We use our own timer routine rather than relying upon
3496 * netdev->tx_timeout because we have a very large hardware transmit
3497 * queue. Due to the large queue, the netdev->tx_timeout function
3498 * cannot detect a NIC with a parity error in a timely fashion if the
3499 * NIC is lightly loaded.
3500 */
e99e88a9 3501static void myri10ge_watchdog_timer(struct timer_list *t)
0da34b6d
BG		 3502{
3503 struct myri10ge_priv *mgp;
b53bef84 3504 struct myri10ge_slice_state *ss;
d0234215 3505 int i, reset_needed, busy_slice_cnt;
626fda94 3506 u32 rx_pause_cnt;
d0234215 3507 u16 cmd;
0da34b6d 3508
e99e88a9 3509 mgp = from_timer(mgp, t, watchdog_timer);
c7dab99b 3510
0dcffac1 3511 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
d0234215 3512 busy_slice_cnt = 0;
0dcffac1
BG		 3513 for (i = 0, reset_needed = 0;
3514 i < mgp->num_slices && reset_needed == 0; ++i) {
b53bef84 3515
0dcffac1
BG		 3516 ss = &mgp->ss[i];
3517 if (ss->rx_small.watchdog_needed) {
3518 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3519 mgp->small_bytes + MXGEFW_PAD,
3520 1);
3521 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3522 myri10ge_fill_thresh)
3523 ss->rx_small.watchdog_needed = 0;
3524 }
3525 if (ss->rx_big.watchdog_needed) {
3526 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3527 mgp->big_bytes, 1);
3528 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3529 myri10ge_fill_thresh)
3530 ss->rx_big.watchdog_needed = 0;
3531 }
c689b81b
JM		 3532 myri10ge_check_slice(ss, &reset_needed, &busy_slice_cnt,
3533 rx_pause_cnt);
d0234215
BG		 3534 }
3535 /* if we've sent or received no traffic, poll the NIC to
3536 * ensure it is still there. Otherwise, we risk not noticing
3537 * an error in a timely fashion */
3538 if (busy_slice_cnt == 0) {
3539 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3540 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3541 reset_needed = 1;
3542 }
626fda94 3543 }
626fda94 3544 mgp->watchdog_pause = rx_pause_cnt;
0dcffac1
BG		 3545
3546 if (reset_needed) {
3547 schedule_work(&mgp->watchdog_work);
3548 } else {
3549 /* rearm timer */
3550 mod_timer(&mgp->watchdog_timer,
3551 jiffies + myri10ge_watchdog_timeout * HZ);
3552 }
0da34b6d
BG		 3553}
3554
77929732
BG		 3555static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3556{
3557 struct myri10ge_slice_state *ss;
3558 struct pci_dev *pdev = mgp->pdev;
3559 size_t bytes;
3560 int i;
3561
3562 if (mgp->ss == NULL)
3563 return;
3564
3565 for (i = 0; i < mgp->num_slices; i++) {
3566 ss = &mgp->ss[i];
3567 if (ss->rx_done.entry != NULL) {
3568 bytes = mgp->max_intr_slots *
3569 sizeof(*ss->rx_done.entry);
3570 dma_free_coherent(&pdev->dev, bytes,
3571 ss->rx_done.entry, ss->rx_done.bus);
3572 ss->rx_done.entry = NULL;
3573 }
3574 if (ss->fw_stats != NULL) {
3575 bytes = sizeof(*ss->fw_stats);
3576 dma_free_coherent(&pdev->dev, bytes,
3577 ss->fw_stats, ss->fw_stats_bus);
3578 ss->fw_stats = NULL;
3579 }
0dde8026 3580 napi_hash_del(&ss->napi);
b3b6ae2c 3581 netif_napi_del(&ss->napi);
77929732 3582 }
0dde8026
HYK		 3583 /* Wait till napi structs are no longer used, and then free ss. */
3584 synchronize_rcu();
77929732
BG		 3585 kfree(mgp->ss);
3586 mgp->ss = NULL;
3587}
3588
3589static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3590{
3591 struct myri10ge_slice_state *ss;
3592 struct pci_dev *pdev = mgp->pdev;
3593 size_t bytes;
3594 int i;
3595
3596 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3597 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3598 if (mgp->ss == NULL) {
3599 return -ENOMEM;
3600 }
3601
3602 for (i = 0; i < mgp->num_slices; i++) {
3603 ss = &mgp->ss[i];
3604 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
750afb08
LC		 3605 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3606 &ss->rx_done.bus,
3607 GFP_KERNEL);
77929732
BG		 3608 if (ss->rx_done.entry == NULL)
3609 goto abort;
77929732
BG		 3610 bytes = sizeof(*ss->fw_stats);
3611 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3612 &ss->fw_stats_bus,
3613 GFP_KERNEL);
3614 if (ss->fw_stats == NULL)
3615 goto abort;
3616 ss->mgp = mgp;
3617 ss->dev = mgp->dev;
3618 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3619 myri10ge_napi_weight);
3620 }
3621 return 0;
3622abort:
3623 myri10ge_free_slices(mgp);
3624 return -ENOMEM;
3625}
3626
3627/*
3628 * This function determines the number of slices supported.
25985edc 3629 * The number slices is the minimum of the number of CPUS,
77929732
BG		 3630 * the number of MSI-X irqs supported, the number of slices
3631 * supported by the firmware
3632 */
3633static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3634{
3635 struct myri10ge_cmd cmd;
3636 struct pci_dev *pdev = mgp->pdev;
3637 char *old_fw;
7d351035 3638 bool old_allocated;
40b29562 3639 int i, status, ncpus;
77929732
BG		 3640
3641 mgp->num_slices = 1;
98f2d21f 3642 ncpus = netif_get_num_default_rss_queues();
77929732 3643
40b29562 3644 if (myri10ge_max_slices == 1 || !pdev->msix_cap ||
77929732
BG		 3645 (myri10ge_max_slices == -1 && ncpus < 2))
3646 return;
3647
3648 /* try to load the slice aware rss firmware */
3649 old_fw = mgp->fw_name;
7d351035
RR		 3650 old_allocated = mgp->fw_name_allocated;
3651 /* don't free old_fw if we override it. */
3652 mgp->fw_name_allocated = false;
3653
13b2738c
BG		 3654 if (myri10ge_fw_name != NULL) {
3655 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3656 myri10ge_fw_name);
7d351035 3657 set_fw_name(mgp, myri10ge_fw_name, false);
13b2738c 3658 } else if (old_fw == myri10ge_fw_aligned)
7d351035 3659 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
77929732 3660 else
7d351035 3661 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
77929732
BG		 3662 status = myri10ge_load_firmware(mgp, 0);
3663 if (status != 0) {
3664 dev_info(&pdev->dev, "Rss firmware not found\n");
7d351035
RR		 3665 if (old_allocated)
3666 kfree(old_fw);
77929732
BG		 3667 return;
3668 }
3669
3670 /* hit the board with a reset to ensure it is alive */
3671 memset(&cmd, 0, sizeof(cmd));
3672 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3673 if (status != 0) {
3674 dev_err(&mgp->pdev->dev, "failed reset\n");
3675 goto abort_with_fw;
77929732
BG		 3676 }
3677
3678 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3679
3680 /* tell it the size of the interrupt queues */
3681 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3682 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3683 if (status != 0) {
3684 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3685 goto abort_with_fw;
3686 }
3687
3688 /* ask the maximum number of slices it supports */
3689 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3690 if (status != 0)
3691 goto abort_with_fw;
3692 else
3693 mgp->num_slices = cmd.data0;
3694
3695 /* Only allow multiple slices if MSI-X is usable */
3696 if (!myri10ge_msi) {
3697 goto abort_with_fw;
3698 }
3699
3700 /* if the admin did not specify a limit to how many
3701 * slices we should use, cap it automatically to the
3702 * number of CPUs currently online */
3703 if (myri10ge_max_slices == -1)
3704 myri10ge_max_slices = ncpus;
3705
3706 if (mgp->num_slices > myri10ge_max_slices)
3707 mgp->num_slices = myri10ge_max_slices;
3708
3709 /* Now try to allocate as many MSI-X vectors as we have
3710 * slices. We give up on MSI-X if we can only get a single
3711 * vector. */
3712
baeb2ffa
JP		 3713 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3714 GFP_KERNEL);
77929732 3715 if (mgp->msix_vectors == NULL)
0729cc0c 3716 goto no_msix;
77929732
BG		 3717 for (i = 0; i < mgp->num_slices; i++) {
3718 mgp->msix_vectors[i].entry = i;
3719 }
3720
3721 while (mgp->num_slices > 1) {
0729cc0c 3722 mgp->num_slices = rounddown_pow_of_two(mgp->num_slices);
77929732 3723 if (mgp->num_slices == 1)
0729cc0c
AG		 3724 goto no_msix;
3725 status = pci_enable_msix_range(pdev,
3726 mgp->msix_vectors,
3727 mgp->num_slices,
3728 mgp->num_slices);
3729 if (status < 0)
3730 goto no_msix;
3731
3732 pci_disable_msix(pdev);
3733
3734 if (status == mgp->num_slices) {
7d351035
RR		 3735 if (old_allocated)
3736 kfree(old_fw);
77929732 3737 return;
0729cc0c 3738 } else {
77929732 3739 mgp->num_slices = status;
0729cc0c 3740 }
77929732
BG		 3741 }
3742
0729cc0c 3743no_msix:
77929732
BG		 3744 if (mgp->msix_vectors != NULL) {
3745 kfree(mgp->msix_vectors);
3746 mgp->msix_vectors = NULL;
3747 }
3748
3749abort_with_fw:
3750 mgp->num_slices = 1;
7d351035 3751 set_fw_name(mgp, old_fw, old_allocated);
77929732
BG		 3752 myri10ge_load_firmware(mgp, 0);
3753}
77929732 3754
8126089f
SH		 3755static const struct net_device_ops myri10ge_netdev_ops = {
3756 .ndo_open = myri10ge_open,
3757 .ndo_stop = myri10ge_close,
3758 .ndo_start_xmit = myri10ge_xmit,
c5f7ef72 3759 .ndo_get_stats64 = myri10ge_get_stats,
8126089f
SH		 3760 .ndo_validate_addr = eth_validate_addr,
3761 .ndo_change_mtu = myri10ge_change_mtu,
afc4b13d 3762 .ndo_set_rx_mode = myri10ge_set_multicast_list,
8126089f
SH		 3763 .ndo_set_mac_address = myri10ge_set_mac_address,
3764};
3765
0da34b6d
BG		 3766static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3767{
3768 struct net_device *netdev;
3769 struct myri10ge_priv *mgp;
3770 struct device *dev = &pdev->dev;
0da34b6d
BG		 3771 int i;
3772 int status = -ENXIO;
0da34b6d 3773 int dac_enabled;
00b5e505 3774 unsigned hdr_offset, ss_offset;
2d90b0aa 3775 static int board_number;
0da34b6d 3776
236bb5e6 3777 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
41de8d4c 3778 if (netdev == NULL)
0da34b6d 3779 return -ENOMEM;
0da34b6d 3780
b245fb67
MH		 3781 SET_NETDEV_DEV(netdev, &pdev->dev);
3782
0da34b6d 3783 mgp = netdev_priv(netdev);
0da34b6d
BG		 3784 mgp->dev = netdev;
3785 mgp->pdev = pdev;
0da34b6d
BG		 3786 mgp->pause = myri10ge_flow_control;
3787 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
c58ac5ca 3788 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2d90b0aa 3789 mgp->board_number = board_number;
0da34b6d
BG		 3790 init_waitqueue_head(&mgp->down_wq);
3791
3792 if (pci_enable_device(pdev)) {
3793 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3794 status = -ENODEV;
3795 goto abort_with_netdev;
3796 }
0da34b6d
BG		 3797
3798 /* Find the vendor-specific cap so we can check
3799 * the reboot register later on */
3800 mgp->vendor_specific_offset
3801 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3802
3803 /* Set our max read request to 4KB */
302d242c 3804 status = pcie_set_readrq(pdev, 4096);
0da34b6d
BG		 3805 if (status != 0) {
3806 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3807 status);
e3fd5534 3808 goto abort_with_enabled;
0da34b6d
BG		 3809 }
3810
7539a613 3811 myri10ge_mask_surprise_down(pdev);
0da34b6d
BG		 3812 pci_set_master(pdev);
3813 dac_enabled = 1;
6a35528a 3814 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
0da34b6d
BG		 3815 if (status != 0) {
3816 dac_enabled = 0;
3817 dev_err(&pdev->dev,
898eb71c
JP		 3818 "64-bit pci address mask was refused, "
3819 "trying 32-bit\n");
284901a9 3820 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
0da34b6d
BG		 3821 }
3822 if (status != 0) {
3823 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
e3fd5534 3824 goto abort_with_enabled;
0da34b6d 3825 }
6a35528a 3826 (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
b10c0668
BG		 3827 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3828 &mgp->cmd_bus, GFP_KERNEL);
f12e77ca
JL		 3829 if (!mgp->cmd) {
3830 status = -ENOMEM;
e3fd5534 3831 goto abort_with_enabled;
f12e77ca 3832 }
0da34b6d 3833
0da34b6d
BG		 3834 mgp->board_span = pci_resource_len(pdev, 0);
3835 mgp->iomem_base = pci_resource_start(pdev, 0);
e4b6c303 3836 mgp->wc_cookie = arch_phys_wc_add(mgp->iomem_base, mgp->board_span);
c7f80993 3837 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
0da34b6d
BG		 3838 if (mgp->sram == NULL) {
3839 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3840 mgp->board_span, mgp->iomem_base);
3841 status = -ENXIO;
c7f80993 3842 goto abort_with_mtrr;
0da34b6d 3843 }
00b5e505 3844 hdr_offset =
59e955ed 3845 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
00b5e505 3846 ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
59e955ed 3847 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
00b5e505
BG		 3848 if (mgp->sram_size > mgp->board_span ||
3849 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3850 dev_err(&pdev->dev,
3851 "invalid sram_size %dB or board span %ldB\n",
3852 mgp->sram_size, mgp->board_span);
3853 goto abort_with_ioremap;
3854 }
0da34b6d 3855 memcpy_fromio(mgp->eeprom_strings,
00b5e505 3856 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
0da34b6d
BG		 3857 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3858 status = myri10ge_read_mac_addr(mgp);
3859 if (status)
3860 goto abort_with_ioremap;
3861
3862 for (i = 0; i < ETH_ALEN; i++)
3863 netdev->dev_addr[i] = mgp->mac_addr[i];
3864
5443e9ea
BG		 3865 myri10ge_select_firmware(mgp);
3866
0dcffac1 3867 status = myri10ge_load_firmware(mgp, 1);
0da34b6d
BG		 3868 if (status != 0) {
3869 dev_err(&pdev->dev, "failed to load firmware\n");
0dcffac1
BG		 3870 goto abort_with_ioremap;
3871 }
3872 myri10ge_probe_slices(mgp);
3873 status = myri10ge_alloc_slices(mgp);
3874 if (status != 0) {
3875 dev_err(&pdev->dev, "failed to alloc slice state\n");
3876 goto abort_with_firmware;
0da34b6d 3877 }
c9920268
BH		 3878 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3879 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
0da34b6d
BG		 3880 status = myri10ge_reset(mgp);
3881 if (status != 0) {
3882 dev_err(&pdev->dev, "failed reset\n");
0dcffac1 3883 goto abort_with_slices;
0da34b6d 3884 }
5dd2d332 3885#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 3886 myri10ge_setup_dca(mgp);
3887#endif
0da34b6d 3888 pci_set_drvdata(pdev, mgp);
8126089f 3889
44770e11
JW		 3890 /* MTU range: 68 - 9000 */
3891 netdev->min_mtu = ETH_MIN_MTU;
3892 netdev->max_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3893
3894 if (myri10ge_initial_mtu > netdev->max_mtu)
3895 myri10ge_initial_mtu = netdev->max_mtu;
3896 if (myri10ge_initial_mtu < netdev->min_mtu)
3897 myri10ge_initial_mtu = netdev->min_mtu;
3898
0da34b6d 3899 netdev->mtu = myri10ge_initial_mtu;
44770e11
JW		 3900
3901 netdev->netdev_ops = &myri10ge_netdev_ops;
4ca3221f 3902 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
1b4c44e6 3903
f646968f
PM		 3904 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
3905 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1b4c44e6 3906
47c2cdf5 3907 netdev->features = netdev->hw_features;
236bb5e6 3908
0da34b6d
BG		 3909 if (dac_enabled)
3910 netdev->features |= NETIF_F_HIGHDMA;
0da34b6d 3911
dddc045e
BG		 3912 netdev->vlan_features |= mgp->features;
3913 if (mgp->fw_ver_tiny < 37)
3914 netdev->vlan_features &= ~NETIF_F_TSO6;
3915 if (mgp->fw_ver_tiny < 32)
3916 netdev->vlan_features &= ~NETIF_F_TSO;
3917
21d05db1 3918 /* make sure we can get an irq, and that MSI can be
a7425458 3919 * setup (if available). */
21d05db1
BG		 3920 status = myri10ge_request_irq(mgp);
3921 if (status != 0)
20fb7c7a 3922 goto abort_with_slices;
21d05db1
BG		 3923 myri10ge_free_irq(mgp);
3924
0da34b6d
BG		 3925 /* Save configuration space to be restored if the
3926 * nic resets due to a parity error */
83f6e152 3927 pci_save_state(pdev);
0da34b6d
BG		 3928
3929 /* Setup the watchdog timer */
e99e88a9 3930 timer_setup(&mgp->watchdog_timer, myri10ge_watchdog_timer, 0);
0da34b6d 3931
7ad24ea4 3932 netdev->ethtool_ops = &myri10ge_ethtool_ops;
c4028958 3933 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
0da34b6d
BG		 3934 status = register_netdev(netdev);
3935 if (status != 0) {
3936 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
7adda30c 3937 goto abort_with_state;
0da34b6d 3938 }
0dcffac1 3939 if (mgp->msix_enabled)
e4b6c303 3940 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, MTRR %s, WC Enabled\n",
0dcffac1 3941 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
e4b6c303 3942 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
0dcffac1 3943 else
e4b6c303 3944 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, MTRR %s, WC Enabled\n",
0dcffac1 3945 mgp->msi_enabled ? "MSI" : "xPIC",
a7425458 3946 pdev->irq, mgp->tx_boundary, mgp->fw_name,
e4b6c303 3947 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
0da34b6d 3948
2d90b0aa 3949 board_number++;
0da34b6d
BG		 3950 return 0;
3951
7adda30c 3952abort_with_state:
83f6e152 3953 pci_restore_state(pdev);
0da34b6d 3954
0dcffac1
BG		 3955abort_with_slices:
3956 myri10ge_free_slices(mgp);
3957
0da34b6d
BG		 3958abort_with_firmware:
3959 myri10ge_dummy_rdma(mgp, 0);
3960
0da34b6d 3961abort_with_ioremap:
0f840011
BG		 3962 if (mgp->mac_addr_string != NULL)
3963 dev_err(&pdev->dev,
3964 "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
3965 mgp->mac_addr_string, mgp->serial_number);
0da34b6d
BG		 3966 iounmap(mgp->sram);
3967
c7f80993 3968abort_with_mtrr:
e4b6c303 3969 arch_phys_wc_del(mgp->wc_cookie);
b10c0668
BG		 3970 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3971 mgp->cmd, mgp->cmd_bus);
0da34b6d 3972
e3fd5534
BG		 3973abort_with_enabled:
3974 pci_disable_device(pdev);
0da34b6d 3975
e3fd5534 3976abort_with_netdev:
7d351035 3977 set_fw_name(mgp, NULL, false);
0da34b6d
BG		 3978 free_netdev(netdev);
3979 return status;
3980}
3981
3982/*
3983 * myri10ge_remove
3984 *
3985 * Does what is necessary to shutdown one Myrinet device. Called
3986 * once for each Myrinet card by the kernel when a module is
3987 * unloaded.
3988 */
3989static void myri10ge_remove(struct pci_dev *pdev)
3990{
3991 struct myri10ge_priv *mgp;
3992 struct net_device *netdev;
0da34b6d
BG		 3993
3994 mgp = pci_get_drvdata(pdev);
3995 if (mgp == NULL)
3996 return;
3997
23f333a2 3998 cancel_work_sync(&mgp->watchdog_work);
0da34b6d
BG		 3999 netdev = mgp->dev;
4000 unregister_netdev(netdev);
0da34b6d 4001
5dd2d332 4002#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4003 myri10ge_teardown_dca(mgp);
4004#endif
0da34b6d
BG		 4005 myri10ge_dummy_rdma(mgp, 0);
4006
7adda30c 4007 /* avoid a memory leak */
83f6e152 4008 pci_restore_state(pdev);
7adda30c 4009
0da34b6d 4010 iounmap(mgp->sram);
e4b6c303 4011 arch_phys_wc_del(mgp->wc_cookie);
0dcffac1 4012 myri10ge_free_slices(mgp);
2d4ad4f6 4013 kfree(mgp->msix_vectors);
b10c0668
BG		 4014 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4015 mgp->cmd, mgp->cmd_bus);
0da34b6d 4016
7d351035 4017 set_fw_name(mgp, NULL, false);
0da34b6d 4018 free_netdev(netdev);
e3fd5534 4019 pci_disable_device(pdev);
0da34b6d
BG		 4020}
4021
b10c0668 4022#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
a07bc1ff 4023#define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
0da34b6d 4024
9baa3c34 4025static const struct pci_device_id myri10ge_pci_tbl[] = {
b10c0668 4026 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
a07bc1ff
BG		 4027 {PCI_DEVICE
4028 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
0da34b6d
BG		 4029 {0},
4030};
4031
97131079
BG		 4032MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4033
0da34b6d
BG		 4034static struct pci_driver myri10ge_driver = {
4035 .name = "myri10ge",
4036 .probe = myri10ge_probe,
4037 .remove = myri10ge_remove,
4038 .id_table = myri10ge_pci_tbl,
4039#ifdef CONFIG_PM
4040 .suspend = myri10ge_suspend,
4041 .resume = myri10ge_resume,
4042#endif
4043};
4044
5dd2d332 4045#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4046static int
4047myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4048{
4049 int err = driver_for_each_device(&myri10ge_driver.driver,
4050 NULL, &event,
4051 myri10ge_notify_dca_device);
4052
4053 if (err)
4054 return NOTIFY_BAD;
4055 return NOTIFY_DONE;
4056}
4057
4058static struct notifier_block myri10ge_dca_notifier = {
4059 .notifier_call = myri10ge_notify_dca,
4060 .next = NULL,
4061 .priority = 0,
4062};
4ee2ac51 4063#endif /* CONFIG_MYRI10GE_DCA */
981813d8 4064
0da34b6d
BG		 4065static __init int myri10ge_init_module(void)
4066{
78ca90ea 4067 pr_info("Version %s\n", MYRI10GE_VERSION_STR);
0dcffac1 4068
236bb5e6 4069 if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
78ca90ea
JP		 4070 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4071 myri10ge_rss_hash);
0dcffac1
BG		 4072 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4073 }
5dd2d332 4074#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4075 dca_register_notify(&myri10ge_dca_notifier);
4076#endif
236bb5e6
BG		 4077 if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4078 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
0dcffac1 4079
0da34b6d
BG		 4080 return pci_register_driver(&myri10ge_driver);
4081}
4082
4083module_init(myri10ge_init_module);
4084
4085static __exit void myri10ge_cleanup_module(void)
4086{
5dd2d332 4087#ifdef CONFIG_MYRI10GE_DCA
981813d8
BG		 4088 dca_unregister_notify(&myri10ge_dca_notifier);
4089#endif
0da34b6d
BG		 4090 pci_unregister_driver(&myri10ge_driver);
4091}
4092
4093module_exit(myri10ge_cleanup_module);
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