[thirdparty/linux.git] / drivers / pwm / pwm-bcm-kona.c

// SPDX-License-Identifier: GPL-2.0-only
// Copyright (C) 2014 Broadcom Corporation

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/types.h>

/*
 * The Kona PWM has some unusual characteristics.  Here are the main points.
 *
 * 1) There is no disable bit and the hardware docs advise programming a zero
 *    duty to achieve output equivalent to that of a normal disable operation.
 *
 * 2) Changes to prescale, duty, period, and polarity do not take effect until
 *    a subsequent rising edge of the trigger bit.
 *
 * 3) If the smooth bit and trigger bit are both low, the output is a constant
 *    high signal.  Otherwise, the earlier waveform continues to be output.
 *
 * 4) If the smooth bit is set on the rising edge of the trigger bit, output
 *    will transition to the new settings on a period boundary (which could be
 *    seconds away).  If the smooth bit is clear, new settings will be applied
 *    as soon as possible (the hardware always has a 400ns delay).
 *
 * 5) When the external clock that feeds the PWM is disabled, output is pegged
 *    high or low depending on its state at that exact instant.
 */

#define PWM_CONTROL_OFFSET			0x00000000
#define PWM_CONTROL_SMOOTH_SHIFT(chan)		(24 + (chan))
#define PWM_CONTROL_TYPE_SHIFT(chan)		(16 + (chan))
#define PWM_CONTROL_POLARITY_SHIFT(chan)	(8 + (chan))
#define PWM_CONTROL_TRIGGER_SHIFT(chan)		(chan)

#define PRESCALE_OFFSET				0x00000004
#define PRESCALE_SHIFT(chan)			((chan) << 2)
#define PRESCALE_MASK(chan)			(0x7 << PRESCALE_SHIFT(chan))
#define PRESCALE_MIN				0x00000000
#define PRESCALE_MAX				0x00000007

#define PERIOD_COUNT_OFFSET(chan)		(0x00000008 + ((chan) << 3))
#define PERIOD_COUNT_MIN			0x00000002
#define PERIOD_COUNT_MAX			0x00ffffff

#define DUTY_CYCLE_HIGH_OFFSET(chan)		(0x0000000c + ((chan) << 3))
#define DUTY_CYCLE_HIGH_MIN			0x00000000
#define DUTY_CYCLE_HIGH_MAX			0x00ffffff

struct kona_pwmc {
	void __iomem *base;
	struct clk *clk;
};

static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

/*
 * Clear trigger bit but set smooth bit to maintain old output.
 */
static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
	unsigned int chan)
{
	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);

	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
	writel(value, kp->base + PWM_CONTROL_OFFSET);

	/*
	 * There must be a min 400ns delay between clearing trigger and setting
	 * it. Failing to do this may result in no PWM signal.
	 */
	ndelay(400);
}

static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
{
	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);

	/* Set trigger bit and clear smooth bit to apply new settings */
	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
	writel(value, kp->base + PWM_CONTROL_OFFSET);

	/* Trigger bit must be held high for at least 400 ns. */
	ndelay(400);
}

static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    u64 duty_ns, u64 period_ns)
{
	struct kona_pwmc *kp = to_kona_pwmc(chip);
	u64 div, rate;
	unsigned long prescale = PRESCALE_MIN, pc, dc;
	unsigned int value, chan = pwm->hwpwm;

	/*
	 * Find period count, duty count and prescale to suit duty_ns and
	 * period_ns. This is done according to formulas described below:
	 *
	 * period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
	 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
	 *
	 * PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
	 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
	 */

	rate = clk_get_rate(kp->clk);

	while (1) {
		div = 1000000000;
		div *= 1 + prescale;
		pc = mul_u64_u64_div_u64(rate, period_ns, div);
		dc = mul_u64_u64_div_u64(rate, duty_ns, div);

		/* If duty_ns or period_ns are not achievable then return */
		if (pc < PERIOD_COUNT_MIN)
			return -EINVAL;

		/* If pc and dc are in bounds, the calculation is done */
		if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
			break;

		/* Otherwise, increase prescale and recalculate pc and dc */
		if (++prescale > PRESCALE_MAX)
			return -EINVAL;
	}

	kona_pwmc_prepare_for_settings(kp, chan);

	value = readl(kp->base + PRESCALE_OFFSET);
	value &= ~PRESCALE_MASK(chan);
	value |= prescale << PRESCALE_SHIFT(chan);
	writel(value, kp->base + PRESCALE_OFFSET);

	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));

	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));

	kona_pwmc_apply_settings(kp, chan);

	return 0;
}

static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
				  enum pwm_polarity polarity)
{
	struct kona_pwmc *kp = to_kona_pwmc(chip);
	unsigned int chan = pwm->hwpwm;
	unsigned int value;
	int ret;

	ret = clk_prepare_enable(kp->clk);
	if (ret < 0) {
		dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
		return ret;
	}

	kona_pwmc_prepare_for_settings(kp, chan);

	value = readl(kp->base + PWM_CONTROL_OFFSET);

	if (polarity == PWM_POLARITY_NORMAL)
		value |= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
	else
		value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));

	writel(value, kp->base + PWM_CONTROL_OFFSET);

	kona_pwmc_apply_settings(kp, chan);

	clk_disable_unprepare(kp->clk);

	return 0;
}

static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct kona_pwmc *kp = to_kona_pwmc(chip);
	int ret;

	ret = clk_prepare_enable(kp->clk);
	if (ret < 0) {
		dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
		return ret;
	}

	return 0;
}

static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct kona_pwmc *kp = to_kona_pwmc(chip);
	unsigned int chan = pwm->hwpwm;
	unsigned int value;

	kona_pwmc_prepare_for_settings(kp, chan);

	/* Simulate a disable by configuring for zero duty */
	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
	writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));

	/* Set prescale to 0 for this channel */
	value = readl(kp->base + PRESCALE_OFFSET);
	value &= ~PRESCALE_MASK(chan);
	writel(value, kp->base + PRESCALE_OFFSET);

	kona_pwmc_apply_settings(kp, chan);

	clk_disable_unprepare(kp->clk);
}

static int kona_pwmc_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	int err;
	struct kona_pwmc *kp = to_kona_pwmc(chip);
	bool enabled = pwm->state.enabled;

	if (state->polarity != pwm->state.polarity) {
		if (enabled) {
			kona_pwmc_disable(chip, pwm);
			enabled = false;
		}

		err = kona_pwmc_set_polarity(chip, pwm, state->polarity);
		if (err)
			return err;

		pwm->state.polarity = state->polarity;
	}

	if (!state->enabled) {
		if (enabled)
			kona_pwmc_disable(chip, pwm);
		return 0;
	} else if (!enabled) {
		/*
		 * This is a bit special here, usually the PWM should only be
		 * enabled when duty and period are setup. But before this
		 * driver was converted to .apply it was done the other way
		 * around and so this behaviour was kept even though this might
		 * result in a glitch. This might be improvable by someone with
		 * hardware and/or documentation.
		 */
		err = kona_pwmc_enable(chip, pwm);
		if (err)
			return err;
	}

	err = kona_pwmc_config(chip, pwm, state->duty_cycle, state->period);
	if (err && !pwm->state.enabled)
		clk_disable_unprepare(kp->clk);

	return err;
}

static const struct pwm_ops kona_pwm_ops = {
	.apply = kona_pwmc_apply,
};

static int kona_pwmc_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct kona_pwmc *kp;
	unsigned int chan;
	unsigned int value = 0;
	int ret = 0;

	chip = devm_pwmchip_alloc(&pdev->dev, 6, sizeof(*kp));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	kp = to_kona_pwmc(chip);

	chip->ops = &kona_pwm_ops;

	kp->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(kp->base))
		return PTR_ERR(kp->base);

	kp->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(kp->clk)) {
		dev_err(&pdev->dev, "failed to get clock: %ld\n",
			PTR_ERR(kp->clk));
		return PTR_ERR(kp->clk);
	}

	ret = clk_prepare_enable(kp->clk);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
		return ret;
	}

	/* Set push/pull for all channels */
	for (chan = 0; chan < chip->npwm; chan++)
		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));

	writel(value, kp->base + PWM_CONTROL_OFFSET);

	clk_disable_unprepare(kp->clk);

	ret = devm_pwmchip_add(&pdev->dev, chip);
	if (ret < 0)
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);

	return ret;
}

static const struct of_device_id bcm_kona_pwmc_dt[] = {
	{ .compatible = "brcm,kona-pwm" },
	{ },
};
MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);

static struct platform_driver kona_pwmc_driver = {
	.driver = {
		.name = "bcm-kona-pwm",
		.of_match_table = bcm_kona_pwmc_dt,
	},
	.probe = kona_pwmc_probe,
};
module_platform_driver(kona_pwmc_driver);

MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
MODULE_DESCRIPTION("Broadcom Kona PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2aec85b2 TG	1	// SPDX-License-Identifier: GPL-2.0-only
2aec85b2 TG	2	// Copyright (C) 2014 Broadcom Corporation
6a4e4bff TK	3
	4	#include <linux/clk.h>
	5	#include <linux/delay.h>
	6	#include <linux/err.h>
	7	#include <linux/io.h>
	8	#include <linux/ioport.h>
	9	#include <linux/math64.h>
	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/pwm.h>
	14	#include <linux/slab.h>
	15	#include <linux/types.h>
	16
	17	/*
	18	* The Kona PWM has some unusual characteristics. Here are the main points.
	19	*
	20	* 1) There is no disable bit and the hardware docs advise programming a zero
	21	* duty to achieve output equivalent to that of a normal disable operation.
	22	*
	23	* 2) Changes to prescale, duty, period, and polarity do not take effect until
	24	* a subsequent rising edge of the trigger bit.
	25	*
	26	* 3) If the smooth bit and trigger bit are both low, the output is a constant
	27	* high signal. Otherwise, the earlier waveform continues to be output.
	28	*
	29	* 4) If the smooth bit is set on the rising edge of the trigger bit, output
	30	* will transition to the new settings on a period boundary (which could be
	31	* seconds away). If the smooth bit is clear, new settings will be applied
	32	* as soon as possible (the hardware always has a 400ns delay).
	33	*
	34	* 5) When the external clock that feeds the PWM is disabled, output is pegged
	35	* high or low depending on its state at that exact instant.
	36	*/
	37
6571d13e	38	#define PWM_CONTROL_OFFSET 0x00000000
6a4e4bff TK	39	#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
	40	#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
	41	#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
	42	#define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
	43
6571d13e	44	#define PRESCALE_OFFSET 0x00000004
6a4e4bff TK	45	#define PRESCALE_SHIFT(chan) ((chan) << 2)
6a4e4bff TK	46	#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
6571d13e ST	47	#define PRESCALE_MIN 0x00000000
6571d13e ST	48	#define PRESCALE_MAX 0x00000007
6a4e4bff TK	49
6a4e4bff TK	50	#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
6571d13e ST	51	#define PERIOD_COUNT_MIN 0x00000002
6571d13e ST	52	#define PERIOD_COUNT_MAX 0x00ffffff
6a4e4bff TK	53
6a4e4bff TK	54	#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
6571d13e ST	55	#define DUTY_CYCLE_HIGH_MIN 0x00000000
6571d13e ST	56	#define DUTY_CYCLE_HIGH_MAX 0x00ffffff
6a4e4bff TK	57
6a4e4bff TK	58	struct kona_pwmc {
6a4e4bff TK	59	void __iomem *base;
	60	struct clk *clk;
	61	};
	62
51352c09	63	static inline struct kona_pwmc to_kona_pwmc(struct pwm_chip chip)
6a4e4bff	64	{
e5c368b8	65	return pwmchip_get_drvdata(chip);
6a4e4bff TK	66	}
6a4e4bff TK	67
fe0aea79 JR	68	/*
	69	* Clear trigger bit but set smooth bit to maintain old output.
	70	*/
	71	static void kona_pwmc_prepare_for_settings(struct kona_pwmc *kp,
	72	unsigned int chan)
6a4e4bff TK	73	{
	74	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
	75
6a4e4bff TK	76	value \|= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
	77	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
	78	writel(value, kp->base + PWM_CONTROL_OFFSET);
	79
fe0aea79 JR	80	/*
	81	* There must be a min 400ns delay between clearing trigger and setting
	82	* it. Failing to do this may result in no PWM signal.
	83	*/
	84	ndelay(400);
	85	}
	86
	87	static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
	88	{
	89	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
	90
6a4e4bff TK	91	/* Set trigger bit and clear smooth bit to apply new settings */
	92	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
	93	value \|= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
	94	writel(value, kp->base + PWM_CONTROL_OFFSET);
fe0aea79 JR	95
	96	/* Trigger bit must be held high for at least 400 ns. */
	97	ndelay(400);
6a4e4bff TK	98	}
	99
	100	static int kona_pwmc_config(struct pwm_chip chip, struct pwm_device pwm,
1c1283db	101	u64 duty_ns, u64 period_ns)
6a4e4bff TK	102	{
6a4e4bff TK	103	struct kona_pwmc *kp = to_kona_pwmc(chip);
1c1283db	104	u64 div, rate;
6a4e4bff TK	105	unsigned long prescale = PRESCALE_MIN, pc, dc;
	106	unsigned int value, chan = pwm->hwpwm;
	107
	108	/*
	109	* Find period count, duty count and prescale to suit duty_ns and
	110	* period_ns. This is done according to formulas described below:
	111	*
	112	* period_ns = 10^9 * (PRESCALE + 1) * PC / PWM_CLK_RATE
	113	* duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
	114	*
	115	* PC = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
	116	* DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
	117	*/
	118
	119	rate = clk_get_rate(kp->clk);
	120
	121	while (1) {
	122	div = 1000000000;
	123	div *= 1 + prescale;
1c1283db UKK	124	pc = mul_u64_u64_div_u64(rate, period_ns, div);
1c1283db UKK	125	dc = mul_u64_u64_div_u64(rate, duty_ns, div);
6a4e4bff TK	126
6a4e4bff TK	127	/* If duty_ns or period_ns are not achievable then return */
75de7259	128	if (pc < PERIOD_COUNT_MIN)
6a4e4bff TK	129	return -EINVAL;
	130
	131	/* If pc and dc are in bounds, the calculation is done */
	132	if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX)
	133	break;
	134
	135	/* Otherwise, increase prescale and recalculate pc and dc */
	136	if (++prescale > PRESCALE_MAX)
	137	return -EINVAL;
	138	}
	139
1c1283db	140	kona_pwmc_prepare_for_settings(kp, chan);
fe0aea79	141
1c1283db UKK	142	value = readl(kp->base + PRESCALE_OFFSET);
	143	value &= ~PRESCALE_MASK(chan);
	144	value \|= prescale << PRESCALE_SHIFT(chan);
	145	writel(value, kp->base + PRESCALE_OFFSET);
6a4e4bff	146
1c1283db	147	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
6a4e4bff	148
1c1283db	149	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
6a4e4bff	150
1c1283db	151	kona_pwmc_apply_settings(kp, chan);
6a4e4bff TK	152
	153	return 0;
	154	}
	155
	156	static int kona_pwmc_set_polarity(struct pwm_chip chip, struct pwm_device pwm,
	157	enum pwm_polarity polarity)
	158	{
	159	struct kona_pwmc *kp = to_kona_pwmc(chip);
	160	unsigned int chan = pwm->hwpwm;
	161	unsigned int value;
	162	int ret;
	163
	164	ret = clk_prepare_enable(kp->clk);
	165	if (ret < 0) {
2089ecaa	166	dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
6a4e4bff TK	167	return ret;
	168	}
	169
fe0aea79 JR	170	kona_pwmc_prepare_for_settings(kp, chan);
fe0aea79 JR	171
6a4e4bff TK	172	value = readl(kp->base + PWM_CONTROL_OFFSET);
	173
	174	if (polarity == PWM_POLARITY_NORMAL)
	175	value \|= 1 << PWM_CONTROL_POLARITY_SHIFT(chan);
	176	else
	177	value &= ~(1 << PWM_CONTROL_POLARITY_SHIFT(chan));
	178
	179	writel(value, kp->base + PWM_CONTROL_OFFSET);
	180
	181	kona_pwmc_apply_settings(kp, chan);
	182
6a4e4bff TK	183	clk_disable_unprepare(kp->clk);
	184
	185	return 0;
	186	}
	187
	188	static int kona_pwmc_enable(struct pwm_chip chip, struct pwm_device pwm)
	189	{
	190	struct kona_pwmc *kp = to_kona_pwmc(chip);
	191	int ret;
	192
	193	ret = clk_prepare_enable(kp->clk);
	194	if (ret < 0) {
2089ecaa	195	dev_err(pwmchip_parent(chip), "failed to enable clock: %d\n", ret);
6a4e4bff TK	196	return ret;
	197	}
	198
6a4e4bff TK	199	return 0;
	200	}
	201
	202	static void kona_pwmc_disable(struct pwm_chip chip, struct pwm_device pwm)
	203	{
	204	struct kona_pwmc *kp = to_kona_pwmc(chip);
	205	unsigned int chan = pwm->hwpwm;
fe0aea79 JR	206	unsigned int value;
	207
	208	kona_pwmc_prepare_for_settings(kp, chan);
6a4e4bff TK	209
	210	/* Simulate a disable by configuring for zero duty */
	211	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
fe0aea79	212	writel(0, kp->base + PERIOD_COUNT_OFFSET(chan));
6a4e4bff	213
fe0aea79 JR	214	/* Set prescale to 0 for this channel */
	215	value = readl(kp->base + PRESCALE_OFFSET);
	216	value &= ~PRESCALE_MASK(chan);
	217	writel(value, kp->base + PRESCALE_OFFSET);
	218
	219	kona_pwmc_apply_settings(kp, chan);
6a4e4bff TK	220
	221	clk_disable_unprepare(kp->clk);
	222	}
	223
1c1283db UKK	224	static int kona_pwmc_apply(struct pwm_chip chip, struct pwm_device pwm,
	225	const struct pwm_state *state)
	226	{
	227	int err;
	228	struct kona_pwmc *kp = to_kona_pwmc(chip);
	229	bool enabled = pwm->state.enabled;
	230
	231	if (state->polarity != pwm->state.polarity) {
	232	if (enabled) {
	233	kona_pwmc_disable(chip, pwm);
	234	enabled = false;
	235	}
	236
	237	err = kona_pwmc_set_polarity(chip, pwm, state->polarity);
	238	if (err)
	239	return err;
	240
	241	pwm->state.polarity = state->polarity;
	242	}
	243
	244	if (!state->enabled) {
	245	if (enabled)
	246	kona_pwmc_disable(chip, pwm);
	247	return 0;
	248	} else if (!enabled) {
	249	/*
	250	* This is a bit special here, usually the PWM should only be
	251	* enabled when duty and period are setup. But before this
	252	* driver was converted to .apply it was done the other way
	253	* around and so this behaviour was kept even though this might
	254	* result in a glitch. This might be improvable by someone with
	255	* hardware and/or documentation.
	256	*/
	257	err = kona_pwmc_enable(chip, pwm);
	258	if (err)
	259	return err;
	260	}
	261
80943bbd	262	err = kona_pwmc_config(chip, pwm, state->duty_cycle, state->period);
1c1283db UKK	263	if (err && !pwm->state.enabled)
	264	clk_disable_unprepare(kp->clk);
	265
	266	return err;
	267	}
	268
6a4e4bff	269	static const struct pwm_ops kona_pwm_ops = {
1c1283db	270	.apply = kona_pwmc_apply,
6a4e4bff TK	271	};
	272
	273	static int kona_pwmc_probe(struct platform_device *pdev)
	274	{
e5c368b8	275	struct pwm_chip *chip;
6a4e4bff	276	struct kona_pwmc *kp;
6a4e4bff TK	277	unsigned int chan;
	278	unsigned int value = 0;
	279	int ret = 0;
	280
e5c368b8 UKK	281	chip = devm_pwmchip_alloc(&pdev->dev, 6, sizeof(*kp));
	282	if (IS_ERR(chip))
	283	return PTR_ERR(chip);
	284	kp = to_kona_pwmc(chip);
6a4e4bff	285
e5c368b8	286	chip->ops = &kona_pwm_ops;
6a4e4bff	287
537fe687	288	kp->base = devm_platform_ioremap_resource(pdev, 0);
6a4e4bff TK	289	if (IS_ERR(kp->base))
	290	return PTR_ERR(kp->base);
	291
	292	kp->clk = devm_clk_get(&pdev->dev, NULL);
	293	if (IS_ERR(kp->clk)) {
	294	dev_err(&pdev->dev, "failed to get clock: %ld\n",
	295	PTR_ERR(kp->clk));
	296	return PTR_ERR(kp->clk);
	297	}
	298
	299	ret = clk_prepare_enable(kp->clk);
	300	if (ret < 0) {
	301	dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
	302	return ret;
	303	}
	304
e23db65f	305	/* Set push/pull for all channels */
e5c368b8	306	for (chan = 0; chan < chip->npwm; chan++)
6a4e4bff	307	value \|= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
6a4e4bff TK	308
	309	writel(value, kp->base + PWM_CONTROL_OFFSET);
	310
	311	clk_disable_unprepare(kp->clk);
	312
e5c368b8	313	ret = devm_pwmchip_add(&pdev->dev, chip);
6a4e4bff TK	314	if (ret < 0)
	315	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	316
	317	return ret;
	318	}
	319
6a4e4bff TK	320	static const struct of_device_id bcm_kona_pwmc_dt[] = {
	321	{ .compatible = "brcm,kona-pwm" },
	322	{ },
	323	};
	324	MODULE_DEVICE_TABLE(of, bcm_kona_pwmc_dt);
	325
	326	static struct platform_driver kona_pwmc_driver = {
	327	.driver = {
	328	.name = "bcm-kona-pwm",
	329	.of_match_table = bcm_kona_pwmc_dt,
	330	},
	331	.probe = kona_pwmc_probe,
6a4e4bff TK	332	};
	333	module_platform_driver(kona_pwmc_driver);
	334
	335	MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
	336	MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
	337	MODULE_DESCRIPTION("Broadcom Kona PWM driver");
	338	MODULE_LICENSE("GPL v2");