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author	Andrey Matyukov <andrey.matyukov@intel.com>
	Tue, 8 Dec 2020 19:53:39 +0000 (22:53 +0300)
committer	Matt Caswell <matt@openssl.org>
	Mon, 22 Mar 2021 09:48:00 +0000 (09:48 +0000)
commit	c781eb1c63c243cb64dbe3066a43dc172aaab3b8
tree	36adf4600064afddfb87e16bee0736c6427ca523	tree \| snapshot
parent	db89d8f04bb131bbf0e2b87eb9a1515076c893d3	commit \| diff

Dual 1024-bit exponentiation optimization for Intel IceLake CPU
with AVX512_IFMA + AVX512_VL instructions, primarily for RSA CRT private key
operations. It uses 256-bit registers to avoid CPU frequency scaling issues.
The performance speedup for RSA2k signature on ICL is ~2x.

Reviewed-by: Paul Dale <pauli@openssl.org>
Reviewed-by: Matt Caswell <matt@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/13750)

14 files changed:

CHANGES.md		diff \| blob \| blame \| history
crypto/bn/asm/rsaz-avx512.pl	[new file with mode: 0644]	blob
crypto/bn/bn_exp.c		diff \| blob \| blame \| history
crypto/bn/build.info		diff \| blob \| blame \| history
crypto/bn/rsaz_exp.h		diff \| blob \| blame \| history
crypto/bn/rsaz_exp_x2.c	[new file with mode: 0644]	blob
crypto/rsa/rsa_ossl.c		diff \| blob \| blame \| history
crypto/x86_64cpuid.pl		diff \| blob \| blame \| history
doc/build.info		diff \| blob \| blame \| history
doc/man3/BN_mod_exp_mont.pod	[new file with mode: 0644]	blob
include/openssl/bn.h		diff \| blob \| blame \| history
test/exptest.c		diff \| blob \| blame \| history
util/libcrypto.num		diff \| blob \| blame \| history
util/missingcrypto.txt		diff \| blob \| blame \| history

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