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Commit | Line | Data |
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c7a34993 MM |
1 | /* |
2 | * The PCI Utilities -- Show Extended Capabilities | |
3 | * | |
2849db67 | 4 | * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz> |
c7a34993 | 5 | * |
61829219 MM |
6 | * Can be freely distributed and used under the terms of the GNU GPL v2+. |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0-or-later | |
c7a34993 MM |
9 | */ |
10 | ||
11 | #include <stdio.h> | |
12 | #include <string.h> | |
13 | ||
14 | #include "lspci.h" | |
15 | ||
67da1792 MM |
16 | static void |
17 | cap_tph(struct device *d, int where) | |
18 | { | |
19 | u32 tph_cap; | |
20 | printf("Transaction Processing Hints\n"); | |
21 | if (verbose < 2) | |
22 | return; | |
23 | ||
24 | if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4)) | |
25 | return; | |
26 | ||
27 | tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES); | |
28 | ||
29 | if (tph_cap & PCI_TPH_INTVEC_SUP) | |
30 | printf("\t\tInterrupt vector mode supported\n"); | |
31 | if (tph_cap & PCI_TPH_DEV_SUP) | |
32 | printf("\t\tDevice specific mode supported\n"); | |
33 | if (tph_cap & PCI_TPH_EXT_REQ_SUP) | |
34 | printf("\t\tExtended requester support\n"); | |
35 | ||
36 | switch (tph_cap & PCI_TPH_ST_LOC_MASK) { | |
37 | case PCI_TPH_ST_NONE: | |
38 | printf("\t\tNo steering table available\n"); | |
39 | break; | |
40 | case PCI_TPH_ST_CAP: | |
41 | printf("\t\tSteering table in TPH capability structure\n"); | |
42 | break; | |
43 | case PCI_TPH_ST_MSIX: | |
44 | printf("\t\tSteering table in MSI-X table\n"); | |
45 | break; | |
46 | default: | |
47 | printf("\t\tReserved steering table location\n"); | |
48 | break; | |
49 | } | |
50 | } | |
51 | ||
52 | static u32 | |
53 | cap_ltr_scale(u8 scale) | |
54 | { | |
55 | return 1 << (scale * 5); | |
56 | } | |
57 | ||
58 | static void | |
59 | cap_ltr(struct device *d, int where) | |
60 | { | |
61 | u32 scale; | |
62 | u16 snoop, nosnoop; | |
63 | printf("Latency Tolerance Reporting\n"); | |
64 | if (verbose < 2) | |
65 | return; | |
66 | ||
67 | if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4)) | |
68 | return; | |
69 | ||
70 | snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP); | |
71 | scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
c3d1d465 | 72 | printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n", |
6811edb8 | 73 | ((u64)snoop & PCI_LTR_VALUE_MASK) * scale); |
67da1792 MM |
74 | |
75 | nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP); | |
76 | scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK); | |
c3d1d465 | 77 | printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n", |
6811edb8 | 78 | ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale); |
67da1792 MM |
79 | } |
80 | ||
21ff9851 | 81 | static void |
9225e71d | 82 | cap_sec(struct device *d, int where) |
21ff9851 B |
83 | { |
84 | u32 ctrl3, lane_err_stat; | |
85 | u8 lane; | |
86 | printf("Secondary PCI Express\n"); | |
9225e71d | 87 | if (verbose < 2) |
21ff9851 B |
88 | return; |
89 | ||
90 | if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12)) | |
91 | return; | |
92 | ||
93 | ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3); | |
018f413c | 94 | printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n", |
21ff9851 B |
95 | FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN), |
96 | FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU)); | |
97 | ||
98 | lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR); | |
99 | printf("\t\tLaneErrStat: "); | |
100 | if (lane_err_stat) | |
101 | { | |
9f7dc65c | 102 | printf("LaneErr at lane:"); |
21ff9851 B |
103 | for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1) |
104 | if (BITS(lane_err_stat, 0, 1)) | |
105 | printf(" %u", lane); | |
106 | } | |
107 | else | |
108 | printf("0"); | |
109 | printf("\n"); | |
110 | } | |
111 | ||
c7a34993 MM |
112 | static void |
113 | cap_dsn(struct device *d, int where) | |
114 | { | |
115 | u32 t1, t2; | |
116 | if (!config_fetch(d, where + 4, 8)) | |
117 | return; | |
118 | t1 = get_conf_long(d, where + 4); | |
119 | t2 = get_conf_long(d, where + 8); | |
120 | printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", | |
6f9f8fd7 MW |
121 | t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff, |
122 | t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff); | |
c7a34993 MM |
123 | } |
124 | ||
125 | static void | |
a1492b88 | 126 | cap_aer(struct device *d, int where, int type) |
c7a34993 | 127 | { |
a6625432 | 128 | u32 l, l0, l1, l2, l3; |
a1492b88 | 129 | u16 w; |
c7a34993 MM |
130 | |
131 | printf("Advanced Error Reporting\n"); | |
9a2e4b35 YZ |
132 | if (verbose < 2) |
133 | return; | |
134 | ||
a6625432 | 135 | if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40)) |
c7a34993 MM |
136 | return; |
137 | ||
138 | l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS); | |
139 | printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
140 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
141 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
142 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
143 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
144 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
145 | l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK); | |
146 | printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
147 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
148 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
149 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
150 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
151 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
152 | l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER); | |
153 | printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c " | |
154 | "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n", | |
155 | FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP), | |
156 | FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT), | |
157 | FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP), | |
158 | FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL)); | |
159 | l = get_conf_long(d, where + PCI_ERR_COR_STATUS); | |
aca48104 | 160 | printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", |
c7a34993 MM |
161 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), |
162 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
163 | l = get_conf_long(d, where + PCI_ERR_COR_MASK); | |
aca48104 | 164 | printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n", |
c7a34993 MM |
165 | FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP), |
166 | FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE)); | |
167 | l = get_conf_long(d, where + PCI_ERR_CAP); | |
9a54979e | 168 | printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n" |
b33a4a2b | 169 | "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n", |
c7a34993 | 170 | PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE), |
b33a4a2b BH |
171 | FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE), |
172 | FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE), | |
173 | FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG)); | |
a6625432 BH |
174 | |
175 | l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG); | |
176 | l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4); | |
177 | l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8); | |
178 | l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12); | |
179 | printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3); | |
a1492b88 BH |
180 | |
181 | if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC) | |
182 | { | |
183 | if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12)) | |
184 | return; | |
185 | ||
186 | l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND); | |
187 | printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n", | |
188 | FLAG(l, PCI_ERR_ROOT_CMD_COR_EN), | |
189 | FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN), | |
190 | FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN)); | |
191 | ||
192 | l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS); | |
193 | printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n" | |
aeb74fe2 | 194 | "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n", |
a1492b88 BH |
195 | FLAG(l, PCI_ERR_ROOT_COR_RCV), |
196 | FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV), | |
197 | FLAG(l, PCI_ERR_ROOT_UNCOR_RCV), | |
198 | FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV), | |
199 | FLAG(l, PCI_ERR_ROOT_FIRST_FATAL), | |
200 | FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV), | |
201 | FLAG(l, PCI_ERR_ROOT_FATAL_RCV), | |
202 | PCI_ERR_MSG_NUM(l)); | |
203 | ||
204 | w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC); | |
205 | printf("\t\tErrorSrc: ERR_COR: %04x ", w); | |
206 | ||
207 | w = get_conf_word(d, where + PCI_ERR_ROOT_SRC); | |
208 | printf("ERR_FATAL/NONFATAL: %04x\n", w); | |
209 | } | |
c7a34993 MM |
210 | } |
211 | ||
de91b6f2 KB |
212 | static void cap_dpc(struct device *d, int where) |
213 | { | |
214 | u16 l; | |
215 | ||
216 | printf("Downstream Port Containment\n"); | |
217 | if (verbose < 2) | |
218 | return; | |
219 | ||
220 | if (!config_fetch(d, where + PCI_DPC_CAP, 8)) | |
221 | return; | |
222 | ||
223 | l = get_conf_word(d, where + PCI_DPC_CAP); | |
aeb74fe2 | 224 | printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", |
de91b6f2 KB |
225 | PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK), |
226 | FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR)); | |
227 | ||
228 | l = get_conf_word(d, where + PCI_DPC_CTL); | |
229 | printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n", | |
230 | PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT), | |
231 | FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER), | |
232 | FLAG(l, PCI_DPC_CTL_DL_ACTIVE)); | |
233 | ||
234 | l = get_conf_word(d, where + PCI_DPC_STATUS); | |
235 | printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n", | |
236 | FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT), | |
237 | FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l)); | |
238 | ||
239 | l = get_conf_word(d, where + PCI_DPC_SOURCE); | |
240 | printf("\t\tSource:\t%04x\n", l); | |
241 | } | |
242 | ||
c7a34993 MM |
243 | static void |
244 | cap_acs(struct device *d, int where) | |
245 | { | |
246 | u16 w; | |
247 | ||
248 | printf("Access Control Services\n"); | |
9a2e4b35 YZ |
249 | if (verbose < 2) |
250 | return; | |
251 | ||
c7a34993 MM |
252 | if (!config_fetch(d, where + PCI_ACS_CAP, 4)) |
253 | return; | |
254 | ||
255 | w = get_conf_word(d, where + PCI_ACS_CAP); | |
256 | printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
257 | "DirectTrans%c\n", | |
258 | FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED), | |
259 | FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS), | |
260 | FLAG(w, PCI_ACS_CAP_TRANS)); | |
261 | w = get_conf_word(d, where + PCI_ACS_CTRL); | |
262 | printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c " | |
263 | "DirectTrans%c\n", | |
264 | FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED), | |
265 | FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS), | |
266 | FLAG(w, PCI_ACS_CTRL_TRANS)); | |
267 | } | |
268 | ||
269 | static void | |
270 | cap_ari(struct device *d, int where) | |
271 | { | |
272 | u16 w; | |
273 | ||
274 | printf("Alternative Routing-ID Interpretation (ARI)\n"); | |
9a2e4b35 YZ |
275 | if (verbose < 2) |
276 | return; | |
277 | ||
c7a34993 MM |
278 | if (!config_fetch(d, where + PCI_ARI_CAP, 4)) |
279 | return; | |
280 | ||
281 | w = get_conf_word(d, where + PCI_ARI_CAP); | |
282 | printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n", | |
283 | FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS), | |
284 | PCI_ARI_CAP_NFN(w)); | |
285 | w = get_conf_word(d, where + PCI_ARI_CTRL); | |
286 | printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n", | |
287 | FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS), | |
288 | PCI_ARI_CTRL_FG(w)); | |
289 | } | |
290 | ||
291 | static void | |
292 | cap_ats(struct device *d, int where) | |
293 | { | |
294 | u16 w; | |
295 | ||
296 | printf("Address Translation Service (ATS)\n"); | |
9a2e4b35 YZ |
297 | if (verbose < 2) |
298 | return; | |
299 | ||
c7a34993 MM |
300 | if (!config_fetch(d, where + PCI_ATS_CAP, 4)) |
301 | return; | |
302 | ||
303 | w = get_conf_word(d, where + PCI_ATS_CAP); | |
304 | printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w)); | |
305 | w = get_conf_word(d, where + PCI_ATS_CTRL); | |
306 | printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n", | |
307 | FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w)); | |
308 | } | |
309 | ||
a858df0d DW |
310 | static void |
311 | cap_pri(struct device *d, int where) | |
312 | { | |
313 | u16 w; | |
314 | u32 l; | |
315 | ||
316 | printf("Page Request Interface (PRI)\n"); | |
317 | if (verbose < 2) | |
318 | return; | |
319 | ||
320 | if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc)) | |
321 | return; | |
322 | ||
323 | w = get_conf_word(d, where + PCI_PRI_CTRL); | |
bfd8658f | 324 | printf("\t\tPRICtl: Enable%c Reset%c\n", |
a858df0d DW |
325 | FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET)); |
326 | w = get_conf_word(d, where + PCI_PRI_STATUS); | |
548a6e3b | 327 | printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n", |
a858df0d | 328 | FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI), |
548a6e3b | 329 | FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID)); |
a858df0d DW |
330 | l = get_conf_long(d, where + PCI_PRI_MAX_REQ); |
331 | printf("\t\tPage Request Capacity: %08x, ", l); | |
332 | l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ); | |
333 | printf("Page Request Allocation: %08x\n", l); | |
334 | } | |
335 | ||
336 | static void | |
337 | cap_pasid(struct device *d, int where) | |
338 | { | |
339 | u16 w; | |
340 | ||
341 | printf("Process Address Space ID (PASID)\n"); | |
342 | if (verbose < 2) | |
343 | return; | |
344 | ||
345 | if (!config_fetch(d, where + PCI_PASID_CAP, 4)) | |
346 | return; | |
347 | ||
348 | w = get_conf_word(d, where + PCI_PASID_CAP); | |
bfd8658f | 349 | printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n", |
a858df0d DW |
350 | FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV), |
351 | PCI_PASID_CAP_WIDTH(w)); | |
352 | w = get_conf_word(d, where + PCI_PASID_CTRL); | |
bfd8658f | 353 | printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n", |
a858df0d DW |
354 | FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC), |
355 | FLAG(w, PCI_PASID_CTRL_PRIV)); | |
356 | } | |
357 | ||
c7a34993 MM |
358 | static void |
359 | cap_sriov(struct device *d, int where) | |
360 | { | |
361 | u16 b; | |
362 | u16 w; | |
363 | u32 l; | |
67e78b32 | 364 | int i; |
c7a34993 MM |
365 | |
366 | printf("Single Root I/O Virtualization (SR-IOV)\n"); | |
9a2e4b35 YZ |
367 | if (verbose < 2) |
368 | return; | |
369 | ||
c7a34993 MM |
370 | if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c)) |
371 | return; | |
372 | ||
373 | l = get_conf_long(d, where + PCI_IOV_CAP); | |
aeb74fe2 | 374 | printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n", |
053d08d2 | 375 | FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l)); |
c7a34993 | 376 | w = get_conf_word(d, where + PCI_IOV_CTRL); |
053d08d2 | 377 | printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n", |
c7a34993 MM |
378 | FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME), |
379 | FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE), | |
053d08d2 | 380 | FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN)); |
c7a34993 MM |
381 | w = get_conf_word(d, where + PCI_IOV_STATUS); |
382 | printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS)); | |
383 | w = get_conf_word(d, where + PCI_IOV_INITIALVF); | |
384 | printf("\t\tInitial VFs: %d, ", w); | |
385 | w = get_conf_word(d, where + PCI_IOV_TOTALVF); | |
386 | printf("Total VFs: %d, ", w); | |
387 | w = get_conf_word(d, where + PCI_IOV_NUMVF); | |
388 | printf("Number of VFs: %d, ", w); | |
389 | b = get_conf_byte(d, where + PCI_IOV_FDL); | |
390 | printf("Function Dependency Link: %02x\n", b); | |
391 | w = get_conf_word(d, where + PCI_IOV_OFFSET); | |
392 | printf("\t\tVF offset: %d, ", w); | |
393 | w = get_conf_word(d, where + PCI_IOV_STRIDE); | |
394 | printf("stride: %d, ", w); | |
395 | w = get_conf_word(d, where + PCI_IOV_DID); | |
396 | printf("Device ID: %04x\n", w); | |
397 | l = get_conf_long(d, where + PCI_IOV_SUPPS); | |
398 | printf("\t\tSupported Page Size: %08x, ", l); | |
399 | l = get_conf_long(d, where + PCI_IOV_SYSPS); | |
400 | printf("System Page Size: %08x\n", l); | |
b9e11c65 MM |
401 | |
402 | for (i=0; i < PCI_IOV_NUM_BAR; i++) | |
403 | { | |
187bf2f5 | 404 | u32 addr; |
b9e11c65 MM |
405 | int type; |
406 | u32 h; | |
407 | l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i); | |
408 | if (l == 0xffffffff) | |
409 | l = 0; | |
410 | if (!l) | |
411 | continue; | |
412 | printf("\t\tRegion %d: Memory at ", i); | |
413 | addr = l & PCI_ADDR_MEM_MASK; | |
414 | type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
415 | if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
416 | { | |
417 | i++; | |
418 | h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4)); | |
187bf2f5 | 419 | printf("%08x", h); |
b9e11c65 | 420 | } |
187bf2f5 MM |
421 | printf("%08x (%s-bit, %sprefetchable)\n", |
422 | addr, | |
b9e11c65 MM |
423 | (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64", |
424 | (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-"); | |
67e78b32 | 425 | } |
b9e11c65 | 426 | |
edca3520 | 427 | l = get_conf_long(d, where + PCI_IOV_MSAO); |
c7a34993 MM |
428 | printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l), |
429 | PCI_IOV_MSA_BIR(l)); | |
430 | } | |
431 | ||
c0d9545c BH |
432 | static void |
433 | cap_multicast(struct device *d, int where, int type) | |
434 | { | |
435 | u16 w; | |
436 | u32 l; | |
437 | u64 bar, rcv, block; | |
438 | ||
439 | printf("Multicast\n"); | |
440 | if (verbose < 2) | |
441 | return; | |
442 | ||
443 | if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30)) | |
444 | return; | |
445 | ||
446 | w = get_conf_word(d, where + PCI_MCAST_CAP); | |
447 | printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1); | |
448 | if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) | |
449 | printf(", WindowSz %d (%d bytes)", | |
450 | PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w)); | |
451 | if (type == PCI_EXP_TYPE_ROOT_PORT || | |
452 | type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM) | |
453 | printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC)); | |
454 | w = get_conf_word(d, where + PCI_MCAST_CTRL); | |
455 | printf("\t\tMcastCtl: NumGroups %d, Enable%c\n", | |
456 | PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE)); | |
457 | bar = get_conf_long(d, where + PCI_MCAST_BAR); | |
458 | l = get_conf_long(d, where + PCI_MCAST_BAR + 4); | |
459 | bar |= (u64) l << 32; | |
460 | printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n", | |
461 | PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK); | |
462 | rcv = get_conf_long(d, where + PCI_MCAST_RCV); | |
463 | l = get_conf_long(d, where + PCI_MCAST_RCV + 4); | |
464 | rcv |= (u64) l << 32; | |
465 | printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv); | |
466 | block = get_conf_long(d, where + PCI_MCAST_BLOCK); | |
467 | l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4); | |
468 | block |= (u64) l << 32; | |
469 | printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block); | |
470 | block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS); | |
471 | l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4); | |
472 | block |= (u64) l << 32; | |
473 | printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block); | |
474 | ||
475 | if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP) | |
476 | return; | |
477 | bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR); | |
478 | l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4); | |
479 | bar |= (u64) l << 32; | |
480 | printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar)); | |
481 | if (PCI_MCAST_OVL_SIZE(bar) >= 6) | |
482 | printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar)); | |
483 | else | |
484 | printf("(disabled)"); | |
485 | printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK); | |
486 | } | |
487 | ||
33088c24 MM |
488 | static void |
489 | cap_vc(struct device *d, int where) | |
490 | { | |
491 | u32 cr1, cr2; | |
492 | u16 ctrl, status; | |
493 | int evc_cnt; | |
494 | int arb_table_pos; | |
495 | int i, j; | |
3d8b5258 | 496 | static const char ref_clocks[][6] = { "100ns" }; |
3edae14a MM |
497 | static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" }; |
498 | static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" }; | |
3d8b5258 | 499 | char buf[8]; |
33088c24 MM |
500 | |
501 | printf("Virtual Channel\n"); | |
502 | if (verbose < 2) | |
503 | return; | |
504 | ||
505 | if (!config_fetch(d, where + 4, 0x1c - 4)) | |
506 | return; | |
507 | ||
508 | cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1); | |
509 | cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2); | |
510 | ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL); | |
511 | status = get_conf_word(d, where + PCI_VC_PORT_STATUS); | |
512 | ||
3d8b5258 | 513 | evc_cnt = BITS(cr1, 0, 3); |
d676f20d | 514 | printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n", |
3d8b5258 MM |
515 | BITS(cr1, 4, 3), |
516 | TABLE(ref_clocks, BITS(cr1, 8, 2), buf), | |
d676f20d | 517 | 1 << BITS(cr1, 10, 2)); |
33088c24 | 518 | |
d676f20d | 519 | printf("\t\tArb:"); |
33088c24 MM |
520 | for (i=0; i<8; i++) |
521 | if (arb_selects[i][0] != '?' || cr2 & (1 << i)) | |
d676f20d | 522 | printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i)); |
3d8b5258 | 523 | arb_table_pos = BITS(cr2, 24, 8); |
33088c24 | 524 | |
d676f20d | 525 | printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf)); |
33088c24 MM |
526 | printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1)); |
527 | ||
528 | if (arb_table_pos) | |
d676f20d MM |
529 | { |
530 | arb_table_pos = where + 16*arb_table_pos; | |
531 | printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos); | |
532 | } | |
33088c24 MM |
533 | |
534 | for (i=0; i<=evc_cnt; i++) | |
535 | { | |
536 | int pos = where + PCI_VC_RES_CAP + 12*i; | |
537 | u32 rcap, rctrl; | |
538 | u16 rstatus; | |
539 | int pat_pos; | |
540 | ||
5a9a932c | 541 | printf("\t\tVC%d:\t", i); |
33088c24 MM |
542 | if (!config_fetch(d, pos, 12)) |
543 | { | |
5a9a932c | 544 | printf("<unreadable>\n"); |
33088c24 MM |
545 | continue; |
546 | } | |
547 | rcap = get_conf_long(d, pos); | |
548 | rctrl = get_conf_long(d, pos+4); | |
7970509b | 549 | rstatus = get_conf_word(d, pos+10); |
33088c24 | 550 | |
3d8b5258 | 551 | pat_pos = BITS(rcap, 24, 8); |
5a9a932c | 552 | printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n", |
33088c24 | 553 | pat_pos, |
3711e86f | 554 | BITS(rcap, 16, 7) + 1, |
33088c24 MM |
555 | FLAG(rcap, 1 << 15)); |
556 | ||
557 | printf("\t\t\tArb:"); | |
558 | for (j=0; j<8; j++) | |
559 | if (vc_arb_selects[j][0] != '?' || rcap & (1 << j)) | |
560 | printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j)); | |
561 | ||
562 | printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n", | |
563 | FLAG(rctrl, 1 << 31), | |
3d8b5258 MM |
564 | BITS(rctrl, 24, 3), |
565 | TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf), | |
566 | BITS(rctrl, 0, 8)); | |
33088c24 MM |
567 | |
568 | printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n", | |
569 | FLAG(rstatus, 2), | |
570 | FLAG(rstatus, 1)); | |
571 | ||
572 | if (pat_pos) | |
573 | printf("\t\t\tPort Arbitration Table <?>\n"); | |
574 | } | |
575 | } | |
576 | ||
5a9a932c MM |
577 | static void |
578 | cap_rclink(struct device *d, int where) | |
579 | { | |
580 | u32 esd; | |
581 | int num_links; | |
582 | int i; | |
583 | static const char elt_types[][9] = { "Config", "Egress", "Internal" }; | |
584 | char buf[8]; | |
585 | ||
586 | printf("Root Complex Link\n"); | |
587 | if (verbose < 2) | |
588 | return; | |
589 | ||
590 | if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4)) | |
591 | return; | |
592 | ||
593 | esd = get_conf_long(d, where + PCI_RCLINK_ESD); | |
594 | num_links = BITS(esd, 8, 8); | |
595 | printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n", | |
596 | BITS(esd, 24, 8), | |
597 | BITS(esd, 16, 8), | |
598 | TABLE(elt_types, BITS(esd, 0, 8), buf)); | |
599 | ||
600 | for (i=0; i<num_links; i++) | |
601 | { | |
602 | int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE; | |
603 | u32 desc; | |
604 | u32 addr_lo, addr_hi; | |
605 | ||
606 | printf("\t\tLink%d:\t", i); | |
607 | if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE)) | |
608 | { | |
609 | printf("<unreadable>\n"); | |
610 | return; | |
611 | } | |
612 | desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC); | |
613 | addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR); | |
614 | addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4); | |
615 | ||
616 | printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n", | |
617 | BITS(desc, 24, 8), | |
618 | BITS(desc, 16, 8), | |
619 | FLAG(desc, 4), | |
620 | ((desc & 2) ? "Config" : "MemMapped"), | |
621 | FLAG(desc, 1)); | |
622 | ||
623 | if (desc & 2) | |
624 | { | |
625 | int n = addr_lo & 7; | |
626 | if (!n) | |
627 | n = 8; | |
628 | printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n", | |
629 | BITS(addr_lo, 20, n), | |
630 | BITS(addr_lo, 15, 5), | |
631 | BITS(addr_lo, 12, 3), | |
632 | addr_hi, addr_lo); | |
633 | } | |
634 | else | |
635 | printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo); | |
636 | } | |
637 | } | |
638 | ||
e12bd01e SK |
639 | static void |
640 | cap_rcec(struct device *d, int where) | |
641 | { | |
642 | printf("Root Complex Event Collector Endpoint Association\n"); | |
643 | if (verbose < 2) | |
644 | return; | |
645 | ||
646 | if (!config_fetch(d, where, 12)) | |
647 | return; | |
648 | ||
649 | u32 hdr = get_conf_long(d, where); | |
650 | byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr); | |
651 | u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP); | |
652 | printf("\t\tRCiEPBitmap: "); | |
653 | if (bmap) | |
654 | { | |
655 | int prevmatched=0; | |
656 | int adjcount=0; | |
657 | int prevdev=0; | |
658 | printf("RCiEP at Device(s):"); | |
659 | for (int dev=0; dev < 32; dev++) | |
660 | { | |
661 | if (BITS(bmap, dev, 1)) | |
662 | { | |
663 | if (!adjcount) | |
664 | printf("%s %u", (prevmatched) ? "," : "", dev); | |
665 | adjcount++; | |
666 | prevdev=dev; | |
667 | prevmatched=1; | |
668 | } | |
669 | else | |
670 | { | |
671 | if (adjcount > 1) | |
672 | printf("-%u", prevdev); | |
673 | adjcount=0; | |
674 | } | |
675 | } | |
676 | } | |
677 | else | |
678 | printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]"); | |
679 | printf("\n"); | |
680 | ||
681 | if (cap_ver < PCI_RCEC_BUSN_REG_VER) | |
682 | return; | |
683 | ||
684 | u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG); | |
685 | u8 lastbusn = BITS(busn, 16, 8); | |
686 | u8 nextbusn = BITS(busn, 8, 8); | |
687 | ||
688 | if ((lastbusn == 0x00) && (nextbusn == 0xff)) | |
689 | printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]"); | |
690 | else | |
691 | printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn ); | |
692 | } | |
693 | ||
d016c32d NP |
694 | static void |
695 | cap_lmr(struct device *d, int where) | |
696 | { | |
697 | printf("Lane Margining at the Receiver\n"); | |
698 | ||
699 | if (verbose < 2) | |
700 | return; | |
701 | ||
702 | if (!config_fetch(d, where, 8)) | |
703 | return; | |
704 | ||
705 | u16 port_caps = get_conf_word(d, where + PCI_LMR_CAPS); | |
706 | u16 port_status = get_conf_word(d, where + PCI_LMR_PORT_STS); | |
707 | ||
708 | printf("\t\tPortCap: Uses Driver%c\n", FLAG(port_caps, PCI_LMR_CAPS_DRVR)); | |
709 | printf("\t\tPortSta: MargReady%c MargSoftReady%c\n", | |
710 | FLAG(port_status, PCI_LMR_PORT_STS_READY), | |
711 | FLAG(port_status, PCI_LMR_PORT_STS_SOFT_READY)); | |
712 | } | |
713 | ||
52097446 BW |
714 | static void |
715 | cxl_range(u64 base, u64 size, int n) | |
716 | { | |
717 | u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 }; | |
718 | const char *type[] = { "Volatile", "Non-volatile", "CDAT" }; | |
719 | const char *class[] = { "DRAM", "Storage", "CDAT" }; | |
720 | u16 w; | |
721 | ||
722 | w = (u16) size; | |
723 | ||
724 | size &= ~0x0fffffffULL; | |
725 | ||
c0ccce1b | 726 | printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X" [size=0x%"PCI_U64_FMT_X"]\n", n, base, base + size - 1, size); |
52097446 BW |
727 | printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n", |
728 | FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE), | |
729 | type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)], | |
730 | interleave[PCI_CXL_RANGE_INTERLEAVE(w)], | |
731 | 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2)); | |
732 | } | |
733 | ||
bd853ef8 | 734 | static void |
2849db67 | 735 | dvsec_cxl_device(struct device *d, int rev, int where, int len) |
bd853ef8 | 736 | { |
2849db67 | 737 | u32 cache_size, cache_unit_size; |
52097446 | 738 | u64 range_base, range_size; |
ccf5ff41 | 739 | u16 w; |
bd853ef8 | 740 | |
0d4491cb | 741 | /* Legacy 1.1 revs aren't handled */ |
c0ccce1b | 742 | if (rev == 0) |
bd853ef8 SK |
743 | return; |
744 | ||
944bb1df | 745 | if (rev >= 1 && len >= PCI_CXL_DEV_LEN) |
3d2d69cb MM |
746 | { |
747 | w = get_conf_word(d, where + PCI_CXL_DEV_CAP); | |
748 | printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n", | |
749 | FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM), | |
750 | FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL)); | |
751 | ||
752 | w = get_conf_word(d, where + PCI_CXL_DEV_CTRL); | |
753 | printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n", | |
754 | FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM), | |
755 | PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN), | |
756 | FLAG(w, PCI_CXL_DEV_CTRL_VIRAL)); | |
757 | ||
758 | w = get_conf_word(d, where + PCI_CXL_DEV_STATUS); | |
759 | printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL)); | |
760 | ||
761 | w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2); | |
762 | printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c", | |
763 | FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING), | |
764 | FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL), | |
765 | FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST), | |
766 | FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN)); | |
767 | if (rev >= 2) | |
768 | printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST)); | |
769 | printf("\n"); | |
770 | ||
771 | w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2); | |
772 | printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n", | |
773 | FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC)); | |
774 | ||
775 | w = get_conf_word(d, where + PCI_CXL_DEV_CAP2); | |
776 | printf("\t\tCXLCap2:\t"); | |
777 | cache_unit_size = BITS(w, 0, 4); | |
778 | cache_size = BITS(w, 8, 8); | |
779 | switch (cache_unit_size) | |
780 | { | |
781 | case PCI_CXL_DEV_CAP2_CACHE_1M: | |
782 | printf("Cache Size: %08x\n", cache_size * (1<<20)); | |
783 | break; | |
784 | case PCI_CXL_DEV_CAP2_CACHE_64K: | |
785 | printf("Cache Size: %08x\n", cache_size * (64<<10)); | |
786 | break; | |
787 | case PCI_CXL_DEV_CAP2_CACHE_UNK: | |
788 | printf("Cache Size Not Reported\n"); | |
789 | break; | |
790 | default: | |
791 | printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size); | |
792 | break; | |
793 | } | |
794 | ||
795 | range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32; | |
796 | range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO); | |
797 | range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32; | |
798 | range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO); | |
799 | cxl_range(range_base, range_size, 1); | |
800 | ||
801 | range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32; | |
802 | range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO); | |
803 | range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32; | |
804 | range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO); | |
805 | cxl_range(range_base, range_size, 2); | |
c0ccce1b | 806 | } |
52097446 | 807 | |
944bb1df | 808 | if (rev >= 2 && len >= PCI_CXL_DEV_LEN_REV2) |
3d2d69cb MM |
809 | { |
810 | w = get_conf_word(d, where + PCI_CXL_DEV_CAP3); | |
811 | printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n", | |
812 | FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD), | |
813 | FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM), | |
814 | FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT), | |
815 | FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG)); | |
816 | } | |
52097446 | 817 | |
c0ccce1b | 818 | // Unparsed data |
944bb1df | 819 | if (len > PCI_CXL_DEV_LEN_REV2) |
c0ccce1b | 820 | printf("\t\t<?>\n"); |
bd853ef8 SK |
821 | } |
822 | ||
c8b83c6c | 823 | static void |
2849db67 | 824 | dvsec_cxl_port(struct device *d, int where, int len) |
c8b83c6c BW |
825 | { |
826 | u16 w, m1, m2; | |
827 | u8 b1, b2; | |
828 | ||
2849db67 MM |
829 | if (len < PCI_CXL_PORT_EXT_LEN) |
830 | return; | |
831 | ||
c8b83c6c BW |
832 | w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS); |
833 | printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS)); | |
834 | ||
835 | w = get_conf_word(d, where + PCI_CXL_PORT_CTRL); | |
836 | printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n", | |
837 | FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK), | |
838 | FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME), | |
839 | FLAG(w, PCI_CXL_PORT_VIRAL_EN)); | |
840 | ||
841 | b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE); | |
842 | b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT); | |
843 | printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2); | |
844 | m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE); | |
845 | m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT); | |
846 | printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2); | |
847 | } | |
848 | ||
2849db67 MM |
849 | static void |
850 | dvsec_cxl_register_locator(struct device *d, int where, int len) | |
0dfa1050 | 851 | { |
2849db67 MM |
852 | static const char * const id_names[] = { |
853 | "empty", | |
854 | "component registers", | |
855 | "BAR virtualization", | |
856 | "CXL device registers", | |
857 | "CPMU registers", | |
858 | }; | |
859 | ||
860 | for (int i=0; ; i++) | |
861 | { | |
55704534 JH |
862 | int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i; |
863 | if (pos + 7 >= where + len) | |
2849db67 | 864 | break; |
0dfa1050 | 865 | |
2849db67 MM |
866 | u32 lo = get_conf_long(d, pos); |
867 | u32 hi = get_conf_long(d, pos + 4); | |
0dfa1050 | 868 | |
2849db67 MM |
869 | unsigned int bir = BITS(lo, 0, 3); |
870 | unsigned int block_id = BITS(lo, 8, 8); | |
871 | u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32); | |
0dfa1050 | 872 | |
2849db67 MM |
873 | if (!block_id) |
874 | continue; | |
0dfa1050 | 875 | |
2849db67 MM |
876 | const char *id_name; |
877 | if (block_id < sizeof(id_names) / sizeof(*id_names)) | |
878 | id_name = id_names[block_id]; | |
879 | else if (block_id == 0xff) | |
880 | id_name = "vendor-specific"; | |
881 | else | |
882 | id_name = "<?>"; | |
0dfa1050 | 883 | |
55704534 | 884 | printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base); |
2849db67 | 885 | } |
0dfa1050 BW |
886 | } |
887 | ||
d462e89c JH |
888 | static void |
889 | dvsec_cxl_gpf_device(struct device *d, int where) | |
890 | { | |
891 | u32 l; | |
892 | u16 w, duration; | |
893 | u8 time_base, time_scale; | |
894 | ||
895 | w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR); | |
896 | time_base = BITS(w, 0, 4); | |
897 | time_scale = BITS(w, 8, 4); | |
898 | ||
899 | switch (time_scale) | |
900 | { | |
901 | case PCI_CXL_GPF_DEV_100US: | |
902 | case PCI_CXL_GPF_DEV_100MS: | |
903 | duration = time_base * 100; | |
904 | break; | |
905 | case PCI_CXL_GPF_DEV_10US: | |
906 | case PCI_CXL_GPF_DEV_10MS: | |
907 | case PCI_CXL_GPF_DEV_10S: | |
908 | duration = time_base * 10; | |
909 | break; | |
910 | case PCI_CXL_GPF_DEV_1US: | |
911 | case PCI_CXL_GPF_DEV_1MS: | |
912 | case PCI_CXL_GPF_DEV_1S: | |
913 | duration = time_base; | |
914 | break; | |
915 | default: | |
916 | /* Reserved */ | |
917 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
918 | duration = time_base; | |
919 | } | |
920 | ||
921 | printf("\t\tGPF Phase 2 Duration: %u%s\n", duration, | |
922 | (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us": | |
923 | (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" : | |
924 | (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>"); | |
925 | ||
926 | l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW); | |
927 | printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l); | |
928 | } | |
929 | ||
5c75f737 JH |
930 | static void |
931 | dvsec_cxl_gpf_port(struct device *d, int where) | |
932 | { | |
933 | u16 w, timeout; | |
934 | u8 time_base, time_scale; | |
935 | ||
936 | w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL); | |
937 | time_base = BITS(w, 0, 4); | |
938 | time_scale = BITS(w, 8, 4); | |
939 | ||
940 | switch (time_scale) | |
941 | { | |
942 | case PCI_CXL_GPF_PORT_100US: | |
943 | case PCI_CXL_GPF_PORT_100MS: | |
944 | timeout = time_base * 100; | |
945 | break; | |
946 | case PCI_CXL_GPF_PORT_10US: | |
947 | case PCI_CXL_GPF_PORT_10MS: | |
948 | case PCI_CXL_GPF_PORT_10S: | |
949 | timeout = time_base * 10; | |
950 | break; | |
951 | case PCI_CXL_GPF_PORT_1US: | |
952 | case PCI_CXL_GPF_PORT_1MS: | |
953 | case PCI_CXL_GPF_PORT_1S: | |
954 | timeout = time_base; | |
955 | break; | |
956 | default: | |
957 | /* Reserved */ | |
958 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
959 | timeout = time_base; | |
960 | } | |
961 | ||
962 | printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout, | |
963 | (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": | |
964 | (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : | |
965 | (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>"); | |
966 | ||
967 | w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL); | |
968 | time_base = BITS(w, 0, 4); | |
969 | time_scale = BITS(w, 8, 4); | |
970 | ||
971 | switch (time_scale) | |
972 | { | |
973 | case PCI_CXL_GPF_PORT_100US: | |
974 | case PCI_CXL_GPF_PORT_100MS: | |
975 | timeout = time_base * 100; | |
976 | break; | |
977 | case PCI_CXL_GPF_PORT_10US: | |
978 | case PCI_CXL_GPF_PORT_10MS: | |
979 | case PCI_CXL_GPF_PORT_10S: | |
980 | timeout = time_base * 10; | |
981 | break; | |
982 | case PCI_CXL_GPF_PORT_1US: | |
983 | case PCI_CXL_GPF_PORT_1MS: | |
984 | case PCI_CXL_GPF_PORT_1S: | |
985 | timeout = time_base; | |
986 | break; | |
987 | default: | |
988 | /* Reserved */ | |
989 | printf("\t\tReserved time scale encoding %x\n", time_scale); | |
990 | timeout = time_base; | |
991 | } | |
992 | ||
993 | printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout, | |
994 | (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us": | |
995 | (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" : | |
996 | (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>"); | |
997 | } | |
998 | ||
9e567a4e | 999 | static void |
23b1ee0c | 1000 | dvsec_cxl_flex_bus(struct device *d, int where, int rev, int len) |
9e567a4e JH |
1001 | { |
1002 | u16 w; | |
1003 | u32 l, data; | |
1004 | ||
23b1ee0c AG |
1005 | // Sanity check: Does the length correspond to its revision? |
1006 | switch (rev) { | |
1007 | case 0: | |
3d2d69cb | 1008 | if (len != PCI_CXL_FB_MOD_TS_DATA) |
23b1ee0c | 1009 | printf("\t\t<Wrong length for Revision %d>\n", rev); |
23b1ee0c AG |
1010 | break; |
1011 | case 1: | |
3d2d69cb | 1012 | if (len != PCI_CXL_FB_PORT_CAP2) |
23b1ee0c | 1013 | printf("\t\t<Wrong length for Revision %d>\n", rev); |
23b1ee0c AG |
1014 | break; |
1015 | case 2: | |
3d2d69cb | 1016 | if (len != PCI_CXL_FB_NEXT_UNSUPPORTED) |
23b1ee0c | 1017 | printf("\t\t<Wrong length for Revision %d>\n", rev); |
23b1ee0c AG |
1018 | break; |
1019 | default: | |
1020 | break; | |
9e567a4e JH |
1021 | } |
1022 | ||
23b1ee0c | 1023 | // From Rev 0 |
9e567a4e JH |
1024 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP); |
1025 | printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c", | |
1026 | FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO), | |
1027 | FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT), | |
1028 | FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV)); | |
1029 | ||
1030 | if (rev > 1) | |
1031 | printf(" 256BFlit%c PBRFlit%c", | |
1032 | FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT)); | |
1033 | ||
1034 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL); | |
1035 | printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c", | |
1036 | FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO), | |
1037 | FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP), | |
1038 | FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT), | |
1039 | FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD), | |
1040 | FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2)); | |
1041 | ||
1042 | if (rev > 1) | |
1043 | printf(" 256BFlit%c PBRFlit%c", | |
1044 | FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT)); | |
1045 | ||
1046 | w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS); | |
1047 | printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c", | |
1048 | FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO), | |
1049 | FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP), | |
1050 | FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT), | |
1051 | FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV)); | |
1052 | ||
1053 | if (rev > 1) | |
1054 | printf(" 256BFlit%c PBRFlit%c", | |
1055 | FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT)); | |
23b1ee0c | 1056 | printf("\n"); |
9e567a4e | 1057 | |
23b1ee0c AG |
1058 | // From Rev 1 |
1059 | if (rev >= 1) | |
3d2d69cb MM |
1060 | { |
1061 | l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA); | |
1062 | data = BITS(l, 0, 24); | |
1063 | printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data); | |
1064 | } | |
9e567a4e | 1065 | |
23b1ee0c AG |
1066 | // From Rev 2 |
1067 | if (rev >= 2) | |
3d2d69cb MM |
1068 | { |
1069 | u8 nop; | |
9e567a4e | 1070 | |
3d2d69cb MM |
1071 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2); |
1072 | printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT)); | |
9e567a4e | 1073 | |
3d2d69cb MM |
1074 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2); |
1075 | printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT)); | |
9e567a4e | 1076 | |
3d2d69cb MM |
1077 | l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2); |
1078 | nop = BITS(l, 0, 2); | |
1079 | printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop); | |
1080 | } | |
23b1ee0c AG |
1081 | |
1082 | // Unparsed data | |
3d2d69cb | 1083 | if (len > PCI_CXL_FB_LEN) |
23b1ee0c | 1084 | printf("\t\t<?>\n"); |
9e567a4e JH |
1085 | } |
1086 | ||
45824262 JH |
1087 | static void |
1088 | dvsec_cxl_mld(struct device *d, int where) | |
1089 | { | |
1090 | u16 w; | |
1091 | ||
1092 | w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD); | |
1093 | ||
1094 | /* Encodings greater than 16 are reserved */ | |
1095 | if (w && w <= PCI_CXL_MLD_MAX_LD) | |
1096 | printf("\t\tNumLogDevs: %d\n", w); | |
1097 | } | |
1098 | ||
ec4cd47b JH |
1099 | static void |
1100 | dvsec_cxl_function_map(struct device *d, int where) | |
1101 | { | |
1102 | ||
1103 | printf("\t\tFuncMap 0: %08x\n", | |
1104 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0))); | |
1105 | ||
1106 | printf("\t\tFuncMap 1: %08x\n", | |
1107 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1))); | |
1108 | ||
1109 | printf("\t\tFuncMap 2: %08x\n", | |
1110 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2))); | |
1111 | ||
1112 | printf("\t\tFuncMap 3: %08x\n", | |
1113 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3))); | |
1114 | ||
1115 | printf("\t\tFuncMap 4: %08x\n", | |
1116 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4))); | |
1117 | ||
1118 | printf("\t\tFuncMap 5: %08x\n", | |
1119 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5))); | |
1120 | ||
1121 | printf("\t\tFuncMap 6: %08x\n", | |
1122 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6))); | |
1123 | ||
1124 | printf("\t\tFuncMap 7: %08x\n", | |
1125 | (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7))); | |
1126 | } | |
1127 | ||
0d4491cb | 1128 | static void |
2849db67 | 1129 | cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len) |
0d4491cb | 1130 | { |
0d4491cb BW |
1131 | printf(": CXL\n"); |
1132 | if (verbose < 2) | |
1133 | return; | |
1134 | ||
2849db67 MM |
1135 | if (!config_fetch(d, where, len)) |
1136 | return; | |
0d4491cb | 1137 | |
2849db67 MM |
1138 | switch (id) |
1139 | { | |
c8b83c6c | 1140 | case 0: |
23b1ee0c | 1141 | printf("\t\tPCIe DVSEC for CXL Devices\n"); |
2849db67 | 1142 | dvsec_cxl_device(d, rev, where, len); |
0dfa1050 | 1143 | break; |
fe0df5d3 | 1144 | case 2: |
23b1ee0c | 1145 | printf("\t\tNon-CXL Function Map DVSEC\n"); |
ec4cd47b | 1146 | dvsec_cxl_function_map(d, where); |
fe0df5d3 | 1147 | break; |
2849db67 | 1148 | case 3: |
23b1ee0c | 1149 | printf("\t\tCXL Extensions DVSEC for Ports\n"); |
2849db67 MM |
1150 | dvsec_cxl_port(d, where, len); |
1151 | break; | |
fe0df5d3 | 1152 | case 4: |
23b1ee0c | 1153 | printf("\t\tGPF DVSEC for CXL Ports\n"); |
5c75f737 | 1154 | dvsec_cxl_gpf_port(d, where); |
fe0df5d3 BW |
1155 | break; |
1156 | case 5: | |
23b1ee0c | 1157 | printf("\t\tGPF DVSEC for CXL Devices\n"); |
d462e89c | 1158 | dvsec_cxl_gpf_device(d, where); |
fe0df5d3 BW |
1159 | break; |
1160 | case 7: | |
23b1ee0c AG |
1161 | printf("\t\tPCIe DVSEC for Flex Bus Port\n"); |
1162 | dvsec_cxl_flex_bus(d, where, rev, len); | |
fe0df5d3 | 1163 | break; |
2849db67 | 1164 | case 8: |
23b1ee0c | 1165 | printf("\t\tRegister Locator DVSEC\n"); |
2849db67 MM |
1166 | dvsec_cxl_register_locator(d, where, len); |
1167 | break; | |
fe0df5d3 | 1168 | case 9: |
23b1ee0c | 1169 | printf("\t\tMLD DVSEC\n"); |
45824262 | 1170 | dvsec_cxl_mld(d, where); |
fe0df5d3 | 1171 | break; |
23b1ee0c AG |
1172 | case 0xa: |
1173 | printf("\t\tPCIe DVSEC for Test Capability <?>\n"); | |
1174 | break; | |
c8b83c6c | 1175 | default: |
2849db67 MM |
1176 | printf("\t\tUnknown ID %04x\n", id); |
1177 | } | |
0d4491cb BW |
1178 | } |
1179 | ||
5f1d1265 SK |
1180 | static void |
1181 | cap_dvsec(struct device *d, int where) | |
1182 | { | |
71aeac63 | 1183 | printf("Designated Vendor-Specific: "); |
5f1d1265 SK |
1184 | if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8)) |
1185 | { | |
1186 | printf("<unreadable>\n"); | |
1187 | return; | |
1188 | } | |
1189 | ||
71aeac63 MM |
1190 | u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1); |
1191 | u16 vendor = BITS(hdr, 0, 16); | |
1192 | byte rev = BITS(hdr, 16, 4); | |
1193 | u16 len = BITS(hdr, 20, 12); | |
5f1d1265 | 1194 | |
71aeac63 MM |
1195 | u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2); |
1196 | ||
1197 | printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len); | |
6c138204 | 1198 | if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16) |
2849db67 | 1199 | cap_dvsec_cxl(d, id, rev, where, len); |
71aeac63 MM |
1200 | else |
1201 | printf(" <?>\n"); | |
5f1d1265 SK |
1202 | } |
1203 | ||
78ca9582 MM |
1204 | static void |
1205 | cap_evendor(struct device *d, int where) | |
1206 | { | |
1207 | u32 hdr; | |
1208 | ||
1209 | printf("Vendor Specific Information: "); | |
1210 | if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4)) | |
1211 | { | |
1212 | printf("<unreadable>\n"); | |
1213 | return; | |
1214 | } | |
1215 | ||
1216 | hdr = get_conf_long(d, where + PCI_EVNDR_HEADER); | |
1217 | printf("ID=%04x Rev=%d Len=%03x <?>\n", | |
1218 | BITS(hdr, 0, 16), | |
1219 | BITS(hdr, 16, 4), | |
1220 | BITS(hdr, 20, 12)); | |
1221 | } | |
1222 | ||
fb17077d | 1223 | static int l1pm_calc_pwron(int scale, int value) |
8efbe075 RJ |
1224 | { |
1225 | switch (scale) | |
1226 | { | |
1227 | case 0: | |
1228 | return 2 * value; | |
1229 | case 1: | |
1230 | return 10 * value; | |
1231 | case 2: | |
1232 | return 100 * value; | |
1233 | } | |
1234 | return -1; | |
1235 | } | |
1236 | ||
214c9a95 DB |
1237 | static void |
1238 | cap_l1pm(struct device *d, int where) | |
1239 | { | |
8efbe075 RJ |
1240 | u32 l1_cap, val, scale; |
1241 | int time; | |
214c9a95 DB |
1242 | |
1243 | printf("L1 PM Substates\n"); | |
1244 | ||
1245 | if (verbose < 2) | |
1246 | return; | |
1247 | ||
8efbe075 | 1248 | if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12)) |
214c9a95 DB |
1249 | { |
1250 | printf("\t\t<unreadable>\n"); | |
1251 | return; | |
1252 | } | |
1253 | ||
8efbe075 | 1254 | l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP); |
214c9a95 | 1255 | printf("\t\tL1SubCap: "); |
e495466c | 1256 | printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n", |
8efbe075 RJ |
1257 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12), |
1258 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11), | |
1259 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12), | |
1260 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11), | |
1261 | FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP)); | |
1262 | ||
fb17077d | 1263 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
214c9a95 | 1264 | { |
fb17077d | 1265 | printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8)); |
8efbe075 RJ |
1266 | time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5)); |
1267 | if (time != -1) | |
1268 | printf("PortTPowerOnTime=%dus\n", time); | |
1269 | else | |
1270 | printf("PortTPowerOnTime=<error>\n"); | |
1271 | } | |
214c9a95 | 1272 | |
8efbe075 | 1273 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1); |
fb17077d | 1274 | printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n", |
8efbe075 RJ |
1275 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12), |
1276 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11), | |
1277 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12), | |
1278 | FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11)); | |
1279 | ||
fb17077d | 1280 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) |
8efbe075 | 1281 | { |
6469d596 VL |
1282 | printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8)); |
1283 | ||
1284 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
1285 | { | |
1286 | scale = BITS(val, 29, 3); | |
1287 | if (scale > 5) | |
1288 | printf(" LTR1.2_Threshold=<error>"); | |
1289 | else | |
c3d1d465 | 1290 | printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale)); |
6469d596 VL |
1291 | } |
1292 | printf("\n"); | |
8efbe075 RJ |
1293 | } |
1294 | ||
1295 | val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2); | |
fb17077d MM |
1296 | printf("\t\tL1SubCtl2:"); |
1297 | if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12) | |
8efbe075 RJ |
1298 | { |
1299 | time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5)); | |
1300 | if (time != -1) | |
fb17077d | 1301 | printf(" T_PwrOn=%dus", time); |
8efbe075 | 1302 | else |
fb17077d | 1303 | printf(" T_PwrOn=<error>"); |
214c9a95 | 1304 | } |
fb17077d | 1305 | printf("\n"); |
214c9a95 DB |
1306 | } |
1307 | ||
415a9c18 YJ |
1308 | static void |
1309 | cap_ptm(struct device *d, int where) | |
1310 | { | |
1311 | u32 buff; | |
1312 | u16 clock; | |
1313 | ||
1314 | printf("Precision Time Measurement\n"); | |
1315 | ||
1316 | if (verbose < 2) | |
1317 | return; | |
1318 | ||
1319 | if (!config_fetch(d, where + 4, 8)) | |
1320 | { | |
1321 | printf("\t\t<unreadable>\n"); | |
1322 | return; | |
1323 | } | |
1324 | ||
1325 | buff = get_conf_long(d, where + 4); | |
1326 | printf("\t\tPTMCap: "); | |
b2caca01 | 1327 | printf("Requester%c Responder%c Root%c\n", |
415a9c18 YJ |
1328 | FLAG(buff, 0x1), |
1329 | FLAG(buff, 0x2), | |
1330 | FLAG(buff, 0x4)); | |
1331 | ||
1332 | clock = BITS(buff, 8, 8); | |
1333 | printf("\t\tPTMClockGranularity: "); | |
1334 | switch (clock) | |
1335 | { | |
1336 | case 0x00: | |
1337 | printf("Unimplemented\n"); | |
1338 | break; | |
1339 | case 0xff: | |
1340 | printf("Greater than 254ns\n"); | |
1341 | break; | |
1342 | default: | |
1343 | printf("%huns\n", clock); | |
1344 | } | |
1345 | ||
1346 | buff = get_conf_long(d, where + 8); | |
1347 | printf("\t\tPTMControl: "); | |
b2caca01 | 1348 | printf("Enabled%c RootSelected%c\n", |
415a9c18 YJ |
1349 | FLAG(buff, 0x1), |
1350 | FLAG(buff, 0x2)); | |
1351 | ||
1352 | clock = BITS(buff, 8, 8); | |
1353 | printf("\t\tPTMEffectiveGranularity: "); | |
1354 | switch (clock) | |
1355 | { | |
1356 | case 0x00: | |
1357 | printf("Unknown\n"); | |
1358 | break; | |
1359 | case 0xff: | |
1360 | printf("Greater than 254ns\n"); | |
1361 | break; | |
1362 | default: | |
1363 | printf("%huns\n", clock); | |
1364 | } | |
1365 | } | |
1366 | ||
44c6c7fc MM |
1367 | static void |
1368 | print_rebar_range_size(int ld2_size) | |
1369 | { | |
1370 | // This function prints the input as a power-of-2 size value | |
1371 | // It is biased with 1MB = 0, ... | |
1372 | // Maximum resizable BAR value supported is 2^63 bytes = 43 | |
1373 | // for the extended resizable BAR capability definition | |
1374 | // (otherwise it would stop at 2^28) | |
1375 | ||
1376 | if (ld2_size >= 0 && ld2_size < 10) | |
1377 | printf(" %dMB", (1 << ld2_size)); | |
1378 | else if (ld2_size >= 10 && ld2_size < 20) | |
1379 | printf(" %dGB", (1 << (ld2_size-10))); | |
1380 | else if (ld2_size >= 20 && ld2_size < 30) | |
1381 | printf(" %dTB", (1 << (ld2_size-20))); | |
1382 | else if (ld2_size >= 30 && ld2_size < 40) | |
1383 | printf(" %dPB", (1 << (ld2_size-30))); | |
1384 | else if (ld2_size >= 40 && ld2_size < 44) | |
1385 | printf(" %dEB", (1 << (ld2_size-40))); | |
1386 | else | |
1387 | printf(" <unknown>"); | |
1388 | } | |
1389 | ||
1390 | static void | |
1391 | cap_rebar(struct device *d, int where, int virtual) | |
1392 | { | |
1393 | u32 sizes_buffer, control_buffer, ext_sizes, current_size; | |
d10c2aa1 MM |
1394 | u16 bar_index, barcount, i; |
1395 | // If the structure exists, at least one bar is defined | |
44c6c7fc MM |
1396 | u16 num_bars = 1; |
1397 | ||
1398 | printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical"); | |
1399 | ||
d10c2aa1 | 1400 | if (verbose < 2) |
44c6c7fc MM |
1401 | return; |
1402 | ||
1403 | // Go through all defined BAR definitions of the caps, at minimum 1 | |
1404 | // (loop also terminates if num_bars read from caps is > 6) | |
1405 | for (barcount = 0; barcount < num_bars; barcount++) | |
1406 | { | |
1407 | where += 4; | |
1408 | ||
1409 | // Get the next BAR configuration | |
1410 | if (!config_fetch(d, where, 8)) | |
1411 | { | |
1412 | printf("\t\t<unreadable>\n"); | |
1413 | return; | |
1414 | } | |
1415 | ||
1416 | sizes_buffer = get_conf_long(d, where) >> 4; | |
44c6c7fc | 1417 | where += 4; |
44c6c7fc MM |
1418 | control_buffer = get_conf_long(d, where); |
1419 | ||
d10c2aa1 MM |
1420 | bar_index = BITS(control_buffer, 0, 3); |
1421 | current_size = BITS(control_buffer, 8, 6); | |
1422 | ext_sizes = BITS(control_buffer, 16, 16); | |
44c6c7fc MM |
1423 | |
1424 | if (barcount == 0) | |
1425 | { | |
1426 | // Only index 0 controlreg has the num_bar count definition | |
d10c2aa1 MM |
1427 | num_bars = BITS(control_buffer, 5, 3); |
1428 | if (num_bars < 1 || num_bars > 6) | |
1429 | { | |
1430 | printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars); | |
1431 | break; | |
1432 | } | |
44c6c7fc MM |
1433 | } |
1434 | ||
1435 | // Resizable BAR list entry have an arbitrary index and current size | |
d10c2aa1 | 1436 | printf("\t\tBAR %d: current size:", bar_index); |
44c6c7fc MM |
1437 | print_rebar_range_size(current_size); |
1438 | ||
d10c2aa1 MM |
1439 | if (sizes_buffer || ext_sizes) |
1440 | { | |
1441 | printf(", supported:"); | |
44c6c7fc | 1442 | |
d10c2aa1 MM |
1443 | for (i=0; i<28; i++) |
1444 | if (sizes_buffer & (1U << i)) | |
1445 | print_rebar_range_size(i); | |
44c6c7fc | 1446 | |
d10c2aa1 MM |
1447 | for (i=0; i<16; i++) |
1448 | if (ext_sizes & (1U << i)) | |
1449 | print_rebar_range_size(i + 28); | |
1450 | } | |
44c6c7fc | 1451 | |
44c6c7fc MM |
1452 | printf("\n"); |
1453 | } | |
1454 | } | |
1455 | ||
60be9345 JC |
1456 | static void |
1457 | cap_doe(struct device *d, int where) | |
1458 | { | |
1459 | u32 l; | |
1460 | ||
1461 | printf("Data Object Exchange\n"); | |
1462 | ||
1463 | if (verbose < 2) | |
1464 | return; | |
1465 | ||
1466 | if (!config_fetch(d, where + PCI_DOE_CAP, 0x14)) | |
1467 | { | |
1468 | printf("\t\t<unreadable>\n"); | |
1469 | return; | |
1470 | } | |
1471 | ||
1472 | l = get_conf_long(d, where + PCI_DOE_CAP); | |
1473 | printf("\t\tDOECap: IntSup%c\n", | |
1474 | FLAG(l, PCI_DOE_CAP_INT_SUPP)); | |
1475 | if (l & PCI_DOE_CAP_INT_SUPP) | |
aeb74fe2 | 1476 | printf("\t\t\tIntMsgNum %d\n", |
60be9345 JC |
1477 | PCI_DOE_CAP_INT_MSG(l)); |
1478 | ||
1479 | l = get_conf_long(d, where + PCI_DOE_CTL); | |
1480 | printf("\t\tDOECtl: IntEn%c\n", | |
1481 | FLAG(l, PCI_DOE_CTL_INT)); | |
1482 | ||
1483 | l = get_conf_long(d, where + PCI_DOE_STS); | |
1484 | printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n", | |
1485 | FLAG(l, PCI_DOE_STS_BUSY), | |
1486 | FLAG(l, PCI_DOE_STS_INT), | |
1487 | FLAG(l, PCI_DOE_STS_ERROR), | |
1488 | FLAG(l, PCI_DOE_STS_OBJECT_READY)); | |
1489 | } | |
1490 | ||
42fc4263 AK |
1491 | static const char *offstr(char *buf, u32 off) |
1492 | { | |
1493 | if (verbose < 3) | |
1494 | return ""; | |
1495 | ||
1496 | sprintf(buf, "[%x]", off); | |
1497 | return buf; | |
1498 | } | |
1499 | ||
1500 | static const char *ide_alg(char *buf, size_t len, u32 l) | |
1501 | { | |
1502 | const char *algo[] = { "AES-GCM-256-96b" }; // AES-GCM 256 key size, 96b MAC | |
1503 | ||
1504 | if (l == 0) | |
1505 | snprintf(buf, len, "%s", algo[l]); | |
1506 | else | |
1507 | snprintf(buf, len, "%s", "reserved"); | |
1508 | return buf; | |
1509 | } | |
1510 | ||
1511 | static void | |
1512 | cap_ide(struct device *d, int where) | |
1513 | { | |
1514 | const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" }; | |
1515 | const char *stream_state[] = { "insecure", "secure" }; | |
1516 | const char *aggr[] = { "-", "=2", "=4", "=8" }; | |
1517 | u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j; | |
1518 | char buf1[16], buf2[16], offs[16]; | |
1519 | ||
1520 | printf("Integrity & Data Encryption\n"); | |
1521 | ||
1522 | if (verbose < 2) | |
1523 | return; | |
1524 | ||
1525 | if (!config_fetch(d, where + PCI_IDE_CAP, 8)) | |
1526 | { | |
1527 | printf("\t\t<unreadable>\n"); | |
1528 | return; | |
1529 | } | |
1530 | ||
1531 | l = get_conf_long(d, where + PCI_IDE_CAP); | |
1532 | if (l & PCI_IDE_CAP_LINK_IDE_SUPP) | |
1533 | linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1; | |
1534 | if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP) | |
1535 | selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1; | |
1536 | ||
1537 | printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c\n", | |
1538 | linknum, | |
1539 | selnum, | |
1540 | FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP), | |
1541 | FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP), | |
1542 | FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP), | |
1543 | FLAG(l, PCI_IDE_CAP_PCRC_SUPP), | |
1544 | FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP), | |
1545 | ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)), | |
1546 | PCI_IDE_CAP_LINK_TC_NUM(l) + 1, | |
1547 | FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP) | |
1548 | ); | |
1549 | ||
1550 | l = get_conf_long(d, where + PCI_IDE_CTL); | |
1551 | printf("\t\tIDECtl: FTEn%c\n", | |
1552 | FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE)); | |
1553 | ||
1554 | // The rest of the capability is variable length arrays | |
1555 | off = where + PCI_IDE_LINK_STREAM; | |
1556 | ||
1557 | // Link IDE Register Block repeated 0 to 8 times | |
1558 | if (linknum) | |
1559 | { | |
1560 | if (!config_fetch(d, off, 8 * linknum)) | |
1561 | { | |
1562 | printf("\t\t<unreadable>\n"); | |
1563 | return; | |
1564 | } | |
1565 | for (i = 0; i < linknum; ++i) | |
1566 | { | |
1567 | // Link IDE Stream Control Register | |
1568 | l = get_conf_long(d, off); | |
1569 | printf("\t\t%sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n", | |
1570 | offstr(offs, off), | |
1571 | i, | |
1572 | FLAG(l, PCI_IDE_LINK_CTL_EN), | |
1573 | aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)], | |
1574 | aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)], | |
1575 | aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)], | |
1576 | FLAG(l, PCI_IDE_LINK_CTL_EN), | |
1577 | TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1), | |
1578 | ide_alg(buf2, sizeof(buf2), PCI_IDE_LINK_CTL_ALG(l)), | |
1579 | PCI_IDE_LINK_CTL_TC(l), | |
1580 | PCI_IDE_LINK_CTL_ID(l) | |
1581 | ); | |
1582 | off += 4; | |
1583 | ||
1584 | /* Link IDE Stream Status Register */ | |
1585 | l = get_conf_long(d, off); | |
1586 | printf("\t\t%sLinkIDE#%d Sta: Status=%s RecvChkFail%c\n", | |
1587 | offstr(offs, off), | |
1588 | i, | |
1589 | TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1), | |
1590 | FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK)); | |
1591 | off += 4; | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | for (i = 0; i < selnum; ++i) | |
1596 | { | |
1597 | // Fetching Selective IDE Stream Capability/Control/Status/RID1/RID2 | |
1598 | if (!config_fetch(d, off, 20)) | |
1599 | { | |
1600 | printf("\t\t<unreadable>\n"); | |
1601 | return; | |
1602 | } | |
1603 | ||
1604 | // Selective IDE Stream Capability Register | |
1605 | l = get_conf_long(d, off); | |
1606 | printf("\t\t%sSelectiveIDE#%d Cap: RID#=%d\n", | |
1607 | offstr(offs, off), | |
1608 | i, | |
1609 | PCI_IDE_SEL_CAP_BLOCKS_NUM(l)); | |
1610 | off += 4; | |
1611 | addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l); | |
1612 | ||
1613 | // Selective IDE Stream Control Register | |
1614 | l = get_conf_long(d, off); | |
1615 | ||
1616 | printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n", | |
1617 | offstr(offs, off), | |
1618 | i, | |
1619 | FLAG(l, PCI_IDE_SEL_CTL_EN), | |
1620 | aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)], | |
1621 | aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)], | |
1622 | aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)], | |
1623 | FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN), | |
1624 | TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1), | |
1625 | ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)), | |
1626 | PCI_IDE_SEL_CTL_TC(l), | |
1627 | PCI_IDE_SEL_CTL_ID(l), | |
1628 | (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : "" | |
1629 | ); | |
1630 | off += 4; | |
1631 | ||
1632 | // Selective IDE Stream Status Register | |
1633 | l = get_conf_long(d, off); | |
1634 | printf("\t\t%sSelectiveIDE#%d Sta: %s RecvChkFail%c\n", | |
1635 | offstr(offs, off), | |
1636 | i , | |
1637 | TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1), | |
1638 | FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK)); | |
1639 | off += 4; | |
1640 | ||
1641 | // IDE RID Association Registers | |
1642 | l = get_conf_long(d, off); | |
1643 | l2 = get_conf_long(d, off + 4); | |
1644 | ||
1645 | printf("\t\t%sSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x\n", | |
1646 | offstr(offs, off), | |
1647 | i, | |
1648 | FLAG(l2, PCI_IDE_SEL_RID_2_VALID), | |
1649 | PCI_IDE_SEL_RID_2_BASE(l2), | |
1650 | PCI_IDE_SEL_RID_1_LIMIT(l), | |
1651 | PCI_IDE_SEL_RID_2_SEG_BASE(l2)); | |
1652 | off += 8; | |
1653 | ||
1654 | if (!config_fetch(d, off, addrnum * 12)) | |
1655 | { | |
1656 | printf("\t\t<unreadable>\n"); | |
1657 | return; | |
1658 | } | |
1659 | ||
1660 | // IDE Address Association Registers | |
1661 | for (j = 0; j < addrnum; ++j) | |
1662 | { | |
1663 | u64 limit, base; | |
1664 | ||
1665 | l = get_conf_long(d, off); | |
1666 | limit = get_conf_long(d, off + 4); | |
1667 | base = get_conf_long(d, off + 8); | |
1668 | printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n", | |
1669 | offstr(offs, off), | |
1670 | i, | |
1671 | j, | |
1672 | FLAG(l, PCI_IDE_SEL_ADDR_1_VALID), | |
1673 | (base << 32) | PCI_IDE_SEL_ADDR_1_BASE_LOW(l), | |
1674 | (limit << 32) | PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l)); | |
1675 | off += 12; | |
1676 | } | |
1677 | } | |
1678 | } | |
1679 | ||
c7a34993 | 1680 | void |
a1492b88 | 1681 | show_ext_caps(struct device *d, int type) |
c7a34993 MM |
1682 | { |
1683 | int where = 0x100; | |
1684 | char been_there[0x1000]; | |
1685 | memset(been_there, 0, 0x1000); | |
1686 | do | |
1687 | { | |
1688 | u32 header; | |
33088c24 | 1689 | int id, version; |
c7a34993 MM |
1690 | |
1691 | if (!config_fetch(d, where, 4)) | |
1692 | break; | |
1693 | header = get_conf_long(d, where); | |
861063f3 | 1694 | if (!header || header == 0xffffffff) |
c7a34993 MM |
1695 | break; |
1696 | id = header & 0xffff; | |
33088c24 MM |
1697 | version = (header >> 16) & 0xf; |
1698 | printf("\tCapabilities: [%03x", where); | |
1699 | if (verbose > 1) | |
1700 | printf(" v%d", version); | |
1701 | printf("] "); | |
c7a34993 MM |
1702 | if (been_there[where]++) |
1703 | { | |
1704 | printf("<chain looped>\n"); | |
1705 | break; | |
1706 | } | |
1707 | switch (id) | |
1708 | { | |
c508d1c9 BH |
1709 | case PCI_EXT_CAP_ID_NULL: |
1710 | printf("Null\n"); | |
1711 | break; | |
c7a34993 | 1712 | case PCI_EXT_CAP_ID_AER: |
a1492b88 | 1713 | cap_aer(d, where, type); |
c7a34993 | 1714 | break; |
de91b6f2 KB |
1715 | case PCI_EXT_CAP_ID_DPC: |
1716 | cap_dpc(d, where); | |
1717 | break; | |
c7a34993 | 1718 | case PCI_EXT_CAP_ID_VC: |
33088c24 MM |
1719 | case PCI_EXT_CAP_ID_VC2: |
1720 | cap_vc(d, where); | |
c7a34993 MM |
1721 | break; |
1722 | case PCI_EXT_CAP_ID_DSN: | |
1723 | cap_dsn(d, where); | |
1724 | break; | |
1725 | case PCI_EXT_CAP_ID_PB: | |
1726 | printf("Power Budgeting <?>\n"); | |
1727 | break; | |
1728 | case PCI_EXT_CAP_ID_RCLINK: | |
5a9a932c | 1729 | cap_rclink(d, where); |
c7a34993 MM |
1730 | break; |
1731 | case PCI_EXT_CAP_ID_RCILINK: | |
1732 | printf("Root Complex Internal Link <?>\n"); | |
1733 | break; | |
e12bd01e SK |
1734 | case PCI_EXT_CAP_ID_RCEC: |
1735 | cap_rcec(d, where); | |
c7a34993 MM |
1736 | break; |
1737 | case PCI_EXT_CAP_ID_MFVC: | |
1738 | printf("Multi-Function Virtual Channel <?>\n"); | |
1739 | break; | |
eff08b33 BH |
1740 | case PCI_EXT_CAP_ID_RCRB: |
1741 | printf("Root Complex Register Block <?>\n"); | |
c7a34993 MM |
1742 | break; |
1743 | case PCI_EXT_CAP_ID_VNDR: | |
78ca9582 | 1744 | cap_evendor(d, where); |
c7a34993 MM |
1745 | break; |
1746 | case PCI_EXT_CAP_ID_ACS: | |
1747 | cap_acs(d, where); | |
1748 | break; | |
1749 | case PCI_EXT_CAP_ID_ARI: | |
1750 | cap_ari(d, where); | |
1751 | break; | |
1752 | case PCI_EXT_CAP_ID_ATS: | |
1753 | cap_ats(d, where); | |
1754 | break; | |
1755 | case PCI_EXT_CAP_ID_SRIOV: | |
1756 | cap_sriov(d, where); | |
1757 | break; | |
b8f7cd64 BH |
1758 | case PCI_EXT_CAP_ID_MRIOV: |
1759 | printf("Multi-Root I/O Virtualization <?>\n"); | |
1760 | break; | |
c0d9545c BH |
1761 | case PCI_EXT_CAP_ID_MCAST: |
1762 | cap_multicast(d, where, type); | |
1763 | break; | |
a858df0d DW |
1764 | case PCI_EXT_CAP_ID_PRI: |
1765 | cap_pri(d, where); | |
1766 | break; | |
b8f7cd64 | 1767 | case PCI_EXT_CAP_ID_REBAR: |
44c6c7fc | 1768 | cap_rebar(d, where, 0); |
b8f7cd64 BH |
1769 | break; |
1770 | case PCI_EXT_CAP_ID_DPA: | |
1771 | printf("Dynamic Power Allocation <?>\n"); | |
1772 | break; | |
67da1792 MM |
1773 | case PCI_EXT_CAP_ID_TPH: |
1774 | cap_tph(d, where); | |
1775 | break; | |
1776 | case PCI_EXT_CAP_ID_LTR: | |
1777 | cap_ltr(d, where); | |
1778 | break; | |
b8f7cd64 | 1779 | case PCI_EXT_CAP_ID_SECPCI: |
9225e71d | 1780 | cap_sec(d, where); |
b8f7cd64 BH |
1781 | break; |
1782 | case PCI_EXT_CAP_ID_PMUX: | |
1783 | printf("Protocol Multiplexing <?>\n"); | |
1784 | break; | |
a858df0d DW |
1785 | case PCI_EXT_CAP_ID_PASID: |
1786 | cap_pasid(d, where); | |
1787 | break; | |
b8f7cd64 BH |
1788 | case PCI_EXT_CAP_ID_LNR: |
1789 | printf("LN Requester <?>\n"); | |
1790 | break; | |
214c9a95 DB |
1791 | case PCI_EXT_CAP_ID_L1PM: |
1792 | cap_l1pm(d, where); | |
1793 | break; | |
415a9c18 YJ |
1794 | case PCI_EXT_CAP_ID_PTM: |
1795 | cap_ptm(d, where); | |
1796 | break; | |
b8f7cd64 BH |
1797 | case PCI_EXT_CAP_ID_M_PCIE: |
1798 | printf("PCI Express over M_PHY <?>\n"); | |
1799 | break; | |
1800 | case PCI_EXT_CAP_ID_FRS: | |
1801 | printf("FRS Queueing <?>\n"); | |
1802 | break; | |
1803 | case PCI_EXT_CAP_ID_RTR: | |
1804 | printf("Readiness Time Reporting <?>\n"); | |
1805 | break; | |
1806 | case PCI_EXT_CAP_ID_DVSEC: | |
71aeac63 | 1807 | cap_dvsec(d, where); |
b8f7cd64 BH |
1808 | break; |
1809 | case PCI_EXT_CAP_ID_VF_REBAR: | |
44c6c7fc | 1810 | cap_rebar(d, where, 1); |
b8f7cd64 BH |
1811 | break; |
1812 | case PCI_EXT_CAP_ID_DLNK: | |
1813 | printf("Data Link Feature <?>\n"); | |
1814 | break; | |
1815 | case PCI_EXT_CAP_ID_16GT: | |
1816 | printf("Physical Layer 16.0 GT/s <?>\n"); | |
1817 | break; | |
1818 | case PCI_EXT_CAP_ID_LMR: | |
d016c32d | 1819 | cap_lmr(d, where); |
b8f7cd64 BH |
1820 | break; |
1821 | case PCI_EXT_CAP_ID_HIER_ID: | |
1822 | printf("Hierarchy ID <?>\n"); | |
1823 | break; | |
1824 | case PCI_EXT_CAP_ID_NPEM: | |
1825 | printf("Native PCIe Enclosure Management <?>\n"); | |
1826 | break; | |
db43fb5e MN |
1827 | case PCI_EXT_CAP_ID_32GT: |
1828 | printf("Physical Layer 32.0 GT/s <?>\n"); | |
1829 | break; | |
60be9345 JC |
1830 | case PCI_EXT_CAP_ID_DOE: |
1831 | cap_doe(d, where); | |
1832 | break; | |
42fc4263 AK |
1833 | case PCI_EXT_CAP_ID_IDE: |
1834 | cap_ide(d, where); | |
1835 | break; | |
c7a34993 | 1836 | default: |
60a45a7e | 1837 | printf("Extended Capability ID %#02x\n", id); |
c7a34993 MM |
1838 | break; |
1839 | } | |
d61c4772 | 1840 | where = (header >> 20) & ~3; |
c7a34993 MM |
1841 | } while (where); |
1842 | } |