ls-caps.c

   1 /*
   2  *      The PCI Utilities -- Show Capabilities
   3  *
   4  *      Copyright (c) 1997--2018 Martin Mares <mj@ucw.cz>
   5  *
   6  *      Can be freely distributed and used under the terms of the GNU GPL.
   7  */
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11
  12 #include "lspci.h"
  13
  14 static void
  15 cap_pm(struct device *d, int where, int cap)
  16 {
  17   int t, b;
  18   static int pm_aux_current[8] = { 0, 55, 100, 160, 220, 270, 320, 375 };
  19
  20   printf("Power Management version %d\n", cap & PCI_PM_CAP_VER_MASK);
  21   if (verbose < 2)
  22     return;
  23   printf("\t\tFlags: PMEClk%c DSI%c D1%c D2%c AuxCurrent=%dmA PME(D0%c,D1%c,D2%c,D3hot%c,D3cold%c)\n",
  24          FLAG(cap, PCI_PM_CAP_PME_CLOCK),
  25          FLAG(cap, PCI_PM_CAP_DSI),
  26          FLAG(cap, PCI_PM_CAP_D1),
  27          FLAG(cap, PCI_PM_CAP_D2),
  28          pm_aux_current[(cap & PCI_PM_CAP_AUX_C_MASK) >> 6],
  29          FLAG(cap, PCI_PM_CAP_PME_D0),
  30          FLAG(cap, PCI_PM_CAP_PME_D1),
  31          FLAG(cap, PCI_PM_CAP_PME_D2),
  32          FLAG(cap, PCI_PM_CAP_PME_D3_HOT),
  33          FLAG(cap, PCI_PM_CAP_PME_D3_COLD));
  34   if (!config_fetch(d, where + PCI_PM_CTRL, PCI_PM_SIZEOF - PCI_PM_CTRL))
  35     return;
  36   t = get_conf_word(d, where + PCI_PM_CTRL);
  37   printf("\t\tStatus: D%d NoSoftRst%c PME-Enable%c DSel=%d DScale=%d PME%c\n",
  38          t & PCI_PM_CTRL_STATE_MASK,
  39          FLAG(t, PCI_PM_CTRL_NO_SOFT_RST),
  40          FLAG(t, PCI_PM_CTRL_PME_ENABLE),
  41          (t & PCI_PM_CTRL_DATA_SEL_MASK) >> 9,
  42          (t & PCI_PM_CTRL_DATA_SCALE_MASK) >> 13,
  43          FLAG(t, PCI_PM_CTRL_PME_STATUS));
  44   b = get_conf_byte(d, where + PCI_PM_PPB_EXTENSIONS);
  45   if (b)
  46     printf("\t\tBridge: PM%c B3%c\n",
  47            FLAG(t, PCI_PM_BPCC_ENABLE),
  48            FLAG(~t, PCI_PM_PPB_B2_B3));
  49 }
  50
  51 static void
  52 format_agp_rate(int rate, char *buf, int agp3)
  53 {
  54   char *c = buf;
  55   int i;
  56
  57   for (i=0; i<=2; i++)
  58     if (rate & (1 << i))
  59       {
  60         if (c != buf)
  61           *c++ = ',';
  62         c += sprintf(c, "x%d", 1 << (i + 2*agp3));
  63       }
  64   if (c != buf)
  65     *c = 0;
  66   else
  67     strcpy(buf, "<none>");
  68 }
  69
  70 static void
  71 cap_agp(struct device *d, int where, int cap)
  72 {
  73   u32 t;
  74   char rate[16];
  75   int ver, rev;
  76   int agp3 = 0;
  77
  78   ver = (cap >> 4) & 0x0f;
  79   rev = cap & 0x0f;
  80   printf("AGP version %x.%x\n", ver, rev);
  81   if (verbose < 2)
  82     return;
  83   if (!config_fetch(d, where + PCI_AGP_STATUS, PCI_AGP_SIZEOF - PCI_AGP_STATUS))
  84     return;
  85   t = get_conf_long(d, where + PCI_AGP_STATUS);
  86   if (ver >= 3 && (t & PCI_AGP_STATUS_AGP3))
  87     agp3 = 1;
  88   format_agp_rate(t & 7, rate, agp3);
  89   printf("\t\tStatus: RQ=%d Iso%c ArqSz=%d Cal=%d SBA%c ITACoh%c GART64%c HTrans%c 64bit%c FW%c AGP3%c Rate=%s\n",
  90          ((t & PCI_AGP_STATUS_RQ_MASK) >> 24U) + 1,
  91          FLAG(t, PCI_AGP_STATUS_ISOCH),
  92          ((t & PCI_AGP_STATUS_ARQSZ_MASK) >> 13),
  93          ((t & PCI_AGP_STATUS_CAL_MASK) >> 10),
  94          FLAG(t, PCI_AGP_STATUS_SBA),
  95          FLAG(t, PCI_AGP_STATUS_ITA_COH),
  96          FLAG(t, PCI_AGP_STATUS_GART64),
  97          FLAG(t, PCI_AGP_STATUS_HTRANS),
  98          FLAG(t, PCI_AGP_STATUS_64BIT),
  99          FLAG(t, PCI_AGP_STATUS_FW),
 100          FLAG(t, PCI_AGP_STATUS_AGP3),
 101          rate);
 102   t = get_conf_long(d, where + PCI_AGP_COMMAND);
 103   format_agp_rate(t & 7, rate, agp3);
 104   printf("\t\tCommand: RQ=%d ArqSz=%d Cal=%d SBA%c AGP%c GART64%c 64bit%c FW%c Rate=%s\n",
 105          ((t & PCI_AGP_COMMAND_RQ_MASK) >> 24U) + 1,
 106          ((t & PCI_AGP_COMMAND_ARQSZ_MASK) >> 13),
 107          ((t & PCI_AGP_COMMAND_CAL_MASK) >> 10),
 108          FLAG(t, PCI_AGP_COMMAND_SBA),
 109          FLAG(t, PCI_AGP_COMMAND_AGP),
 110          FLAG(t, PCI_AGP_COMMAND_GART64),
 111          FLAG(t, PCI_AGP_COMMAND_64BIT),
 112          FLAG(t, PCI_AGP_COMMAND_FW),
 113          rate);
 114 }
 115
 116 static void
 117 cap_pcix_nobridge(struct device *d, int where)
 118 {
 119   u16 command;
 120   u32 status;
 121   static const byte max_outstanding[8] = { 1, 2, 3, 4, 8, 12, 16, 32 };
 122
 123   printf("PCI-X non-bridge device\n");
 124
 125   if (verbose < 2)
 126     return;
 127
 128   if (!config_fetch(d, where + PCI_PCIX_STATUS, 4))
 129     return;
 130
 131   command = get_conf_word(d, where + PCI_PCIX_COMMAND);
 132   status = get_conf_long(d, where + PCI_PCIX_STATUS);
 133   printf("\t\tCommand: DPERE%c ERO%c RBC=%d OST=%d\n",
 134          FLAG(command, PCI_PCIX_COMMAND_DPERE),
 135          FLAG(command, PCI_PCIX_COMMAND_ERO),
 136          1 << (9 + ((command & PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT) >> 2U)),
 137          max_outstanding[(command & PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS) >> 4U]);
 138   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c DC=%s DMMRBC=%u DMOST=%u DMCRS=%u RSCEM%c 266MHz%c 533MHz%c\n",
 139          (status & PCI_PCIX_STATUS_BUS) >> 8,
 140          (status & PCI_PCIX_STATUS_DEVICE) >> 3,
 141          (status & PCI_PCIX_STATUS_FUNCTION),
 142          FLAG(status, PCI_PCIX_STATUS_64BIT),
 143          FLAG(status, PCI_PCIX_STATUS_133MHZ),
 144          FLAG(status, PCI_PCIX_STATUS_SC_DISCARDED),
 145          FLAG(status, PCI_PCIX_STATUS_UNEXPECTED_SC),
 146          ((status & PCI_PCIX_STATUS_DEVICE_COMPLEXITY) ? "bridge" : "simple"),
 147          1 << (9 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT) >> 21)),
 148          max_outstanding[(status & PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS) >> 23],
 149          1 << (3 + ((status & PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE) >> 26)),
 150          FLAG(status, PCI_PCIX_STATUS_RCVD_SC_ERR_MESS),
 151          FLAG(status, PCI_PCIX_STATUS_266MHZ),
 152          FLAG(status, PCI_PCIX_STATUS_533MHZ));
 153 }
 154
 155 static void
 156 cap_pcix_bridge(struct device *d, int where)
 157 {
 158   static const char * const sec_clock_freq[8] = { "conv", "66MHz", "100MHz", "133MHz", "?4", "?5", "?6", "?7" };
 159   u16 secstatus;
 160   u32 status, upstcr, downstcr;
 161
 162   printf("PCI-X bridge device\n");
 163
 164   if (verbose < 2)
 165     return;
 166
 167   if (!config_fetch(d, where + PCI_PCIX_BRIDGE_STATUS, 12))
 168     return;
 169
 170   secstatus = get_conf_word(d, where + PCI_PCIX_BRIDGE_SEC_STATUS);
 171   printf("\t\tSecondary Status: 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c Freq=%s\n",
 172          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_64BIT),
 173          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ),
 174          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED),
 175          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC),
 176          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN),
 177          FLAG(secstatus, PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED),
 178          sec_clock_freq[(secstatus & PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ) >> 6]);
 179   status = get_conf_long(d, where + PCI_PCIX_BRIDGE_STATUS);
 180   printf("\t\tStatus: Dev=%02x:%02x.%d 64bit%c 133MHz%c SCD%c USC%c SCO%c SRD%c\n",
 181          (status & PCI_PCIX_BRIDGE_STATUS_BUS) >> 8,
 182          (status & PCI_PCIX_BRIDGE_STATUS_DEVICE) >> 3,
 183          (status & PCI_PCIX_BRIDGE_STATUS_FUNCTION),
 184          FLAG(status, PCI_PCIX_BRIDGE_STATUS_64BIT),
 185          FLAG(status, PCI_PCIX_BRIDGE_STATUS_133MHZ),
 186          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED),
 187          FLAG(status, PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC),
 188          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN),
 189          FLAG(status, PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED));
 190   upstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL);
 191   printf("\t\tUpstream: Capacity=%u CommitmentLimit=%u\n",
 192          (upstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 193          (upstcr >> 16) & 0xffff);
 194   downstcr = get_conf_long(d, where + PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL);
 195   printf("\t\tDownstream: Capacity=%u CommitmentLimit=%u\n",
 196          (downstcr & PCI_PCIX_BRIDGE_STR_CAPACITY),
 197          (downstcr >> 16) & 0xffff);
 198 }
 199
 200 static void
 201 cap_pcix(struct device *d, int where)
 202 {
 203   switch (get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f)
 204     {
 205     case PCI_HEADER_TYPE_NORMAL:
 206       cap_pcix_nobridge(d, where);
 207       break;
 208     case PCI_HEADER_TYPE_BRIDGE:
 209       cap_pcix_bridge(d, where);
 210       break;
 211     }
 212 }
 213
 214 static inline char *
 215 ht_link_width(unsigned width)
 216 {
 217   static char * const widths[8] = { "8bit", "16bit", "[2]", "32bit", "2bit", "4bit", "[6]", "N/C" };
 218   return widths[width];
 219 }
 220
 221 static inline char *
 222 ht_link_freq(unsigned freq)
 223 {
 224   static char * const freqs[16] = { "200MHz", "300MHz", "400MHz", "500MHz", "600MHz", "800MHz", "1.0GHz", "1.2GHz",
 225                                     "1.4GHz", "1.6GHz", "[a]", "[b]", "[c]", "[d]", "[e]", "Vend" };
 226   return freqs[freq];
 227 }
 228
 229 static void
 230 cap_ht_pri(struct device *d, int where, int cmd)
 231 {
 232   u16 lctr0, lcnf0, lctr1, lcnf1, eh;
 233   u8 rid, lfrer0, lfcap0, ftr, lfrer1, lfcap1, mbu, mlu, bn;
 234
 235   printf("HyperTransport: Slave or Primary Interface\n");
 236   if (verbose < 2)
 237     return;
 238
 239   if (!config_fetch(d, where + PCI_HT_PRI_LCTR0, PCI_HT_PRI_SIZEOF - PCI_HT_PRI_LCTR0))
 240     return;
 241   rid = get_conf_byte(d, where + PCI_HT_PRI_RID);
 242   if (rid < 0x22 && rid > 0x11)
 243     printf("\t\t!!! Possibly incomplete decoding\n");
 244
 245   printf("\t\tCommand: BaseUnitID=%u UnitCnt=%u MastHost%c DefDir%c",
 246          (cmd & PCI_HT_PRI_CMD_BUID),
 247          (cmd & PCI_HT_PRI_CMD_UC) >> 5,
 248          FLAG(cmd, PCI_HT_PRI_CMD_MH),
 249          FLAG(cmd, PCI_HT_PRI_CMD_DD));
 250   if (rid >= 0x22)
 251     printf(" DUL%c", FLAG(cmd, PCI_HT_PRI_CMD_DUL));
 252   printf("\n");
 253
 254   lctr0 = get_conf_word(d, where + PCI_HT_PRI_LCTR0);
 255   printf("\t\tLink Control 0: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 256          FLAG(lctr0, PCI_HT_LCTR_CFLE),
 257          FLAG(lctr0, PCI_HT_LCTR_CST),
 258          FLAG(lctr0, PCI_HT_LCTR_CFE),
 259          FLAG(lctr0, PCI_HT_LCTR_LKFAIL),
 260          FLAG(lctr0, PCI_HT_LCTR_INIT),
 261          FLAG(lctr0, PCI_HT_LCTR_EOC),
 262          FLAG(lctr0, PCI_HT_LCTR_TXO),
 263          (lctr0 & PCI_HT_LCTR_CRCERR) >> 8);
 264   if (rid >= 0x22)
 265     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 266            FLAG(lctr0, PCI_HT_LCTR_ISOCEN),
 267            FLAG(lctr0, PCI_HT_LCTR_LSEN),
 268            FLAG(lctr0, PCI_HT_LCTR_EXTCTL),
 269            FLAG(lctr0, PCI_HT_LCTR_64B));
 270   printf("\n");
 271
 272   lcnf0 = get_conf_word(d, where + PCI_HT_PRI_LCNF0);
 273   if (rid < 0x22)
 274     printf("\t\tLink Config 0: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 275            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 276            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 277            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 278            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12));
 279   else
 280     printf("\t\tLink Config 0: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 281            ht_link_width(lcnf0 & PCI_HT_LCNF_MLWI),
 282            FLAG(lcnf0, PCI_HT_LCNF_DFI),
 283            ht_link_width((lcnf0 & PCI_HT_LCNF_MLWO) >> 4),
 284            FLAG(lcnf0, PCI_HT_LCNF_DFO),
 285            ht_link_width((lcnf0 & PCI_HT_LCNF_LWI) >> 8),
 286            FLAG(lcnf0, PCI_HT_LCNF_DFIE),
 287            ht_link_width((lcnf0 & PCI_HT_LCNF_LWO) >> 12),
 288            FLAG(lcnf0, PCI_HT_LCNF_DFOE));
 289
 290   lctr1 = get_conf_word(d, where + PCI_HT_PRI_LCTR1);
 291   printf("\t\tLink Control 1: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x",
 292          FLAG(lctr1, PCI_HT_LCTR_CFLE),
 293          FLAG(lctr1, PCI_HT_LCTR_CST),
 294          FLAG(lctr1, PCI_HT_LCTR_CFE),
 295          FLAG(lctr1, PCI_HT_LCTR_LKFAIL),
 296          FLAG(lctr1, PCI_HT_LCTR_INIT),
 297          FLAG(lctr1, PCI_HT_LCTR_EOC),
 298          FLAG(lctr1, PCI_HT_LCTR_TXO),
 299          (lctr1 & PCI_HT_LCTR_CRCERR) >> 8);
 300   if (rid >= 0x22)
 301     printf(" IsocEn%c LSEn%c ExtCTL%c 64b%c",
 302          FLAG(lctr1, PCI_HT_LCTR_ISOCEN),
 303          FLAG(lctr1, PCI_HT_LCTR_LSEN),
 304          FLAG(lctr1, PCI_HT_LCTR_EXTCTL),
 305          FLAG(lctr1, PCI_HT_LCTR_64B));
 306   printf("\n");
 307
 308   lcnf1 = get_conf_word(d, where + PCI_HT_PRI_LCNF1);
 309   if (rid < 0x22)
 310     printf("\t\tLink Config 1: MLWI=%s MLWO=%s LWI=%s LWO=%s\n",
 311            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 312            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 313            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 314            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12));
 315   else
 316     printf("\t\tLink Config 1: MLWI=%s DwFcIn%c MLWO=%s DwFcOut%c LWI=%s DwFcInEn%c LWO=%s DwFcOutEn%c\n",
 317            ht_link_width(lcnf1 & PCI_HT_LCNF_MLWI),
 318            FLAG(lcnf1, PCI_HT_LCNF_DFI),
 319            ht_link_width((lcnf1 & PCI_HT_LCNF_MLWO) >> 4),
 320            FLAG(lcnf1, PCI_HT_LCNF_DFO),
 321            ht_link_width((lcnf1 & PCI_HT_LCNF_LWI) >> 8),
 322            FLAG(lcnf1, PCI_HT_LCNF_DFIE),
 323            ht_link_width((lcnf1 & PCI_HT_LCNF_LWO) >> 12),
 324            FLAG(lcnf1, PCI_HT_LCNF_DFOE));
 325
 326   printf("\t\tRevision ID: %u.%02u\n",
 327          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 328   if (rid < 0x22)
 329     return;
 330
 331   lfrer0 = get_conf_byte(d, where + PCI_HT_PRI_LFRER0);
 332   printf("\t\tLink Frequency 0: %s\n", ht_link_freq(lfrer0 & PCI_HT_LFRER_FREQ));
 333   printf("\t\tLink Error 0: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 334          FLAG(lfrer0, PCI_HT_LFRER_PROT),
 335          FLAG(lfrer0, PCI_HT_LFRER_OV),
 336          FLAG(lfrer0, PCI_HT_LFRER_EOC),
 337          FLAG(lfrer0, PCI_HT_LFRER_CTLT));
 338
 339   lfcap0 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP0);
 340   printf("\t\tLink Frequency Capability 0: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 341          FLAG(lfcap0, PCI_HT_LFCAP_200),
 342          FLAG(lfcap0, PCI_HT_LFCAP_300),
 343          FLAG(lfcap0, PCI_HT_LFCAP_400),
 344          FLAG(lfcap0, PCI_HT_LFCAP_500),
 345          FLAG(lfcap0, PCI_HT_LFCAP_600),
 346          FLAG(lfcap0, PCI_HT_LFCAP_800),
 347          FLAG(lfcap0, PCI_HT_LFCAP_1000),
 348          FLAG(lfcap0, PCI_HT_LFCAP_1200),
 349          FLAG(lfcap0, PCI_HT_LFCAP_1400),
 350          FLAG(lfcap0, PCI_HT_LFCAP_1600),
 351          FLAG(lfcap0, PCI_HT_LFCAP_VEND));
 352
 353   ftr = get_conf_byte(d, where + PCI_HT_PRI_FTR);
 354   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c\n",
 355          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 356          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 357          FLAG(ftr, PCI_HT_FTR_CRCTM),
 358          FLAG(ftr, PCI_HT_FTR_ECTLT),
 359          FLAG(ftr, PCI_HT_FTR_64BA),
 360          FLAG(ftr, PCI_HT_FTR_UIDRD));
 361
 362   lfrer1 = get_conf_byte(d, where + PCI_HT_PRI_LFRER1);
 363   printf("\t\tLink Frequency 1: %s\n", ht_link_freq(lfrer1 & PCI_HT_LFRER_FREQ));
 364   printf("\t\tLink Error 1: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 365          FLAG(lfrer1, PCI_HT_LFRER_PROT),
 366          FLAG(lfrer1, PCI_HT_LFRER_OV),
 367          FLAG(lfrer1, PCI_HT_LFRER_EOC),
 368          FLAG(lfrer1, PCI_HT_LFRER_CTLT));
 369
 370   lfcap1 = get_conf_byte(d, where + PCI_HT_PRI_LFCAP1);
 371   printf("\t\tLink Frequency Capability 1: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 372          FLAG(lfcap1, PCI_HT_LFCAP_200),
 373          FLAG(lfcap1, PCI_HT_LFCAP_300),
 374          FLAG(lfcap1, PCI_HT_LFCAP_400),
 375          FLAG(lfcap1, PCI_HT_LFCAP_500),
 376          FLAG(lfcap1, PCI_HT_LFCAP_600),
 377          FLAG(lfcap1, PCI_HT_LFCAP_800),
 378          FLAG(lfcap1, PCI_HT_LFCAP_1000),
 379          FLAG(lfcap1, PCI_HT_LFCAP_1200),
 380          FLAG(lfcap1, PCI_HT_LFCAP_1400),
 381          FLAG(lfcap1, PCI_HT_LFCAP_1600),
 382          FLAG(lfcap1, PCI_HT_LFCAP_VEND));
 383
 384   eh = get_conf_word(d, where + PCI_HT_PRI_EH);
 385   printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 386          FLAG(eh, PCI_HT_EH_PFLE),
 387          FLAG(eh, PCI_HT_EH_OFLE),
 388          FLAG(eh, PCI_HT_EH_PFE),
 389          FLAG(eh, PCI_HT_EH_OFE),
 390          FLAG(eh, PCI_HT_EH_EOCFE),
 391          FLAG(eh, PCI_HT_EH_RFE),
 392          FLAG(eh, PCI_HT_EH_CRCFE),
 393          FLAG(eh, PCI_HT_EH_SERRFE),
 394          FLAG(eh, PCI_HT_EH_CF),
 395          FLAG(eh, PCI_HT_EH_RE),
 396          FLAG(eh, PCI_HT_EH_PNFE),
 397          FLAG(eh, PCI_HT_EH_ONFE),
 398          FLAG(eh, PCI_HT_EH_EOCNFE),
 399          FLAG(eh, PCI_HT_EH_RNFE),
 400          FLAG(eh, PCI_HT_EH_CRCNFE),
 401          FLAG(eh, PCI_HT_EH_SERRNFE));
 402
 403   mbu = get_conf_byte(d, where + PCI_HT_PRI_MBU);
 404   mlu = get_conf_byte(d, where + PCI_HT_PRI_MLU);
 405   printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 406
 407   bn = get_conf_byte(d, where + PCI_HT_PRI_BN);
 408   printf("\t\tBus Number: %02x\n", bn);
 409 }
 410
 411 static void
 412 cap_ht_sec(struct device *d, int where, int cmd)
 413 {
 414   u16 lctr, lcnf, ftr, eh;
 415   u8 rid, lfrer, lfcap, mbu, mlu;
 416   char *fmt;
 417
 418   printf("HyperTransport: Host or Secondary Interface\n");
 419   if (verbose < 2)
 420     return;
 421
 422   if (!config_fetch(d, where + PCI_HT_SEC_LCTR, PCI_HT_SEC_SIZEOF - PCI_HT_SEC_LCTR))
 423     return;
 424   rid = get_conf_byte(d, where + PCI_HT_SEC_RID);
 425   if (rid < 0x22 && rid > 0x11)
 426     printf("\t\t!!! Possibly incomplete decoding\n");
 427
 428   if (rid >= 0x22)
 429     fmt = "\t\tCommand: WarmRst%c DblEnd%c DevNum=%u ChainSide%c HostHide%c Slave%c <EOCErr%c DUL%c\n";
 430   else
 431     fmt = "\t\tCommand: WarmRst%c DblEnd%c\n";
 432   printf(fmt,
 433          FLAG(cmd, PCI_HT_SEC_CMD_WR),
 434          FLAG(cmd, PCI_HT_SEC_CMD_DE),
 435          (cmd & PCI_HT_SEC_CMD_DN) >> 2,
 436          FLAG(cmd, PCI_HT_SEC_CMD_CS),
 437          FLAG(cmd, PCI_HT_SEC_CMD_HH),
 438          FLAG(cmd, PCI_HT_SEC_CMD_AS),
 439          FLAG(cmd, PCI_HT_SEC_CMD_HIECE),
 440          FLAG(cmd, PCI_HT_SEC_CMD_DUL));
 441   lctr = get_conf_word(d, where + PCI_HT_SEC_LCTR);
 442   if (rid >= 0x22)
 443     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x IsocEn%c LSEn%c ExtCTL%c 64b%c\n";
 444   else
 445     fmt = "\t\tLink Control: CFlE%c CST%c CFE%c <LkFail%c Init%c EOC%c TXO%c <CRCErr=%x\n";
 446   printf(fmt,
 447          FLAG(lctr, PCI_HT_LCTR_CFLE),
 448          FLAG(lctr, PCI_HT_LCTR_CST),
 449          FLAG(lctr, PCI_HT_LCTR_CFE),
 450          FLAG(lctr, PCI_HT_LCTR_LKFAIL),
 451          FLAG(lctr, PCI_HT_LCTR_INIT),
 452          FLAG(lctr, PCI_HT_LCTR_EOC),
 453          FLAG(lctr, PCI_HT_LCTR_TXO),
 454          (lctr & PCI_HT_LCTR_CRCERR) >> 8,
 455          FLAG(lctr, PCI_HT_LCTR_ISOCEN),
 456          FLAG(lctr, PCI_HT_LCTR_LSEN),
 457          FLAG(lctr, PCI_HT_LCTR_EXTCTL),
 458          FLAG(lctr, PCI_HT_LCTR_64B));
 459   lcnf = get_conf_word(d, where + PCI_HT_SEC_LCNF);
 460   if (rid >= 0x22)
 461     fmt = "\t\tLink Config: MLWI=%1$s DwFcIn%5$c MLWO=%2$s DwFcOut%6$c LWI=%3$s DwFcInEn%7$c LWO=%4$s DwFcOutEn%8$c\n";
 462   else
 463     fmt = "\t\tLink Config: MLWI=%s MLWO=%s LWI=%s LWO=%s\n";
 464   printf(fmt,
 465          ht_link_width(lcnf & PCI_HT_LCNF_MLWI),
 466          ht_link_width((lcnf & PCI_HT_LCNF_MLWO) >> 4),
 467          ht_link_width((lcnf & PCI_HT_LCNF_LWI) >> 8),
 468          ht_link_width((lcnf & PCI_HT_LCNF_LWO) >> 12),
 469          FLAG(lcnf, PCI_HT_LCNF_DFI),
 470          FLAG(lcnf, PCI_HT_LCNF_DFO),
 471          FLAG(lcnf, PCI_HT_LCNF_DFIE),
 472          FLAG(lcnf, PCI_HT_LCNF_DFOE));
 473   printf("\t\tRevision ID: %u.%02u\n",
 474          (rid & PCI_HT_RID_MAJ) >> 5, (rid & PCI_HT_RID_MIN));
 475   if (rid < 0x22)
 476     return;
 477   lfrer = get_conf_byte(d, where + PCI_HT_SEC_LFRER);
 478   printf("\t\tLink Frequency: %s\n", ht_link_freq(lfrer & PCI_HT_LFRER_FREQ));
 479   printf("\t\tLink Error: <Prot%c <Ovfl%c <EOC%c CTLTm%c\n",
 480          FLAG(lfrer, PCI_HT_LFRER_PROT),
 481          FLAG(lfrer, PCI_HT_LFRER_OV),
 482          FLAG(lfrer, PCI_HT_LFRER_EOC),
 483          FLAG(lfrer, PCI_HT_LFRER_CTLT));
 484   lfcap = get_conf_byte(d, where + PCI_HT_SEC_LFCAP);
 485   printf("\t\tLink Frequency Capability: 200MHz%c 300MHz%c 400MHz%c 500MHz%c 600MHz%c 800MHz%c 1.0GHz%c 1.2GHz%c 1.4GHz%c 1.6GHz%c Vend%c\n",
 486          FLAG(lfcap, PCI_HT_LFCAP_200),
 487          FLAG(lfcap, PCI_HT_LFCAP_300),
 488          FLAG(lfcap, PCI_HT_LFCAP_400),
 489          FLAG(lfcap, PCI_HT_LFCAP_500),
 490          FLAG(lfcap, PCI_HT_LFCAP_600),
 491          FLAG(lfcap, PCI_HT_LFCAP_800),
 492          FLAG(lfcap, PCI_HT_LFCAP_1000),
 493          FLAG(lfcap, PCI_HT_LFCAP_1200),
 494          FLAG(lfcap, PCI_HT_LFCAP_1400),
 495          FLAG(lfcap, PCI_HT_LFCAP_1600),
 496          FLAG(lfcap, PCI_HT_LFCAP_VEND));
 497   ftr = get_conf_word(d, where + PCI_HT_SEC_FTR);
 498   printf("\t\tFeature Capability: IsocFC%c LDTSTOP%c CRCTM%c ECTLT%c 64bA%c UIDRD%c ExtRS%c UCnfE%c\n",
 499          FLAG(ftr, PCI_HT_FTR_ISOCFC),
 500          FLAG(ftr, PCI_HT_FTR_LDTSTOP),
 501          FLAG(ftr, PCI_HT_FTR_CRCTM),
 502          FLAG(ftr, PCI_HT_FTR_ECTLT),
 503          FLAG(ftr, PCI_HT_FTR_64BA),
 504          FLAG(ftr, PCI_HT_FTR_UIDRD),
 505          FLAG(ftr, PCI_HT_SEC_FTR_EXTRS),
 506          FLAG(ftr, PCI_HT_SEC_FTR_UCNFE));
 507   if (ftr & PCI_HT_SEC_FTR_EXTRS)
 508     {
 509       eh = get_conf_word(d, where + PCI_HT_SEC_EH);
 510       printf("\t\tError Handling: PFlE%c OFlE%c PFE%c OFE%c EOCFE%c RFE%c CRCFE%c SERRFE%c CF%c RE%c PNFE%c ONFE%c EOCNFE%c RNFE%c CRCNFE%c SERRNFE%c\n",
 511              FLAG(eh, PCI_HT_EH_PFLE),
 512              FLAG(eh, PCI_HT_EH_OFLE),
 513              FLAG(eh, PCI_HT_EH_PFE),
 514              FLAG(eh, PCI_HT_EH_OFE),
 515              FLAG(eh, PCI_HT_EH_EOCFE),
 516              FLAG(eh, PCI_HT_EH_RFE),
 517              FLAG(eh, PCI_HT_EH_CRCFE),
 518              FLAG(eh, PCI_HT_EH_SERRFE),
 519              FLAG(eh, PCI_HT_EH_CF),
 520              FLAG(eh, PCI_HT_EH_RE),
 521              FLAG(eh, PCI_HT_EH_PNFE),
 522              FLAG(eh, PCI_HT_EH_ONFE),
 523              FLAG(eh, PCI_HT_EH_EOCNFE),
 524              FLAG(eh, PCI_HT_EH_RNFE),
 525              FLAG(eh, PCI_HT_EH_CRCNFE),
 526              FLAG(eh, PCI_HT_EH_SERRNFE));
 527       mbu = get_conf_byte(d, where + PCI_HT_SEC_MBU);
 528       mlu = get_conf_byte(d, where + PCI_HT_SEC_MLU);
 529       printf("\t\tPrefetchable memory behind bridge Upper: %02x-%02x\n", mbu, mlu);
 530     }
 531 }
 532
 533 static void
 534 cap_ht(struct device *d, int where, int cmd)
 535 {
 536   int type;
 537
 538   switch (cmd & PCI_HT_CMD_TYP_HI)
 539     {
 540     case PCI_HT_CMD_TYP_HI_PRI:
 541       cap_ht_pri(d, where, cmd);
 542       return;
 543     case PCI_HT_CMD_TYP_HI_SEC:
 544       cap_ht_sec(d, where, cmd);
 545       return;
 546     }
 547
 548   type = cmd & PCI_HT_CMD_TYP;
 549   switch (type)
 550     {
 551     case PCI_HT_CMD_TYP_SW:
 552       printf("HyperTransport: Switch\n");
 553       break;
 554     case PCI_HT_CMD_TYP_IDC:
 555       printf("HyperTransport: Interrupt Discovery and Configuration\n");
 556       break;
 557     case PCI_HT_CMD_TYP_RID:
 558       printf("HyperTransport: Revision ID: %u.%02u\n",
 559              (cmd & PCI_HT_RID_MAJ) >> 5, (cmd & PCI_HT_RID_MIN));
 560       break;
 561     case PCI_HT_CMD_TYP_UIDC:
 562       printf("HyperTransport: UnitID Clumping\n");
 563       break;
 564     case PCI_HT_CMD_TYP_ECSA:
 565       printf("HyperTransport: Extended Configuration Space Access\n");
 566       break;
 567     case PCI_HT_CMD_TYP_AM:
 568       printf("HyperTransport: Address Mapping\n");
 569       break;
 570     case PCI_HT_CMD_TYP_MSIM:
 571       printf("HyperTransport: MSI Mapping Enable%c Fixed%c\n",
 572              FLAG(cmd, PCI_HT_MSIM_CMD_EN),
 573              FLAG(cmd, PCI_HT_MSIM_CMD_FIXD));
 574       if (verbose >= 2 && !(cmd & PCI_HT_MSIM_CMD_FIXD))
 575         {
 576           u32 offl, offh;
 577           if (!config_fetch(d, where + PCI_HT_MSIM_ADDR_LO, 8))
 578             break;
 579           offl = get_conf_long(d, where + PCI_HT_MSIM_ADDR_LO);
 580           offh = get_conf_long(d, where + PCI_HT_MSIM_ADDR_HI);
 581           printf("\t\tMapping Address Base: %016llx\n", ((unsigned long long)offh << 32) | (offl & ~0xfffff));
 582         }
 583       break;
 584     case PCI_HT_CMD_TYP_DR:
 585       printf("HyperTransport: DirectRoute\n");
 586       break;
 587     case PCI_HT_CMD_TYP_VCS:
 588       printf("HyperTransport: VCSet\n");
 589       break;
 590     case PCI_HT_CMD_TYP_RM:
 591       printf("HyperTransport: Retry Mode\n");
 592       break;
 593     case PCI_HT_CMD_TYP_X86:
 594       printf("HyperTransport: X86 (reserved)\n");
 595       break;
 596     default:
 597       printf("HyperTransport: #%02x\n", type >> 11);
 598     }
 599 }
 600
 601 static void
 602 cap_msi(struct device *d, int where, int cap)
 603 {
 604   int is64;
 605   u32 t;
 606   u16 w;
 607
 608   printf("MSI: Enable%c Count=%d/%d Maskable%c 64bit%c\n",
 609          FLAG(cap, PCI_MSI_FLAGS_ENABLE),
 610          1 << ((cap & PCI_MSI_FLAGS_QSIZE) >> 4),
 611          1 << ((cap & PCI_MSI_FLAGS_QMASK) >> 1),
 612          FLAG(cap, PCI_MSI_FLAGS_MASK_BIT),
 613          FLAG(cap, PCI_MSI_FLAGS_64BIT));
 614   if (verbose < 2)
 615     return;
 616   is64 = cap & PCI_MSI_FLAGS_64BIT;
 617   if (!config_fetch(d, where + PCI_MSI_ADDRESS_LO, (is64 ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32) + 2 - PCI_MSI_ADDRESS_LO))
 618     return;
 619   printf("\t\tAddress: ");
 620   if (is64)
 621     {
 622       t = get_conf_long(d, where + PCI_MSI_ADDRESS_HI);
 623       w = get_conf_word(d, where + PCI_MSI_DATA_64);
 624       printf("%08x", t);
 625     }
 626   else
 627     w = get_conf_word(d, where + PCI_MSI_DATA_32);
 628   t = get_conf_long(d, where + PCI_MSI_ADDRESS_LO);
 629   printf("%08x  Data: %04x\n", t, w);
 630   if (cap & PCI_MSI_FLAGS_MASK_BIT)
 631     {
 632       u32 mask, pending;
 633
 634       if (is64)
 635         {
 636           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_64, 8))
 637             return;
 638           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_64);
 639           pending = get_conf_long(d, where + PCI_MSI_PENDING_64);
 640         }
 641       else
 642         {
 643           if (!config_fetch(d, where + PCI_MSI_MASK_BIT_32, 8))
 644             return;
 645           mask = get_conf_long(d, where + PCI_MSI_MASK_BIT_32);
 646           pending = get_conf_long(d, where + PCI_MSI_PENDING_32);
 647         }
 648       printf("\t\tMasking: %08x  Pending: %08x\n", mask, pending);
 649     }
 650 }
 651
 652 static float power_limit(int value, int scale)
 653 {
 654   static const float scales[4] = { 1.0, 0.1, 0.01, 0.001 };
 655   return value * scales[scale];
 656 }
 657
 658 static const char *latency_l0s(int value)
 659 {
 660   static const char *latencies[] = { "<64ns", "<128ns", "<256ns", "<512ns", "<1us", "<2us", "<4us", "unlimited" };
 661   return latencies[value];
 662 }
 663
 664 static const char *latency_l1(int value)
 665 {
 666   static const char *latencies[] = { "<1us", "<2us", "<4us", "<8us", "<16us", "<32us", "<64us", "unlimited" };
 667   return latencies[value];
 668 }
 669
 670 static void cap_express_dev(struct device *d, int where, int type)
 671 {
 672   u32 t;
 673   u16 w;
 674
 675   t = get_conf_long(d, where + PCI_EXP_DEVCAP);
 676   printf("\t\tDevCap:\tMaxPayload %d bytes, PhantFunc %d",
 677         128 << (t & PCI_EXP_DEVCAP_PAYLOAD),
 678         (1 << ((t & PCI_EXP_DEVCAP_PHANTOM) >> 3)) - 1);
 679   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END))
 680     printf(", Latency L0s %s, L1 %s",
 681         latency_l0s((t & PCI_EXP_DEVCAP_L0S) >> 6),
 682         latency_l1((t & PCI_EXP_DEVCAP_L1) >> 9));
 683   printf("\n");
 684   printf("\t\t\tExtTag%c", FLAG(t, PCI_EXP_DEVCAP_EXT_TAG));
 685   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) ||
 686       (type == PCI_EXP_TYPE_UPSTREAM) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 687     printf(" AttnBtn%c AttnInd%c PwrInd%c",
 688         FLAG(t, PCI_EXP_DEVCAP_ATN_BUT),
 689         FLAG(t, PCI_EXP_DEVCAP_ATN_IND), FLAG(t, PCI_EXP_DEVCAP_PWR_IND));
 690   printf(" RBE%c",
 691         FLAG(t, PCI_EXP_DEVCAP_RBE));
 692   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP))
 693     printf(" FLReset%c",
 694         FLAG(t, PCI_EXP_DEVCAP_FLRESET));
 695   if ((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_UPSTREAM) ||
 696       (type == PCI_EXP_TYPE_PCI_BRIDGE))
 697     printf(" SlotPowerLimit %.3fW",
 698         power_limit((t & PCI_EXP_DEVCAP_PWR_VAL) >> 18,
 699                     (t & PCI_EXP_DEVCAP_PWR_SCL) >> 26));
 700   printf("\n");
 701
 702   w = get_conf_word(d, where + PCI_EXP_DEVCTL);
 703   printf("\t\tDevCtl:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c\n",
 704         FLAG(w, PCI_EXP_DEVCTL_CERE),
 705         FLAG(w, PCI_EXP_DEVCTL_NFERE),
 706         FLAG(w, PCI_EXP_DEVCTL_FERE),
 707         FLAG(w, PCI_EXP_DEVCTL_URRE));
 708   printf("\t\t\tRlxdOrd%c ExtTag%c PhantFunc%c AuxPwr%c NoSnoop%c",
 709         FLAG(w, PCI_EXP_DEVCTL_RELAXED),
 710         FLAG(w, PCI_EXP_DEVCTL_EXT_TAG),
 711         FLAG(w, PCI_EXP_DEVCTL_PHANTOM),
 712         FLAG(w, PCI_EXP_DEVCTL_AUX_PME),
 713         FLAG(w, PCI_EXP_DEVCTL_NOSNOOP));
 714   if (type == PCI_EXP_TYPE_PCI_BRIDGE)
 715     printf(" BrConfRtry%c", FLAG(w, PCI_EXP_DEVCTL_BCRE));
 716   if (((type == PCI_EXP_TYPE_ENDPOINT) || (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_ROOT_INT_EP)) &&
 717       (t & PCI_EXP_DEVCAP_FLRESET))
 718     printf(" FLReset%c", FLAG(w, PCI_EXP_DEVCTL_FLRESET));
 719   printf("\n\t\t\tMaxPayload %d bytes, MaxReadReq %d bytes\n",
 720         128 << ((w & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
 721         128 << ((w & PCI_EXP_DEVCTL_READRQ) >> 12));
 722
 723   w = get_conf_word(d, where + PCI_EXP_DEVSTA);
 724   printf("\t\tDevSta:\tCorrErr%c NonFatalErr%c FatalErr%c UnsupReq%c AuxPwr%c TransPend%c\n",
 725         FLAG(w, PCI_EXP_DEVSTA_CED),
 726         FLAG(w, PCI_EXP_DEVSTA_NFED),
 727         FLAG(w, PCI_EXP_DEVSTA_FED),
 728         FLAG(w, PCI_EXP_DEVSTA_URD),
 729         FLAG(w, PCI_EXP_DEVSTA_AUXPD),
 730         FLAG(w, PCI_EXP_DEVSTA_TRPND));
 731 }
 732
 733 static char *link_speed(int speed)
 734 {
 735   switch (speed)
 736     {
 737       case 1:
 738         return "2.5GT/s";
 739       case 2:
 740         return "5GT/s";
 741       case 3:
 742         return "8GT/s";
 743       case 4:
 744         return "16GT/s";
 745       case 5:
 746         return "32GT/s";
 747       default:
 748         return "unknown";
 749     }
 750 }
 751
 752 static char *link_compare(int sta, int cap)
 753 {
 754   if (sta < cap)
 755     return "downgraded";
 756   if (sta > cap)
 757     return "strange";
 758   return "ok";
 759 }
 760
 761 static char *aspm_support(int code)
 762 {
 763   switch (code)
 764     {
 765       case 0:
 766         return "not supported";
 767       case 1:
 768         return "L0s";
 769       case 2:
 770         return "L1";
 771       case 3:
 772         return "L0s L1";
 773       default:
 774         return "unknown";
 775     }
 776 }
 777
 778 static const char *aspm_enabled(int code)
 779 {
 780   static const char *desc[] = { "Disabled", "L0s Enabled", "L1 Enabled", "L0s L1 Enabled" };
 781   return desc[code];
 782 }
 783
 784 static void cap_express_link(struct device *d, int where, int type)
 785 {
 786   u32 t, aspm, cap_speed, cap_width, sta_speed, sta_width;
 787   u16 w;
 788
 789   t = get_conf_long(d, where + PCI_EXP_LNKCAP);
 790   aspm = (t & PCI_EXP_LNKCAP_ASPM) >> 10;
 791   cap_speed = t & PCI_EXP_LNKCAP_SPEED;
 792   cap_width = (t & PCI_EXP_LNKCAP_WIDTH) >> 4;
 793   printf("\t\tLnkCap:\tPort #%d, Speed %s, Width x%d, ASPM %s",
 794         t >> 24,
 795         link_speed(cap_speed), cap_width,
 796         aspm_support(aspm));
 797   if (aspm)
 798     {
 799       printf(", Exit Latency ");
 800       if (aspm & 1)
 801         printf("L0s %s", latency_l0s((t & PCI_EXP_LNKCAP_L0S) >> 12));
 802       if (aspm & 2)
 803         printf("%sL1 %s", (aspm & 1) ? ", " : "",
 804             latency_l1((t & PCI_EXP_LNKCAP_L1) >> 15));
 805     }
 806   printf("\n");
 807   printf("\t\t\tClockPM%c Surprise%c LLActRep%c BwNot%c ASPMOptComp%c\n",
 808         FLAG(t, PCI_EXP_LNKCAP_CLOCKPM),
 809         FLAG(t, PCI_EXP_LNKCAP_SURPRISE),
 810         FLAG(t, PCI_EXP_LNKCAP_DLLA),
 811         FLAG(t, PCI_EXP_LNKCAP_LBNC),
 812         FLAG(t, PCI_EXP_LNKCAP_AOC));
 813
 814   w = get_conf_word(d, where + PCI_EXP_LNKCTL);
 815   printf("\t\tLnkCtl:\tASPM %s;", aspm_enabled(w & PCI_EXP_LNKCTL_ASPM));
 816   if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
 817       (type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
 818     printf(" RCB %d bytes", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
 819   printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
 820         FLAG(w, PCI_EXP_LNKCTL_DISABLE),
 821         FLAG(w, PCI_EXP_LNKCTL_CLOCK),
 822         FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
 823         FLAG(w, PCI_EXP_LNKCTL_CLOCKPM),
 824         FLAG(w, PCI_EXP_LNKCTL_HWAUTWD),
 825         FLAG(w, PCI_EXP_LNKCTL_BWMIE),
 826         FLAG(w, PCI_EXP_LNKCTL_AUTBWIE));
 827
 828   w = get_conf_word(d, where + PCI_EXP_LNKSTA);
 829   sta_speed = w & PCI_EXP_LNKSTA_SPEED;
 830   sta_width = (w & PCI_EXP_LNKSTA_WIDTH) >> 4;
 831   printf("\t\tLnkSta:\tSpeed %s (%s), Width x%d (%s)\n",
 832         link_speed(sta_speed),
 833         link_compare(sta_speed, cap_speed),
 834         sta_width,
 835         link_compare(sta_width, cap_width));
 836   printf("\t\t\tTrErr%c Train%c SlotClk%c DLActive%c BWMgmt%c ABWMgmt%c\n",
 837         FLAG(w, PCI_EXP_LNKSTA_TR_ERR),
 838         FLAG(w, PCI_EXP_LNKSTA_TRAIN),
 839         FLAG(w, PCI_EXP_LNKSTA_SL_CLK),
 840         FLAG(w, PCI_EXP_LNKSTA_DL_ACT),
 841         FLAG(w, PCI_EXP_LNKSTA_BWMGMT),
 842         FLAG(w, PCI_EXP_LNKSTA_AUTBW));
 843 }
 844
 845 static const char *indicator(int code)
 846 {
 847   static const char *names[] = { "Unknown", "On", "Blink", "Off" };
 848   return names[code];
 849 }
 850
 851 static void cap_express_slot(struct device *d, int where)
 852 {
 853   u32 t;
 854   u16 w;
 855
 856   t = get_conf_long(d, where + PCI_EXP_SLTCAP);
 857   printf("\t\tSltCap:\tAttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c\n",
 858         FLAG(t, PCI_EXP_SLTCAP_ATNB),
 859         FLAG(t, PCI_EXP_SLTCAP_PWRC),
 860         FLAG(t, PCI_EXP_SLTCAP_MRL),
 861         FLAG(t, PCI_EXP_SLTCAP_ATNI),
 862         FLAG(t, PCI_EXP_SLTCAP_PWRI),
 863         FLAG(t, PCI_EXP_SLTCAP_HPC),
 864         FLAG(t, PCI_EXP_SLTCAP_HPS));
 865   printf("\t\t\tSlot #%d, PowerLimit %.3fW; Interlock%c NoCompl%c\n",
 866         (t & PCI_EXP_SLTCAP_PSN) >> 19,
 867         power_limit((t & PCI_EXP_SLTCAP_PWR_VAL) >> 7, (t & PCI_EXP_SLTCAP_PWR_SCL) >> 15),
 868         FLAG(t, PCI_EXP_SLTCAP_INTERLOCK),
 869         FLAG(t, PCI_EXP_SLTCAP_NOCMDCOMP));
 870
 871   w = get_conf_word(d, where + PCI_EXP_SLTCTL);
 872   printf("\t\tSltCtl:\tEnable: AttnBtn%c PwrFlt%c MRL%c PresDet%c CmdCplt%c HPIrq%c LinkChg%c\n",
 873         FLAG(w, PCI_EXP_SLTCTL_ATNB),
 874         FLAG(w, PCI_EXP_SLTCTL_PWRF),
 875         FLAG(w, PCI_EXP_SLTCTL_MRLS),
 876         FLAG(w, PCI_EXP_SLTCTL_PRSD),
 877         FLAG(w, PCI_EXP_SLTCTL_CMDC),
 878         FLAG(w, PCI_EXP_SLTCTL_HPIE),
 879         FLAG(w, PCI_EXP_SLTCTL_LLCHG));
 880   printf("\t\t\tControl: AttnInd %s, PwrInd %s, Power%c Interlock%c\n",
 881         indicator((w & PCI_EXP_SLTCTL_ATNI) >> 6),
 882         indicator((w & PCI_EXP_SLTCTL_PWRI) >> 8),
 883         FLAG(w, PCI_EXP_SLTCTL_PWRC),
 884         FLAG(w, PCI_EXP_SLTCTL_INTERLOCK));
 885
 886   w = get_conf_word(d, where + PCI_EXP_SLTSTA);
 887   printf("\t\tSltSta:\tStatus: AttnBtn%c PowerFlt%c MRL%c CmdCplt%c PresDet%c Interlock%c\n",
 888         FLAG(w, PCI_EXP_SLTSTA_ATNB),
 889         FLAG(w, PCI_EXP_SLTSTA_PWRF),
 890         FLAG(w, PCI_EXP_SLTSTA_MRL_ST),
 891         FLAG(w, PCI_EXP_SLTSTA_CMDC),
 892         FLAG(w, PCI_EXP_SLTSTA_PRES),
 893         FLAG(w, PCI_EXP_SLTSTA_INTERLOCK));
 894   printf("\t\t\tChanged: MRL%c PresDet%c LinkState%c\n",
 895         FLAG(w, PCI_EXP_SLTSTA_MRLS),
 896         FLAG(w, PCI_EXP_SLTSTA_PRSD),
 897         FLAG(w, PCI_EXP_SLTSTA_LLCHG));
 898 }
 899
 900 static void cap_express_root(struct device *d, int where)
 901 {
 902   u32 w = get_conf_word(d, where + PCI_EXP_RTCTL);
 903   printf("\t\tRootCtl: ErrCorrectable%c ErrNon-Fatal%c ErrFatal%c PMEIntEna%c CRSVisible%c\n",
 904         FLAG(w, PCI_EXP_RTCTL_SECEE),
 905         FLAG(w, PCI_EXP_RTCTL_SENFEE),
 906         FLAG(w, PCI_EXP_RTCTL_SEFEE),
 907         FLAG(w, PCI_EXP_RTCTL_PMEIE),
 908         FLAG(w, PCI_EXP_RTCTL_CRSVIS));
 909
 910   w = get_conf_word(d, where + PCI_EXP_RTCAP);
 911   printf("\t\tRootCap: CRSVisible%c\n",
 912         FLAG(w, PCI_EXP_RTCAP_CRSVIS));
 913
 914   w = get_conf_long(d, where + PCI_EXP_RTSTA);
 915   printf("\t\tRootSta: PME ReqID %04x, PMEStatus%c PMEPending%c\n",
 916         w & PCI_EXP_RTSTA_PME_REQID,
 917         FLAG(w, PCI_EXP_RTSTA_PME_STATUS),
 918         FLAG(w, PCI_EXP_RTSTA_PME_PENDING));
 919 }
 920
 921 static const char *cap_express_dev2_timeout_range(int type)
 922 {
 923   /* Decode Completion Timeout Ranges. */
 924   switch (type)
 925     {
 926       case 0:
 927         return "Not Supported";
 928       case 1:
 929         return "Range A";
 930       case 2:
 931         return "Range B";
 932       case 3:
 933         return "Range AB";
 934       case 6:
 935         return "Range BC";
 936       case 7:
 937         return "Range ABC";
 938       case 14:
 939         return "Range BCD";
 940       case 15:
 941         return "Range ABCD";
 942       default:
 943         return "Unknown";
 944     }
 945 }
 946
 947 static const char *cap_express_dev2_timeout_value(int type)
 948 {
 949   /* Decode Completion Timeout Value. */
 950   switch (type)
 951     {
 952       case 0:
 953         return "50us to 50ms";
 954       case 1:
 955         return "50us to 100us";
 956       case 2:
 957         return "1ms to 10ms";
 958       case 5:
 959         return "16ms to 55ms";
 960       case 6:
 961         return "65ms to 210ms";
 962       case 9:
 963         return "260ms to 900ms";
 964       case 10:
 965         return "1s to 3.5s";
 966       case 13:
 967         return "4s to 13s";
 968       case 14:
 969         return "17s to 64s";
 970       default:
 971         return "Unknown";
 972     }
 973 }
 974
 975 static const char *cap_express_devcap2_obff(int obff)
 976 {
 977   switch (obff)
 978     {
 979       case 1:
 980         return "Via message";
 981       case 2:
 982         return "Via WAKE#";
 983       case 3:
 984         return "Via message/WAKE#";
 985       default:
 986         return "Not Supported";
 987     }
 988 }
 989
 990 static const char *cap_express_devcap2_epr(int epr)
 991 {
 992   switch (epr)
 993     {
 994       case 1:
 995         return "Dev Specific";
 996       case 2:
 997         return "Form Factor Dev Specific";
 998       case 3:
 999         return "Reserved";
1000       default:
1001         return "Not Supported";
1002     }
1003 }
1004
1005 static const char *cap_express_devcap2_lncls(int lncls)
1006 {
1007   switch (lncls)
1008     {
1009       case 1:
1010         return "64byte cachelines";
1011       case 2:
1012         return "128byte cachelines";
1013       case 3:
1014         return "Reserved";
1015       default:
1016         return "Not Supported";
1017     }
1018 }
1019
1020 static const char *cap_express_devcap2_tphcomp(int tph)
1021 {
1022   switch (tph)
1023     {
1024       case 1:
1025         return "TPHComp+, ExtTPHComp-";
1026       case 2:
1027         /* Reserved; intentionally left blank */
1028         return "";
1029       case 3:
1030         return "TPHComp+, ExtTPHComp+";
1031       default:
1032         return "TPHComp-, ExtTPHComp-";
1033     }
1034 }
1035
1036 static const char *cap_express_devctl2_obff(int obff)
1037 {
1038   switch (obff)
1039     {
1040       case 0:
1041         return "Disabled";
1042       case 1:
1043         return "Via message A";
1044       case 2:
1045         return "Via message B";
1046       case 3:
1047         return "Via WAKE#";
1048       default:
1049         return "Unknown";
1050     }
1051 }
1052
1053 static int
1054 device_has_memory_space_bar(struct device *d)
1055 {
1056   struct pci_dev *p = d->dev;
1057   int i, found = 0;
1058
1059   for (i=0; i<6; i++)
1060     if (p->base_addr[i] && p->size[i])
1061       {
1062         if (!(p->base_addr[i] & PCI_BASE_ADDRESS_SPACE_IO))
1063           {
1064             found = 1;
1065             break;
1066           }
1067       }
1068   return found;
1069 }
1070
1071 static void cap_express_dev2(struct device *d, int where, int type)
1072 {
1073   u32 l;
1074   u16 w;
1075   int has_mem_bar = device_has_memory_space_bar(d);
1076
1077   l = get_conf_long(d, where + PCI_EXP_DEVCAP2);
1078   printf("\t\tDevCap2: Completion Timeout: %s, TimeoutDis%c, NROPrPrP%c, LTR%c",
1079         cap_express_dev2_timeout_range(PCI_EXP_DEV2_TIMEOUT_RANGE(l)),
1080         FLAG(l, PCI_EXP_DEV2_TIMEOUT_DIS),
1081         FLAG(l, PCI_EXP_DEVCAP2_NROPRPRP),
1082         FLAG(l, PCI_EXP_DEVCAP2_LTR));
1083   printf("\n\t\t\t 10BitTagComp%c, 10BitTagReq%c, OBFF %s, ExtFmt%c, EETLPPrefix%c",
1084         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_COMP),
1085         FLAG(l, PCI_EXP_DEVCAP2_10BIT_TAG_REQ),
1086         cap_express_devcap2_obff(PCI_EXP_DEVCAP2_OBFF(l)),
1087         FLAG(l, PCI_EXP_DEVCAP2_EXTFMT),
1088         FLAG(l, PCI_EXP_DEVCAP2_EE_TLP));
1089
1090   if (PCI_EXP_DEVCAP2_EE_TLP == (l & PCI_EXP_DEVCAP2_EE_TLP))
1091     {
1092       printf(", MaxEETLPPrefixes %d",
1093              PCI_EXP_DEVCAP2_MEE_TLP(l) ? PCI_EXP_DEVCAP2_MEE_TLP(l) : 4);
1094     }
1095
1096   printf("\n\t\t\t EmergencyPowerReduction %s, EmergencyPowerReductionInit%c",
1097         cap_express_devcap2_epr(PCI_EXP_DEVCAP2_EPR(l)),
1098         FLAG(l, PCI_EXP_DEVCAP2_EPR_INIT));
1099   printf("\n\t\t\t FRS%c", FLAG(l, PCI_EXP_DEVCAP2_FRS));
1100
1101   if (type == PCI_EXP_TYPE_ROOT_PORT)
1102     printf(", LN System CLS %s",
1103           cap_express_devcap2_lncls(PCI_EXP_DEVCAP2_LN_CLS(l)));
1104
1105   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT)
1106     printf(", %s", cap_express_devcap2_tphcomp(PCI_EXP_DEVCAP2_TPH_COMP(l)));
1107
1108   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1109     printf(", ARIFwd%c\n", FLAG(l, PCI_EXP_DEV2_ARI));
1110   else
1111     printf("\n");
1112   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1113       type == PCI_EXP_TYPE_DOWNSTREAM || has_mem_bar)
1114     {
1115        printf("\t\t\t AtomicOpsCap:");
1116        if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1117            type == PCI_EXP_TYPE_DOWNSTREAM)
1118          printf(" Routing%c", FLAG(l, PCI_EXP_DEVCAP2_ATOMICOP_ROUTING));
1119        if (type == PCI_EXP_TYPE_ROOT_PORT || has_mem_bar)
1120          printf(" 32bit%c 64bit%c 128bitCAS%c",
1121                 FLAG(l, PCI_EXP_DEVCAP2_32BIT_ATOMICOP_COMP),
1122                 FLAG(l, PCI_EXP_DEVCAP2_64BIT_ATOMICOP_COMP),
1123                 FLAG(l, PCI_EXP_DEVCAP2_128BIT_CAS_COMP));
1124        printf("\n");
1125     }
1126
1127   w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
1128   printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c, LTR%c, OBFF %s",
1129         cap_express_dev2_timeout_value(PCI_EXP_DEV2_TIMEOUT_VALUE(w)),
1130         FLAG(w, PCI_EXP_DEV2_TIMEOUT_DIS),
1131         FLAG(w, PCI_EXP_DEV2_LTR),
1132         cap_express_devctl2_obff(PCI_EXP_DEV2_OBFF(w)));
1133   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
1134     printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEV2_ARI));
1135   else
1136     printf("\n");
1137   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1138       type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ENDPOINT ||
1139       type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1140     {
1141       printf("\t\t\t AtomicOpsCtl:");
1142       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ENDPOINT ||
1143           type == PCI_EXP_TYPE_ROOT_INT_EP || type == PCI_EXP_TYPE_LEG_END)
1144         printf(" ReqEn%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_REQUESTER_EN));
1145       if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_UPSTREAM ||
1146           type == PCI_EXP_TYPE_DOWNSTREAM)
1147         printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEV2_ATOMICOP_EGRESS_BLOCK));
1148       printf("\n");
1149     }
1150 }
1151
1152 static const char *cap_express_link2_speed(int type)
1153 {
1154   switch (type)
1155     {
1156       case 0: /* hardwire to 0 means only the 2.5GT/s is supported */
1157       case 1:
1158         return "2.5GT/s";
1159       case 2:
1160         return "5GT/s";
1161       case 3:
1162         return "8GT/s";
1163       case 4:
1164         return "16GT/s";
1165       case 5:
1166         return "32GT/s";
1167       default:
1168         return "Unknown";
1169     }
1170 }
1171
1172 static const char *cap_express_link2_deemphasis(int type)
1173 {
1174   switch (type)
1175     {
1176       case 0:
1177         return "-6dB";
1178       case 1:
1179         return "-3.5dB";
1180       default:
1181         return "Unknown";
1182     }
1183 }
1184
1185 static const char *cap_express_link2_transmargin(int type)
1186 {
1187   switch (type)
1188     {
1189       case 0:
1190         return "Normal Operating Range";
1191       case 1:
1192         return "800-1200mV(full-swing)/400-700mV(half-swing)";
1193       case 2:
1194       case 3:
1195       case 4:
1196       case 5:
1197         return "200-400mV(full-swing)/100-200mV(half-swing)";
1198       default:
1199         return "Unknown";
1200     }
1201 }
1202
1203 static void cap_express_link2(struct device *d, int where, int type)
1204 {
1205   u16 w;
1206
1207   if (!((type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_LEG_END) &&
1208         (d->dev->dev != 0 || d->dev->func != 0))) {
1209     w = get_conf_word(d, where + PCI_EXP_LNKCTL2);
1210     printf("\t\tLnkCtl2: Target Link Speed: %s, EnterCompliance%c SpeedDis%c",
1211         cap_express_link2_speed(PCI_EXP_LNKCTL2_SPEED(w)),
1212         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC),
1213         FLAG(w, PCI_EXP_LNKCTL2_SPEED_DIS));
1214     if (type == PCI_EXP_TYPE_DOWNSTREAM)
1215       printf(", Selectable De-emphasis: %s",
1216         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_DEEMPHASIS(w)));
1217     printf("\n"
1218         "\t\t\t Transmit Margin: %s, EnterModifiedCompliance%c ComplianceSOS%c\n"
1219         "\t\t\t Compliance De-emphasis: %s\n",
1220         cap_express_link2_transmargin(PCI_EXP_LNKCTL2_MARGIN(w)),
1221         FLAG(w, PCI_EXP_LNKCTL2_MOD_CMPLNC),
1222         FLAG(w, PCI_EXP_LNKCTL2_CMPLNC_SOS),
1223         cap_express_link2_deemphasis(PCI_EXP_LNKCTL2_COM_DEEMPHASIS(w)));
1224   }
1225
1226   w = get_conf_word(d, where + PCI_EXP_LNKSTA2);
1227   printf("\t\tLnkSta2: Current De-emphasis Level: %s, EqualizationComplete%c, EqualizationPhase1%c\n"
1228         "\t\t\t EqualizationPhase2%c, EqualizationPhase3%c, LinkEqualizationRequest%c\n",
1229         cap_express_link2_deemphasis(PCI_EXP_LINKSTA2_DEEMPHASIS(w)),
1230         FLAG(w, PCI_EXP_LINKSTA2_EQU_COMP),
1231         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE1),
1232         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE2),
1233         FLAG(w, PCI_EXP_LINKSTA2_EQU_PHASE3),
1234         FLAG(w, PCI_EXP_LINKSTA2_EQU_REQ));
1235 }
1236
1237 static void cap_express_slot2(struct device *d UNUSED, int where UNUSED)
1238 {
1239   /* No capabilities that require this field in PCIe rev2.0 spec. */
1240 }
1241
1242 static int
1243 cap_express(struct device *d, int where, int cap)
1244 {
1245   int type = (cap & PCI_EXP_FLAGS_TYPE) >> 4;
1246   int size;
1247   int slot = 0;
1248   int link = 1;
1249
1250   printf("Express ");
1251   if (verbose >= 2)
1252     printf("(v%d) ", cap & PCI_EXP_FLAGS_VERS);
1253   switch (type)
1254     {
1255     case PCI_EXP_TYPE_ENDPOINT:
1256       printf("Endpoint");
1257       break;
1258     case PCI_EXP_TYPE_LEG_END:
1259       printf("Legacy Endpoint");
1260       break;
1261     case PCI_EXP_TYPE_ROOT_PORT:
1262       slot = cap & PCI_EXP_FLAGS_SLOT;
1263       printf("Root Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1264       break;
1265     case PCI_EXP_TYPE_UPSTREAM:
1266       printf("Upstream Port");
1267       break;
1268     case PCI_EXP_TYPE_DOWNSTREAM:
1269       slot = cap & PCI_EXP_FLAGS_SLOT;
1270       printf("Downstream Port (Slot%c)", FLAG(cap, PCI_EXP_FLAGS_SLOT));
1271       break;
1272     case PCI_EXP_TYPE_PCI_BRIDGE:
1273       printf("PCI-Express to PCI/PCI-X Bridge");
1274       break;
1275     case PCI_EXP_TYPE_PCIE_BRIDGE:
1276       slot = cap & PCI_EXP_FLAGS_SLOT;
1277       printf("PCI/PCI-X to PCI-Express Bridge (Slot%c)",
1278              FLAG(cap, PCI_EXP_FLAGS_SLOT));
1279       break;
1280     case PCI_EXP_TYPE_ROOT_INT_EP:
1281       link = 0;
1282       printf("Root Complex Integrated Endpoint");
1283       break;
1284     case PCI_EXP_TYPE_ROOT_EC:
1285       link = 0;
1286       printf("Root Complex Event Collector");
1287       break;
1288     default:
1289       printf("Unknown type %d", type);
1290   }
1291   printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
1292   if (verbose < 2)
1293     return type;
1294
1295   size = 16;
1296   if (slot)
1297     size = 24;
1298   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1299     size = 32;
1300   if (!config_fetch(d, where + PCI_EXP_DEVCAP, size))
1301     return type;
1302
1303   cap_express_dev(d, where, type);
1304   if (link)
1305     cap_express_link(d, where, type);
1306   if (slot)
1307     cap_express_slot(d, where);
1308   if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
1309     cap_express_root(d, where);
1310
1311   if ((cap & PCI_EXP_FLAGS_VERS) < 2)
1312     return type;
1313
1314   size = 16;
1315   if (slot)
1316     size = 24;
1317   if (!config_fetch(d, where + PCI_EXP_DEVCAP2, size))
1318     return type;
1319
1320   cap_express_dev2(d, where, type);
1321   if (link)
1322     cap_express_link2(d, where, type);
1323   if (slot)
1324     cap_express_slot2(d, where);
1325   return type;
1326 }
1327
1328 static void
1329 cap_msix(struct device *d, int where, int cap)
1330 {
1331   u32 off;
1332
1333   printf("MSI-X: Enable%c Count=%d Masked%c\n",
1334          FLAG(cap, PCI_MSIX_ENABLE),
1335          (cap & PCI_MSIX_TABSIZE) + 1,
1336          FLAG(cap, PCI_MSIX_MASK));
1337   if (verbose < 2 || !config_fetch(d, where + PCI_MSIX_TABLE, 8))
1338     return;
1339
1340   off = get_conf_long(d, where + PCI_MSIX_TABLE);
1341   printf("\t\tVector table: BAR=%d offset=%08x\n",
1342          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1343   off = get_conf_long(d, where + PCI_MSIX_PBA);
1344   printf("\t\tPBA: BAR=%d offset=%08x\n",
1345          off & PCI_MSIX_BIR, off & ~PCI_MSIX_BIR);
1346 }
1347
1348 static void
1349 cap_slotid(int cap)
1350 {
1351   int esr = cap & 0xff;
1352   int chs = cap >> 8;
1353
1354   printf("Slot ID: %d slots, First%c, chassis %02x\n",
1355          esr & PCI_SID_ESR_NSLOTS,
1356          FLAG(esr, PCI_SID_ESR_FIC),
1357          chs);
1358 }
1359
1360 static void
1361 cap_ssvid(struct device *d, int where)
1362 {
1363   u16 subsys_v, subsys_d;
1364   char ssnamebuf[256];
1365
1366   if (!config_fetch(d, where, 8))
1367     return;
1368   subsys_v = get_conf_word(d, where + PCI_SSVID_VENDOR);
1369   subsys_d = get_conf_word(d, where + PCI_SSVID_DEVICE);
1370   printf("Subsystem: %s\n",
1371            pci_lookup_name(pacc, ssnamebuf, sizeof(ssnamebuf),
1372                            PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE,
1373                            d->dev->vendor_id, d->dev->device_id, subsys_v, subsys_d));
1374 }
1375
1376 static void
1377 cap_debug_port(int cap)
1378 {
1379   int bar = cap >> 13;
1380   int pos = cap & 0x1fff;
1381   printf("Debug port: BAR=%d offset=%04x\n", bar, pos);
1382 }
1383
1384 static void
1385 cap_af(struct device *d, int where)
1386 {
1387   u8 reg;
1388
1389   printf("PCI Advanced Features\n");
1390   if (verbose < 2 || !config_fetch(d, where + PCI_AF_CAP, 3))
1391     return;
1392
1393   reg = get_conf_byte(d, where + PCI_AF_CAP);
1394   printf("\t\tAFCap: TP%c FLR%c\n", FLAG(reg, PCI_AF_CAP_TP),
1395          FLAG(reg, PCI_AF_CAP_FLR));
1396   reg = get_conf_byte(d, where + PCI_AF_CTRL);
1397   printf("\t\tAFCtrl: FLR%c\n", FLAG(reg, PCI_AF_CTRL_FLR));
1398   reg = get_conf_byte(d, where + PCI_AF_STATUS);
1399   printf("\t\tAFStatus: TP%c\n", FLAG(reg, PCI_AF_STATUS_TP));
1400 }
1401
1402 static void
1403 cap_sata_hba(struct device *d, int where, int cap)
1404 {
1405   u32 bars;
1406   int bar;
1407
1408   printf("SATA HBA v%d.%d", BITS(cap, 4, 4), BITS(cap, 0, 4));
1409   if (verbose < 2 || !config_fetch(d, where + PCI_SATA_HBA_BARS, 4))
1410     {
1411       printf("\n");
1412       return;
1413     }
1414
1415   bars = get_conf_long(d, where + PCI_SATA_HBA_BARS);
1416   bar = BITS(bars, 0, 4);
1417   if (bar >= 4 && bar <= 9)
1418     printf(" BAR%d Offset=%08x\n", bar - 4, BITS(bars, 4, 20));
1419   else if (bar == 15)
1420     printf(" InCfgSpace\n");
1421   else
1422     printf(" BAR??%d\n", bar);
1423 }
1424
1425 static const char *cap_ea_property(int p, int is_secondary)
1426 {
1427   switch (p) {
1428   case 0x00:
1429     return "memory space, non-prefetchable";
1430   case 0x01:
1431     return "memory space, prefetchable";
1432   case 0x02:
1433     return "I/O space";
1434   case 0x03:
1435     return "VF memory space, prefetchable";
1436   case 0x04:
1437     return "VF memory space, non-prefetchable";
1438   case 0x05:
1439     return "allocation behind bridge, non-prefetchable memory";
1440   case 0x06:
1441     return "allocation behind bridge, prefetchable memory";
1442   case 0x07:
1443     return "allocation behind bridge, I/O space";
1444   case 0xfd:
1445     return "memory space resource unavailable for use";
1446   case 0xfe:
1447     return "I/O space resource unavailable for use";
1448   case 0xff:
1449     if (is_secondary)
1450       return "entry unavailable for use, PrimaryProperties should be used";
1451     else
1452       return "entry unavailable for use";
1453   default:
1454     return NULL;
1455   }
1456 }
1457
1458 static void cap_ea(struct device *d, int where, int cap)
1459 {
1460   int entry;
1461   int entry_base = where + 4;
1462   int num_entries = BITS(cap, 0, 6);
1463   u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
1464
1465   printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
1466   if (htype == PCI_HEADER_TYPE_BRIDGE) {
1467     byte fixed_sub, fixed_sec;
1468
1469     entry_base += 4;
1470     if (!config_fetch(d, where + 4, 2)) {
1471       printf("\n");
1472       return;
1473     }
1474     fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
1475     fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
1476     printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
1477   }
1478   printf("\n");
1479   if (verbose < 2)
1480     return;
1481
1482   for (entry = 0; entry < num_entries; entry++) {
1483     int max_offset_high_pos, has_base_high, has_max_offset_high;
1484     u32 entry_header;
1485     u32 base, max_offset;
1486     int es, bei, pp, sp;
1487     const char *prop_text;
1488
1489     if (!config_fetch(d, entry_base, 4))
1490       return;
1491     entry_header = get_conf_long(d, entry_base);
1492     es = BITS(entry_header, 0, 3);
1493     bei = BITS(entry_header, 4, 4);
1494     pp = BITS(entry_header, 8, 8);
1495     sp = BITS(entry_header, 16, 8);
1496     if (!config_fetch(d, entry_base + 4, es * 4))
1497       return;
1498     printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
1499            FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
1500            FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
1501     printf("\t\t\t BAR Equivalent Indicator: ");
1502     switch (bei) {
1503     case 0:
1504     case 1:
1505     case 2:
1506     case 3:
1507     case 4:
1508     case 5:
1509       printf("BAR %u", bei);
1510       break;
1511     case 6:
1512       printf("resource behind function");
1513       break;
1514     case 7:
1515       printf("not indicated");
1516       break;
1517     case 8:
1518       printf("expansion ROM");
1519       break;
1520     case 9:
1521     case 10:
1522     case 11:
1523     case 12:
1524     case 13:
1525     case 14:
1526       printf("VF-BAR %u", bei - 9);
1527       break;
1528     default:
1529       printf("reserved");
1530       break;
1531     }
1532     printf("\n");
1533
1534     prop_text = cap_ea_property(pp, 0);
1535     printf("\t\t\t PrimaryProperties: ");
1536     if (prop_text)
1537       printf("%s\n", prop_text);
1538     else
1539       printf("[%02x]\n", pp);
1540
1541     prop_text = cap_ea_property(sp, 1);
1542     printf("\t\t\t SecondaryProperties: ");
1543     if (prop_text)
1544       printf("%s\n", prop_text);
1545     else
1546       printf("[%02x]\n", sp);
1547
1548     base = get_conf_long(d, entry_base + 4);
1549     has_base_high = ((base & 2) != 0);
1550     base &= ~3;
1551
1552     max_offset = get_conf_long(d, entry_base + 8);
1553     has_max_offset_high = ((max_offset & 2) != 0);
1554     max_offset |= 3;
1555     max_offset_high_pos = entry_base + 12;
1556
1557     printf("\t\t\t Base: ");
1558     if (has_base_high) {
1559       u32 base_high = get_conf_long(d, entry_base + 12);
1560
1561       printf("%x", base_high);
1562       max_offset_high_pos += 4;
1563     }
1564     printf("%08x\n", base);
1565
1566     printf("\t\t\t MaxOffset: ");
1567     if (has_max_offset_high) {
1568       u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
1569
1570       printf("%x", max_offset_high);
1571     }
1572     printf("%08x\n", max_offset);
1573
1574     entry_base += 4 + 4 * es;
1575   }
1576 }
1577
1578 void
1579 show_caps(struct device *d, int where)
1580 {
1581   int can_have_ext_caps = 0;
1582   int type = -1;
1583
1584   if (get_conf_word(d, PCI_STATUS) & PCI_STATUS_CAP_LIST)
1585     {
1586       byte been_there[256];
1587       where = get_conf_byte(d, where) & ~3;
1588       memset(been_there, 0, 256);
1589       while (where)
1590         {
1591           int id, next, cap;
1592           printf("\tCapabilities: ");
1593           if (!config_fetch(d, where, 4))
1594             {
1595               puts("<access denied>");
1596               break;
1597             }
1598           id = get_conf_byte(d, where + PCI_CAP_LIST_ID);
1599           next = get_conf_byte(d, where + PCI_CAP_LIST_NEXT) & ~3;
1600           cap = get_conf_word(d, where + PCI_CAP_FLAGS);
1601           printf("[%02x] ", where);
1602           if (been_there[where]++)
1603             {
1604               printf("<chain looped>\n");
1605               break;
1606             }
1607           if (id == 0xff)
1608             {
1609               printf("<chain broken>\n");
1610               break;
1611             }
1612           switch (id)
1613             {
1614             case PCI_CAP_ID_NULL:
1615               printf("Null\n");
1616               break;
1617             case PCI_CAP_ID_PM:
1618               cap_pm(d, where, cap);
1619               break;
1620             case PCI_CAP_ID_AGP:
1621               cap_agp(d, where, cap);
1622               break;
1623             case PCI_CAP_ID_VPD:
1624               cap_vpd(d);
1625               break;
1626             case PCI_CAP_ID_SLOTID:
1627               cap_slotid(cap);
1628               break;
1629             case PCI_CAP_ID_MSI:
1630               cap_msi(d, where, cap);
1631               break;
1632             case PCI_CAP_ID_CHSWP:
1633               printf("CompactPCI hot-swap <?>\n");
1634               break;
1635             case PCI_CAP_ID_PCIX:
1636               cap_pcix(d, where);
1637               can_have_ext_caps = 1;
1638               break;
1639             case PCI_CAP_ID_HT:
1640               cap_ht(d, where, cap);
1641               break;
1642             case PCI_CAP_ID_VNDR:
1643               show_vendor_caps(d, where, cap);
1644               break;
1645             case PCI_CAP_ID_DBG:
1646               cap_debug_port(cap);
1647               break;
1648             case PCI_CAP_ID_CCRC:
1649               printf("CompactPCI central resource control <?>\n");
1650               break;
1651             case PCI_CAP_ID_HOTPLUG:
1652               printf("Hot-plug capable\n");
1653               break;
1654             case PCI_CAP_ID_SSVID:
1655               cap_ssvid(d, where);
1656               break;
1657             case PCI_CAP_ID_AGP3:
1658               printf("AGP3 <?>\n");
1659               break;
1660             case PCI_CAP_ID_SECURE:
1661               printf("Secure device <?>\n");
1662               break;
1663             case PCI_CAP_ID_EXP:
1664               type = cap_express(d, where, cap);
1665               can_have_ext_caps = 1;
1666               break;
1667             case PCI_CAP_ID_MSIX:
1668               cap_msix(d, where, cap);
1669               break;
1670             case PCI_CAP_ID_SATA:
1671               cap_sata_hba(d, where, cap);
1672               break;
1673             case PCI_CAP_ID_AF:
1674               cap_af(d, where);
1675               break;
1676             case PCI_CAP_ID_EA:
1677               cap_ea(d, where, cap);
1678               break;
1679             default:
1680               printf("Capability ID %#02x [%04x]\n", id, cap);
1681             }
1682           where = next;
1683         }
1684     }
1685   if (can_have_ext_caps)
1686     show_ext_caps(d, type);
1687 }