lspci: Decode DevCap SlotPowerLimit for all components with Upstream Ports

lspci: Decode DevCap SlotPowerLimit for all components with Upstream Ports

The SlotPowerLimit in the Slot Capability indicates how much power the slot
can supply to a downstream device.  A Root Port or Switch Downstream Port
communicates the limit via a Set_Slot_Power_Limit Message on the link.  The
component on the other end of the link copies the limit from the message to
the Captured Slot Power Limit in its Device Capability [see PCIe r3.0, sec
2.2.8.5].

The Captured SlotPowerLimit is relevant for all devices on the downstream
end of a Link.  This includes Endpoints and Bridges as well as
Switch Upstream Ports.

Decode the DevCap Captured SlotPowerLimit for Endpoints and Bridges as well
as Switch Upstream Ports.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>